File Index
Files and directories
Sign in
FILE

sdma1_4_0_default.h

File preview with syntax highlighting.

linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h C
  1/*
  2 * Copyright (C) 2017  Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included
 12 * in all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 20 */
 21#ifndef _sdma1_4_0_DEFAULT_HEADER
 22#define _sdma1_4_0_DEFAULT_HEADER
 23
 24
 25// addressBlock: sdma1_sdma1dec
 26#define mmSDMA1_UCODE_ADDR_DEFAULT	0x00000000
 27#define mmSDMA1_UCODE_DATA_DEFAULT	0x00000000
 28#define mmSDMA1_VM_CNTL_DEFAULT	0x00000000
 29#define mmSDMA1_VM_CTX_LO_DEFAULT	0x00000000
 30#define mmSDMA1_VM_CTX_HI_DEFAULT	0x00000000
 31#define mmSDMA1_ACTIVE_FCN_ID_DEFAULT	0x00000000
 32#define mmSDMA1_VM_CTX_CNTL_DEFAULT	0x00000000
 33#define mmSDMA1_VIRT_RESET_REQ_DEFAULT	0x00000000
 34#define mmSDMA1_VF_ENABLE_DEFAULT	0x00000000
 35#define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT	0xfffdf79f
 36#define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT	0x003fbcff
 37#define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT	0x000003ff
 38#define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT	0x00000000
 39#define mmSDMA1_PUB_REG_TYPE0_DEFAULT	0x3c000000
 40#define mmSDMA1_PUB_REG_TYPE1_DEFAULT	0x30003882
 41#define mmSDMA1_PUB_REG_TYPE2_DEFAULT	0x0fc6e880
 42#define mmSDMA1_PUB_REG_TYPE3_DEFAULT	0x00000000
 43#define mmSDMA1_MMHUB_CNTL_DEFAULT	0x00000000
 44#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT	0x00000000
 45#define mmSDMA1_POWER_CNTL_DEFAULT	0x0003c000
 46#define mmSDMA1_CLK_CTRL_DEFAULT	0xff000100
 47#define mmSDMA1_CNTL_DEFAULT	0x00000002
 48#define mmSDMA1_CHICKEN_BITS_DEFAULT	0x00831f07
 49#define mmSDMA1_GB_ADDR_CONFIG_DEFAULT	0x00100012
 50#define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT	0x00100012
 51#define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT	0x00000000
 52#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT	0x00000000
 53#define mmSDMA1_RB_RPTR_FETCH_DEFAULT	0x00000000
 54#define mmSDMA1_IB_OFFSET_FETCH_DEFAULT	0x00000000
 55#define mmSDMA1_PROGRAM_DEFAULT	0x00000000
 56#define mmSDMA1_STATUS_REG_DEFAULT	0x46dee557
 57#define mmSDMA1_STATUS1_REG_DEFAULT	0x000003ff
 58#define mmSDMA1_RD_BURST_CNTL_DEFAULT	0x00000003
 59#define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT	0x00000000
 60#define mmSDMA1_UCODE_CHECKSUM_DEFAULT	0x00000000
 61#define mmSDMA1_F32_CNTL_DEFAULT	0x00000001
 62#define mmSDMA1_FREEZE_DEFAULT	0x00000000
 63#define mmSDMA1_PHASE0_QUANTUM_DEFAULT	0x00010002
 64#define mmSDMA1_PHASE1_QUANTUM_DEFAULT	0x00010002
 65#define mmSDMA1_EDC_CONFIG_DEFAULT	0x00000002
 66#define mmSDMA1_BA_THRESHOLD_DEFAULT	0x03ff03ff
 67#define mmSDMA1_ID_DEFAULT	0x00000001
 68#define mmSDMA1_VERSION_DEFAULT	0x00000400
 69#define mmSDMA1_EDC_COUNTER_DEFAULT	0x00000000
 70#define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT	0x00000000
 71#define mmSDMA1_STATUS2_REG_DEFAULT	0x00000001
 72#define mmSDMA1_ATOMIC_CNTL_DEFAULT	0x00000200
 73#define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT	0x00000000
 74#define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT	0x00000000
 75#define mmSDMA1_UTCL1_CNTL_DEFAULT	0xd0003019
 76#define mmSDMA1_UTCL1_WATERMK_DEFAULT	0xfffbe1fe
 77#define mmSDMA1_UTCL1_RD_STATUS_DEFAULT	0x201001ff
 78#define mmSDMA1_UTCL1_WR_STATUS_DEFAULT	0x503001ff
 79#define mmSDMA1_UTCL1_INV0_DEFAULT	0x00000600
 80#define mmSDMA1_UTCL1_INV1_DEFAULT	0x00000000
 81#define mmSDMA1_UTCL1_INV2_DEFAULT	0x00000000
 82#define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT	0x00000000
 83#define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT	0x00000000
 84#define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT	0x00000000
 85#define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT	0x00000000
 86#define mmSDMA1_UTCL1_TIMEOUT_DEFAULT	0x00010001
 87#define mmSDMA1_UTCL1_PAGE_DEFAULT	0x000003e0
 88#define mmSDMA1_POWER_CNTL_IDLE_DEFAULT	0x06060200
 89#define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT	0xc0000006
 90#define mmSDMA1_CHICKEN_BITS_2_DEFAULT	0x00000005
 91#define mmSDMA1_STATUS3_REG_DEFAULT	0x00100000
 92#define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT	0x00000000
 93#define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT	0x00000000
 94#define mmSDMA1_PHASE2_QUANTUM_DEFAULT	0x00010002
 95#define mmSDMA1_ERROR_LOG_DEFAULT	0x0000000f
 96#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT	0x00000000
 97#define mmSDMA1_PUB_DUMMY_REG1_DEFAULT	0x00000000
 98#define mmSDMA1_PUB_DUMMY_REG2_DEFAULT	0x00000000
 99#define mmSDMA1_PUB_DUMMY_REG3_DEFAULT	0x00000000
100#define mmSDMA1_F32_COUNTER_DEFAULT	0x00000000
101#define mmSDMA1_UNBREAKABLE_DEFAULT	0x00000000
102#define mmSDMA1_PERFMON_CNTL_DEFAULT	0x000ff7fd
103#define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT	0x00000000
104#define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT	0x00000000
105#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT	0x00640000
106#define mmSDMA1_CRD_CNTL_DEFAULT	0x000085c0
107#define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT	0x00000000
108#define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT	0x00000000
109#define mmSDMA1_ULV_CNTL_DEFAULT	0x00000000
110#define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT	0x00000000
111#define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT	0x00000000
112#define mmSDMA1_GFX_RB_CNTL_DEFAULT	0x00040000
113#define mmSDMA1_GFX_RB_BASE_DEFAULT	0x00000000
114#define mmSDMA1_GFX_RB_BASE_HI_DEFAULT	0x00000000
115#define mmSDMA1_GFX_RB_RPTR_DEFAULT	0x00000000
116#define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT	0x00000000
117#define mmSDMA1_GFX_RB_WPTR_DEFAULT	0x00000000
118#define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT	0x00000000
119#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT	0x00401000
120#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT	0x00000000
121#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT	0x00000000
122#define mmSDMA1_GFX_IB_CNTL_DEFAULT	0x00000100
123#define mmSDMA1_GFX_IB_RPTR_DEFAULT	0x00000000
124#define mmSDMA1_GFX_IB_OFFSET_DEFAULT	0x00000000
125#define mmSDMA1_GFX_IB_BASE_LO_DEFAULT	0x00000000
126#define mmSDMA1_GFX_IB_BASE_HI_DEFAULT	0x00000000
127#define mmSDMA1_GFX_IB_SIZE_DEFAULT	0x00000000
128#define mmSDMA1_GFX_SKIP_CNTL_DEFAULT	0x00000000
129#define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT	0x00000005
130#define mmSDMA1_GFX_DOORBELL_DEFAULT	0x00000000
131#define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT	0x00000000
132#define mmSDMA1_GFX_STATUS_DEFAULT	0x00000000
133#define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT	0x00000000
134#define mmSDMA1_GFX_WATERMARK_DEFAULT	0x00000000
135#define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT	0x00000000
136#define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT	0x00000000
137#define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT	0x00000000
138#define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT	0x00000000
139#define mmSDMA1_GFX_PREEMPT_DEFAULT	0x00000000
140#define mmSDMA1_GFX_DUMMY_REG_DEFAULT	0x0000000f
141#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT	0x00000000
142#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT	0x00000000
143#define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT	0x00004000
144#define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT	0x00000000
145#define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT	0x00000000
146#define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT	0x00000000
147#define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT	0x00000000
148#define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT	0x00000000
149#define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT	0x00000000
150#define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT	0x00000000
151#define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT	0x00000000
152#define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT	0x00000000
153#define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT	0x00000000
154#define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT	0x00000000
155#define mmSDMA1_PAGE_RB_CNTL_DEFAULT	0x00040000
156#define mmSDMA1_PAGE_RB_BASE_DEFAULT	0x00000000
157#define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT	0x00000000
158#define mmSDMA1_PAGE_RB_RPTR_DEFAULT	0x00000000
159#define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT	0x00000000
160#define mmSDMA1_PAGE_RB_WPTR_DEFAULT	0x00000000
161#define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT	0x00000000
162#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT	0x00401000
163#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT	0x00000000
164#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT	0x00000000
165#define mmSDMA1_PAGE_IB_CNTL_DEFAULT	0x00000100
166#define mmSDMA1_PAGE_IB_RPTR_DEFAULT	0x00000000
167#define mmSDMA1_PAGE_IB_OFFSET_DEFAULT	0x00000000
168#define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT	0x00000000
169#define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT	0x00000000
170#define mmSDMA1_PAGE_IB_SIZE_DEFAULT	0x00000000
171#define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT	0x00000000
172#define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT	0x00000004
173#define mmSDMA1_PAGE_DOORBELL_DEFAULT	0x00000000
174#define mmSDMA1_PAGE_STATUS_DEFAULT	0x00000000
175#define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT	0x00000000
176#define mmSDMA1_PAGE_WATERMARK_DEFAULT	0x00000000
177#define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT	0x00000000
178#define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT	0x00000000
179#define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT	0x00000000
180#define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT	0x00000000
181#define mmSDMA1_PAGE_PREEMPT_DEFAULT	0x00000000
182#define mmSDMA1_PAGE_DUMMY_REG_DEFAULT	0x0000000f
183#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT	0x00000000
184#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT	0x00000000
185#define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT	0x00004000
186#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT	0x00000000
187#define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT	0x00000000
188#define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT	0x00000000
189#define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT	0x00000000
190#define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT	0x00000000
191#define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT	0x00000000
192#define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT	0x00000000
193#define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT	0x00000000
194#define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT	0x00000000
195#define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT	0x00000000
196#define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT	0x00000000
197#define mmSDMA1_RLC0_RB_CNTL_DEFAULT	0x00040000
198#define mmSDMA1_RLC0_RB_BASE_DEFAULT	0x00000000
199#define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT	0x00000000
200#define mmSDMA1_RLC0_RB_RPTR_DEFAULT	0x00000000
201#define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT	0x00000000
202#define mmSDMA1_RLC0_RB_WPTR_DEFAULT	0x00000000
203#define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT	0x00000000
204#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT	0x00401000
205#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT	0x00000000
206#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT	0x00000000
207#define mmSDMA1_RLC0_IB_CNTL_DEFAULT	0x00000100
208#define mmSDMA1_RLC0_IB_RPTR_DEFAULT	0x00000000
209#define mmSDMA1_RLC0_IB_OFFSET_DEFAULT	0x00000000
210#define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT	0x00000000
211#define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT	0x00000000
212#define mmSDMA1_RLC0_IB_SIZE_DEFAULT	0x00000000
213#define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT	0x00000000
214#define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT	0x00000004
215#define mmSDMA1_RLC0_DOORBELL_DEFAULT	0x00000000
216#define mmSDMA1_RLC0_STATUS_DEFAULT	0x00000000
217#define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT	0x00000000
218#define mmSDMA1_RLC0_WATERMARK_DEFAULT	0x00000000
219#define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT	0x00000000
220#define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT	0x00000000
221#define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT	0x00000000
222#define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT	0x00000000
223#define mmSDMA1_RLC0_PREEMPT_DEFAULT	0x00000000
224#define mmSDMA1_RLC0_DUMMY_REG_DEFAULT	0x0000000f
225#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT	0x00000000
226#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT	0x00000000
227#define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT	0x00004000
228#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT	0x00000000
229#define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT	0x00000000
230#define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT	0x00000000
231#define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT	0x00000000
232#define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT	0x00000000
233#define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT	0x00000000
234#define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT	0x00000000
235#define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT	0x00000000
236#define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT	0x00000000
237#define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT	0x00000000
238#define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT	0x00000000
239#define mmSDMA1_RLC1_RB_CNTL_DEFAULT	0x00040000
240#define mmSDMA1_RLC1_RB_BASE_DEFAULT	0x00000000
241#define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT	0x00000000
242#define mmSDMA1_RLC1_RB_RPTR_DEFAULT	0x00000000
243#define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT	0x00000000
244#define mmSDMA1_RLC1_RB_WPTR_DEFAULT	0x00000000
245#define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT	0x00000000
246#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT	0x00401000
247#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT	0x00000000
248#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT	0x00000000
249#define mmSDMA1_RLC1_IB_CNTL_DEFAULT	0x00000100
250#define mmSDMA1_RLC1_IB_RPTR_DEFAULT	0x00000000
251#define mmSDMA1_RLC1_IB_OFFSET_DEFAULT	0x00000000
252#define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT	0x00000000
253#define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT	0x00000000
254#define mmSDMA1_RLC1_IB_SIZE_DEFAULT	0x00000000
255#define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT	0x00000000
256#define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT	0x00000004
257#define mmSDMA1_RLC1_DOORBELL_DEFAULT	0x00000000
258#define mmSDMA1_RLC1_STATUS_DEFAULT	0x00000000
259#define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT	0x00000000
260#define mmSDMA1_RLC1_WATERMARK_DEFAULT	0x00000000
261#define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT	0x00000000
262#define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT	0x00000000
263#define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT	0x00000000
264#define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT	0x00000000
265#define mmSDMA1_RLC1_PREEMPT_DEFAULT	0x00000000
266#define mmSDMA1_RLC1_DUMMY_REG_DEFAULT	0x0000000f
267#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT	0x00000000
268#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT	0x00000000
269#define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT	0x00004000
270#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT	0x00000000
271#define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT	0x00000000
272#define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT	0x00000000
273#define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT	0x00000000
274#define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT	0x00000000
275#define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT	0x00000000
276#define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT	0x00000000
277#define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT	0x00000000
278#define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT	0x00000000
279#define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT	0x00000000
280#define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT	0x00000000
281
282#endif
~/ Read-only file preview.