FILE
sdma0_4_1_sh_mask.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h
1/* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _sdma0_4_1_SH_MASK_HEADER 22#define _sdma0_4_1_SH_MASK_HEADER 23 24 25// addressBlock: sdma0_sdma0dec 26//SDMA0_UCODE_ADDR 27#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 28#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29//SDMA0_UCODE_DATA 30#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 31#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32//SDMA0_VM_CNTL 33#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 34#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 35//SDMA0_VM_CTX_LO 36#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 37#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38//SDMA0_VM_CTX_HI 39#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 40#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41//SDMA0_ACTIVE_FCN_ID 42#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48//SDMA0_VM_CTX_CNTL 49#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 50#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 51#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53//SDMA0_VIRT_RESET_REQ 54#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 55#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 56#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 58//SDMA0_CONTEXT_REG_TYPE0 59#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 60#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 61#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 62#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 63#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 64#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 65#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 66#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 67#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 68#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 69#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 70#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 71#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 72#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 73#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 74#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 75#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 76#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 77#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 78#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 79#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 80#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 81#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 82#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 83#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 84#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 85#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 86#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 87#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 88#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 89#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 90#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 91#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 92#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 93#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 94#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 95#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 96#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 97#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 98#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 99//SDMA0_CONTEXT_REG_TYPE1 100#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 101#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 102#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 103#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 104#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 105#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 106#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 107#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 108#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 109#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 110#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 111#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 112#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 113#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 114#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 115#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 116#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 117#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 118#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 119#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 120#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 121#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 122#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 123#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 124#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 125#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 126#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 127#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 128#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 129#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 130//SDMA0_CONTEXT_REG_TYPE2 131#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 132#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 133#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 134#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 135#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 136#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 137#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 138#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 139#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 140#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 141#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 142#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 143#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 144#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 145#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 146#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 147#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 148#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 149#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 150#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 151#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 152#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 153//SDMA0_CONTEXT_REG_TYPE3 154#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 155#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 156//SDMA0_PUB_REG_TYPE0 157#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 158#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 159#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 160#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 161#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 162#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 163#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 164#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 165#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 166#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 167#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 168#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 169#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 170#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 171#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 172#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 173#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 174#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 175#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 176#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 177#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 178#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 179#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 180#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 181#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 182#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 183#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 184#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 185#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 186#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 187#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 188#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 189#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 190#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 191#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 192#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 193#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 194#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 195#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 196#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 197#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 198#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 199#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 200#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 201#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 202#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 203#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 204#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 205#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 206#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 207#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 208#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 209#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 210#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 211//SDMA0_PUB_REG_TYPE1 212#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 213#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 214#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 215#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 216#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 217#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 218#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 219#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 220#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 221#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 222#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 223#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 224#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 225#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 226#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 227#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 228#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 229#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 230#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 231#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 232#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 233#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 234#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 235#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 236#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 237#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 238#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 239#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 240#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 241#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 242#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 243#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 244#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 245#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 246#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 247#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 248#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 249#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 250#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 251#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 252#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 253#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 254#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 255#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 256#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 257#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 258#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 259#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 260#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 261#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 262#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 263#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 264#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 265#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 266#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 267#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 268#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 269#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 270#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 271#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 272#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 273#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 274#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 275#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 276//SDMA0_PUB_REG_TYPE2 277#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 278#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 279#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 280#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 281#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 282#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 283#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 284#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 285#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 286#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 287#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 288#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 289#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 290#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 291#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 292#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 293#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 294#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 295#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 296#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 297#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 298#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 299#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 300#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 301#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 302#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 303#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 304#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c 305#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 306#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 307#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 308#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 309#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 310#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 311#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 312#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 313#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 314#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 315#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 316#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 317#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 318#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 319#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 320#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 321#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 322#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 323#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 324#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 325#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 326#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 327#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 328#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 329#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L 330#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 331#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 332#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 333#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 334#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 335#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L 336#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 337#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 338#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 339//SDMA0_PUB_REG_TYPE3 340#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 341#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 342#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 343#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 344#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 345#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 346//SDMA0_MMHUB_CNTL 347#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 348#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 349//SDMA0_CONTEXT_GROUP_BOUNDARY 350#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 351#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 352//SDMA0_POWER_CNTL 353#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 354#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 355#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 356#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 357#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 358#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 359#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 360#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 361#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 362#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 363#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 364#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 365#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 366#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 367#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 368#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 369#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 370#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 371#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 372#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 373//SDMA0_CLK_CTRL 374#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 375#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 376#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 377#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 378#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 379#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 380#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 381#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 382#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 383#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 384#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 385#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 386#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 387#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 388#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 389#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 390#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 391#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 392#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 393#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 394#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 395#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 396//SDMA0_CNTL 397#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 398#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 399#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 400#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 401#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 402#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 403#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 404#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 405#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 406#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 407#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 408#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 409#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 410#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 411#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 412#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 413#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 414#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 415#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 416#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 417#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 418#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 419//SDMA0_CHICKEN_BITS 420#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 421#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 422#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 423#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 424#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 425#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 426#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 427#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 428#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 429#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 430#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 431#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 432#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 433#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 434#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 435#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 436#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 437#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 438#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 439#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 440#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 441#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 442#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 443#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 444#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 445#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 446//SDMA0_GB_ADDR_CONFIG 447#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 448#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 449#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 450#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 451#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 452#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 453#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 454#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 455#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 456#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 457//SDMA0_GB_ADDR_CONFIG_READ 458#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 459#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 460#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 461#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 462#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 463#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 464#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 465#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 466#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 467#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 468//SDMA0_RB_RPTR_FETCH_HI 469#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 470#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 471//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 472#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 473#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 474//SDMA0_RB_RPTR_FETCH 475#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 476#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 477//SDMA0_IB_OFFSET_FETCH 478#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 479#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 480//SDMA0_PROGRAM 481#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 482#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 483//SDMA0_STATUS_REG 484#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 485#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 486#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 487#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 488#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 489#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 490#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 491#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 492#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 493#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 494#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 495#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 496#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 497#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 498#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 499#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 500#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 501#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 502#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 503#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 504#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 505#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 506#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 507#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 508#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 509#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 510#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 511#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 512#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 513#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 514#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 515#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 516#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 517#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 518#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 519#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 520#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 521#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 522#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 523#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 524#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 525#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 526#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 527#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 528#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 529#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 530#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 531#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 532#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 533#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 534#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 535#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 536#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 537#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 538#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 539#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 540#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 541#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 542//SDMA0_STATUS1_REG 543#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 544#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 545#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 546#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 547#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 548#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 549#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 550#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 551#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 552#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 553#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 554#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 555#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 556#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 557#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 558#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 559#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 560#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 561#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 562#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 563#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 564#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 565#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 566#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 567#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 568#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 569#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 570#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 571//SDMA0_RD_BURST_CNTL 572#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 573#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 574//SDMA0_HBM_PAGE_CONFIG 575#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 576#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 577//SDMA0_UCODE_CHECKSUM 578#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 579#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 580//SDMA0_F32_CNTL 581#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 582#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 583#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 584#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 585//SDMA0_FREEZE 586#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 587#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 588#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 589#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 590#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 591#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 592#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 593#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 594//SDMA0_PHASE0_QUANTUM 595#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 596#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 597#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 598#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 599#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 600#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 601//SDMA0_PHASE1_QUANTUM 602#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 603#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 604#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 605#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 606#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 607#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 608//SDMA_POWER_GATING 609#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 610#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 611#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 612#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 613#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 614#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 615#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 616#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 617#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 618#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 619//SDMA_PGFSM_CONFIG 620#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 621#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 622#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 623#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 624#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 625#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 626#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 627#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 628#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 629#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 630#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 631#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 632#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 633#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 634#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 635#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 636#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 637#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 638//SDMA_PGFSM_WRITE 639#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 640#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 641//SDMA_PGFSM_READ 642#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 643#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 644//SDMA0_EDC_CONFIG 645#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 646#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 647#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 648#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 649//SDMA0_BA_THRESHOLD 650#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 651#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 652#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 653#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 654//SDMA0_ID 655#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 656#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 657//SDMA0_VERSION 658#define SDMA0_VERSION__MINVER__SHIFT 0x0 659#define SDMA0_VERSION__MAJVER__SHIFT 0x8 660#define SDMA0_VERSION__REV__SHIFT 0x10 661#define SDMA0_VERSION__MINVER_MASK 0x0000007FL 662#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 663#define SDMA0_VERSION__REV_MASK 0x003F0000L 664//SDMA0_EDC_COUNTER 665#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 666#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 667#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 668#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 669#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 670#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 671#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 672#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 673#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 674#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 675#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 676#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 677#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 678#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 679#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 680#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf 681#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 682#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L 683#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L 684#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 685#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 686#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 687#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 688#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 689#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 690#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 691#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 692#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 693#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 694#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 695#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 696#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 697#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L 698#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L 699//SDMA0_EDC_COUNTER_CLEAR 700#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 701#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 702//SDMA0_STATUS2_REG 703#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 704#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 705#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 706#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L 707#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 708#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 709//SDMA0_ATOMIC_CNTL 710#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 711#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 712#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 713#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 714//SDMA0_ATOMIC_PREOP_LO 715#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 716#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 717//SDMA0_ATOMIC_PREOP_HI 718#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 719#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 720//SDMA0_UTCL1_CNTL 721#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 722#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 723#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 724#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 725#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 726#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 727#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 728#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 729#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 730#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 731#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 732#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 733//SDMA0_UTCL1_WATERMK 734#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 735#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 736#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 737#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a 738#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL 739#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L 740#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L 741#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L 742//SDMA0_UTCL1_RD_STATUS 743#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 744#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 745#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 746#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 747#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 748#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 749#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 750#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 751#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 752#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 753#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 754#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 755#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 756#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 757#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 758#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 759#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 760#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 761#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 762#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 763#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 764#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 765#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 766#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 767#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 768#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 769#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 770#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 771#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 772#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 773#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 774#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 775#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 776#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 777#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 778#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 779#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 780#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 781#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 782#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 783#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 784#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 785#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 786#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 787#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 788#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 789#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 790#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 791#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 792#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 793#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 794#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 795#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 796#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 797//SDMA0_UTCL1_WR_STATUS 798#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 799#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 800#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 801#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 802#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 803#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 804#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 805#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 806#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 807#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 808#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 809#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 810#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 811#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 812#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 813#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 814#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 815#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 816#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 817#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 818#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 819#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 820#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 821#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 822#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 823#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 824#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 825#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 826#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 827#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 828#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 829#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 830#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 831#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 832#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 833#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 834#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 835#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 836#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 837#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 838#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 839#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 840#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 841#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 842#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 843#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 844#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 845#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 846#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 847#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 848#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 849#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 850#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 851#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 852#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 853#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 854//SDMA0_UTCL1_INV0 855#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 856#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 857#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 858#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 859#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 860#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 861#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 862#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 863#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 864#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 865#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 866#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 867#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 868#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 869#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 870#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 871#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 872#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 873#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 874#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 875#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 876#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 877#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 878#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 879#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 880#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 881#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 882#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 883//SDMA0_UTCL1_INV1 884#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 885#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 886//SDMA0_UTCL1_INV2 887#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 888#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 889//SDMA0_UTCL1_RD_XNACK0 890#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 891#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 892//SDMA0_UTCL1_RD_XNACK1 893#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 894#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 895#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 896#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 897#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 898#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 899#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 900#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 901//SDMA0_UTCL1_WR_XNACK0 902#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 903#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 904//SDMA0_UTCL1_WR_XNACK1 905#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 906#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 907#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 908#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 909#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 910#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 911#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 912#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 913//SDMA0_UTCL1_TIMEOUT 914#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 915#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 916#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 917#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 918//SDMA0_UTCL1_PAGE 919#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 920#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 921#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 922#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 923#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 924#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 925#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 926#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 927//SDMA0_POWER_CNTL_IDLE 928#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 929#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 930#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 931#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 932#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 933#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 934//SDMA0_RELAX_ORDERING_LUT 935#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 936#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 937#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 938#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 939#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 940#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 941#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 942#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 943#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 944#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 945#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 946#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 947#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 948#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 949#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 950#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 951#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 952#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 953#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 954#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 955#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 956#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 957#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 958#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 959#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 960#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 961#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 962#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 963#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 964#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 965#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 966#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 967#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 968#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 969#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 970#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 971#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 972#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 973//SDMA0_CHICKEN_BITS_2 974#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 975#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 976//SDMA0_STATUS3_REG 977#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 978#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 979#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 980#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 981#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 982#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 983//SDMA0_PHYSICAL_ADDR_LO 984#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 985#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 986#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 987#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 988#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 989#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 990#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 991#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 992//SDMA0_PHYSICAL_ADDR_HI 993#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 994#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 995//SDMA0_ERROR_LOG 996#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 997#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 998#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 999#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1000//SDMA0_PUB_DUMMY_REG0 1001#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1002#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1003//SDMA0_PUB_DUMMY_REG1 1004#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1005#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1006//SDMA0_PUB_DUMMY_REG2 1007#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1008#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1009//SDMA0_PUB_DUMMY_REG3 1010#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1011#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1012//SDMA0_F32_COUNTER 1013#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1014#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1015//SDMA0_UNBREAKABLE 1016#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 1017#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L 1018//SDMA0_PERFMON_CNTL 1019#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1020#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1021#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1022#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1023#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1024#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1025#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1026#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1027#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1028#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1029#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1030#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1031//SDMA0_PERFCOUNTER0_RESULT 1032#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1033#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1034//SDMA0_PERFCOUNTER1_RESULT 1035#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1036#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1037//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1038#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1039#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1040#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1041#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1042#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1043#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1044//SDMA0_CRD_CNTL 1045#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1046#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1047#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1048#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1049//SDMA0_MMHUB_TRUSTLVL 1050#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 1051#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 1052#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 1053#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 1054#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc 1055#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf 1056#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 1057#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 1058#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L 1059#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L 1060#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L 1061#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L 1062#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L 1063#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L 1064#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L 1065#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L 1066//SDMA0_GPU_IOV_VIOLATION_LOG 1067#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1068#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1069#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1070#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1071#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1072#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1073#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1074#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1075#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1076#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1077#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1078#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1079#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1080#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1081//SDMA0_ULV_CNTL 1082#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1083#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1084#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1085#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1086#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1087#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1088#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1089#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1090//SDMA0_EA_DBIT_ADDR_DATA 1091#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1092#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1093//SDMA0_EA_DBIT_ADDR_INDEX 1094#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1095#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1096//SDMA0_GFX_RB_CNTL 1097#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1098#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1099#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1100#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1101#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1102#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1103#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1104#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1105#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1106#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1107#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1108#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1109#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1110#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1111#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1112#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1113//SDMA0_GFX_RB_BASE 1114#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1115#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1116//SDMA0_GFX_RB_BASE_HI 1117#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1118#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1119//SDMA0_GFX_RB_RPTR 1120#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1121#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1122//SDMA0_GFX_RB_RPTR_HI 1123#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1124#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1125//SDMA0_GFX_RB_WPTR 1126#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1127#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1128//SDMA0_GFX_RB_WPTR_HI 1129#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1130#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1131//SDMA0_GFX_RB_WPTR_POLL_CNTL 1132#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1133#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1134#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1135#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1136#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1137#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1138#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1139#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1140#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1141#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1142//SDMA0_GFX_RB_RPTR_ADDR_HI 1143#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1144#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1145//SDMA0_GFX_RB_RPTR_ADDR_LO 1146#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1147#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1148//SDMA0_GFX_IB_CNTL 1149#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1150#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1151#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1152#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1153#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1154#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1155#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1156#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1157//SDMA0_GFX_IB_RPTR 1158#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1159#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1160//SDMA0_GFX_IB_OFFSET 1161#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1162#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1163//SDMA0_GFX_IB_BASE_LO 1164#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1165#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1166//SDMA0_GFX_IB_BASE_HI 1167#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1168#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1169//SDMA0_GFX_IB_SIZE 1170#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1171#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1172//SDMA0_GFX_SKIP_CNTL 1173#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1174#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1175//SDMA0_GFX_CONTEXT_STATUS 1176#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1177#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1178#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1179#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1180#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1181#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1182#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1183#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1184#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1185#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1186#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1187#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1188#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1189#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1190#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1191#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1192//SDMA0_GFX_DOORBELL 1193#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1194#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1195#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1196#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1197//SDMA0_GFX_CONTEXT_CNTL 1198#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1199#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1200//SDMA0_GFX_STATUS 1201#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1202#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1203#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1204#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1205//SDMA0_GFX_DOORBELL_LOG 1206#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1207#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1208#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1209#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1210//SDMA0_GFX_WATERMARK 1211#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1212#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1213#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1214#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1215//SDMA0_GFX_DOORBELL_OFFSET 1216#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1217#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1218//SDMA0_GFX_CSA_ADDR_LO 1219#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1220#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1221//SDMA0_GFX_CSA_ADDR_HI 1222#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1223#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1224//SDMA0_GFX_IB_SUB_REMAIN 1225#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1226#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1227//SDMA0_GFX_PREEMPT 1228#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1229#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1230//SDMA0_GFX_DUMMY_REG 1231#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1232#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1233//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1234#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1235#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1236//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1237#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1238#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1239//SDMA0_GFX_RB_AQL_CNTL 1240#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1241#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1242#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1243#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1244#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1245#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1246//SDMA0_GFX_MINOR_PTR_UPDATE 1247#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1248#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1249//SDMA0_GFX_MIDCMD_DATA0 1250#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1251#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1252//SDMA0_GFX_MIDCMD_DATA1 1253#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1254#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1255//SDMA0_GFX_MIDCMD_DATA2 1256#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1257#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1258//SDMA0_GFX_MIDCMD_DATA3 1259#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1260#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1261//SDMA0_GFX_MIDCMD_DATA4 1262#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1263#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1264//SDMA0_GFX_MIDCMD_DATA5 1265#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1266#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1267//SDMA0_GFX_MIDCMD_DATA6 1268#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1269#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1270//SDMA0_GFX_MIDCMD_DATA7 1271#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1272#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1273//SDMA0_GFX_MIDCMD_DATA8 1274#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1275#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1276//SDMA0_GFX_MIDCMD_CNTL 1277#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1278#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1279#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1280#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1281#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1282#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1283#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1284#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1285//SDMA0_RLC0_RB_CNTL 1286#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1287#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1288#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1289#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1290#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1291#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1292#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1293#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1294#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1295#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1296#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1297#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1298#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1299#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1300#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1301#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1302//SDMA0_RLC0_RB_BASE 1303#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1304#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1305//SDMA0_RLC0_RB_BASE_HI 1306#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1307#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1308//SDMA0_RLC0_RB_RPTR 1309#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1310#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1311//SDMA0_RLC0_RB_RPTR_HI 1312#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1313#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1314//SDMA0_RLC0_RB_WPTR 1315#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1316#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1317//SDMA0_RLC0_RB_WPTR_HI 1318#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1319#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1320//SDMA0_RLC0_RB_WPTR_POLL_CNTL 1321#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1322#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1323#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1324#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1325#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1326#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1327#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1328#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1329#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1330#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1331//SDMA0_RLC0_RB_RPTR_ADDR_HI 1332#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1333#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1334//SDMA0_RLC0_RB_RPTR_ADDR_LO 1335#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1336#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1337//SDMA0_RLC0_IB_CNTL 1338#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1339#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1340#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1341#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1342#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1343#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1344#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1345#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1346//SDMA0_RLC0_IB_RPTR 1347#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1348#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1349//SDMA0_RLC0_IB_OFFSET 1350#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1351#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1352//SDMA0_RLC0_IB_BASE_LO 1353#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1354#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1355//SDMA0_RLC0_IB_BASE_HI 1356#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1357#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1358//SDMA0_RLC0_IB_SIZE 1359#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1360#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1361//SDMA0_RLC0_SKIP_CNTL 1362#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1363#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1364//SDMA0_RLC0_CONTEXT_STATUS 1365#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1366#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1367#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1368#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1369#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1370#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1371#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1372#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1373#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1374#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1375#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1376#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1377#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1378#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1379#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1380#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1381//SDMA0_RLC0_DOORBELL 1382#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1383#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1384#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1385#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1386//SDMA0_RLC0_STATUS 1387#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1388#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1389#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1390#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1391//SDMA0_RLC0_DOORBELL_LOG 1392#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1393#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1394#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1395#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1396//SDMA0_RLC0_WATERMARK 1397#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1398#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1399#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1400#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1401//SDMA0_RLC0_DOORBELL_OFFSET 1402#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1403#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1404//SDMA0_RLC0_CSA_ADDR_LO 1405#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1406#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1407//SDMA0_RLC0_CSA_ADDR_HI 1408#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1409#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1410//SDMA0_RLC0_IB_SUB_REMAIN 1411#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1412#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1413//SDMA0_RLC0_PREEMPT 1414#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1415#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1416//SDMA0_RLC0_DUMMY_REG 1417#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1418#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1419//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1420#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1421#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1422//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1423#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1424#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1425//SDMA0_RLC0_RB_AQL_CNTL 1426#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1427#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1428#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1429#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1430#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1431#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1432//SDMA0_RLC0_MINOR_PTR_UPDATE 1433#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1434#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1435//SDMA0_RLC0_MIDCMD_DATA0 1436#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1437#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1438//SDMA0_RLC0_MIDCMD_DATA1 1439#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1440#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1441//SDMA0_RLC0_MIDCMD_DATA2 1442#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1443#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1444//SDMA0_RLC0_MIDCMD_DATA3 1445#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1446#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1447//SDMA0_RLC0_MIDCMD_DATA4 1448#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1449#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1450//SDMA0_RLC0_MIDCMD_DATA5 1451#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1452#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1453//SDMA0_RLC0_MIDCMD_DATA6 1454#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1455#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1456//SDMA0_RLC0_MIDCMD_DATA7 1457#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1458#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1459//SDMA0_RLC0_MIDCMD_DATA8 1460#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1461#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1462//SDMA0_RLC0_MIDCMD_CNTL 1463#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1464#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1465#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1466#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1467#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1468#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1469#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1470#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1471//SDMA0_RLC1_RB_CNTL 1472#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1473#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1474#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1475#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1476#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1477#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1478#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1479#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1480#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1481#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1482#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1483#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1484#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1485#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1486#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1487#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1488//SDMA0_RLC1_RB_BASE 1489#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1490#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1491//SDMA0_RLC1_RB_BASE_HI 1492#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1493#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1494//SDMA0_RLC1_RB_RPTR 1495#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1496#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1497//SDMA0_RLC1_RB_RPTR_HI 1498#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1499#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1500//SDMA0_RLC1_RB_WPTR 1501#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1502#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1503//SDMA0_RLC1_RB_WPTR_HI 1504#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1505#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1506//SDMA0_RLC1_RB_WPTR_POLL_CNTL 1507#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1508#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1509#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1510#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1511#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1512#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1513#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1514#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1515#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1516#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1517//SDMA0_RLC1_RB_RPTR_ADDR_HI 1518#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1519#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1520//SDMA0_RLC1_RB_RPTR_ADDR_LO 1521#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1522#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1523//SDMA0_RLC1_IB_CNTL 1524#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1525#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1526#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1527#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1528#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1529#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1530#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1531#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1532//SDMA0_RLC1_IB_RPTR 1533#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1534#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1535//SDMA0_RLC1_IB_OFFSET 1536#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1537#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1538//SDMA0_RLC1_IB_BASE_LO 1539#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1540#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1541//SDMA0_RLC1_IB_BASE_HI 1542#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1543#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1544//SDMA0_RLC1_IB_SIZE 1545#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1546#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1547//SDMA0_RLC1_SKIP_CNTL 1548#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1549#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1550//SDMA0_RLC1_CONTEXT_STATUS 1551#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1552#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1553#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1554#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1555#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1556#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1557#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1558#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1559#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1560#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1561#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1562#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1563#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1564#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1565#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1566#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1567//SDMA0_RLC1_DOORBELL 1568#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1569#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1570#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1571#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1572//SDMA0_RLC1_STATUS 1573#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1574#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1575#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1576#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1577//SDMA0_RLC1_DOORBELL_LOG 1578#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1579#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1580#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1581#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1582//SDMA0_RLC1_WATERMARK 1583#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1584#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1585#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1586#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1587//SDMA0_RLC1_DOORBELL_OFFSET 1588#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1589#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1590//SDMA0_RLC1_CSA_ADDR_LO 1591#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1592#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1593//SDMA0_RLC1_CSA_ADDR_HI 1594#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1595#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1596//SDMA0_RLC1_IB_SUB_REMAIN 1597#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1598#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1599//SDMA0_RLC1_PREEMPT 1600#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1601#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1602//SDMA0_RLC1_DUMMY_REG 1603#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1604#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1605//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1606#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1607#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1608//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1609#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1610#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1611//SDMA0_RLC1_RB_AQL_CNTL 1612#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1613#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1614#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1615#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1616#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1617#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1618//SDMA0_RLC1_MINOR_PTR_UPDATE 1619#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1620#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1621//SDMA0_RLC1_MIDCMD_DATA0 1622#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1623#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1624//SDMA0_RLC1_MIDCMD_DATA1 1625#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1626#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1627//SDMA0_RLC1_MIDCMD_DATA2 1628#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1629#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1630//SDMA0_RLC1_MIDCMD_DATA3 1631#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1632#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1633//SDMA0_RLC1_MIDCMD_DATA4 1634#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1635#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1636//SDMA0_RLC1_MIDCMD_DATA5 1637#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1638#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1639//SDMA0_RLC1_MIDCMD_DATA6 1640#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1641#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1642//SDMA0_RLC1_MIDCMD_DATA7 1643#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1644#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1645//SDMA0_RLC1_MIDCMD_DATA8 1646#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1647#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1648//SDMA0_RLC1_MIDCMD_CNTL 1649#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1650#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1651#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1652#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1653#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1654#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1655#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1656#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1657 1658#endif
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