nbio_7_4_0_smn.h

 1/*
 2 * Copyright (C) 2019  Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22#ifndef _nbio_7_4_0_SMN_HEADER
23#define _nbio_7_4_0_SMN_HEADER
24
25// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk
26// base address: 0x10100000
27#define smnBIFL_RAS_CENTRAL_STATUS			0x10139040
28
29#define smnNBIF_MGCG_CTRL_LCLK				0x1013a21c
30#define smnCPM_CONTROL					0x11180460
31#define smnPCIE_CNTL2					0x11180070
32#define smnPCIE_CI_CNTL					0x11180080
33
34#define smnPCIE_PERF_COUNT_CNTL				0x11180200
35#define smnPCIE_PERF_CNTL_TXCLK1			0x11180204
36#define smnPCIE_PERF_COUNT0_TXCLK1			0x11180208
37#define smnPCIE_PERF_COUNT1_TXCLK1			0x1118020c
38#define smnPCIE_PERF_CNTL_TXCLK2			0x11180210
39#define smnPCIE_PERF_COUNT0_TXCLK2			0x11180214
40#define smnPCIE_PERF_COUNT1_TXCLK2			0x11180218
41#define smnPCIE_PERF_CNTL_TXCLK3			0x1118021c
42#define smnPCIE_PERF_COUNT0_TXCLK3			0x11180220
43#define smnPCIE_PERF_COUNT1_TXCLK3			0x11180224
44#define smnPCIE_PERF_CNTL_TXCLK4			0x11180228
45#define smnPCIE_PERF_COUNT0_TXCLK4			0x1118022c
46#define smnPCIE_PERF_COUNT1_TXCLK4			0x11180230
47#define smnPCIE_PERF_CNTL_SCLK1				0x11180234
48#define smnPCIE_PERF_COUNT0_SCLK1			0x11180238
49#define smnPCIE_PERF_COUNT1_SCLK1			0x1118023c
50#define smnPCIE_PERF_CNTL_SCLK2				0x11180240
51#define smnPCIE_PERF_COUNT0_SCLK2			0x11180244
52#define smnPCIE_PERF_COUNT1_SCLK2			0x11180248
53#define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL		0x1118024c
54#define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL		0x11180250
55
56#define smnPCIE_RX_NUM_NAK				0x11180038
57#define smnPCIE_RX_NUM_NAK_GENERATED			0x1118003c
58
59// addressBlock: nbio_iohub_nb_misc_misc_cfgdec
60// base address: 0x13a10000
61#define smnIOHC_INTERRUPT_EOI				0x13a10120
62
63// addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec
64// base address: 0x13a20000
65#define smnRAS_GLOBAL_STATUS_LO				0x13a20020
66#define smnRAS_GLOBAL_STATUS_HI				0x13a20024
67
68#endif	// _nbio_7_4_0_SMN_HEADER