nbio_7_0_smn.h

 1/*
 2 * Copyright (C) 2019  Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22#ifndef _nbio_7_0_SMN_HEADER
23#define _nbio_7_0_SMN_HEADER
24
25
26#define smnCPM_CONTROL					0x11180460
27#define smnPCIE_CNTL2					0x11180070
28
29#define smnPCIE_PERF_COUNT_CNTL				0x11180200
30#define smnPCIE_PERF_CNTL_TXCLK				0x11180204
31#define smnPCIE_PERF_COUNT0_TXCLK			0x11180208
32#define smnPCIE_PERF_COUNT1_TXCLK			0x1118020c
33#define smnPCIE_PERF_CNTL_MST_R_CLK			0x11180210
34#define smnPCIE_PERF_COUNT0_MST_R_CLK			0x11180214
35#define smnPCIE_PERF_COUNT1_MST_R_CLK			0x11180218
36#define smnPCIE_PERF_CNTL_MST_C_CLK			0x1118021c
37#define smnPCIE_PERF_COUNT0_MST_C_CLK			0x11180220
38#define smnPCIE_PERF_COUNT1_MST_C_CLK			0x11180224
39#define smnPCIE_PERF_CNTL_SLV_R_CLK			0x11180228
40#define smnPCIE_PERF_COUNT0_SLV_R_CLK			0x1118022c
41#define smnPCIE_PERF_COUNT1_SLV_R_CLK			0x11180230
42#define smnPCIE_PERF_CNTL_SLV_S_C_CLK			0x11180234
43#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK			0x11180238
44#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK			0x1118023c
45#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK			0x11180240
46#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK		0x11180244
47#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK		0x11180248
48#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL		0x1118024c
49#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL		0x11180250
50#define smnPCIE_PERF_CNTL_TXCLK2			0x11180254
51#define smnPCIE_PERF_COUNT0_TXCLK2			0x11180258
52#define smnPCIE_PERF_COUNT1_TXCLK2			0x1118025c
53#define smnPCIE_PERF_CNTL_TXCLK3                        0x1118021c
54#define smnPCIE_PERF_COUNT0_TXCLK3                      0x11180220
55#define smnPCIE_PERF_COUNT1_TXCLK3                      0x11180224
56#define smnPCIE_PERF_CNTL_TXCLK4                        0x11180228
57#define smnPCIE_PERF_COUNT0_TXCLK4                      0x1118022c
58#define smnPCIE_PERF_COUNT1_TXCLK4                      0x11180230
59
60#define smnPCIE_RX_NUM_NAK				0x11180038
61#define smnPCIE_RX_NUM_NAK_GENERATED			0x1118003c
62
63#endif	// _nbio_7_0_SMN_HEADER