FILE
mmhub_4_1_0_offset.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_1_0_offset.h
1/* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _mmhub_4_1_0_OFFSET_HEADER 24#define _mmhub_4_1_0_OFFSET_HEADER 25 26 27 28// addressBlock: mmhub_dagb_dagbdec 29// base address: 0x68000 30#define regDAGB0_RDCLI0 0x0000 31#define regDAGB0_RDCLI0_BASE_IDX 0 32#define regDAGB0_RDCLI1 0x0001 33#define regDAGB0_RDCLI1_BASE_IDX 0 34#define regDAGB0_RDCLI2 0x0002 35#define regDAGB0_RDCLI2_BASE_IDX 0 36#define regDAGB0_RDCLI3 0x0003 37#define regDAGB0_RDCLI3_BASE_IDX 0 38#define regDAGB0_RDCLI4 0x0004 39#define regDAGB0_RDCLI4_BASE_IDX 0 40#define regDAGB0_RDCLI5 0x0005 41#define regDAGB0_RDCLI5_BASE_IDX 0 42#define regDAGB0_RDCLI6 0x0006 43#define regDAGB0_RDCLI6_BASE_IDX 0 44#define regDAGB0_RDCLI7 0x0007 45#define regDAGB0_RDCLI7_BASE_IDX 0 46#define regDAGB0_RDCLI8 0x0008 47#define regDAGB0_RDCLI8_BASE_IDX 0 48#define regDAGB0_RDCLI9 0x0009 49#define regDAGB0_RDCLI9_BASE_IDX 0 50#define regDAGB0_RDCLI10 0x000a 51#define regDAGB0_RDCLI10_BASE_IDX 0 52#define regDAGB0_RDCLI11 0x000b 53#define regDAGB0_RDCLI11_BASE_IDX 0 54#define regDAGB0_RDCLI12 0x000c 55#define regDAGB0_RDCLI12_BASE_IDX 0 56#define regDAGB0_RDCLI13 0x000d 57#define regDAGB0_RDCLI13_BASE_IDX 0 58#define regDAGB0_RDCLI14 0x000e 59#define regDAGB0_RDCLI14_BASE_IDX 0 60#define regDAGB0_RDCLI15 0x000f 61#define regDAGB0_RDCLI15_BASE_IDX 0 62#define regDAGB0_RDCLI16 0x0010 63#define regDAGB0_RDCLI16_BASE_IDX 0 64#define regDAGB0_RDCLI17 0x0011 65#define regDAGB0_RDCLI17_BASE_IDX 0 66#define regDAGB0_RDCLI18 0x0012 67#define regDAGB0_RDCLI18_BASE_IDX 0 68#define regDAGB0_RDCLI19 0x0013 69#define regDAGB0_RDCLI19_BASE_IDX 0 70#define regDAGB0_RDCLI20 0x0014 71#define regDAGB0_RDCLI20_BASE_IDX 0 72#define regDAGB0_RDCLI21 0x0015 73#define regDAGB0_RDCLI21_BASE_IDX 0 74#define regDAGB0_RDCLI22 0x0016 75#define regDAGB0_RDCLI22_BASE_IDX 0 76#define regDAGB0_RDCLI23 0x0017 77#define regDAGB0_RDCLI23_BASE_IDX 0 78#define regDAGB0_RD_CNTL 0x001a 79#define regDAGB0_RD_CNTL_BASE_IDX 0 80#define regDAGB0_RD_IO_CNTL 0x001b 81#define regDAGB0_RD_IO_CNTL_BASE_IDX 0 82#define regDAGB0_RD_GMI_CNTL 0x001c 83#define regDAGB0_RD_GMI_CNTL_BASE_IDX 0 84#define regDAGB0_RD_ADDR_DAGB 0x001d 85#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0 86#define regDAGB0_RD_CGTT_CLK_CTRL 0x001e 87#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 88#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x001f 89#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 90#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0020 91#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 92#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0021 93#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 94#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0022 95#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 96#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x0023 97#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 98#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x0024 99#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 100#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0025 101#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 102#define regDAGB0_RD_VC0_CNTL 0x0026 103#define regDAGB0_RD_VC0_CNTL_BASE_IDX 0 104#define regDAGB0_RD_VC1_CNTL 0x0027 105#define regDAGB0_RD_VC1_CNTL_BASE_IDX 0 106#define regDAGB0_RD_VC2_CNTL 0x0028 107#define regDAGB0_RD_VC2_CNTL_BASE_IDX 0 108#define regDAGB0_RD_VC3_CNTL 0x0029 109#define regDAGB0_RD_VC3_CNTL_BASE_IDX 0 110#define regDAGB0_RD_VC4_CNTL 0x002a 111#define regDAGB0_RD_VC4_CNTL_BASE_IDX 0 112#define regDAGB0_RD_VC5_CNTL 0x002b 113#define regDAGB0_RD_VC5_CNTL_BASE_IDX 0 114#define regDAGB0_RD_IO_VC_CNTL 0x002c 115#define regDAGB0_RD_IO_VC_CNTL_BASE_IDX 0 116#define regDAGB0_RD_GMI_VC_CNTL 0x002d 117#define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX 0 118#define regDAGB0_RD_CNTL_MISC 0x002e 119#define regDAGB0_RD_CNTL_MISC_BASE_IDX 0 120#define regDAGB0_RD_TLB_CREDIT 0x002f 121#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0 122#define regDAGB0_RDCLI_ASK_PENDING 0x0030 123#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 124#define regDAGB0_RDCLI_GO_PENDING 0x0031 125#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 126#define regDAGB0_RDCLI_GBLSEND_PENDING 0x0032 127#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 128#define regDAGB0_RDCLI_TLB_PENDING 0x0033 129#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 130#define regDAGB0_RDCLI_OARB_PENDING 0x0034 131#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 132#define regDAGB0_RDCLI_ASK2ARB_PENDING 0x0035 133#define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX 0 134#define regDAGB0_RDCLI_ASK2DF_PENDING 0x0036 135#define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX 0 136#define regDAGB0_RDCLI_OSD_PENDING 0x0037 137#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 138#define regDAGB0_RDCLI_ASK_OSD_PENDING 0x0038 139#define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX 0 140#define regDAGB0_WRCLI0 0x0039 141#define regDAGB0_WRCLI0_BASE_IDX 0 142#define regDAGB0_WRCLI1 0x003a 143#define regDAGB0_WRCLI1_BASE_IDX 0 144#define regDAGB0_WRCLI2 0x003b 145#define regDAGB0_WRCLI2_BASE_IDX 0 146#define regDAGB0_WRCLI3 0x003c 147#define regDAGB0_WRCLI3_BASE_IDX 0 148#define regDAGB0_WRCLI4 0x003d 149#define regDAGB0_WRCLI4_BASE_IDX 0 150#define regDAGB0_WRCLI5 0x003e 151#define regDAGB0_WRCLI5_BASE_IDX 0 152#define regDAGB0_WRCLI6 0x003f 153#define regDAGB0_WRCLI6_BASE_IDX 0 154#define regDAGB0_WRCLI7 0x0040 155#define regDAGB0_WRCLI7_BASE_IDX 0 156#define regDAGB0_WRCLI8 0x0041 157#define regDAGB0_WRCLI8_BASE_IDX 0 158#define regDAGB0_WRCLI9 0x0042 159#define regDAGB0_WRCLI9_BASE_IDX 0 160#define regDAGB0_WRCLI10 0x0043 161#define regDAGB0_WRCLI10_BASE_IDX 0 162#define regDAGB0_WRCLI11 0x0044 163#define regDAGB0_WRCLI11_BASE_IDX 0 164#define regDAGB0_WRCLI12 0x0045 165#define regDAGB0_WRCLI12_BASE_IDX 0 166#define regDAGB0_WRCLI13 0x0046 167#define regDAGB0_WRCLI13_BASE_IDX 0 168#define regDAGB0_WRCLI14 0x0047 169#define regDAGB0_WRCLI14_BASE_IDX 0 170#define regDAGB0_WRCLI15 0x0048 171#define regDAGB0_WRCLI15_BASE_IDX 0 172#define regDAGB0_WRCLI16 0x0049 173#define regDAGB0_WRCLI16_BASE_IDX 0 174#define regDAGB0_WRCLI17 0x004a 175#define regDAGB0_WRCLI17_BASE_IDX 0 176#define regDAGB0_WRCLI18 0x004b 177#define regDAGB0_WRCLI18_BASE_IDX 0 178#define regDAGB0_WRCLI19 0x004c 179#define regDAGB0_WRCLI19_BASE_IDX 0 180#define regDAGB0_WRCLI20 0x004d 181#define regDAGB0_WRCLI20_BASE_IDX 0 182#define regDAGB0_WRCLI21 0x004e 183#define regDAGB0_WRCLI21_BASE_IDX 0 184#define regDAGB0_WRCLI22 0x004f 185#define regDAGB0_WRCLI22_BASE_IDX 0 186#define regDAGB0_WRCLI23 0x0050 187#define regDAGB0_WRCLI23_BASE_IDX 0 188#define regDAGB0_WR_CNTL 0x0071 189#define regDAGB0_WR_CNTL_BASE_IDX 0 190#define regDAGB0_WR_IO_CNTL 0x0072 191#define regDAGB0_WR_IO_CNTL_BASE_IDX 0 192#define regDAGB0_WR_GMI_CNTL 0x0073 193#define regDAGB0_WR_GMI_CNTL_BASE_IDX 0 194#define regDAGB0_WR_ADDR_DAGB 0x0074 195#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0 196#define regDAGB0_WR_CGTT_CLK_CTRL 0x0075 197#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 198#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0076 199#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 200#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0077 201#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 202#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0078 203#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 204#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0079 205#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 206#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x007a 207#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 208#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x007b 209#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 210#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x007c 211#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 212#define regDAGB0_WR_DATA_DAGB 0x007d 213#define regDAGB0_WR_DATA_DAGB_BASE_IDX 0 214#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x007e 215#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 216#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x007f 217#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 218#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0080 219#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 220#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0081 221#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 222#define regDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0082 223#define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 0 224#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0083 225#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 0 226#define regDAGB0_WR_VC0_CNTL 0x0084 227#define regDAGB0_WR_VC0_CNTL_BASE_IDX 0 228#define regDAGB0_WR_VC1_CNTL 0x0085 229#define regDAGB0_WR_VC1_CNTL_BASE_IDX 0 230#define regDAGB0_WR_VC2_CNTL 0x0086 231#define regDAGB0_WR_VC2_CNTL_BASE_IDX 0 232#define regDAGB0_WR_VC3_CNTL 0x0087 233#define regDAGB0_WR_VC3_CNTL_BASE_IDX 0 234#define regDAGB0_WR_VC4_CNTL 0x0088 235#define regDAGB0_WR_VC4_CNTL_BASE_IDX 0 236#define regDAGB0_WR_VC5_CNTL 0x0089 237#define regDAGB0_WR_VC5_CNTL_BASE_IDX 0 238#define regDAGB0_WR_IO_VC_CNTL 0x008a 239#define regDAGB0_WR_IO_VC_CNTL_BASE_IDX 0 240#define regDAGB0_WR_GMI_VC_CNTL 0x008b 241#define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX 0 242#define regDAGB0_WR_CNTL_MISC 0x008c 243#define regDAGB0_WR_CNTL_MISC_BASE_IDX 0 244#define regDAGB0_WR_TLB_CREDIT 0x008d 245#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0 246#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x008e 247#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 0 248#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x008f 249#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 250#define regDAGB0_WRCLI_ASK_PENDING 0x0090 251#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 252#define regDAGB0_WRCLI_GO_PENDING 0x0091 253#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 254#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0092 255#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 256#define regDAGB0_WRCLI_TLB_PENDING 0x0093 257#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 258#define regDAGB0_WRCLI_OARB_PENDING 0x0094 259#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 260#define regDAGB0_WRCLI_ASK2ARB_PENDING 0x0095 261#define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX 0 262#define regDAGB0_WRCLI_ASK2DF_PENDING 0x0096 263#define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX 0 264#define regDAGB0_WRCLI_OSD_PENDING 0x0097 265#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 266#define regDAGB0_WRCLI_ASK_OSD_PENDING 0x0098 267#define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX 0 268#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x0099 269#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 270#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x009a 271#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 272#define regDAGB0_SDP_ERR_STATUS 0x009d 273#define regDAGB0_SDP_ERR_STATUS_BASE_IDX 0 274#define regDAGB0_DAGB_DLY 0x009f 275#define regDAGB0_DAGB_DLY_BASE_IDX 0 276#define regDAGB0_CNTL_MISC 0x00a0 277#define regDAGB0_CNTL_MISC_BASE_IDX 0 278#define regDAGB0_CNTL_MISC2 0x00a1 279#define regDAGB0_CNTL_MISC2_BASE_IDX 0 280#define regDAGB0_FIFO_EMPTY 0x00a2 281#define regDAGB0_FIFO_EMPTY_BASE_IDX 0 282#define regDAGB0_FIFO_FULL 0x00a3 283#define regDAGB0_FIFO_FULL_BASE_IDX 0 284#define regDAGB0_RD_CREDITS_FULL 0x00a4 285#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0 286#define regDAGB0_WR_CREDITS_FULL 0x00a5 287#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0 288#define regDAGB0_PERFCOUNTER_LO 0x00a6 289#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0 290#define regDAGB0_PERFCOUNTER_HI 0x00a7 291#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0 292#define regDAGB0_PERFCOUNTER0_CFG 0x00a8 293#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 294#define regDAGB0_PERFCOUNTER1_CFG 0x00a9 295#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 296#define regDAGB0_PERFCOUNTER2_CFG 0x00aa 297#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 298#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x00ab 299#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 300#define regDAGB0_L1TLB_REG_RW 0x00ac 301#define regDAGB0_L1TLB_REG_RW_BASE_IDX 0 302#define regDAGB0_RESERVE0 0x00ad 303#define regDAGB0_RESERVE0_BASE_IDX 0 304#define regDAGB0_RESERVE1 0x00ae 305#define regDAGB0_RESERVE1_BASE_IDX 0 306#define regDAGB0_RESERVE2 0x00af 307#define regDAGB0_RESERVE2_BASE_IDX 0 308#define regDAGB0_RESERVE3 0x00b0 309#define regDAGB0_RESERVE3_BASE_IDX 0 310#define regDAGB0_SDP_RD_BW_CNTL 0x00b1 311#define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX 0 312#define regDAGB0_SDP_PRIORITY_OVERRIDE 0x00b3 313#define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX 0 314#define regDAGB0_SDP_RD_PRIORITY 0x00b4 315#define regDAGB0_SDP_RD_PRIORITY_BASE_IDX 0 316#define regDAGB0_SDP_WR_PRIORITY 0x00b5 317#define regDAGB0_SDP_WR_PRIORITY_BASE_IDX 0 318#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP 0x00b6 319#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 0 320#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP 0x00b7 321#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX 0 322#define regDAGB0_SDP_ENABLE 0x00b8 323#define regDAGB0_SDP_ENABLE_BASE_IDX 0 324#define regDAGB0_SDP_CREDITS 0x00b9 325#define regDAGB0_SDP_CREDITS_BASE_IDX 0 326#define regDAGB0_SDP_TAG_RESERVE0 0x00ba 327#define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX 0 328#define regDAGB0_SDP_TAG_RESERVE1 0x00bb 329#define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX 0 330#define regDAGB0_SDP_VCC_RESERVE0 0x00bc 331#define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX 0 332#define regDAGB0_SDP_VCC_RESERVE1 0x00bd 333#define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX 0 334#define regDAGB0_SDP_REQ_CNTL 0x00be 335#define regDAGB0_SDP_REQ_CNTL_BASE_IDX 0 336#define regDAGB0_SDP_MISC_AON 0x00bf 337#define regDAGB0_SDP_MISC_AON_BASE_IDX 0 338#define regDAGB0_SDP_MISC 0x00c0 339#define regDAGB0_SDP_MISC_BASE_IDX 0 340#define regDAGB0_SDP_MISC2 0x00c1 341#define regDAGB0_SDP_MISC2_BASE_IDX 0 342#define regDAGB0_SDP_VCD_RESERVE0 0x00c2 343#define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX 0 344#define regDAGB0_SDP_VCD_RESERVE1 0x00c3 345#define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX 0 346#define regDAGB0_SDP_ARB_CNTL0 0x00c4 347#define regDAGB0_SDP_ARB_CNTL0_BASE_IDX 0 348#define regDAGB0_SDP_ARB_CNTL1 0x00c5 349#define regDAGB0_SDP_ARB_CNTL1_BASE_IDX 0 350#define regDAGB0_FATAL_ERROR_CLEAR 0x00c8 351#define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0 352#define regDAGB0_FATAL_ERROR_STATUS0 0x00c9 353#define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0 354#define regDAGB0_FATAL_ERROR_STATUS1 0x00ca 355#define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0 356#define regDAGB0_FATAL_ERROR_STATUS2 0x00cb 357#define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0 358#define regDAGB0_FATAL_ERROR_STATUS3 0x00cc 359#define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0 360#define regDAGB0_FATAL_ERROR_STATUS4 0x00cd 361#define regDAGB0_FATAL_ERROR_STATUS4_BASE_IDX 0 362#define regDAGB0_SDP_CGTT_CLK_CTRL 0x00ce 363#define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX 0 364#define regDAGB0_SDP_LATENCY_SAMPLING 0x00cf 365#define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX 0 366#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x00d4 367#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 368#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x00d9 369#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 370#define regDAGB1_RDCLI0 0x0200 371#define regDAGB1_RDCLI0_BASE_IDX 0 372#define regDAGB1_RDCLI1 0x0201 373#define regDAGB1_RDCLI1_BASE_IDX 0 374#define regDAGB1_RDCLI2 0x0202 375#define regDAGB1_RDCLI2_BASE_IDX 0 376#define regDAGB1_RDCLI3 0x0203 377#define regDAGB1_RDCLI3_BASE_IDX 0 378#define regDAGB1_RDCLI4 0x0204 379#define regDAGB1_RDCLI4_BASE_IDX 0 380#define regDAGB1_RDCLI5 0x0205 381#define regDAGB1_RDCLI5_BASE_IDX 0 382#define regDAGB1_RDCLI6 0x0206 383#define regDAGB1_RDCLI6_BASE_IDX 0 384#define regDAGB1_RDCLI7 0x0207 385#define regDAGB1_RDCLI7_BASE_IDX 0 386#define regDAGB1_RDCLI8 0x0208 387#define regDAGB1_RDCLI8_BASE_IDX 0 388#define regDAGB1_RDCLI9 0x0209 389#define regDAGB1_RDCLI9_BASE_IDX 0 390#define regDAGB1_RDCLI10 0x020a 391#define regDAGB1_RDCLI10_BASE_IDX 0 392#define regDAGB1_RDCLI11 0x020b 393#define regDAGB1_RDCLI11_BASE_IDX 0 394#define regDAGB1_RDCLI12 0x020c 395#define regDAGB1_RDCLI12_BASE_IDX 0 396#define regDAGB1_RDCLI13 0x020d 397#define regDAGB1_RDCLI13_BASE_IDX 0 398#define regDAGB1_RDCLI14 0x020e 399#define regDAGB1_RDCLI14_BASE_IDX 0 400#define regDAGB1_RDCLI15 0x020f 401#define regDAGB1_RDCLI15_BASE_IDX 0 402#define regDAGB1_RDCLI16 0x0210 403#define regDAGB1_RDCLI16_BASE_IDX 0 404#define regDAGB1_RDCLI17 0x0211 405#define regDAGB1_RDCLI17_BASE_IDX 0 406#define regDAGB1_RDCLI18 0x0212 407#define regDAGB1_RDCLI18_BASE_IDX 0 408#define regDAGB1_RDCLI19 0x0213 409#define regDAGB1_RDCLI19_BASE_IDX 0 410#define regDAGB1_RDCLI20 0x0214 411#define regDAGB1_RDCLI20_BASE_IDX 0 412#define regDAGB1_RDCLI21 0x0215 413#define regDAGB1_RDCLI21_BASE_IDX 0 414#define regDAGB1_RDCLI22 0x0216 415#define regDAGB1_RDCLI22_BASE_IDX 0 416#define regDAGB1_RDCLI23 0x0217 417#define regDAGB1_RDCLI23_BASE_IDX 0 418#define regDAGB1_RD_CNTL 0x021a 419#define regDAGB1_RD_CNTL_BASE_IDX 0 420#define regDAGB1_RD_IO_CNTL 0x021b 421#define regDAGB1_RD_IO_CNTL_BASE_IDX 0 422#define regDAGB1_RD_GMI_CNTL 0x021c 423#define regDAGB1_RD_GMI_CNTL_BASE_IDX 0 424#define regDAGB1_RD_ADDR_DAGB 0x021d 425#define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0 426#define regDAGB1_RD_CGTT_CLK_CTRL 0x021e 427#define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0 428#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x021f 429#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 430#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0220 431#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 432#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0221 433#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 434#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x0222 435#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 436#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x0223 437#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 438#define regDAGB1_RD_ADDR_DAGB_MAX_BURST2 0x0224 439#define regDAGB1_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 440#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2 0x0225 441#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 442#define regDAGB1_RD_VC0_CNTL 0x0226 443#define regDAGB1_RD_VC0_CNTL_BASE_IDX 0 444#define regDAGB1_RD_VC1_CNTL 0x0227 445#define regDAGB1_RD_VC1_CNTL_BASE_IDX 0 446#define regDAGB1_RD_VC2_CNTL 0x0228 447#define regDAGB1_RD_VC2_CNTL_BASE_IDX 0 448#define regDAGB1_RD_VC3_CNTL 0x0229 449#define regDAGB1_RD_VC3_CNTL_BASE_IDX 0 450#define regDAGB1_RD_VC4_CNTL 0x022a 451#define regDAGB1_RD_VC4_CNTL_BASE_IDX 0 452#define regDAGB1_RD_VC5_CNTL 0x022b 453#define regDAGB1_RD_VC5_CNTL_BASE_IDX 0 454#define regDAGB1_RD_IO_VC_CNTL 0x022c 455#define regDAGB1_RD_IO_VC_CNTL_BASE_IDX 0 456#define regDAGB1_RD_GMI_VC_CNTL 0x022d 457#define regDAGB1_RD_GMI_VC_CNTL_BASE_IDX 0 458#define regDAGB1_RD_CNTL_MISC 0x022e 459#define regDAGB1_RD_CNTL_MISC_BASE_IDX 0 460#define regDAGB1_RD_TLB_CREDIT 0x022f 461#define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0 462#define regDAGB1_RDCLI_ASK_PENDING 0x0230 463#define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0 464#define regDAGB1_RDCLI_GO_PENDING 0x0231 465#define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0 466#define regDAGB1_RDCLI_GBLSEND_PENDING 0x0232 467#define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0 468#define regDAGB1_RDCLI_TLB_PENDING 0x0233 469#define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0 470#define regDAGB1_RDCLI_OARB_PENDING 0x0234 471#define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0 472#define regDAGB1_RDCLI_ASK2ARB_PENDING 0x0235 473#define regDAGB1_RDCLI_ASK2ARB_PENDING_BASE_IDX 0 474#define regDAGB1_RDCLI_ASK2DF_PENDING 0x0236 475#define regDAGB1_RDCLI_ASK2DF_PENDING_BASE_IDX 0 476#define regDAGB1_RDCLI_OSD_PENDING 0x0237 477#define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0 478#define regDAGB1_RDCLI_ASK_OSD_PENDING 0x0238 479#define regDAGB1_RDCLI_ASK_OSD_PENDING_BASE_IDX 0 480#define regDAGB1_SDP_ERR_STATUS 0x023b 481#define regDAGB1_SDP_ERR_STATUS_BASE_IDX 0 482#define regDAGB1_DAGB_DLY 0x023c 483#define regDAGB1_DAGB_DLY_BASE_IDX 0 484#define regDAGB1_CNTL_MISC 0x023d 485#define regDAGB1_CNTL_MISC_BASE_IDX 0 486#define regDAGB1_CNTL_MISC2 0x023e 487#define regDAGB1_CNTL_MISC2_BASE_IDX 0 488#define regDAGB1_FIFO_EMPTY 0x023f 489#define regDAGB1_FIFO_EMPTY_BASE_IDX 0 490#define regDAGB1_FIFO_FULL 0x0240 491#define regDAGB1_FIFO_FULL_BASE_IDX 0 492#define regDAGB1_RD_CREDITS_FULL 0x0241 493#define regDAGB1_RD_CREDITS_FULL_BASE_IDX 0 494#define regDAGB1_PERFCOUNTER_LO 0x0242 495#define regDAGB1_PERFCOUNTER_LO_BASE_IDX 0 496#define regDAGB1_PERFCOUNTER_HI 0x0243 497#define regDAGB1_PERFCOUNTER_HI_BASE_IDX 0 498#define regDAGB1_PERFCOUNTER0_CFG 0x0244 499#define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0 500#define regDAGB1_PERFCOUNTER1_CFG 0x0245 501#define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0 502#define regDAGB1_PERFCOUNTER2_CFG 0x0246 503#define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0 504#define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x0247 505#define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 506#define regDAGB1_L1TLB_REG_RW 0x0248 507#define regDAGB1_L1TLB_REG_RW_BASE_IDX 0 508#define regDAGB1_RESERVE0 0x0249 509#define regDAGB1_RESERVE0_BASE_IDX 0 510#define regDAGB1_RESERVE1 0x024a 511#define regDAGB1_RESERVE1_BASE_IDX 0 512#define regDAGB1_RESERVE2 0x024b 513#define regDAGB1_RESERVE2_BASE_IDX 0 514#define regDAGB1_RESERVE3 0x024c 515#define regDAGB1_RESERVE3_BASE_IDX 0 516#define regDAGB1_SDP_RD_BW_CNTL 0x024d 517#define regDAGB1_SDP_RD_BW_CNTL_BASE_IDX 0 518#define regDAGB1_SDP_PRIORITY_OVERRIDE 0x024f 519#define regDAGB1_SDP_PRIORITY_OVERRIDE_BASE_IDX 0 520#define regDAGB1_SDP_RD_PRIORITY 0x0250 521#define regDAGB1_SDP_RD_PRIORITY_BASE_IDX 0 522#define regDAGB1_SDP_RD_CLI2SDP_VC_MAP 0x0251 523#define regDAGB1_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 0 524#define regDAGB1_SDP_ENABLE 0x0252 525#define regDAGB1_SDP_ENABLE_BASE_IDX 0 526#define regDAGB1_SDP_CREDITS 0x0253 527#define regDAGB1_SDP_CREDITS_BASE_IDX 0 528#define regDAGB1_SDP_TAG_RESERVE0 0x0254 529#define regDAGB1_SDP_TAG_RESERVE0_BASE_IDX 0 530#define regDAGB1_SDP_TAG_RESERVE1 0x0255 531#define regDAGB1_SDP_TAG_RESERVE1_BASE_IDX 0 532#define regDAGB1_SDP_VCC_RESERVE0 0x0256 533#define regDAGB1_SDP_VCC_RESERVE0_BASE_IDX 0 534#define regDAGB1_SDP_VCC_RESERVE1 0x0257 535#define regDAGB1_SDP_VCC_RESERVE1_BASE_IDX 0 536#define regDAGB1_SDP_REQ_CNTL 0x0258 537#define regDAGB1_SDP_REQ_CNTL_BASE_IDX 0 538#define regDAGB1_SDP_MISC_AON 0x0259 539#define regDAGB1_SDP_MISC_AON_BASE_IDX 0 540#define regDAGB1_SDP_MISC 0x025a 541#define regDAGB1_SDP_MISC_BASE_IDX 0 542#define regDAGB1_SDP_MISC2 0x025b 543#define regDAGB1_SDP_MISC2_BASE_IDX 0 544#define regDAGB1_SDP_ARB_CNTL0 0x025c 545#define regDAGB1_SDP_ARB_CNTL0_BASE_IDX 0 546#define regDAGB1_SDP_ARB_CNTL1 0x025d 547#define regDAGB1_SDP_ARB_CNTL1_BASE_IDX 0 548#define regDAGB1_SDP_CGTT_CLK_CTRL 0x025e 549#define regDAGB1_SDP_CGTT_CLK_CTRL_BASE_IDX 0 550#define regDAGB1_SDP_LATENCY_SAMPLING 0x025f 551#define regDAGB1_SDP_LATENCY_SAMPLING_BASE_IDX 0 552 553 554// addressBlock: mmhub_pctldec 555// base address: 0x69000 556#define regPCTL_CTRL 0x0400 557#define regPCTL_CTRL_BASE_IDX 0 558#define regPCTL_MMHUB_DEEPSLEEP_IB 0x0401 559#define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 0 560#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0402 561#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 562#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0403 563#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 0 564#define regPCTL_PG_IGNORE_DEEPSLEEP 0x0404 565#define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 566#define regPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0405 567#define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 0 568#define regPCTL_UTCL2_MISC 0x0406 569#define regPCTL_UTCL2_MISC_BASE_IDX 0 570#define regPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0407 571#define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 0 572#define regPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0408 573#define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 0 574#define regPCTL_SLICE0_CFG_DS_ALLOW 0x0409 575#define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 0 576#define regPCTL_SLICE0_CFG_DS_ALLOW_IB 0x040a 577#define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 0 578#define regPCTL_SLICE0_MISC 0x040b 579#define regPCTL_SLICE0_MISC_BASE_IDX 0 580#define regPCTL_SLICE1_CFG_DAGB_WRBUSY 0x040c 581#define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 0 582#define regPCTL_SLICE1_CFG_DAGB_RDBUSY 0x040d 583#define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 0 584#define regPCTL_SLICE1_CFG_DS_ALLOW 0x040e 585#define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 0 586#define regPCTL_SLICE1_CFG_DS_ALLOW_IB 0x040f 587#define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 0 588#define regPCTL_SLICE1_MISC 0x0410 589#define regPCTL_SLICE1_MISC_BASE_IDX 0 590#define regPCTL_RENG_CTRL 0x0416 591#define regPCTL_RENG_CTRL_BASE_IDX 0 592#define regPCTL_UTCL2_RENG_EXECUTE 0x0417 593#define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 0 594#define regPCTL_UTCL2_RENG_RAM_INDEX 0x0418 595#define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 0 596#define regPCTL_UTCL2_RENG_RAM_DATA 0x0419 597#define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 0 598#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x041a 599#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 600#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x041b 601#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 602#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x041c 603#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 604#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x041d 605#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 606#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x041e 607#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 608#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x041f 609#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 610#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0420 611#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 612#define regPCTL_SLICE0_RENG_EXECUTE 0x0421 613#define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 0 614#define regPCTL_SLICE0_RENG_RAM_INDEX 0x0422 615#define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 0 616#define regPCTL_SLICE0_RENG_RAM_DATA 0x0423 617#define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 0 618#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x0424 619#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 620#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x0425 621#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 622#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x0426 623#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 624#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x0427 625#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 626#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x0428 627#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 628#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0429 629#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 630#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x042a 631#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 632#define regPCTL_SLICE1_RENG_EXECUTE 0x042b 633#define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 0 634#define regPCTL_SLICE1_RENG_RAM_INDEX 0x042c 635#define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 0 636#define regPCTL_SLICE1_RENG_RAM_DATA 0x042d 637#define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 0 638#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x042e 639#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 640#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x042f 641#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 642#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x0430 643#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 644#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x0431 645#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 646#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x0432 647#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 648#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0433 649#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 650#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0434 651#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 652#define regPCTL_STATUS 0x043f 653#define regPCTL_STATUS_BASE_IDX 0 654#define regPCTL_PERFCOUNTER_LO 0x0440 655#define regPCTL_PERFCOUNTER_LO_BASE_IDX 0 656#define regPCTL_PERFCOUNTER_HI 0x0441 657#define regPCTL_PERFCOUNTER_HI_BASE_IDX 0 658#define regPCTL_PERFCOUNTER0_CFG 0x0442 659#define regPCTL_PERFCOUNTER0_CFG_BASE_IDX 0 660#define regPCTL_PERFCOUNTER1_CFG 0x0443 661#define regPCTL_PERFCOUNTER1_CFG_BASE_IDX 0 662#define regPCTL_PERFCOUNTER_RSLT_CNTL 0x0444 663#define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 664#define regPCTL_RESERVED_0 0x0445 665#define regPCTL_RESERVED_0_BASE_IDX 0 666#define regPCTL_RESERVED_1 0x0446 667#define regPCTL_RESERVED_1_BASE_IDX 0 668#define regPCTL_RESERVED_2 0x0447 669#define regPCTL_RESERVED_2_BASE_IDX 0 670#define regPCTL_RESERVED_3 0x0448 671#define regPCTL_RESERVED_3_BASE_IDX 0 672 673 674// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 675// base address: 0x69300 676#define regMMMC_VM_NB_MMIOBASE 0x04c0 677#define regMMMC_VM_NB_MMIOBASE_BASE_IDX 0 678#define regMMMC_VM_NB_MMIOLIMIT 0x04c1 679#define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX 0 680#define regMMMC_VM_NB_PCI_CTRL 0x04c2 681#define regMMMC_VM_NB_PCI_CTRL_BASE_IDX 0 682#define regMMMC_VM_NB_PCI_ARB 0x04c3 683#define regMMMC_VM_NB_PCI_ARB_BASE_IDX 0 684#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x04c4 685#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 686#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x04c5 687#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 688#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x04c6 689#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 690#define regMMMC_VM_FB_OFFSET 0x04c7 691#define regMMMC_VM_FB_OFFSET_BASE_IDX 0 692#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x04c8 693#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 694#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x04c9 695#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 696#define regMMMC_VM_STEERING 0x04ca 697#define regMMMC_VM_STEERING_BASE_IDX 0 698#define regMMMC_SHARED_VIRT_RESET_REQ 0x04cb 699#define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 700#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x04cc 701#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 702#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x04cd 703#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 704#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x04ce 705#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 0 706#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x04cf 707#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 0 708#define regMMMC_VM_APT_CNTL 0x04d0 709#define regMMMC_VM_APT_CNTL_BASE_IDX 0 710#define regMMMC_VM_LOCAL_FB_ADDRESS_START 0x04d1 711#define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 0 712#define regMMMC_VM_LOCAL_FB_ADDRESS_END 0x04d2 713#define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 0 714#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x04d3 715#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 0 716#define regMMUTCL2_CGTT_CLK_CTRL 0x04d4 717#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 718#define regMMMC_SHARED_ACTIVE_FCN_ID 0x04d5 719#define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 720#define regMMUTCL2_CGTT_BUSY_CTRL 0x04d6 721#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 0 722#define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x04d7 723#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 0 724#define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x04d9 725#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 0 726 727 728// addressBlock: mmhub_mmutcl2_mmvml2pfdec 729// base address: 0x69390 730#define regMMVM_L2_CNTL 0x04e4 731#define regMMVM_L2_CNTL_BASE_IDX 0 732#define regMMVM_L2_CNTL2 0x04e5 733#define regMMVM_L2_CNTL2_BASE_IDX 0 734#define regMMVM_L2_CNTL3 0x04e6 735#define regMMVM_L2_CNTL3_BASE_IDX 0 736#define regMMVM_L2_STATUS 0x04e7 737#define regMMVM_L2_STATUS_BASE_IDX 0 738#define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x04e8 739#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 740#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x04e9 741#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 742#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x04ea 743#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 744#define regMMVM_INVALIDATE_CNTL 0x04eb 745#define regMMVM_INVALIDATE_CNTL_BASE_IDX 0 746#define regMMVM_L2_PROTECTION_FAULT_CNTL 0x04ec 747#define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 748#define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x04ed 749#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 750#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x04ee 751#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 752#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x04ef 753#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 754#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32 0x04f0 755#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32_BASE_IDX 0 756#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32 0x04f1 757#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32_BASE_IDX 0 758#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x04f2 759#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 760#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x04f3 761#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 762#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x04f4 763#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 764#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x04f5 765#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 766#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x04f7 767#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 768#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x04f8 769#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 770#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x04f9 771#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 772#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x04fa 773#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 774#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x04fb 775#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 776#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x04fc 777#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 778#define regMMVM_L2_CNTL4 0x04fd 779#define regMMVM_L2_CNTL4_BASE_IDX 0 780#define regMMVM_L2_MM_GROUP_RT_CLASSES 0x04fe 781#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 782#define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x04ff 783#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 784#define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x0500 785#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 786#define regMMVM_L2_CACHE_PARITY_CNTL 0x0501 787#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 788#define regMMVM_L2_CGTT_CLK_CTRL 0x0502 789#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 790#define regMMVM_L2_CNTL5 0x0503 791#define regMMVM_L2_CNTL5_BASE_IDX 0 792#define regMMVM_L2_GCR_CNTL 0x0504 793#define regMMVM_L2_GCR_CNTL_BASE_IDX 0 794#define regMMVM_L2_CGTT_BUSY_CTRL 0x0505 795#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 796#define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0506 797#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0 798#define regMMVM_L2_PTE_CACHE_DUMP_READ 0x0507 799#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0 800#define regMMVM_L2_BANK_SELECT_MASKS 0x0510 801#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 0 802#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0511 803#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 0 804#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0512 805#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 0 806#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x0513 807#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 0 808#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x0514 809#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 0 810#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x0515 811#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 812 813 814// addressBlock: mmhub_mmutcl2_mmvml2prdec 815// base address: 0x694d0 816#define regMMMC_VM_L2_PERFCOUNTER_LO 0x0534 817#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 818#define regMMMC_VM_L2_PERFCOUNTER_HI 0x0535 819#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 820#define regMMUTCL2_PERFCOUNTER_LO 0x0536 821#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 0 822#define regMMUTCL2_PERFCOUNTER_HI 0x0537 823#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 0 824 825 826// addressBlock: mmhub_mmutcl2_mmvml2pldec 827// base address: 0x69510 828#define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x0544 829#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 830#define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x0545 831#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 832#define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x0546 833#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 834#define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x0547 835#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 836#define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x0548 837#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 838#define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x0549 839#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 840#define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x054a 841#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 842#define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x054b 843#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 844#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x054c 845#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 846#define regMMUTCL2_PERFCOUNTER0_CFG 0x054d 847#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 0 848#define regMMUTCL2_PERFCOUNTER1_CFG 0x054e 849#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 0 850#define regMMUTCL2_PERFCOUNTER2_CFG 0x054f 851#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 0 852#define regMMUTCL2_PERFCOUNTER3_CFG 0x0550 853#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 0 854#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x0551 855#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 856 857 858// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 859// base address: 0x69550 860#define regMMMC_VM_FB_LOCATION_BASE 0x0554 861#define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 0 862#define regMMMC_VM_FB_LOCATION_TOP 0x0555 863#define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX 0 864#define regMMMC_VM_AGP_TOP 0x0556 865#define regMMMC_VM_AGP_TOP_BASE_IDX 0 866#define regMMMC_VM_AGP_BOT 0x0557 867#define regMMMC_VM_AGP_BOT_BASE_IDX 0 868#define regMMMC_VM_AGP_BASE 0x0558 869#define regMMMC_VM_AGP_BASE_BASE_IDX 0 870#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0559 871#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 872#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x055a 873#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 874#define regMMMC_VM_MX_L1_TLB_CNTL 0x055b 875#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 876 877 878// addressBlock: mmhub_mmutcl2_mmvml2vcdec 879// base address: 0x69590 880#define regMMVM_CONTEXT0_CNTL 0x0564 881#define regMMVM_CONTEXT0_CNTL_BASE_IDX 0 882#define regMMVM_CONTEXT1_CNTL 0x0565 883#define regMMVM_CONTEXT1_CNTL_BASE_IDX 0 884#define regMMVM_CONTEXT2_CNTL 0x0566 885#define regMMVM_CONTEXT2_CNTL_BASE_IDX 0 886#define regMMVM_CONTEXT3_CNTL 0x0567 887#define regMMVM_CONTEXT3_CNTL_BASE_IDX 0 888#define regMMVM_CONTEXT4_CNTL 0x0568 889#define regMMVM_CONTEXT4_CNTL_BASE_IDX 0 890#define regMMVM_CONTEXT5_CNTL 0x0569 891#define regMMVM_CONTEXT5_CNTL_BASE_IDX 0 892#define regMMVM_CONTEXT6_CNTL 0x056a 893#define regMMVM_CONTEXT6_CNTL_BASE_IDX 0 894#define regMMVM_CONTEXT7_CNTL 0x056b 895#define regMMVM_CONTEXT7_CNTL_BASE_IDX 0 896#define regMMVM_CONTEXT8_CNTL 0x056c 897#define regMMVM_CONTEXT8_CNTL_BASE_IDX 0 898#define regMMVM_CONTEXT9_CNTL 0x056d 899#define regMMVM_CONTEXT9_CNTL_BASE_IDX 0 900#define regMMVM_CONTEXT10_CNTL 0x056e 901#define regMMVM_CONTEXT10_CNTL_BASE_IDX 0 902#define regMMVM_CONTEXT11_CNTL 0x056f 903#define regMMVM_CONTEXT11_CNTL_BASE_IDX 0 904#define regMMVM_CONTEXT12_CNTL 0x0570 905#define regMMVM_CONTEXT12_CNTL_BASE_IDX 0 906#define regMMVM_CONTEXT13_CNTL 0x0571 907#define regMMVM_CONTEXT13_CNTL_BASE_IDX 0 908#define regMMVM_CONTEXT14_CNTL 0x0572 909#define regMMVM_CONTEXT14_CNTL_BASE_IDX 0 910#define regMMVM_CONTEXT15_CNTL 0x0573 911#define regMMVM_CONTEXT15_CNTL_BASE_IDX 0 912#define regMMVM_CONTEXTS_DISABLE 0x0574 913#define regMMVM_CONTEXTS_DISABLE_BASE_IDX 0 914#define regMMVM_INVALIDATE_ENG0_SEM 0x0575 915#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 916#define regMMVM_INVALIDATE_ENG1_SEM 0x0576 917#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 918#define regMMVM_INVALIDATE_ENG2_SEM 0x0577 919#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 920#define regMMVM_INVALIDATE_ENG3_SEM 0x0578 921#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 922#define regMMVM_INVALIDATE_ENG4_SEM 0x0579 923#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 924#define regMMVM_INVALIDATE_ENG5_SEM 0x057a 925#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 926#define regMMVM_INVALIDATE_ENG6_SEM 0x057b 927#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 928#define regMMVM_INVALIDATE_ENG7_SEM 0x057c 929#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 930#define regMMVM_INVALIDATE_ENG8_SEM 0x057d 931#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 932#define regMMVM_INVALIDATE_ENG9_SEM 0x057e 933#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 934#define regMMVM_INVALIDATE_ENG10_SEM 0x057f 935#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 936#define regMMVM_INVALIDATE_ENG11_SEM 0x0580 937#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 938#define regMMVM_INVALIDATE_ENG12_SEM 0x0581 939#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 940#define regMMVM_INVALIDATE_ENG13_SEM 0x0582 941#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 942#define regMMVM_INVALIDATE_ENG14_SEM 0x0583 943#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 944#define regMMVM_INVALIDATE_ENG15_SEM 0x0584 945#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 946#define regMMVM_INVALIDATE_ENG16_SEM 0x0585 947#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 948#define regMMVM_INVALIDATE_ENG17_SEM 0x0586 949#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 950#define regMMVM_INVALIDATE_ENG0_REQ 0x0587 951#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 952#define regMMVM_INVALIDATE_ENG1_REQ 0x0588 953#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 954#define regMMVM_INVALIDATE_ENG2_REQ 0x0589 955#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 956#define regMMVM_INVALIDATE_ENG3_REQ 0x058a 957#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 958#define regMMVM_INVALIDATE_ENG4_REQ 0x058b 959#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 960#define regMMVM_INVALIDATE_ENG5_REQ 0x058c 961#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 962#define regMMVM_INVALIDATE_ENG6_REQ 0x058d 963#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 964#define regMMVM_INVALIDATE_ENG7_REQ 0x058e 965#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 966#define regMMVM_INVALIDATE_ENG8_REQ 0x058f 967#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 968#define regMMVM_INVALIDATE_ENG9_REQ 0x0590 969#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 970#define regMMVM_INVALIDATE_ENG10_REQ 0x0591 971#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 972#define regMMVM_INVALIDATE_ENG11_REQ 0x0592 973#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 974#define regMMVM_INVALIDATE_ENG12_REQ 0x0593 975#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 976#define regMMVM_INVALIDATE_ENG13_REQ 0x0594 977#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 978#define regMMVM_INVALIDATE_ENG14_REQ 0x0595 979#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 980#define regMMVM_INVALIDATE_ENG15_REQ 0x0596 981#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 982#define regMMVM_INVALIDATE_ENG16_REQ 0x0597 983#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 984#define regMMVM_INVALIDATE_ENG17_REQ 0x0598 985#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 986#define regMMVM_INVALIDATE_ENG0_ACK 0x0599 987#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 988#define regMMVM_INVALIDATE_ENG1_ACK 0x059a 989#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 990#define regMMVM_INVALIDATE_ENG2_ACK 0x059b 991#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 992#define regMMVM_INVALIDATE_ENG3_ACK 0x059c 993#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 994#define regMMVM_INVALIDATE_ENG4_ACK 0x059d 995#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 996#define regMMVM_INVALIDATE_ENG5_ACK 0x059e 997#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 998#define regMMVM_INVALIDATE_ENG6_ACK 0x059f 999#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 1000#define regMMVM_INVALIDATE_ENG7_ACK 0x05a0 1001#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 1002#define regMMVM_INVALIDATE_ENG8_ACK 0x05a1 1003#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 1004#define regMMVM_INVALIDATE_ENG9_ACK 0x05a2 1005#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 1006#define regMMVM_INVALIDATE_ENG10_ACK 0x05a3 1007#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 1008#define regMMVM_INVALIDATE_ENG11_ACK 0x05a4 1009#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 1010#define regMMVM_INVALIDATE_ENG12_ACK 0x05a5 1011#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 1012#define regMMVM_INVALIDATE_ENG13_ACK 0x05a6 1013#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 1014#define regMMVM_INVALIDATE_ENG14_ACK 0x05a7 1015#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 1016#define regMMVM_INVALIDATE_ENG15_ACK 0x05a8 1017#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 1018#define regMMVM_INVALIDATE_ENG16_ACK 0x05a9 1019#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 1020#define regMMVM_INVALIDATE_ENG17_ACK 0x05aa 1021#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 1022#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x05ab 1023#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 1024#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x05ac 1025#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 1026#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x05ad 1027#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 1028#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x05ae 1029#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 1030#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x05af 1031#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 1032#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x05b0 1033#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 1034#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x05b1 1035#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 1036#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x05b2 1037#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 1038#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x05b3 1039#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 1040#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x05b4 1041#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 1042#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x05b5 1043#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 1044#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x05b6 1045#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 1046#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x05b7 1047#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 1048#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x05b8 1049#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 1050#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x05b9 1051#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 1052#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x05ba 1053#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 1054#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x05bb 1055#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 1056#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x05bc 1057#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 1058#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x05bd 1059#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 1060#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x05be 1061#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 1062#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x05bf 1063#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 1064#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x05c0 1065#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 1066#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x05c1 1067#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 1068#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x05c2 1069#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 1070#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x05c3 1071#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 1072#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x05c4 1073#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 1074#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x05c5 1075#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 1076#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x05c6 1077#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 1078#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x05c7 1079#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 1080#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x05c8 1081#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 1082#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x05c9 1083#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 1084#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x05ca 1085#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 1086#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x05cb 1087#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 1088#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x05cc 1089#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 1090#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x05cd 1091#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 1092#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x05ce 1093#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 1094#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x05cf 1095#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1096#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x05d0 1097#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1098#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x05d1 1099#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1100#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x05d2 1101#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1102#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x05d3 1103#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1104#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x05d4 1105#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1106#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x05d5 1107#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1108#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x05d6 1109#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1110#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x05d7 1111#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1112#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x05d8 1113#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1114#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x05d9 1115#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1116#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x05da 1117#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1118#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x05db 1119#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1120#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x05dc 1121#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1122#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x05dd 1123#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1124#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x05de 1125#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1126#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x05df 1127#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1128#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x05e0 1129#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1130#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x05e1 1131#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1132#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x05e2 1133#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1134#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05e3 1135#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1136#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05e4 1137#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1138#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05e5 1139#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1140#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05e6 1141#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1142#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05e7 1143#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1144#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05e8 1145#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1146#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05e9 1147#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1148#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05ea 1149#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1150#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05eb 1151#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1152#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05ec 1153#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1154#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05ed 1155#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1156#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05ee 1157#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1158#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x05ef 1159#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1160#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x05f0 1161#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1162#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x05f1 1163#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1164#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x05f2 1165#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1166#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x05f3 1167#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1168#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x05f4 1169#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1170#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x05f5 1171#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1172#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x05f6 1173#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1174#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x05f7 1175#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1176#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x05f8 1177#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1178#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x05f9 1179#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1180#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x05fa 1181#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1182#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x05fb 1183#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1184#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x05fc 1185#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1186#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x05fd 1187#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1188#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x05fe 1189#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1190#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x05ff 1191#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1192#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0600 1193#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1194#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0601 1195#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1196#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0602 1197#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1198#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0603 1199#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1200#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0604 1201#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1202#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0605 1203#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1204#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0606 1205#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1206#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0607 1207#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1208#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0608 1209#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1210#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0609 1211#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1212#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x060a 1213#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1214#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x060b 1215#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1216#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x060c 1217#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1218#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x060d 1219#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1220#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x060e 1221#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1222#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x060f 1223#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1224#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0610 1225#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1226#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0611 1227#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1228#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0612 1229#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1230#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0613 1231#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1232#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0614 1233#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1234#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0615 1235#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1236#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0616 1237#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1238#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0617 1239#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1240#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0618 1241#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1242#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0619 1243#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1244#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x061a 1245#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1246#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x061b 1247#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1248#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x061c 1249#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1250#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x061d 1251#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1252#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x061e 1253#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1254#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x061f 1255#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1256#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0620 1257#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1258#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0621 1259#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1260#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0622 1261#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1262#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0623 1263#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1264#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0624 1265#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1266#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0625 1267#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1268#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0626 1269#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1270#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0627 1271#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1272#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0628 1273#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1274#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0629 1275#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1276#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x062a 1277#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1278#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x062b 1279#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1280#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x062c 1281#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1282#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x062d 1283#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1284#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x062e 1285#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1286#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x062f 1287#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1288#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0630 1289#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1290#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0631 1291#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1292#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0632 1293#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1294#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0633 1295#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1296#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0634 1297#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1298#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0635 1299#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1300#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0636 1301#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1302#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0637 1303#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1304#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0638 1305#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1306#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0639 1307#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1308#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063a 1309#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1310#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063b 1311#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1312#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063c 1313#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1314#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063d 1315#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1316#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063e 1317#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1318#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063f 1319#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1320 1321 1322// addressBlock: mmhub_mmutcl2_mmvml2pspdec 1323// base address: 0x69b10 1324#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID 0x06c4 1325#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 0 1326#define regMMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE 0x06c6 1327#define regMMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX 0 1328#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x06c7 1329#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 0 1330#define regMMVM_IOMMU_CONTROL_REGISTER 0x06c8 1331#define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0 1332#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x06c9 1333#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0 1334#define regMMUTC_TRANSLATION_FAULT_CNTL0 0x06ca 1335#define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 0 1336#define regMMUTC_TRANSLATION_FAULT_CNTL1 0x06cb 1337#define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 0 1338#define regMMUTCL2_VSCH_POWER_STATUS 0x06cc 1339#define regMMUTCL2_VSCH_POWER_STATUS_BASE_IDX 0 1340 1341#endif
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