FILE
mmhub_3_0_1_offset.h
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h
1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _mmhub_3_0_1_OFFSET_HEADER 24#define _mmhub_3_0_1_OFFSET_HEADER 25 26 27 28// addressBlock: mmhub_dagbdec 29// base address: 0x68000 30#define regDAGB0_RDCLI0 0x0000 31#define regDAGB0_RDCLI0_BASE_IDX 1 32#define regDAGB0_RDCLI1 0x0001 33#define regDAGB0_RDCLI1_BASE_IDX 1 34#define regDAGB0_RDCLI2 0x0002 35#define regDAGB0_RDCLI2_BASE_IDX 1 36#define regDAGB0_RDCLI3 0x0003 37#define regDAGB0_RDCLI3_BASE_IDX 1 38#define regDAGB0_RDCLI4 0x0004 39#define regDAGB0_RDCLI4_BASE_IDX 1 40#define regDAGB0_RDCLI5 0x0005 41#define regDAGB0_RDCLI5_BASE_IDX 1 42#define regDAGB0_RDCLI6 0x0006 43#define regDAGB0_RDCLI6_BASE_IDX 1 44#define regDAGB0_RDCLI7 0x0007 45#define regDAGB0_RDCLI7_BASE_IDX 1 46#define regDAGB0_RDCLI8 0x0008 47#define regDAGB0_RDCLI8_BASE_IDX 1 48#define regDAGB0_RDCLI9 0x0009 49#define regDAGB0_RDCLI9_BASE_IDX 1 50#define regDAGB0_RDCLI10 0x000a 51#define regDAGB0_RDCLI10_BASE_IDX 1 52#define regDAGB0_RDCLI11 0x000b 53#define regDAGB0_RDCLI11_BASE_IDX 1 54#define regDAGB0_RDCLI12 0x000c 55#define regDAGB0_RDCLI12_BASE_IDX 1 56#define regDAGB0_RDCLI13 0x000d 57#define regDAGB0_RDCLI13_BASE_IDX 1 58#define regDAGB0_RDCLI14 0x000e 59#define regDAGB0_RDCLI14_BASE_IDX 1 60#define regDAGB0_RDCLI15 0x000f 61#define regDAGB0_RDCLI15_BASE_IDX 1 62#define regDAGB0_RDCLI16 0x0010 63#define regDAGB0_RDCLI16_BASE_IDX 1 64#define regDAGB0_RDCLI17 0x0011 65#define regDAGB0_RDCLI17_BASE_IDX 1 66#define regDAGB0_RDCLI18 0x0012 67#define regDAGB0_RDCLI18_BASE_IDX 1 68#define regDAGB0_RDCLI19 0x0013 69#define regDAGB0_RDCLI19_BASE_IDX 1 70#define regDAGB0_RDCLI20 0x0014 71#define regDAGB0_RDCLI20_BASE_IDX 1 72#define regDAGB0_RDCLI21 0x0015 73#define regDAGB0_RDCLI21_BASE_IDX 1 74#define regDAGB0_RDCLI22 0x0016 75#define regDAGB0_RDCLI22_BASE_IDX 1 76#define regDAGB0_RDCLI23 0x0017 77#define regDAGB0_RDCLI23_BASE_IDX 1 78#define regDAGB0_RDCLI24 0x0018 79#define regDAGB0_RDCLI24_BASE_IDX 1 80#define regDAGB0_RDCLI25 0x0019 81#define regDAGB0_RDCLI25_BASE_IDX 1 82#define regDAGB0_RDCLI26 0x001a 83#define regDAGB0_RDCLI26_BASE_IDX 1 84#define regDAGB0_RDCLI27 0x001b 85#define regDAGB0_RDCLI27_BASE_IDX 1 86#define regDAGB0_RDCLI28 0x001c 87#define regDAGB0_RDCLI28_BASE_IDX 1 88#define regDAGB0_RDCLI29 0x001d 89#define regDAGB0_RDCLI29_BASE_IDX 1 90#define regDAGB0_RD_CNTL 0x001e 91#define regDAGB0_RD_CNTL_BASE_IDX 1 92#define regDAGB0_RD_IO_CNTL 0x001f 93#define regDAGB0_RD_IO_CNTL_BASE_IDX 1 94#define regDAGB0_RD_GMI_CNTL 0x0020 95#define regDAGB0_RD_GMI_CNTL_BASE_IDX 1 96#define regDAGB0_RD_ADDR_DAGB 0x0021 97#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 1 98#define regDAGB0_RD_CGTT_CLK_CTRL 0x0022 99#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1 100#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0023 101#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 102#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0024 103#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 104#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0025 105#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 106#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0026 107#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 108#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x0027 109#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 110#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x0028 111#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 112#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0029 113#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 114#define regDAGB0_RD_ADDR_DAGB_MAX_BURST3 0x002a 115#define regDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 116#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3 0x002b 117#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 118#define regDAGB0_RD_VC0_CNTL 0x002c 119#define regDAGB0_RD_VC0_CNTL_BASE_IDX 1 120#define regDAGB0_RD_VC1_CNTL 0x002d 121#define regDAGB0_RD_VC1_CNTL_BASE_IDX 1 122#define regDAGB0_RD_VC2_CNTL 0x002e 123#define regDAGB0_RD_VC2_CNTL_BASE_IDX 1 124#define regDAGB0_RD_VC3_CNTL 0x002f 125#define regDAGB0_RD_VC3_CNTL_BASE_IDX 1 126#define regDAGB0_RD_VC4_CNTL 0x0030 127#define regDAGB0_RD_VC4_CNTL_BASE_IDX 1 128#define regDAGB0_RD_VC5_CNTL 0x0031 129#define regDAGB0_RD_VC5_CNTL_BASE_IDX 1 130#define regDAGB0_RD_IO_VC_CNTL 0x0032 131#define regDAGB0_RD_IO_VC_CNTL_BASE_IDX 1 132#define regDAGB0_RD_GMI_VC_CNTL 0x0033 133#define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX 1 134#define regDAGB0_RD_CNTL_MISC 0x0034 135#define regDAGB0_RD_CNTL_MISC_BASE_IDX 1 136#define regDAGB0_RD_TLB_CREDIT 0x0035 137#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 1 138#define regDAGB0_RDCLI_ASK_PENDING 0x0036 139#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1 140#define regDAGB0_RDCLI_GO_PENDING 0x0037 141#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 1 142#define regDAGB0_RDCLI_GBLSEND_PENDING 0x0038 143#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1 144#define regDAGB0_RDCLI_TLB_PENDING 0x0039 145#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1 146#define regDAGB0_RDCLI_OARB_PENDING 0x003a 147#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1 148#define regDAGB0_RDCLI_ASK2ARB_PENDING 0x003b 149#define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX 1 150#define regDAGB0_RDCLI_ASK2DF_PENDING 0x003c 151#define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX 1 152#define regDAGB0_RDCLI_OSD_PENDING 0x003d 153#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1 154#define regDAGB0_RDCLI_ASK_OSD_PENDING 0x003e 155#define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX 1 156#define regDAGB0_WRCLI0 0x003f 157#define regDAGB0_WRCLI0_BASE_IDX 1 158#define regDAGB0_WRCLI1 0x0040 159#define regDAGB0_WRCLI1_BASE_IDX 1 160#define regDAGB0_WRCLI2 0x0041 161#define regDAGB0_WRCLI2_BASE_IDX 1 162#define regDAGB0_WRCLI3 0x0042 163#define regDAGB0_WRCLI3_BASE_IDX 1 164#define regDAGB0_WRCLI4 0x0043 165#define regDAGB0_WRCLI4_BASE_IDX 1 166#define regDAGB0_WRCLI5 0x0044 167#define regDAGB0_WRCLI5_BASE_IDX 1 168#define regDAGB0_WRCLI6 0x0045 169#define regDAGB0_WRCLI6_BASE_IDX 1 170#define regDAGB0_WRCLI7 0x0046 171#define regDAGB0_WRCLI7_BASE_IDX 1 172#define regDAGB0_WRCLI8 0x0047 173#define regDAGB0_WRCLI8_BASE_IDX 1 174#define regDAGB0_WRCLI9 0x0048 175#define regDAGB0_WRCLI9_BASE_IDX 1 176#define regDAGB0_WRCLI10 0x0049 177#define regDAGB0_WRCLI10_BASE_IDX 1 178#define regDAGB0_WRCLI11 0x004a 179#define regDAGB0_WRCLI11_BASE_IDX 1 180#define regDAGB0_WRCLI12 0x004b 181#define regDAGB0_WRCLI12_BASE_IDX 1 182#define regDAGB0_WRCLI13 0x004c 183#define regDAGB0_WRCLI13_BASE_IDX 1 184#define regDAGB0_WRCLI14 0x004d 185#define regDAGB0_WRCLI14_BASE_IDX 1 186#define regDAGB0_WRCLI15 0x004e 187#define regDAGB0_WRCLI15_BASE_IDX 1 188#define regDAGB0_WRCLI16 0x004f 189#define regDAGB0_WRCLI16_BASE_IDX 1 190#define regDAGB0_WRCLI17 0x0050 191#define regDAGB0_WRCLI17_BASE_IDX 1 192#define regDAGB0_WRCLI18 0x0051 193#define regDAGB0_WRCLI18_BASE_IDX 1 194#define regDAGB0_WRCLI19 0x0052 195#define regDAGB0_WRCLI19_BASE_IDX 1 196#define regDAGB0_WRCLI20 0x0053 197#define regDAGB0_WRCLI20_BASE_IDX 1 198#define regDAGB0_WRCLI21 0x0054 199#define regDAGB0_WRCLI21_BASE_IDX 1 200#define regDAGB0_WRCLI22 0x0055 201#define regDAGB0_WRCLI22_BASE_IDX 1 202#define regDAGB0_WRCLI23 0x0056 203#define regDAGB0_WRCLI23_BASE_IDX 1 204#define regDAGB0_WRCLI24 0x0057 205#define regDAGB0_WRCLI24_BASE_IDX 1 206#define regDAGB0_WRCLI25 0x0058 207#define regDAGB0_WRCLI25_BASE_IDX 1 208#define regDAGB0_WRCLI26 0x0059 209#define regDAGB0_WRCLI26_BASE_IDX 1 210#define regDAGB0_WRCLI27 0x005a 211#define regDAGB0_WRCLI27_BASE_IDX 1 212#define regDAGB0_WRCLI28 0x005b 213#define regDAGB0_WRCLI28_BASE_IDX 1 214#define regDAGB0_WRCLI29 0x005c 215#define regDAGB0_WRCLI29_BASE_IDX 1 216#define regDAGB0_WR_CNTL 0x005d 217#define regDAGB0_WR_CNTL_BASE_IDX 1 218#define regDAGB0_WR_IO_CNTL 0x005e 219#define regDAGB0_WR_IO_CNTL_BASE_IDX 1 220#define regDAGB0_WR_GMI_CNTL 0x005f 221#define regDAGB0_WR_GMI_CNTL_BASE_IDX 1 222#define regDAGB0_WR_ADDR_DAGB 0x0060 223#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 1 224#define regDAGB0_WR_CGTT_CLK_CTRL 0x0061 225#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1 226#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0062 227#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 228#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0063 229#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 230#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0064 231#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 232#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0065 233#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 234#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0066 235#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 236#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x0067 237#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 238#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x0068 239#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 240#define regDAGB0_WR_ADDR_DAGB_MAX_BURST3 0x0069 241#define regDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 242#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3 0x006a 243#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 244#define regDAGB0_WR_DATA_DAGB 0x006b 245#define regDAGB0_WR_DATA_DAGB_BASE_IDX 1 246#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x006c 247#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 248#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x006d 249#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 250#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x006e 251#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 252#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x006f 253#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 254#define regDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0070 255#define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 1 256#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0071 257#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 1 258#define regDAGB0_WR_DATA_DAGB_MAX_BURST3 0x0072 259#define regDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX 1 260#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3 0x0073 261#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX 1 262#define regDAGB0_WR_VC0_CNTL 0x0074 263#define regDAGB0_WR_VC0_CNTL_BASE_IDX 1 264#define regDAGB0_WR_VC1_CNTL 0x0075 265#define regDAGB0_WR_VC1_CNTL_BASE_IDX 1 266#define regDAGB0_WR_VC2_CNTL 0x0076 267#define regDAGB0_WR_VC2_CNTL_BASE_IDX 1 268#define regDAGB0_WR_VC3_CNTL 0x0077 269#define regDAGB0_WR_VC3_CNTL_BASE_IDX 1 270#define regDAGB0_WR_VC4_CNTL 0x0078 271#define regDAGB0_WR_VC4_CNTL_BASE_IDX 1 272#define regDAGB0_WR_VC5_CNTL 0x0079 273#define regDAGB0_WR_VC5_CNTL_BASE_IDX 1 274#define regDAGB0_WR_IO_VC_CNTL 0x007a 275#define regDAGB0_WR_IO_VC_CNTL_BASE_IDX 1 276#define regDAGB0_WR_GMI_VC_CNTL 0x007b 277#define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX 1 278#define regDAGB0_WR_CNTL_MISC 0x007c 279#define regDAGB0_WR_CNTL_MISC_BASE_IDX 1 280#define regDAGB0_WR_TLB_CREDIT 0x007d 281#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 1 282#define regDAGB0_WR_DATA_CREDIT 0x007e 283#define regDAGB0_WR_DATA_CREDIT_BASE_IDX 1 284#define regDAGB0_WR_MISC_CREDIT 0x007f 285#define regDAGB0_WR_MISC_CREDIT_BASE_IDX 1 286#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x0080 287#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 1 288#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x0081 289#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 1 290#define regDAGB0_WRCLI_ASK_PENDING 0x0082 291#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1 292#define regDAGB0_WRCLI_GO_PENDING 0x0083 293#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 1 294#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0084 295#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1 296#define regDAGB0_WRCLI_TLB_PENDING 0x0085 297#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1 298#define regDAGB0_WRCLI_OARB_PENDING 0x0086 299#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1 300#define regDAGB0_WRCLI_ASK2ARB_PENDING 0x0087 301#define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX 1 302#define regDAGB0_WRCLI_ASK2DF_PENDING 0x0088 303#define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX 1 304#define regDAGB0_WRCLI_OSD_PENDING 0x0089 305#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1 306#define regDAGB0_WRCLI_ASK_OSD_PENDING 0x008a 307#define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX 1 308#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x008b 309#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 310#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x008c 311#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 312#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x008d 313#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1 314#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x008e 315#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1 316#define regDAGB0_DAGB_DLY 0x008f 317#define regDAGB0_DAGB_DLY_BASE_IDX 1 318#define regDAGB0_CNTL_MISC 0x0090 319#define regDAGB0_CNTL_MISC_BASE_IDX 1 320#define regDAGB0_CNTL_MISC2 0x0091 321#define regDAGB0_CNTL_MISC2_BASE_IDX 1 322#define regDAGB0_FIFO_EMPTY 0x0092 323#define regDAGB0_FIFO_EMPTY_BASE_IDX 1 324#define regDAGB0_FIFO_FULL 0x0093 325#define regDAGB0_FIFO_FULL_BASE_IDX 1 326#define regDAGB0_RD_CREDITS_FULL 0x0094 327#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 1 328#define regDAGB0_WR_CREDITS_FULL 0x0095 329#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 1 330#define regDAGB0_PERFCOUNTER_LO 0x0096 331#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 1 332#define regDAGB0_PERFCOUNTER_HI 0x0097 333#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 1 334#define regDAGB0_PERFCOUNTER0_CFG 0x0098 335#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1 336#define regDAGB0_PERFCOUNTER1_CFG 0x0099 337#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1 338#define regDAGB0_PERFCOUNTER2_CFG 0x009a 339#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1 340#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x009b 341#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 342#define regDAGB0_L1TLB_REG_RW 0x009c 343#define regDAGB0_L1TLB_REG_RW_BASE_IDX 1 344#define regDAGB0_RESERVE1 0x009d 345#define regDAGB0_RESERVE1_BASE_IDX 1 346#define regDAGB0_RESERVE2 0x009e 347#define regDAGB0_RESERVE2_BASE_IDX 1 348#define regDAGB0_RESERVE3 0x009f 349#define regDAGB0_RESERVE3_BASE_IDX 1 350#define regDAGB0_RESERVE4 0x00a0 351#define regDAGB0_RESERVE4_BASE_IDX 1 352#define regDAGB0_SDP_RD_BW_CNTL 0x00a1 353#define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX 1 354#define regDAGB0_SDP_PRIORITY_OVERRIDE 0x00a2 355#define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX 1 356#define regDAGB0_SDP_RD_PRIORITY 0x00a3 357#define regDAGB0_SDP_RD_PRIORITY_BASE_IDX 1 358#define regDAGB0_SDP_WR_PRIORITY 0x00a4 359#define regDAGB0_SDP_WR_PRIORITY_BASE_IDX 1 360#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP 0x00a5 361#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 1 362#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP 0x00a6 363#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX 1 364#define regDAGB0_SDP_ENABLE 0x00a7 365#define regDAGB0_SDP_ENABLE_BASE_IDX 1 366#define regDAGB0_SDP_CREDITS 0x00a8 367#define regDAGB0_SDP_CREDITS_BASE_IDX 1 368#define regDAGB0_SDP_TAG_RESERVE0 0x00a9 369#define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX 1 370#define regDAGB0_SDP_TAG_RESERVE1 0x00aa 371#define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX 1 372#define regDAGB0_SDP_VCC_RESERVE0 0x00ab 373#define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX 1 374#define regDAGB0_SDP_VCC_RESERVE1 0x00ac 375#define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX 1 376#define regDAGB0_SDP_ERR_STATUS 0x00ad 377#define regDAGB0_SDP_ERR_STATUS_BASE_IDX 1 378#define regDAGB0_SDP_REQ_CNTL 0x00ae 379#define regDAGB0_SDP_REQ_CNTL_BASE_IDX 1 380#define regDAGB0_SDP_MISC_AON 0x00af 381#define regDAGB0_SDP_MISC_AON_BASE_IDX 1 382#define regDAGB0_SDP_MISC 0x00b0 383#define regDAGB0_SDP_MISC_BASE_IDX 1 384#define regDAGB0_SDP_MISC2 0x00b1 385#define regDAGB0_SDP_MISC2_BASE_IDX 1 386#define regDAGB0_SDP_VCD_RESERVE0 0x00b3 387#define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX 1 388#define regDAGB0_SDP_VCD_RESERVE1 0x00b4 389#define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX 1 390#define regDAGB0_SDP_ARB_CNTL0 0x00b5 391#define regDAGB0_SDP_ARB_CNTL0_BASE_IDX 1 392#define regDAGB0_SDP_ARB_CNTL1 0x00b6 393#define regDAGB0_SDP_ARB_CNTL1_BASE_IDX 1 394#define regDAGB0_SDP_CGTT_CLK_CTRL 0x00b7 395#define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX 1 396#define regDAGB0_SDP_LATENCY_SAMPLING 0x00b8 397#define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX 1 398 399 400// addressBlock: mmhub_pctldec 401// base address: 0x68e00 402#define regPCTL_CTRL 0x0380 403#define regPCTL_CTRL_BASE_IDX 1 404#define regPCTL_MMHUB_DEEPSLEEP_IB 0x0381 405#define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 406#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 407#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 408#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0383 409#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 410#define regPCTL_PG_IGNORE_DEEPSLEEP 0x0384 411#define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 412#define regPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0385 413#define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 414#define regPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0386 415#define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 1 416#define regPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0387 417#define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 1 418#define regPCTL_SLICE0_CFG_DS_ALLOW 0x0388 419#define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 420#define regPCTL_SLICE0_CFG_DS_ALLOW_IB 0x0389 421#define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 422#define regPCTL_SLICE1_CFG_DAGB_WRBUSY 0x038a 423#define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 1 424#define regPCTL_SLICE1_CFG_DAGB_RDBUSY 0x038b 425#define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 1 426#define regPCTL_SLICE1_CFG_DS_ALLOW 0x038c 427#define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 428#define regPCTL_SLICE1_CFG_DS_ALLOW_IB 0x038d 429#define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 430#define regPCTL_UTCL2_MISC 0x038e 431#define regPCTL_UTCL2_MISC_BASE_IDX 1 432#define regPCTL_SLICE0_MISC 0x038f 433#define regPCTL_SLICE0_MISC_BASE_IDX 1 434#define regPCTL_SLICE1_MISC 0x0390 435#define regPCTL_SLICE1_MISC_BASE_IDX 1 436#define regPCTL_RENG_CTRL 0x0391 437#define regPCTL_RENG_CTRL_BASE_IDX 1 438#define regPCTL_UTCL2_RENG_EXECUTE 0x0392 439#define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 1 440#define regPCTL_SLICE0_RENG_EXECUTE 0x0393 441#define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 1 442#define regPCTL_SLICE1_RENG_EXECUTE 0x0394 443#define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 1 444#define regPCTL_UTCL2_RENG_RAM_INDEX 0x0395 445#define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 446#define regPCTL_UTCL2_RENG_RAM_DATA 0x0396 447#define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 1 448#define regPCTL_SLICE0_RENG_RAM_INDEX 0x0397 449#define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 450#define regPCTL_SLICE0_RENG_RAM_DATA 0x0398 451#define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 1 452#define regPCTL_SLICE1_RENG_RAM_INDEX 0x0399 453#define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 454#define regPCTL_SLICE1_RENG_RAM_DATA 0x039a 455#define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 1 456#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b 457#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 458#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c 459#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 460#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d 461#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 462#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x039e 463#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 464#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x039f 465#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 466#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a0 467#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 468#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a1 469#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 470#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x03a2 471#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 472#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x03a3 473#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 474#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x03a4 475#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 476#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x03a5 477#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 478#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x03a6 479#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 480#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a7 481#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 482#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a8 483#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 484#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x03a9 485#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 486#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x03aa 487#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 488#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x03ab 489#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 490#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x03ac 491#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 492#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x03ad 493#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 494#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03ae 495#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 496#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03af 497#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 498#define regPCTL_STATUS 0x03b0 499#define regPCTL_STATUS_BASE_IDX 1 500#define regPCTL_PERFCOUNTER_LO 0x03b1 501#define regPCTL_PERFCOUNTER_LO_BASE_IDX 1 502#define regPCTL_PERFCOUNTER_HI 0x03b2 503#define regPCTL_PERFCOUNTER_HI_BASE_IDX 1 504#define regPCTL_PERFCOUNTER0_CFG 0x03b3 505#define regPCTL_PERFCOUNTER0_CFG_BASE_IDX 1 506#define regPCTL_PERFCOUNTER1_CFG 0x03b4 507#define regPCTL_PERFCOUNTER1_CFG_BASE_IDX 1 508#define regPCTL_PERFCOUNTER_RSLT_CNTL 0x03b5 509#define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 510#define regPCTL_RESERVED_0 0x03b6 511#define regPCTL_RESERVED_0_BASE_IDX 1 512#define regPCTL_RESERVED_1 0x03b7 513#define regPCTL_RESERVED_1_BASE_IDX 1 514#define regPCTL_RESERVED_2 0x03b8 515#define regPCTL_RESERVED_2_BASE_IDX 1 516#define regPCTL_RESERVED_3 0x03b9 517#define regPCTL_RESERVED_3_BASE_IDX 1 518 519 520// addressBlock: mmhub_l1tlb_mmutcl1pfdec 521// base address: 0x69600 522#define regMMMC_VM_MX_L1_TLB0_STATUS 0x0588 523#define regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 524#define regMMMC_VM_MX_L1_TLB1_STATUS 0x0589 525#define regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 526#define regMMMC_VM_MX_L1_TLB2_STATUS 0x058a 527#define regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 528#define regMMMC_VM_MX_L1_TLB3_STATUS 0x058b 529#define regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 530#define regMMMC_VM_MX_L1_TLB4_STATUS 0x058c 531#define regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 532#define regMMMC_VM_MX_L1_TLB5_STATUS 0x058d 533#define regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 534#define regMMMC_VM_MX_L1_TLB6_STATUS 0x058e 535#define regMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 536#define regMMMC_VM_MX_L1_TLB7_STATUS 0x058f 537#define regMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 538 539 540// addressBlock: mmhub_l1tlb_mmutcl1pldec 541// base address: 0x69670 542#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x059c 543#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 544#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x059d 545#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 546#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x059e 547#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 548#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x059f 549#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 550#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x05a0 551#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 552 553 554// addressBlock: mmhub_l1tlb_mmutcl1prdec 555// base address: 0x69690 556#define regMMMC_VM_MX_L1_PERFCOUNTER_LO 0x05a4 557#define regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 558#define regMMMC_VM_MX_L1_PERFCOUNTER_HI 0x05a5 559#define regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 560 561 562// addressBlock: mmhub_l1tlb_mmvmtlspfdec 563// base address: 0x696c0 564#define regMMMC_VM_MX_L1_TLS0_CNTL 0x05b0 565#define regMMMC_VM_MX_L1_TLS0_CNTL_BASE_IDX 1 566#define regMMMC_VM_MX_L1_TLS0_CNTL0 0x05b1 567#define regMMMC_VM_MX_L1_TLS0_CNTL0_BASE_IDX 1 568#define regMMMC_VM_MX_L1_TLS0_CNTL1 0x05b2 569#define regMMMC_VM_MX_L1_TLS0_CNTL1_BASE_IDX 1 570#define regMMMC_VM_MX_L1_TLS0_CNTL2 0x05b3 571#define regMMMC_VM_MX_L1_TLS0_CNTL2_BASE_IDX 1 572#define regMMMC_VM_MX_L1_TLS0_CNTL3 0x05b4 573#define regMMMC_VM_MX_L1_TLS0_CNTL3_BASE_IDX 1 574#define regMMMC_VM_MX_L1_TLS0_CNTL4 0x05b5 575#define regMMMC_VM_MX_L1_TLS0_CNTL4_BASE_IDX 1 576#define regMMMC_VM_MX_L1_TLS0_CNTL5 0x05b6 577#define regMMMC_VM_MX_L1_TLS0_CNTL5_BASE_IDX 1 578#define regMMMC_VM_MX_L1_TLS0_CNTL6 0x05b7 579#define regMMMC_VM_MX_L1_TLS0_CNTL6_BASE_IDX 1 580#define regMMMC_VM_MX_L1_TLS0_CNTL7 0x05b8 581#define regMMMC_VM_MX_L1_TLS0_CNTL7_BASE_IDX 1 582#define regMMMC_VM_MX_L1_TLS0_CNTL8 0x05b9 583#define regMMMC_VM_MX_L1_TLS0_CNTL8_BASE_IDX 1 584#define regMMMC_VM_MX_L1_TLS0_CNTL9 0x05ba 585#define regMMMC_VM_MX_L1_TLS0_CNTL9_BASE_IDX 1 586#define regMMMC_VM_MX_L1_TLS0_CNTL10 0x05bb 587#define regMMMC_VM_MX_L1_TLS0_CNTL10_BASE_IDX 1 588#define regMMMC_VM_MX_L1_TLS0_CNTL11 0x05bc 589#define regMMMC_VM_MX_L1_TLS0_CNTL11_BASE_IDX 1 590#define regMMMC_VM_MX_L1_TLS0_CNTL12 0x05bd 591#define regMMMC_VM_MX_L1_TLS0_CNTL12_BASE_IDX 1 592#define regMMMC_VM_MX_L1_TLS0_CNTL13 0x05be 593#define regMMMC_VM_MX_L1_TLS0_CNTL13_BASE_IDX 1 594#define regMMMC_VM_MX_L1_TLS0_CNTL14 0x05bf 595#define regMMMC_VM_MX_L1_TLS0_CNTL14_BASE_IDX 1 596#define regMMMC_VM_MX_L1_TLS0_CNTL15 0x05c0 597#define regMMMC_VM_MX_L1_TLS0_CNTL15_BASE_IDX 1 598#define regMMMC_VM_MX_L1_TLS0_CNTL16 0x05c1 599#define regMMMC_VM_MX_L1_TLS0_CNTL16_BASE_IDX 1 600#define regMMMC_VM_MX_L1_TLS0_CNTL17 0x05c2 601#define regMMMC_VM_MX_L1_TLS0_CNTL17_BASE_IDX 1 602#define regMMMC_VM_MX_L1_TLS0_CNTL18 0x05c3 603#define regMMMC_VM_MX_L1_TLS0_CNTL18_BASE_IDX 1 604#define regMMMC_VM_MX_L1_TLS0_CNTL19 0x05c4 605#define regMMMC_VM_MX_L1_TLS0_CNTL19_BASE_IDX 1 606#define regMMMC_VM_MX_L1_TLS0_CNTL20 0x05c5 607#define regMMMC_VM_MX_L1_TLS0_CNTL20_BASE_IDX 1 608#define regMMMC_VM_MX_L1_TLS0_CNTL21 0x05c6 609#define regMMMC_VM_MX_L1_TLS0_CNTL21_BASE_IDX 1 610#define regMMMC_VM_MX_L1_TLS0_CNTL22 0x05c7 611#define regMMMC_VM_MX_L1_TLS0_CNTL22_BASE_IDX 1 612#define regMMMC_VM_MX_L1_TLS0_CNTL23 0x05c8 613#define regMMMC_VM_MX_L1_TLS0_CNTL23_BASE_IDX 1 614#define regMMMC_VM_MX_L1_TLS0_CNTL24 0x05c9 615#define regMMMC_VM_MX_L1_TLS0_CNTL24_BASE_IDX 1 616#define regMMMC_VM_MX_L1_TLS0_CNTL25 0x05ca 617#define regMMMC_VM_MX_L1_TLS0_CNTL25_BASE_IDX 1 618#define regMMMC_VM_MX_L1_TLS0_CNTL26 0x05cb 619#define regMMMC_VM_MX_L1_TLS0_CNTL26_BASE_IDX 1 620#define regMMMC_VM_MX_L1_TLS0_CNTL27 0x05cc 621#define regMMMC_VM_MX_L1_TLS0_CNTL27_BASE_IDX 1 622#define regMMMC_VM_MX_L1_TLS0_CNTL28 0x05cd 623#define regMMMC_VM_MX_L1_TLS0_CNTL28_BASE_IDX 1 624#define regMMMC_VM_MX_L1_TLS0_CNTL29 0x05ce 625#define regMMMC_VM_MX_L1_TLS0_CNTL29_BASE_IDX 1 626#define regMMMC_VM_MX_L1_TLS0_CNTL30 0x05cf 627#define regMMMC_VM_MX_L1_TLS0_CNTL30_BASE_IDX 1 628#define regMMMC_VM_MX_L1_TLS0_CNTL31 0x05d0 629#define regMMMC_VM_MX_L1_TLS0_CNTL31_BASE_IDX 1 630#define regMMMC_VM_MX_L1_TLS0_CNTL32 0x05d1 631#define regMMMC_VM_MX_L1_TLS0_CNTL32_BASE_IDX 1 632#define regMMMC_VM_MX_L1_TLS0_CNTL33 0x05d2 633#define regMMMC_VM_MX_L1_TLS0_CNTL33_BASE_IDX 1 634#define regMMMC_VM_MX_L1_TLS0_CNTL34 0x05d3 635#define regMMMC_VM_MX_L1_TLS0_CNTL34_BASE_IDX 1 636#define regMMMC_VM_MX_L1_TLS0_CNTL35 0x05d4 637#define regMMMC_VM_MX_L1_TLS0_CNTL35_BASE_IDX 1 638#define regMMMC_VM_MX_L1_TLS0_CNTL36 0x05d5 639#define regMMMC_VM_MX_L1_TLS0_CNTL36_BASE_IDX 1 640#define regMMMC_VM_MX_L1_TLS0_CNTL37 0x05d6 641#define regMMMC_VM_MX_L1_TLS0_CNTL37_BASE_IDX 1 642#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 0x05d7 643#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32_BASE_IDX 1 644#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 0x05d8 645#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32_BASE_IDX 1 646#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 0x05d9 647#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32_BASE_IDX 1 648#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 0x05da 649#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32_BASE_IDX 1 650#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 0x05db 651#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32_BASE_IDX 1 652#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 0x05dc 653#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32_BASE_IDX 1 654#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 0x05dd 655#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32_BASE_IDX 1 656#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 0x05de 657#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32_BASE_IDX 1 658#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 0x05df 659#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32_BASE_IDX 1 660#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 0x05e0 661#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32_BASE_IDX 1 662#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 0x05e1 663#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32_BASE_IDX 1 664#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 0x05e2 665#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32_BASE_IDX 1 666#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 0x05e3 667#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32_BASE_IDX 1 668#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 0x05e4 669#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32_BASE_IDX 1 670#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 0x05e5 671#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32_BASE_IDX 1 672#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 0x05e6 673#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32_BASE_IDX 1 674#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 0x05e7 675#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32_BASE_IDX 1 676#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 0x05e8 677#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32_BASE_IDX 1 678#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 0x05e9 679#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32_BASE_IDX 1 680#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 0x05ea 681#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32_BASE_IDX 1 682#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 0x05eb 683#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32_BASE_IDX 1 684#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 0x05ec 685#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32_BASE_IDX 1 686#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 0x05ed 687#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32_BASE_IDX 1 688#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 0x05ee 689#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32_BASE_IDX 1 690#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 0x05ef 691#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32_BASE_IDX 1 692#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 0x05f0 693#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32_BASE_IDX 1 694#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 0x05f1 695#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32_BASE_IDX 1 696#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 0x05f2 697#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32_BASE_IDX 1 698#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 0x05f3 699#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32_BASE_IDX 1 700#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 0x05f4 701#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32_BASE_IDX 1 702#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 0x05f5 703#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32_BASE_IDX 1 704#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 0x05f6 705#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32_BASE_IDX 1 706#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 0x05f7 707#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32_BASE_IDX 1 708#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 0x05f8 709#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32_BASE_IDX 1 710#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 0x05f9 711#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32_BASE_IDX 1 712#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 0x05fa 713#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32_BASE_IDX 1 714#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 0x05fb 715#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32_BASE_IDX 1 716#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 0x05fc 717#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32_BASE_IDX 1 718#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 0x05fd 719#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32_BASE_IDX 1 720#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 0x05fe 721#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32_BASE_IDX 1 722#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 0x05ff 723#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32_BASE_IDX 1 724#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 0x0600 725#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32_BASE_IDX 1 726#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 0x0601 727#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32_BASE_IDX 1 728#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 0x0602 729#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32_BASE_IDX 1 730#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 0x0603 731#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32_BASE_IDX 1 732#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 0x0604 733#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32_BASE_IDX 1 734#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 0x0605 735#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32_BASE_IDX 1 736#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 0x0606 737#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32_BASE_IDX 1 738#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 0x0607 739#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32_BASE_IDX 1 740#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 0x0608 741#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32_BASE_IDX 1 742#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 0x0609 743#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32_BASE_IDX 1 744#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 0x060a 745#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32_BASE_IDX 1 746#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 0x060b 747#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32_BASE_IDX 1 748#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 0x060c 749#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32_BASE_IDX 1 750#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 0x060d 751#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32_BASE_IDX 1 752#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 0x060e 753#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32_BASE_IDX 1 754#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 0x060f 755#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32_BASE_IDX 1 756#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 0x0610 757#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32_BASE_IDX 1 758#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 0x0611 759#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32_BASE_IDX 1 760#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 0x0612 761#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32_BASE_IDX 1 762#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 0x0613 763#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32_BASE_IDX 1 764#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 0x0614 765#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32_BASE_IDX 1 766#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 0x0615 767#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32_BASE_IDX 1 768#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 0x0616 769#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32_BASE_IDX 1 770#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 0x0617 771#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32_BASE_IDX 1 772#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 0x0618 773#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32_BASE_IDX 1 774#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 0x0619 775#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32_BASE_IDX 1 776#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 0x061a 777#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32_BASE_IDX 1 778#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 0x061b 779#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32_BASE_IDX 1 780#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 0x061c 781#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32_BASE_IDX 1 782#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 0x061d 783#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32_BASE_IDX 1 784#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 0x061e 785#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32_BASE_IDX 1 786#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 0x061f 787#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32_BASE_IDX 1 788#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 0x0620 789#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32_BASE_IDX 1 790#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 0x0621 791#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32_BASE_IDX 1 792#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 0x0622 793#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32_BASE_IDX 1 794#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 0x0623 795#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32_BASE_IDX 1 796#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 0x0624 797#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32_BASE_IDX 1 798#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 0x0625 799#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32_BASE_IDX 1 800#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 0x0626 801#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32_BASE_IDX 1 802#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 0x0627 803#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32_BASE_IDX 1 804#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 0x0628 805#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32_BASE_IDX 1 806#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 0x0629 807#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32_BASE_IDX 1 808#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 0x062a 809#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32_BASE_IDX 1 810#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 0x062b 811#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32_BASE_IDX 1 812#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 0x062c 813#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32_BASE_IDX 1 814#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 0x062d 815#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32_BASE_IDX 1 816#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 0x062e 817#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32_BASE_IDX 1 818#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 0x062f 819#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32_BASE_IDX 1 820#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 0x0630 821#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32_BASE_IDX 1 822#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 0x0631 823#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32_BASE_IDX 1 824#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 0x0632 825#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32_BASE_IDX 1 826#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 0x0633 827#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32_BASE_IDX 1 828#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 0x0634 829#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32_BASE_IDX 1 830#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 0x0635 831#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32_BASE_IDX 1 832#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 0x0636 833#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32_BASE_IDX 1 834#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 0x0637 835#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32_BASE_IDX 1 836#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 0x0638 837#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32_BASE_IDX 1 838#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 0x0639 839#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32_BASE_IDX 1 840#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 0x063a 841#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32_BASE_IDX 1 842#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 0x063b 843#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32_BASE_IDX 1 844#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 0x063c 845#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32_BASE_IDX 1 846#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 0x063d 847#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32_BASE_IDX 1 848#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 0x063e 849#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32_BASE_IDX 1 850#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 0x063f 851#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32_BASE_IDX 1 852#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 0x0640 853#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32_BASE_IDX 1 854#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 0x0641 855#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32_BASE_IDX 1 856#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 0x0642 857#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32_BASE_IDX 1 858#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 0x0643 859#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32_BASE_IDX 1 860#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 0x0644 861#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32_BASE_IDX 1 862#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 0x0645 863#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32_BASE_IDX 1 864#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 0x0646 865#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32_BASE_IDX 1 866#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 0x0647 867#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32_BASE_IDX 1 868#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 0x0648 869#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32_BASE_IDX 1 870#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 0x0649 871#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32_BASE_IDX 1 872#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 0x064a 873#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32_BASE_IDX 1 874#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 0x064b 875#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32_BASE_IDX 1 876#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 0x064c 877#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32_BASE_IDX 1 878#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 0x064d 879#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32_BASE_IDX 1 880#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 0x064e 881#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32_BASE_IDX 1 882#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 0x064f 883#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32_BASE_IDX 1 884#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 0x0650 885#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32_BASE_IDX 1 886#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 0x0651 887#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32_BASE_IDX 1 888#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 0x0652 889#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32_BASE_IDX 1 890#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 0x0653 891#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32_BASE_IDX 1 892#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 0x0654 893#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32_BASE_IDX 1 894#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 0x0655 895#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32_BASE_IDX 1 896#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 0x0656 897#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32_BASE_IDX 1 898#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 0x0657 899#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32_BASE_IDX 1 900#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 0x0658 901#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32_BASE_IDX 1 902#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 0x0659 903#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32_BASE_IDX 1 904#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 0x065a 905#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32_BASE_IDX 1 906#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 0x065b 907#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32_BASE_IDX 1 908#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 0x065c 909#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32_BASE_IDX 1 910#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 0x065d 911#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32_BASE_IDX 1 912#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 0x065e 913#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32_BASE_IDX 1 914#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 0x065f 915#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32_BASE_IDX 1 916#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 0x0660 917#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32_BASE_IDX 1 918#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 0x0661 919#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32_BASE_IDX 1 920#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 0x0662 921#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32_BASE_IDX 1 922#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 0x0663 923#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32_BASE_IDX 1 924#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 0x0664 925#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32_BASE_IDX 1 926#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 0x0665 927#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32_BASE_IDX 1 928#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 0x0666 929#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32_BASE_IDX 1 930#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 0x0667 931#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32_BASE_IDX 1 932#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 0x0668 933#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32_BASE_IDX 1 934#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 0x0669 935#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32_BASE_IDX 1 936#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 0x066a 937#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32_BASE_IDX 1 938#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 0x066b 939#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32_BASE_IDX 1 940#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 0x066c 941#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32_BASE_IDX 1 942#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 0x066d 943#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32_BASE_IDX 1 944#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 0x066e 945#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32_BASE_IDX 1 946#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 0x066f 947#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32_BASE_IDX 1 948#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 0x0670 949#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32_BASE_IDX 1 950#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 0x0671 951#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32_BASE_IDX 1 952#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 0x0672 953#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32_BASE_IDX 1 954#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS 0x0673 955#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_BASE_IDX 1 956#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 0x0674 957#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 958#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 0x0675 959#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 960#define regMMVM_L2_SAW_CNTL 0x0676 961#define regMMVM_L2_SAW_CNTL_BASE_IDX 1 962#define regMMVM_L2_SAW_CNTL2 0x0677 963#define regMMVM_L2_SAW_CNTL2_BASE_IDX 1 964#define regMMVM_L2_SAW_CNTL3 0x0678 965#define regMMVM_L2_SAW_CNTL3_BASE_IDX 1 966#define regMMVM_L2_SAW_CNTL4 0x0679 967#define regMMVM_L2_SAW_CNTL4_BASE_IDX 1 968#define regMMVM_L2_SAW_CONTEXT0_CNTL 0x067a 969#define regMMVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX 1 970#define regMMVM_L2_SAW_CONTEXT0_CNTL2 0x067b 971#define regMMVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX 1 972#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x067c 973#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 974#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x067d 975#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 976#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x067e 977#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 978#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x067f 979#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 980#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0680 981#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 982#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0681 983#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 984#define regMMVM_L2_SAW_CONTEXTS_DISABLE 0x0682 985#define regMMVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX 1 986#define regMMVM_L2_SAW_PIPES_BUSY_LO32 0x0683 987#define regMMVM_L2_SAW_PIPES_BUSY_LO32_BASE_IDX 1 988#define regMMVM_L2_SAW_PIPES_BUSY_HI32 0x0684 989#define regMMVM_L2_SAW_PIPES_BUSY_HI32_BASE_IDX 1 990#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS 0x0685 991#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS_BASE_IDX 1 992#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 0x0686 993#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32_BASE_IDX 1 994#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 0x0687 995#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32_BASE_IDX 1 996 997 998// addressBlock: mmhub_mmutcl2_mmatcl2dec 999// base address: 0x69b00 1000#define regMM_ATC_L2_CNTL 0x06c0 1001#define regMM_ATC_L2_CNTL_BASE_IDX 1 1002#define regMM_ATC_L2_CNTL2 0x06c1 1003#define regMM_ATC_L2_CNTL2_BASE_IDX 1 1004#define regMM_ATC_L2_CACHE_DATA0 0x06c4 1005#define regMM_ATC_L2_CACHE_DATA0_BASE_IDX 1 1006#define regMM_ATC_L2_CACHE_DATA1 0x06c5 1007#define regMM_ATC_L2_CACHE_DATA1_BASE_IDX 1 1008#define regMM_ATC_L2_CACHE_DATA2 0x06c6 1009#define regMM_ATC_L2_CACHE_DATA2_BASE_IDX 1 1010#define regMM_ATC_L2_CNTL3 0x06c7 1011#define regMM_ATC_L2_CNTL3_BASE_IDX 1 1012#define regMM_ATC_L2_CNTL4 0x06c8 1013#define regMM_ATC_L2_CNTL4_BASE_IDX 1 1014#define regMM_ATC_L2_CNTL5 0x06c9 1015#define regMM_ATC_L2_CNTL5_BASE_IDX 1 1016#define regMM_ATC_L2_MM_GROUP_RT_CLASSES 0x06ca 1017#define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 1018#define regMM_ATC_L2_STATUS 0x06cb 1019#define regMM_ATC_L2_STATUS_BASE_IDX 1 1020#define regMM_ATC_L2_STATUS2 0x06cc 1021#define regMM_ATC_L2_STATUS2_BASE_IDX 1 1022#define regMM_ATC_L2_MISC_CG 0x06cd 1023#define regMM_ATC_L2_MISC_CG_BASE_IDX 1 1024#define regMM_ATC_L2_MEM_POWER_LS 0x06ce 1025#define regMM_ATC_L2_MEM_POWER_LS_BASE_IDX 1 1026#define regMM_ATC_L2_CGTT_CLK_CTRL 0x06cf 1027#define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 1028#define regMM_ATC_L2_SDPPORT_CTRL 0x06d2 1029#define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 1 1030 1031 1032// addressBlock: mmhub_mmutcl2_mmvml2pfdec 1033// base address: 0x69c00 1034#define regMMVM_L2_CNTL 0x0700 1035#define regMMVM_L2_CNTL_BASE_IDX 1 1036#define regMMVM_L2_CNTL2 0x0701 1037#define regMMVM_L2_CNTL2_BASE_IDX 1 1038#define regMMVM_L2_CNTL3 0x0702 1039#define regMMVM_L2_CNTL3_BASE_IDX 1 1040#define regMMVM_L2_STATUS 0x0703 1041#define regMMVM_L2_STATUS_BASE_IDX 1 1042#define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0704 1043#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 1044#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0705 1045#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 1046#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0706 1047#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 1048#define regMMVM_INVALIDATE_CNTL 0x0707 1049#define regMMVM_INVALIDATE_CNTL_BASE_IDX 1 1050#define regMMVM_L2_PROTECTION_FAULT_CNTL 0x0708 1051#define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 1052#define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x0709 1053#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 1054#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x070a 1055#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 1056#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x070b 1057#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 1058#define regMMVM_L2_PROTECTION_FAULT_STATUS 0x070c 1059#define regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 1060#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x070d 1061#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 1062#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x070e 1063#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 1064#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x070f 1065#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 1066#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0710 1067#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 1068#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0712 1069#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 1070#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0713 1071#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 1072#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0714 1073#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 1074#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0715 1075#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 1076#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0716 1077#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 1078#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0717 1079#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 1080#define regMMVM_L2_CNTL4 0x0718 1081#define regMMVM_L2_CNTL4_BASE_IDX 1 1082#define regMMVM_L2_MM_GROUP_RT_CLASSES 0x0719 1083#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 1084#define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x071a 1085#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 1086#define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x071b 1087#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 1088#define regMMVM_L2_CACHE_PARITY_CNTL 0x071c 1089#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 1090#define regMMVM_L2_CGTT_CLK_CTRL 0x071d 1091#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 1 1092#define regMMVM_L2_CNTL5 0x071e 1093#define regMMVM_L2_CNTL5_BASE_IDX 1 1094#define regMMVM_L2_GCR_CNTL 0x071f 1095#define regMMVM_L2_GCR_CNTL_BASE_IDX 1 1096#define regMMVM_L2_CGTT_BUSY_CTRL 0x0720 1097#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 1 1098#define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0721 1099#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 1 1100#define regMMVM_L2_PTE_CACHE_DUMP_READ 0x0722 1101#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 1 1102#define regMMVM_L2_BANK_SELECT_MASKS 0x0725 1103#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 1 1104#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0726 1105#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 1 1106#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0727 1107#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 1 1108#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x0728 1109#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 1 1110#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x0729 1111#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 1 1112#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x072a 1113#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1 1114 1115 1116// addressBlock: mmhub_mmutcl2_mmvml2vcdec 1117// base address: 0x69d00 1118#define regMMVM_CONTEXT0_CNTL 0x0740 1119#define regMMVM_CONTEXT0_CNTL_BASE_IDX 1 1120#define regMMVM_CONTEXT1_CNTL 0x0741 1121#define regMMVM_CONTEXT1_CNTL_BASE_IDX 1 1122#define regMMVM_CONTEXT2_CNTL 0x0742 1123#define regMMVM_CONTEXT2_CNTL_BASE_IDX 1 1124#define regMMVM_CONTEXT3_CNTL 0x0743 1125#define regMMVM_CONTEXT3_CNTL_BASE_IDX 1 1126#define regMMVM_CONTEXT4_CNTL 0x0744 1127#define regMMVM_CONTEXT4_CNTL_BASE_IDX 1 1128#define regMMVM_CONTEXT5_CNTL 0x0745 1129#define regMMVM_CONTEXT5_CNTL_BASE_IDX 1 1130#define regMMVM_CONTEXT6_CNTL 0x0746 1131#define regMMVM_CONTEXT6_CNTL_BASE_IDX 1 1132#define regMMVM_CONTEXT7_CNTL 0x0747 1133#define regMMVM_CONTEXT7_CNTL_BASE_IDX 1 1134#define regMMVM_CONTEXT8_CNTL 0x0748 1135#define regMMVM_CONTEXT8_CNTL_BASE_IDX 1 1136#define regMMVM_CONTEXT9_CNTL 0x0749 1137#define regMMVM_CONTEXT9_CNTL_BASE_IDX 1 1138#define regMMVM_CONTEXT10_CNTL 0x074a 1139#define regMMVM_CONTEXT10_CNTL_BASE_IDX 1 1140#define regMMVM_CONTEXT11_CNTL 0x074b 1141#define regMMVM_CONTEXT11_CNTL_BASE_IDX 1 1142#define regMMVM_CONTEXT12_CNTL 0x074c 1143#define regMMVM_CONTEXT12_CNTL_BASE_IDX 1 1144#define regMMVM_CONTEXT13_CNTL 0x074d 1145#define regMMVM_CONTEXT13_CNTL_BASE_IDX 1 1146#define regMMVM_CONTEXT14_CNTL 0x074e 1147#define regMMVM_CONTEXT14_CNTL_BASE_IDX 1 1148#define regMMVM_CONTEXT15_CNTL 0x074f 1149#define regMMVM_CONTEXT15_CNTL_BASE_IDX 1 1150#define regMMVM_CONTEXTS_DISABLE 0x0750 1151#define regMMVM_CONTEXTS_DISABLE_BASE_IDX 1 1152#define regMMVM_INVALIDATE_ENG0_SEM 0x0751 1153#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 1 1154#define regMMVM_INVALIDATE_ENG1_SEM 0x0752 1155#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 1 1156#define regMMVM_INVALIDATE_ENG2_SEM 0x0753 1157#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 1 1158#define regMMVM_INVALIDATE_ENG3_SEM 0x0754 1159#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 1 1160#define regMMVM_INVALIDATE_ENG4_SEM 0x0755 1161#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 1 1162#define regMMVM_INVALIDATE_ENG5_SEM 0x0756 1163#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 1 1164#define regMMVM_INVALIDATE_ENG6_SEM 0x0757 1165#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 1 1166#define regMMVM_INVALIDATE_ENG7_SEM 0x0758 1167#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 1 1168#define regMMVM_INVALIDATE_ENG8_SEM 0x0759 1169#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 1 1170#define regMMVM_INVALIDATE_ENG9_SEM 0x075a 1171#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 1 1172#define regMMVM_INVALIDATE_ENG10_SEM 0x075b 1173#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 1 1174#define regMMVM_INVALIDATE_ENG11_SEM 0x075c 1175#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 1 1176#define regMMVM_INVALIDATE_ENG12_SEM 0x075d 1177#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 1 1178#define regMMVM_INVALIDATE_ENG13_SEM 0x075e 1179#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 1 1180#define regMMVM_INVALIDATE_ENG14_SEM 0x075f 1181#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 1 1182#define regMMVM_INVALIDATE_ENG15_SEM 0x0760 1183#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 1 1184#define regMMVM_INVALIDATE_ENG16_SEM 0x0761 1185#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 1 1186#define regMMVM_INVALIDATE_ENG17_SEM 0x0762 1187#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 1 1188#define regMMVM_INVALIDATE_ENG0_REQ 0x0763 1189#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 1 1190#define regMMVM_INVALIDATE_ENG1_REQ 0x0764 1191#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 1 1192#define regMMVM_INVALIDATE_ENG2_REQ 0x0765 1193#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 1 1194#define regMMVM_INVALIDATE_ENG3_REQ 0x0766 1195#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 1 1196#define regMMVM_INVALIDATE_ENG4_REQ 0x0767 1197#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 1 1198#define regMMVM_INVALIDATE_ENG5_REQ 0x0768 1199#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 1 1200#define regMMVM_INVALIDATE_ENG6_REQ 0x0769 1201#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 1 1202#define regMMVM_INVALIDATE_ENG7_REQ 0x076a 1203#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 1 1204#define regMMVM_INVALIDATE_ENG8_REQ 0x076b 1205#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 1 1206#define regMMVM_INVALIDATE_ENG9_REQ 0x076c 1207#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 1 1208#define regMMVM_INVALIDATE_ENG10_REQ 0x076d 1209#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 1 1210#define regMMVM_INVALIDATE_ENG11_REQ 0x076e 1211#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 1 1212#define regMMVM_INVALIDATE_ENG12_REQ 0x076f 1213#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 1 1214#define regMMVM_INVALIDATE_ENG13_REQ 0x0770 1215#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 1 1216#define regMMVM_INVALIDATE_ENG14_REQ 0x0771 1217#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 1 1218#define regMMVM_INVALIDATE_ENG15_REQ 0x0772 1219#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 1 1220#define regMMVM_INVALIDATE_ENG16_REQ 0x0773 1221#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 1 1222#define regMMVM_INVALIDATE_ENG17_REQ 0x0774 1223#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 1 1224#define regMMVM_INVALIDATE_ENG0_ACK 0x0775 1225#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 1 1226#define regMMVM_INVALIDATE_ENG1_ACK 0x0776 1227#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 1 1228#define regMMVM_INVALIDATE_ENG2_ACK 0x0777 1229#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 1 1230#define regMMVM_INVALIDATE_ENG3_ACK 0x0778 1231#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 1 1232#define regMMVM_INVALIDATE_ENG4_ACK 0x0779 1233#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 1 1234#define regMMVM_INVALIDATE_ENG5_ACK 0x077a 1235#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 1 1236#define regMMVM_INVALIDATE_ENG6_ACK 0x077b 1237#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 1 1238#define regMMVM_INVALIDATE_ENG7_ACK 0x077c 1239#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 1 1240#define regMMVM_INVALIDATE_ENG8_ACK 0x077d 1241#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 1 1242#define regMMVM_INVALIDATE_ENG9_ACK 0x077e 1243#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 1 1244#define regMMVM_INVALIDATE_ENG10_ACK 0x077f 1245#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 1 1246#define regMMVM_INVALIDATE_ENG11_ACK 0x0780 1247#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 1 1248#define regMMVM_INVALIDATE_ENG12_ACK 0x0781 1249#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 1 1250#define regMMVM_INVALIDATE_ENG13_ACK 0x0782 1251#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 1 1252#define regMMVM_INVALIDATE_ENG14_ACK 0x0783 1253#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 1 1254#define regMMVM_INVALIDATE_ENG15_ACK 0x0784 1255#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 1 1256#define regMMVM_INVALIDATE_ENG16_ACK 0x0785 1257#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 1 1258#define regMMVM_INVALIDATE_ENG17_ACK 0x0786 1259#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 1 1260#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0787 1261#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 1262#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0788 1263#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 1264#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0789 1265#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 1266#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x078a 1267#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 1268#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x078b 1269#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 1270#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x078c 1271#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 1272#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x078d 1273#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 1274#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x078e 1275#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 1276#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x078f 1277#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 1278#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0790 1279#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 1280#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0791 1281#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 1282#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0792 1283#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 1284#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0793 1285#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 1286#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0794 1287#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 1288#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0795 1289#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 1290#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0796 1291#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 1292#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0797 1293#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 1294#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0798 1295#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 1296#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0799 1297#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 1298#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x079a 1299#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 1300#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x079b 1301#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 1302#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x079c 1303#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 1304#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x079d 1305#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 1306#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x079e 1307#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 1308#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x079f 1309#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 1310#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x07a0 1311#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 1312#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x07a1 1313#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 1314#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x07a2 1315#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 1316#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x07a3 1317#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 1318#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x07a4 1319#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 1320#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x07a5 1321#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 1322#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x07a6 1323#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 1324#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x07a7 1325#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 1326#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x07a8 1327#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 1328#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x07a9 1329#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 1330#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x07aa 1331#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 1332#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x07ab 1333#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1334#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x07ac 1335#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1336#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x07ad 1337#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1338#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x07ae 1339#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1340#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x07af 1341#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1342#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x07b0 1343#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1344#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x07b1 1345#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1346#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x07b2 1347#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1348#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x07b3 1349#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1350#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x07b4 1351#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1352#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x07b5 1353#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1354#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x07b6 1355#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1356#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x07b7 1357#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1358#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x07b8 1359#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1360#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x07b9 1361#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1362#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x07ba 1363#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1364#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x07bb 1365#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1366#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x07bc 1367#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1368#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x07bd 1369#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1370#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x07be 1371#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1372#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x07bf 1373#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1374#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x07c0 1375#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1376#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x07c1 1377#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1378#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x07c2 1379#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1380#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x07c3 1381#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1382#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x07c4 1383#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1384#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x07c5 1385#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1386#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x07c6 1387#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1388#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x07c7 1389#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1390#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x07c8 1391#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1392#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x07c9 1393#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1394#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x07ca 1395#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1396#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x07cb 1397#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1398#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x07cc 1399#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1400#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x07cd 1401#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1402#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x07ce 1403#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1404#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x07cf 1405#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1406#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x07d0 1407#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1408#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x07d1 1409#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1410#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x07d2 1411#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1412#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x07d3 1413#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1414#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x07d4 1415#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1416#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x07d5 1417#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1418#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x07d6 1419#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1420#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x07d7 1421#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1422#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x07d8 1423#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1424#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x07d9 1425#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1426#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x07da 1427#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1428#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x07db 1429#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1430#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x07dc 1431#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1432#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x07dd 1433#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1434#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x07de 1435#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1436#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x07df 1437#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1438#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x07e0 1439#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1440#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x07e1 1441#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1442#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x07e2 1443#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1444#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x07e3 1445#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1446#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x07e4 1447#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1448#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x07e5 1449#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1450#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x07e6 1451#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1452#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x07e7 1453#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1454#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x07e8 1455#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1456#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x07e9 1457#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1458#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x07ea 1459#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1460#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x07eb 1461#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1462#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x07ec 1463#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1464#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x07ed 1465#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1466#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x07ee 1467#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1468#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x07ef 1469#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1470#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x07f0 1471#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1472#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x07f1 1473#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1474#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x07f2 1475#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1476#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x07f3 1477#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1478#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x07f4 1479#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1480#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x07f5 1481#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1482#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x07f6 1483#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1484#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x07f7 1485#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1486#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x07f8 1487#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1488#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x07f9 1489#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1490#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x07fa 1491#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1492#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x07fb 1493#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1494#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x07fc 1495#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1496#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x07fd 1497#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1498#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x07fe 1499#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1500#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x07ff 1501#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1502#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0800 1503#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1504#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0801 1505#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1506#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0802 1507#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1508#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0803 1509#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1510#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0804 1511#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1512#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0805 1513#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1514#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0806 1515#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1516#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0807 1517#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1518#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0808 1519#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1520#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0809 1521#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1522#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x080a 1523#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1524#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080b 1525#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1526#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080c 1527#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1528#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080d 1529#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1530#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080e 1531#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1532#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080f 1533#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1534#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0810 1535#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1536#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0811 1537#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1538#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0812 1539#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1540#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0813 1541#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1542#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0814 1543#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1544#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0815 1545#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1546#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0816 1547#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1548#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0817 1549#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1550#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0818 1551#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1552#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0819 1553#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1554#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081a 1555#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1556#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081b 1557#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1558 1559 1560// addressBlock: mmhub_mmutcl2_mmvml2pldec 1561// base address: 0x6a090 1562#define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x0824 1563#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 1564#define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x0825 1565#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 1566#define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x0826 1567#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 1568#define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x0827 1569#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 1570#define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x0828 1571#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 1572#define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x0829 1573#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 1574#define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x082a 1575#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 1576#define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x082b 1577#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 1578#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x082c 1579#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1580#define regMMUTCL2_PERFCOUNTER0_CFG 0x082d 1581#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 1582#define regMMUTCL2_PERFCOUNTER1_CFG 0x082e 1583#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 1584#define regMMUTCL2_PERFCOUNTER2_CFG 0x082f 1585#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 1586#define regMMUTCL2_PERFCOUNTER3_CFG 0x0830 1587#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 1588#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x0831 1589#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1590 1591 1592// addressBlock: mmhub_mmutcl2_mmvml2prdec 1593// base address: 0x6a0e0 1594#define regMMMC_VM_L2_PERFCOUNTER_LO 0x0838 1595#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 1596#define regMMMC_VM_L2_PERFCOUNTER_HI 0x0839 1597#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 1598#define regMMUTCL2_PERFCOUNTER_LO 0x083a 1599#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 1 1600#define regMMUTCL2_PERFCOUNTER_HI 0x083b 1601#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 1 1602 1603 1604// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 1605// base address: 0x6a130 1606#define regMMVM_PCIE_ATS_CNTL 0x084c 1607#define regMMVM_PCIE_ATS_CNTL_BASE_IDX 1 1608 1609 1610// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 1611// base address: 0x6a340 1612#define regMMMC_VM_NB_MMIOBASE 0x08d0 1613#define regMMMC_VM_NB_MMIOBASE_BASE_IDX 1 1614#define regMMMC_VM_NB_MMIOLIMIT 0x08d1 1615#define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX 1 1616#define regMMMC_VM_NB_PCI_CTRL 0x08d2 1617#define regMMMC_VM_NB_PCI_CTRL_BASE_IDX 1 1618#define regMMMC_VM_NB_PCI_ARB 0x08d3 1619#define regMMMC_VM_NB_PCI_ARB_BASE_IDX 1 1620#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x08d4 1621#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 1622#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x08d5 1623#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 1624#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x08d6 1625#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 1626#define regMMMC_VM_FB_OFFSET 0x08d7 1627#define regMMMC_VM_FB_OFFSET_BASE_IDX 1 1628#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x08d8 1629#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 1630#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x08d9 1631#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 1632#define regMMMC_VM_STEERING 0x08da 1633#define regMMMC_VM_STEERING_BASE_IDX 1 1634#define regMMMC_SHARED_VIRT_RESET_REQ 0x08db 1635#define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 1636#define regMMMC_MEM_POWER_LS 0x08dc 1637#define regMMMC_MEM_POWER_LS_BASE_IDX 1 1638#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x08dd 1639#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 1640#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x08de 1641#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 1642#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x08df 1643#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 1 1644#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x08e0 1645#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 1 1646#define regMMMC_VM_APT_CNTL 0x08e1 1647#define regMMMC_VM_APT_CNTL_BASE_IDX 1 1648#define regMMMC_VM_LOCAL_FB_ADDRESS_START 0x08e2 1649#define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 1 1650#define regMMMC_VM_LOCAL_FB_ADDRESS_END 0x08e3 1651#define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 1 1652#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x08e4 1653#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 1 1654#define regMMUTCL2_CGTT_CLK_CTRL 0x08e5 1655#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 1656#define regMMMC_SHARED_ACTIVE_FCN_ID 0x08e6 1657#define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 1658#define regMMUTCL2_CGTT_BUSY_CTRL 0x08e7 1659#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 1 1660#define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x08e8 1661#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 1 1662#define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x08ea 1663#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 1 1664 1665 1666// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 1667// base address: 0x6a3b0 1668#define regMMMC_VM_FB_LOCATION_BASE 0x08ec 1669#define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 1 1670#define regMMMC_VM_FB_LOCATION_TOP 0x08ed 1671#define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX 1 1672#define regMMMC_VM_AGP_TOP 0x08ee 1673#define regMMMC_VM_AGP_TOP_BASE_IDX 1 1674#define regMMMC_VM_AGP_BOT 0x08ef 1675#define regMMMC_VM_AGP_BOT_BASE_IDX 1 1676#define regMMMC_VM_AGP_BASE 0x08f0 1677#define regMMMC_VM_AGP_BASE_BASE_IDX 1 1678#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x08f1 1679#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 1680#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08f2 1681#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 1682#define regMMMC_VM_MX_L1_TLB_CNTL 0x08f3 1683#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 1684 1685 1686// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 1687// base address: 0x6a400 1688#define regMM_ATC_L2_PERFCOUNTER_LO 0x0900 1689#define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 1690#define regMM_ATC_L2_PERFCOUNTER_HI 0x0901 1691#define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 1692 1693 1694// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 1695// base address: 0x6a420 1696#define regMM_ATC_L2_PERFCOUNTER0_CFG 0x0908 1697#define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 1698#define regMM_ATC_L2_PERFCOUNTER1_CFG 0x0909 1699#define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 1700#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x090a 1701#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1702 1703 1704// addressBlock: mmhub_mmutcl2_mmvml2pspdec 1705// base address: 0x6aa50 1706#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID 0x0a94 1707#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 1708#define regMMVM_IOMMU_CONTROL_REGISTER 0x0a97 1709#define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 1710#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0a98 1711#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 1712#define regMMUTC_TRANSLATION_FAULT_CNTL0 0x0a99 1713#define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1 1714#define regMMUTC_TRANSLATION_FAULT_CNTL1 0x0a9a 1715#define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1 1716 1717 1718// addressBlock: mmhub_mmutcl2_mml2tlbpspdec 1719// base address: 0x6aa80 1720#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x0aa0 1721#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1 1722 1723 1724// addressBlock: mmhub_mmutcl2_mmatcl2pspdec 1725// base address: 0x6aa90 1726#define regMM_ATC_L2_IOV_MODE_CNTL 0x0aa4 1727#define regMM_ATC_L2_IOV_MODE_CNTL_BASE_IDX 1 1728 1729 1730// addressBlock: mmhub_mmutcl2_mml2tlbpfdec 1731// base address: 0x6aac0 1732#define regMML2TLB_TLB0_STATUS 0x0ab1 1733#define regMML2TLB_TLB0_STATUS_BASE_IDX 1 1734#define regMML2TLB_TMZ_CNTL 0x0ab2 1735#define regMML2TLB_TMZ_CNTL_BASE_IDX 1 1736#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0ab3 1737#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 1 1738#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0ab4 1739#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 1 1740#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0ab5 1741#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 1 1742#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0ab6 1743#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 1 1744#define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 0x0ab7 1745#define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1 1746 1747 1748// addressBlock: mmhub_mmutcl2_mml2tlbpldec 1749// base address: 0x6ab00 1750#define regMML2TLB_PERFCOUNTER0_CFG 0x0ac0 1751#define regMML2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 1752#define regMML2TLB_PERFCOUNTER1_CFG 0x0ac1 1753#define regMML2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 1754#define regMML2TLB_PERFCOUNTER2_CFG 0x0ac2 1755#define regMML2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 1756#define regMML2TLB_PERFCOUNTER3_CFG 0x0ac3 1757#define regMML2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 1758#define regMML2TLB_PERFCOUNTER_RSLT_CNTL 0x0ac4 1759#define regMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1760 1761 1762// addressBlock: mmhub_mmutcl2_mml2tlbprdec 1763// base address: 0x6ab20 1764#define regMML2TLB_PERFCOUNTER_LO 0x0ac8 1765#define regMML2TLB_PERFCOUNTER_LO_BASE_IDX 1 1766#define regMML2TLB_PERFCOUNTER_HI 0x0ac9 1767#define regMML2TLB_PERFCOUNTER_HI_BASE_IDX 1 1768 1769#endif
~/
Read-only file preview.