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mmhub_2_3_0_offset.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_offset.h
1/* 2 * Copyright (C) 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _mmhub_2_3_0_OFFSET_HEADER 22#define _mmhub_2_3_0_OFFSET_HEADER 23 24 25 26// addressBlock: mmhub_dagbdec 27// base address: 0x68000 28#define mmDAGB0_RDCLI0 0x0000 29#define mmDAGB0_RDCLI0_BASE_IDX 1 30#define mmDAGB0_RDCLI1 0x0001 31#define mmDAGB0_RDCLI1_BASE_IDX 1 32#define mmDAGB0_RDCLI2 0x0002 33#define mmDAGB0_RDCLI2_BASE_IDX 1 34#define mmDAGB0_RDCLI3 0x0003 35#define mmDAGB0_RDCLI3_BASE_IDX 1 36#define mmDAGB0_RDCLI4 0x0004 37#define mmDAGB0_RDCLI4_BASE_IDX 1 38#define mmDAGB0_RDCLI5 0x0005 39#define mmDAGB0_RDCLI5_BASE_IDX 1 40#define mmDAGB0_RDCLI6 0x0006 41#define mmDAGB0_RDCLI6_BASE_IDX 1 42#define mmDAGB0_RDCLI7 0x0007 43#define mmDAGB0_RDCLI7_BASE_IDX 1 44#define mmDAGB0_RDCLI8 0x0008 45#define mmDAGB0_RDCLI8_BASE_IDX 1 46#define mmDAGB0_RDCLI9 0x0009 47#define mmDAGB0_RDCLI9_BASE_IDX 1 48#define mmDAGB0_RDCLI10 0x000a 49#define mmDAGB0_RDCLI10_BASE_IDX 1 50#define mmDAGB0_RDCLI11 0x000b 51#define mmDAGB0_RDCLI11_BASE_IDX 1 52#define mmDAGB0_RDCLI12 0x000c 53#define mmDAGB0_RDCLI12_BASE_IDX 1 54#define mmDAGB0_RDCLI13 0x000d 55#define mmDAGB0_RDCLI13_BASE_IDX 1 56#define mmDAGB0_RDCLI14 0x000e 57#define mmDAGB0_RDCLI14_BASE_IDX 1 58#define mmDAGB0_RDCLI15 0x000f 59#define mmDAGB0_RDCLI15_BASE_IDX 1 60#define mmDAGB0_RDCLI16 0x0010 61#define mmDAGB0_RDCLI16_BASE_IDX 1 62#define mmDAGB0_RDCLI17 0x0011 63#define mmDAGB0_RDCLI17_BASE_IDX 1 64#define mmDAGB0_RDCLI18 0x0012 65#define mmDAGB0_RDCLI18_BASE_IDX 1 66#define mmDAGB0_RDCLI19 0x0013 67#define mmDAGB0_RDCLI19_BASE_IDX 1 68#define mmDAGB0_RDCLI20 0x0014 69#define mmDAGB0_RDCLI20_BASE_IDX 1 70#define mmDAGB0_RDCLI21 0x0015 71#define mmDAGB0_RDCLI21_BASE_IDX 1 72#define mmDAGB0_RDCLI22 0x0016 73#define mmDAGB0_RDCLI22_BASE_IDX 1 74#define mmDAGB0_RDCLI23 0x0017 75#define mmDAGB0_RDCLI23_BASE_IDX 1 76#define mmDAGB0_RDCLI24 0x0018 77#define mmDAGB0_RDCLI24_BASE_IDX 1 78#define mmDAGB0_RDCLI25 0x0019 79#define mmDAGB0_RDCLI25_BASE_IDX 1 80#define mmDAGB0_RDCLI26 0x001a 81#define mmDAGB0_RDCLI26_BASE_IDX 1 82#define mmDAGB0_RDCLI27 0x001b 83#define mmDAGB0_RDCLI27_BASE_IDX 1 84#define mmDAGB0_RDCLI28 0x001c 85#define mmDAGB0_RDCLI28_BASE_IDX 1 86#define mmDAGB0_RDCLI29 0x001d 87#define mmDAGB0_RDCLI29_BASE_IDX 1 88#define mmDAGB0_RDCLI30 0x001e 89#define mmDAGB0_RDCLI30_BASE_IDX 1 90#define mmDAGB0_RD_CNTL 0x001f 91#define mmDAGB0_RD_CNTL_BASE_IDX 1 92#define mmDAGB0_RD_GMI_CNTL 0x0020 93#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 1 94#define mmDAGB0_RD_ADDR_DAGB 0x0021 95#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 1 96#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0022 97#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 98#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0023 99#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 100#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0024 101#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1 102#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0025 103#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 104#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0026 105#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 106#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0027 107#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 108#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0028 109#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 110#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0029 111#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 112#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x002a 113#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 114#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x002b 115#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 116#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x002c 117#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 118#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3 0x002d 119#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 120#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3 0x002e 121#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 122#define mmDAGB0_RD_VC0_CNTL 0x002f 123#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 1 124#define mmDAGB0_RD_VC1_CNTL 0x0030 125#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 1 126#define mmDAGB0_RD_VC2_CNTL 0x0031 127#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 1 128#define mmDAGB0_RD_VC3_CNTL 0x0032 129#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 1 130#define mmDAGB0_RD_VC4_CNTL 0x0033 131#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 1 132#define mmDAGB0_RD_VC5_CNTL 0x0034 133#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 1 134#define mmDAGB0_RD_VC6_CNTL 0x0035 135#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 1 136#define mmDAGB0_RD_VC7_CNTL 0x0036 137#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 1 138#define mmDAGB0_RD_CNTL_MISC 0x0037 139#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 1 140#define mmDAGB0_RD_TLB_CREDIT 0x0038 141#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 1 142#define mmDAGB0_RD_RDRET_CREDIT_CNTL 0x0039 143#define mmDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 1 144#define mmDAGB0_RD_RDRET_CREDIT_CNTL2 0x003a 145#define mmDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 1 146#define mmDAGB0_RDCLI_ASK_PENDING 0x003b 147#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1 148#define mmDAGB0_RDCLI_GO_PENDING 0x003c 149#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 1 150#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x003d 151#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1 152#define mmDAGB0_RDCLI_TLB_PENDING 0x003e 153#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1 154#define mmDAGB0_RDCLI_OARB_PENDING 0x003f 155#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1 156#define mmDAGB0_RDCLI_OSD_PENDING 0x0040 157#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1 158#define mmDAGB0_WRCLI0 0x0041 159#define mmDAGB0_WRCLI0_BASE_IDX 1 160#define mmDAGB0_WRCLI1 0x0042 161#define mmDAGB0_WRCLI1_BASE_IDX 1 162#define mmDAGB0_WRCLI2 0x0043 163#define mmDAGB0_WRCLI2_BASE_IDX 1 164#define mmDAGB0_WRCLI3 0x0044 165#define mmDAGB0_WRCLI3_BASE_IDX 1 166#define mmDAGB0_WRCLI4 0x0045 167#define mmDAGB0_WRCLI4_BASE_IDX 1 168#define mmDAGB0_WRCLI5 0x0046 169#define mmDAGB0_WRCLI5_BASE_IDX 1 170#define mmDAGB0_WRCLI6 0x0047 171#define mmDAGB0_WRCLI6_BASE_IDX 1 172#define mmDAGB0_WRCLI7 0x0048 173#define mmDAGB0_WRCLI7_BASE_IDX 1 174#define mmDAGB0_WRCLI8 0x0049 175#define mmDAGB0_WRCLI8_BASE_IDX 1 176#define mmDAGB0_WRCLI9 0x004a 177#define mmDAGB0_WRCLI9_BASE_IDX 1 178#define mmDAGB0_WRCLI10 0x004b 179#define mmDAGB0_WRCLI10_BASE_IDX 1 180#define mmDAGB0_WRCLI11 0x004c 181#define mmDAGB0_WRCLI11_BASE_IDX 1 182#define mmDAGB0_WRCLI12 0x004d 183#define mmDAGB0_WRCLI12_BASE_IDX 1 184#define mmDAGB0_WRCLI13 0x004e 185#define mmDAGB0_WRCLI13_BASE_IDX 1 186#define mmDAGB0_WRCLI14 0x004f 187#define mmDAGB0_WRCLI14_BASE_IDX 1 188#define mmDAGB0_WRCLI15 0x0050 189#define mmDAGB0_WRCLI15_BASE_IDX 1 190#define mmDAGB0_WRCLI16 0x0051 191#define mmDAGB0_WRCLI16_BASE_IDX 1 192#define mmDAGB0_WRCLI17 0x0052 193#define mmDAGB0_WRCLI17_BASE_IDX 1 194#define mmDAGB0_WRCLI18 0x0053 195#define mmDAGB0_WRCLI18_BASE_IDX 1 196#define mmDAGB0_WRCLI19 0x0054 197#define mmDAGB0_WRCLI19_BASE_IDX 1 198#define mmDAGB0_WRCLI20 0x0055 199#define mmDAGB0_WRCLI20_BASE_IDX 1 200#define mmDAGB0_WRCLI21 0x0056 201#define mmDAGB0_WRCLI21_BASE_IDX 1 202#define mmDAGB0_WRCLI22 0x0057 203#define mmDAGB0_WRCLI22_BASE_IDX 1 204#define mmDAGB0_WRCLI23 0x0058 205#define mmDAGB0_WRCLI23_BASE_IDX 1 206#define mmDAGB0_WRCLI24 0x0059 207#define mmDAGB0_WRCLI24_BASE_IDX 1 208#define mmDAGB0_WRCLI25 0x005a 209#define mmDAGB0_WRCLI25_BASE_IDX 1 210#define mmDAGB0_WRCLI26 0x005b 211#define mmDAGB0_WRCLI26_BASE_IDX 1 212#define mmDAGB0_WRCLI27 0x005c 213#define mmDAGB0_WRCLI27_BASE_IDX 1 214#define mmDAGB0_WRCLI28 0x005d 215#define mmDAGB0_WRCLI28_BASE_IDX 1 216#define mmDAGB0_WRCLI29 0x005e 217#define mmDAGB0_WRCLI29_BASE_IDX 1 218#define mmDAGB0_WRCLI30 0x005f 219#define mmDAGB0_WRCLI30_BASE_IDX 1 220#define mmDAGB0_WR_CNTL 0x0060 221#define mmDAGB0_WR_CNTL_BASE_IDX 1 222#define mmDAGB0_WR_GMI_CNTL 0x0061 223#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 1 224#define mmDAGB0_WR_ADDR_DAGB 0x0062 225#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 1 226#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0063 227#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 228#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0064 229#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 230#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0065 231#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1 232#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0066 233#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 234#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0067 235#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 236#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0068 237#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 238#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0069 239#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 240#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x006a 241#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 242#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x006b 243#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 244#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x006c 245#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 246#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x006d 247#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 248#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3 0x006e 249#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 250#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3 0x006f 251#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 252#define mmDAGB0_WR_DATA_DAGB 0x0070 253#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 1 254#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0071 255#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 256#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0072 257#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 258#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0073 259#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 260#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0074 261#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 262#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0075 263#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 1 264#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0076 265#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 1 266#define mmDAGB0_WR_DATA_DAGB_MAX_BURST3 0x0077 267#define mmDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX 1 268#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3 0x0078 269#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX 1 270#define mmDAGB0_WR_VC0_CNTL 0x0079 271#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 1 272#define mmDAGB0_WR_VC1_CNTL 0x007a 273#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 1 274#define mmDAGB0_WR_VC2_CNTL 0x007b 275#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 1 276#define mmDAGB0_WR_VC3_CNTL 0x007c 277#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 1 278#define mmDAGB0_WR_VC4_CNTL 0x007d 279#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 1 280#define mmDAGB0_WR_VC5_CNTL 0x007e 281#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 1 282#define mmDAGB0_WR_VC6_CNTL 0x007f 283#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 1 284#define mmDAGB0_WR_VC7_CNTL 0x0080 285#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 1 286#define mmDAGB0_WR_CNTL_MISC 0x0081 287#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 1 288#define mmDAGB0_WR_TLB_CREDIT 0x0082 289#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 1 290#define mmDAGB0_WR_DATA_CREDIT 0x0083 291#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 1 292#define mmDAGB0_WR_MISC_CREDIT 0x0084 293#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 1 294#define mmDAGB0_WR_OSD_CREDIT_CNTL1 0x0085 295#define mmDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX 1 296#define mmDAGB0_WR_OSD_CREDIT_CNTL2 0x0086 297#define mmDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX 1 298#define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x0087 299#define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 1 300#define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL2 0x0088 301#define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL2_BASE_IDX 1 302#define mmDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x0089 303#define mmDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 1 304#define mmDAGB0_WRCLI_ASK_PENDING 0x008a 305#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1 306#define mmDAGB0_WRCLI_GO_PENDING 0x008b 307#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 1 308#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x008c 309#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1 310#define mmDAGB0_WRCLI_TLB_PENDING 0x008d 311#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1 312#define mmDAGB0_WRCLI_OARB_PENDING 0x008e 313#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1 314#define mmDAGB0_WRCLI_OSD_PENDING 0x008f 315#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1 316#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x0090 317#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 318#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0091 319#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 320#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x0092 321#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1 322#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x0093 323#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1 324#define mmDAGB0_DAGB_DLY 0x0094 325#define mmDAGB0_DAGB_DLY_BASE_IDX 1 326#define mmDAGB0_CNTL_MISC 0x0095 327#define mmDAGB0_CNTL_MISC_BASE_IDX 1 328#define mmDAGB0_CNTL_MISC2 0x0096 329#define mmDAGB0_CNTL_MISC2_BASE_IDX 1 330#define mmDAGB0_FIFO_EMPTY 0x0097 331#define mmDAGB0_FIFO_EMPTY_BASE_IDX 1 332#define mmDAGB0_FIFO_FULL 0x0098 333#define mmDAGB0_FIFO_FULL_BASE_IDX 1 334#define mmDAGB0_WR_CREDITS_FULL 0x0099 335#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 1 336#define mmDAGB0_RD_CREDITS_FULL 0x009a 337#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 1 338#define mmDAGB0_PERFCOUNTER_LO 0x009b 339#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 1 340#define mmDAGB0_PERFCOUNTER_HI 0x009c 341#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 1 342#define mmDAGB0_PERFCOUNTER0_CFG 0x009d 343#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1 344#define mmDAGB0_PERFCOUNTER1_CFG 0x009e 345#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1 346#define mmDAGB0_PERFCOUNTER2_CFG 0x009f 347#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1 348#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x00a0 349#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 350#define mmDAGB0_RESERVE0 0x00a1 351#define mmDAGB0_RESERVE0_BASE_IDX 1 352#define mmDAGB0_RESERVE1 0x00a2 353#define mmDAGB0_RESERVE1_BASE_IDX 1 354#define mmDAGB0_RESERVE2 0x00a3 355#define mmDAGB0_RESERVE2_BASE_IDX 1 356#define mmDAGB0_RESERVE3 0x00a4 357#define mmDAGB0_RESERVE3_BASE_IDX 1 358#define mmDAGB0_RESERVE4 0x00a5 359#define mmDAGB0_RESERVE4_BASE_IDX 1 360#define mmDAGB0_RESERVE5 0x00a6 361#define mmDAGB0_RESERVE5_BASE_IDX 1 362#define mmDAGB0_RESERVE6 0x00a7 363#define mmDAGB0_RESERVE6_BASE_IDX 1 364#define mmDAGB0_RESERVE7 0x00a8 365#define mmDAGB0_RESERVE7_BASE_IDX 1 366#define mmDAGB0_RESERVE8 0x00a9 367#define mmDAGB0_RESERVE8_BASE_IDX 1 368#define mmDAGB0_RESERVE9 0x00aa 369#define mmDAGB0_RESERVE9_BASE_IDX 1 370 371 372// addressBlock: mmhub_mmea_mmeadec0 373// base address: 0x68400 374#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100 375#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 376#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101 377#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 378#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102 379#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 380#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103 381#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 382#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104 383#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 384#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105 385#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 386#define mmMMEA0_DRAM_RD_LAZY 0x0106 387#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 1 388#define mmMMEA0_DRAM_WR_LAZY 0x0107 389#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 1 390#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108 391#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 1 392#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109 393#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 1 394#define mmMMEA0_DRAM_PAGE_BURST 0x010a 395#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 1 396#define mmMMEA0_DRAM_RD_PRI_AGE 0x010b 397#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 1 398#define mmMMEA0_DRAM_WR_PRI_AGE 0x010c 399#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 1 400#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d 401#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 1 402#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e 403#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 1 404#define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f 405#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 1 406#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110 407#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 1 408#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111 409#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 1 410#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112 411#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 1 412#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113 413#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 414#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114 415#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 416#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115 417#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 418#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116 419#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 420#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117 421#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 422#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118 423#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 424#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0134 425#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 1 426#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0135 427#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 428#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0136 429#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 1 430#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0137 431#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 432#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0138 433#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 434#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0143 435#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 436#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0145 437#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 438#define mmMMEA0_ADDRDEC_BANK_CFG 0x0147 439#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 1 440#define mmMMEA0_ADDRDEC_MISC_CFG 0x0148 441#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 1 442#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0149 443#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 444#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x014a 445#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 446#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x014b 447#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 448#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x014c 449#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 450#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x014d 451#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 452#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 0x014e 453#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 454#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x014f 455#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 456#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x0150 457#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 458#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x0151 459#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 460#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x0152 461#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 462#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0153 463#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 464#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 0x0154 465#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_BASE_IDX 1 466#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 0x0155 467#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_BASE_IDX 1 468#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 0x0156 469#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_BASE_IDX 1 470#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 0x0157 471#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_BASE_IDX 1 472#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x0167 473#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 474#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0168 475#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 476#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x0169 477#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 478#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x016a 479#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 480#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x016b 481#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 482#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x016c 483#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 484#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x016d 485#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 486#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x016e 487#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 488#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x016f 489#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 490#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0170 491#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 492#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0171 493#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 494#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0172 495#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 496#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0173 497#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 498#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x0174 499#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 500#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x0175 501#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 502#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x0176 503#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 504#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x0177 505#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 506#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x0178 507#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 508#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0179 509#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 510#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x017a 511#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 512#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x017b 513#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 514#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x017c 515#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 516#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x017d 517#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 518#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x017e 519#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 520#define mmMMEA0_ADDRDEC0_RM_SEL_CS1 0x017f 521#define mmMMEA0_ADDRDEC0_RM_SEL_CS1_BASE_IDX 1 522#define mmMMEA0_ADDRDEC0_RM_SEL_CS3 0x0180 523#define mmMMEA0_ADDRDEC0_RM_SEL_CS3_BASE_IDX 1 524#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0181 525#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 526#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x0182 527#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 528#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x0183 529#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 530#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0184 531#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 532#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0185 533#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 534#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x0186 535#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 536#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x0187 537#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 538#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0188 539#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 540#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0189 541#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 542#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x018a 543#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 544#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x018b 545#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 546#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x018c 547#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 548#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x018d 549#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 550#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x018e 551#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 552#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x018f 553#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 554#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0190 555#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 556#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0191 557#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 558#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x0192 559#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 560#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x0193 561#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 562#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x0194 563#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 564#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x0195 565#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 566#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0196 567#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 568#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0197 569#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 570#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0198 571#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 572#define mmMMEA0_ADDRDEC1_RM_SEL_CS1 0x0199 573#define mmMMEA0_ADDRDEC1_RM_SEL_CS1_BASE_IDX 1 574#define mmMMEA0_ADDRDEC1_RM_SEL_CS3 0x019a 575#define mmMMEA0_ADDRDEC1_RM_SEL_CS3_BASE_IDX 1 576#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x01b5 577#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 578#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ0 0x01b7 579#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ0_BASE_IDX 1 580#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ1 0x01b8 581#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ1_BASE_IDX 1 582#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ2 0x01b9 583#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ2_BASE_IDX 1 584#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ3 0x01ba 585#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ3_BASE_IDX 1 586#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ4 0x01bb 587#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ4_BASE_IDX 1 588#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ5 0x01bc 589#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ5_BASE_IDX 1 590#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS1 0x01c3 591#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS1_BASE_IDX 1 592#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS3 0x01c4 593#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS3_BASE_IDX 1 594#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS1 0x01c5 595#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS1_BASE_IDX 1 596#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS3 0x01c6 597#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS3_BASE_IDX 1 598#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS1 0x01c7 599#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS1_BASE_IDX 1 600#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS3 0x01c8 601#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS3_BASE_IDX 1 602#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS1 0x01c9 603#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS1_BASE_IDX 1 604#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS3 0x01ca 605#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS3_BASE_IDX 1 606#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS1 0x01cb 607#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS1_BASE_IDX 1 608#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS3 0x01cc 609#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS3_BASE_IDX 1 610#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS1 0x01cd 611#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS1_BASE_IDX 1 612#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS3 0x01ce 613#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS3_BASE_IDX 1 614#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS1 0x01cf 615#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS1_BASE_IDX 1 616#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS3 0x01d0 617#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS3_BASE_IDX 1 618#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS1 0x01d1 619#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS1_BASE_IDX 1 620#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS3 0x01d2 621#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS3_BASE_IDX 1 622#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS1 0x01d3 623#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS1_BASE_IDX 1 624#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS3 0x01d4 625#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS3_BASE_IDX 1 626#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS1 0x01d5 627#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS1_BASE_IDX 1 628#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS3 0x01d6 629#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS3_BASE_IDX 1 630#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS1 0x01d7 631#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS1_BASE_IDX 1 632#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS3 0x01d8 633#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS3_BASE_IDX 1 634#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS1 0x01d9 635#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS1_BASE_IDX 1 636#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS3 0x01da 637#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS3_BASE_IDX 1 638#define mmMMEA0_ADDRNORMDRAM_MASKING 0x01db 639#define mmMMEA0_ADDRNORMDRAM_MASKING_BASE_IDX 1 640#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01dd 641#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 642#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01de 643#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 644#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01df 645#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 646#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01e0 647#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 648#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01e1 649#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 1 650#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01e2 651#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 1 652#define mmMMEA0_IO_GROUP_BURST 0x01e3 653#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 1 654#define mmMMEA0_IO_RD_PRI_AGE 0x01e4 655#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 1 656#define mmMMEA0_IO_WR_PRI_AGE 0x01e5 657#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 1 658#define mmMMEA0_IO_RD_PRI_QUEUING 0x01e6 659#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 1 660#define mmMMEA0_IO_WR_PRI_QUEUING 0x01e7 661#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 1 662#define mmMMEA0_IO_RD_PRI_FIXED 0x01e8 663#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 1 664#define mmMMEA0_IO_WR_PRI_FIXED 0x01e9 665#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 1 666#define mmMMEA0_IO_RD_PRI_URGENCY 0x01ea 667#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 1 668#define mmMMEA0_IO_WR_PRI_URGENCY 0x01eb 669#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 1 670#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0x01ec 671#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 672#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0x01ed 673#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 674#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01ee 675#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 676#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01ef 677#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 678#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01f0 679#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 680#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01f1 681#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 682#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01f2 683#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 684#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01f3 685#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 686#define mmMMEA0_SDP_ARB_DRAM 0x01f4 687#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 1 688#define mmMMEA0_SDP_ARB_FINAL 0x01f6 689#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 1 690#define mmMMEA0_SDP_DRAM_PRIORITY 0x01f7 691#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 1 692#define mmMMEA0_SDP_IO_PRIORITY 0x01f9 693#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 1 694#define mmMMEA0_SDP_CREDITS 0x01fa 695#define mmMMEA0_SDP_CREDITS_BASE_IDX 1 696#define mmMMEA0_SDP_TAG_RESERVE0 0x01fb 697#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 1 698#define mmMMEA0_SDP_TAG_RESERVE1 0x01fc 699#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 1 700#define mmMMEA0_SDP_VCC_RESERVE0 0x01fd 701#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 1 702#define mmMMEA0_SDP_VCC_RESERVE1 0x01fe 703#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 1 704#define mmMMEA0_SDP_VCD_RESERVE0 0x01ff 705#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 1 706#define mmMMEA0_SDP_VCD_RESERVE1 0x0200 707#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 1 708#define mmMMEA0_SDP_REQ_CNTL 0x0201 709#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 1 710#define mmMMEA0_MISC 0x0202 711#define mmMMEA0_MISC_BASE_IDX 1 712#define mmMMEA0_LATENCY_SAMPLING 0x0203 713#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 1 714#define mmMMEA0_PERFCOUNTER_LO 0x0204 715#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 1 716#define mmMMEA0_PERFCOUNTER_HI 0x0205 717#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 1 718#define mmMMEA0_PERFCOUNTER0_CFG 0x0206 719#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 1 720#define mmMMEA0_PERFCOUNTER1_CFG 0x0207 721#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 1 722#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0208 723#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 724#define mmMMEA0_EDC_CNT 0x020f 725#define mmMMEA0_EDC_CNT_BASE_IDX 1 726#define mmMMEA0_EDC_CNT2 0x0210 727#define mmMMEA0_EDC_CNT2_BASE_IDX 1 728#define mmMMEA0_DSM_CNTL 0x0211 729#define mmMMEA0_DSM_CNTL_BASE_IDX 1 730#define mmMMEA0_DSM_CNTLA 0x0212 731#define mmMMEA0_DSM_CNTLA_BASE_IDX 1 732#define mmMMEA0_DSM_CNTLB 0x0213 733#define mmMMEA0_DSM_CNTLB_BASE_IDX 1 734#define mmMMEA0_DSM_CNTL2 0x0214 735#define mmMMEA0_DSM_CNTL2_BASE_IDX 1 736#define mmMMEA0_DSM_CNTL2A 0x0215 737#define mmMMEA0_DSM_CNTL2A_BASE_IDX 1 738#define mmMMEA0_DSM_CNTL2B 0x0216 739#define mmMMEA0_DSM_CNTL2B_BASE_IDX 1 740#define mmMMEA0_CGTT_CLK_CTRL 0x0218 741#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 1 742#define mmMMEA0_EDC_MODE 0x0219 743#define mmMMEA0_EDC_MODE_BASE_IDX 1 744#define mmMMEA0_ERR_STATUS 0x021a 745#define mmMMEA0_ERR_STATUS_BASE_IDX 1 746#define mmMMEA0_MISC2 0x021b 747#define mmMMEA0_MISC2_BASE_IDX 1 748#define mmMMEA0_ADDRDEC_SELECT 0x021c 749#define mmMMEA0_ADDRDEC_SELECT_BASE_IDX 1 750#define mmMMEA0_EDC_CNT3 0x021d 751#define mmMMEA0_EDC_CNT3_BASE_IDX 1 752#define mmMMEA0_SDP_PRIORITY_OVERRIDE 0x021e 753#define mmMMEA0_SDP_PRIORITY_OVERRIDE_BASE_IDX 1 754#define mmMMEA0_MISC_AON 0x021f 755#define mmMMEA0_MISC_AON_BASE_IDX 1 756 757 758// addressBlock: mmhub_pctldec 759// base address: 0x68e00 760#define mmPCTL_CTRL 0x0380 761#define mmPCTL_CTRL_BASE_IDX 1 762#define mmPCTL_MMHUB_DEEPSLEEP_IB 0x0381 763#define mmPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 764#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 765#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 766#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0383 767#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 768#define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0384 769#define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 770#define mmPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0385 771#define mmPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 772#define mmPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0386 773#define mmPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 1 774#define mmPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0387 775#define mmPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 1 776#define mmPCTL_SLICE0_CFG_DS_ALLOW 0x0388 777#define mmPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 778#define mmPCTL_SLICE0_CFG_DS_ALLOW_IB 0x0389 779#define mmPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 780#define mmPCTL_SLICE1_CFG_DAGB_WRBUSY 0x038a 781#define mmPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 1 782#define mmPCTL_SLICE1_CFG_DAGB_RDBUSY 0x038b 783#define mmPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 1 784#define mmPCTL_SLICE1_CFG_DS_ALLOW 0x038c 785#define mmPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 786#define mmPCTL_SLICE1_CFG_DS_ALLOW_IB 0x038d 787#define mmPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 788#define mmPCTL_UTCL2_MISC 0x038e 789#define mmPCTL_UTCL2_MISC_BASE_IDX 1 790#define mmPCTL_SLICE0_MISC 0x038f 791#define mmPCTL_SLICE0_MISC_BASE_IDX 1 792#define mmPCTL_SLICE1_MISC 0x0390 793#define mmPCTL_SLICE1_MISC_BASE_IDX 1 794#define mmPCTL_RENG_CTRL 0x0391 795#define mmPCTL_RENG_CTRL_BASE_IDX 1 796#define mmPCTL_UTCL2_RENG_EXECUTE 0x0392 797#define mmPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 1 798#define mmPCTL_SLICE0_RENG_EXECUTE 0x0393 799#define mmPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 1 800#define mmPCTL_SLICE1_RENG_EXECUTE 0x0394 801#define mmPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 1 802#define mmPCTL_UTCL2_RENG_RAM_INDEX 0x0395 803#define mmPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 804#define mmPCTL_UTCL2_RENG_RAM_DATA 0x0396 805#define mmPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 1 806#define mmPCTL_SLICE0_RENG_RAM_INDEX 0x0397 807#define mmPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 808#define mmPCTL_SLICE0_RENG_RAM_DATA 0x0398 809#define mmPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 1 810#define mmPCTL_SLICE1_RENG_RAM_INDEX 0x0399 811#define mmPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 812#define mmPCTL_SLICE1_RENG_RAM_DATA 0x039a 813#define mmPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 1 814#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b 815#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 816#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c 817#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 818#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d 819#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 820#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x039e 821#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 822#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x039f 823#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 824#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a0 825#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 826#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a1 827#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 828#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x03a2 829#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 830#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x03a3 831#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 832#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x03a4 833#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 834#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x03a5 835#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 836#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x03a6 837#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 838#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a7 839#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 840#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a8 841#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 842#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x03a9 843#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 844#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x03aa 845#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 846#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x03ab 847#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 848#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x03ac 849#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 850#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x03ad 851#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 852#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03ae 853#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 854#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03af 855#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 856#define mmPCTL_STATUS 0x03b0 857#define mmPCTL_STATUS_BASE_IDX 1 858#define mmPCTL_PERFCOUNTER_LO 0x03b1 859#define mmPCTL_PERFCOUNTER_LO_BASE_IDX 1 860#define mmPCTL_PERFCOUNTER_HI 0x03b2 861#define mmPCTL_PERFCOUNTER_HI_BASE_IDX 1 862#define mmPCTL_PERFCOUNTER0_CFG 0x03b3 863#define mmPCTL_PERFCOUNTER0_CFG_BASE_IDX 1 864#define mmPCTL_PERFCOUNTER1_CFG 0x03b4 865#define mmPCTL_PERFCOUNTER1_CFG_BASE_IDX 1 866#define mmPCTL_PERFCOUNTER_RSLT_CNTL 0x03b5 867#define mmPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 868#define mmPCTL_RESERVED_0 0x03b6 869#define mmPCTL_RESERVED_0_BASE_IDX 1 870#define mmPCTL_RESERVED_1 0x03b7 871#define mmPCTL_RESERVED_1_BASE_IDX 1 872#define mmPCTL_RESERVED_2 0x03b8 873#define mmPCTL_RESERVED_2_BASE_IDX 1 874#define mmPCTL_RESERVED_3 0x03b9 875#define mmPCTL_RESERVED_3_BASE_IDX 1 876 877 878// addressBlock: mmhub_l1tlb_mmutcl1pfdec 879// base address: 0x69600 880#define mmMMMC_VM_MX_L1_TLB0_STATUS 0x0588 881#define mmMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 882#define mmMMMC_VM_MX_L1_TLB1_STATUS 0x0589 883#define mmMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 884#define mmMMMC_VM_MX_L1_TLB2_STATUS 0x058a 885#define mmMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 886#define mmMMMC_VM_MX_L1_TLB3_STATUS 0x058b 887#define mmMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 888#define mmMMMC_VM_MX_L1_TLB4_STATUS 0x058c 889#define mmMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 890#define mmMMMC_VM_MX_L1_TLB5_STATUS 0x058d 891#define mmMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 892#define mmMMMC_VM_MX_L1_TLB6_STATUS 0x058e 893#define mmMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 894#define mmMMMC_VM_MX_L1_TLB7_STATUS 0x058f 895#define mmMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 896 897 898// addressBlock: mmhub_l1tlb_mmutcl1pldec 899// base address: 0x69670 900#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x059c 901#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 902#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x059d 903#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 904#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x059e 905#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 906#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x059f 907#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 908#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x05a0 909#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 910 911 912// addressBlock: mmhub_l1tlb_mmutcl1prdec 913// base address: 0x69690 914#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO 0x05a4 915#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 916#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI 0x05a5 917#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 918 919 920// addressBlock: mmhub_l1tlb_mmvmtlspfdec 921// base address: 0x696c0 922#define mmMMMC_VM_MX_L1_TLS0_CNTL 0x05b0 923#define mmMMMC_VM_MX_L1_TLS0_CNTL_BASE_IDX 1 924#define mmMMMC_VM_MX_L1_TLS0_CNTL0 0x05b1 925#define mmMMMC_VM_MX_L1_TLS0_CNTL0_BASE_IDX 1 926#define mmMMMC_VM_MX_L1_TLS0_CNTL1 0x05b2 927#define mmMMMC_VM_MX_L1_TLS0_CNTL1_BASE_IDX 1 928#define mmMMMC_VM_MX_L1_TLS0_CNTL2 0x05b3 929#define mmMMMC_VM_MX_L1_TLS0_CNTL2_BASE_IDX 1 930#define mmMMMC_VM_MX_L1_TLS0_CNTL3 0x05b4 931#define mmMMMC_VM_MX_L1_TLS0_CNTL3_BASE_IDX 1 932#define mmMMMC_VM_MX_L1_TLS0_CNTL4 0x05b5 933#define mmMMMC_VM_MX_L1_TLS0_CNTL4_BASE_IDX 1 934#define mmMMMC_VM_MX_L1_TLS0_CNTL5 0x05b6 935#define mmMMMC_VM_MX_L1_TLS0_CNTL5_BASE_IDX 1 936#define mmMMMC_VM_MX_L1_TLS0_CNTL6 0x05b7 937#define mmMMMC_VM_MX_L1_TLS0_CNTL6_BASE_IDX 1 938#define mmMMMC_VM_MX_L1_TLS0_CNTL7 0x05b8 939#define mmMMMC_VM_MX_L1_TLS0_CNTL7_BASE_IDX 1 940#define mmMMMC_VM_MX_L1_TLS0_CNTL8 0x05b9 941#define mmMMMC_VM_MX_L1_TLS0_CNTL8_BASE_IDX 1 942#define mmMMMC_VM_MX_L1_TLS0_CNTL9 0x05ba 943#define mmMMMC_VM_MX_L1_TLS0_CNTL9_BASE_IDX 1 944#define mmMMMC_VM_MX_L1_TLS0_CNTL10 0x05bb 945#define mmMMMC_VM_MX_L1_TLS0_CNTL10_BASE_IDX 1 946#define mmMMMC_VM_MX_L1_TLS0_CNTL11 0x05bc 947#define mmMMMC_VM_MX_L1_TLS0_CNTL11_BASE_IDX 1 948#define mmMMMC_VM_MX_L1_TLS0_CNTL12 0x05bd 949#define mmMMMC_VM_MX_L1_TLS0_CNTL12_BASE_IDX 1 950#define mmMMMC_VM_MX_L1_TLS0_CNTL13 0x05be 951#define mmMMMC_VM_MX_L1_TLS0_CNTL13_BASE_IDX 1 952#define mmMMMC_VM_MX_L1_TLS0_CNTL14 0x05bf 953#define mmMMMC_VM_MX_L1_TLS0_CNTL14_BASE_IDX 1 954#define mmMMMC_VM_MX_L1_TLS0_CNTL15 0x05c0 955#define mmMMMC_VM_MX_L1_TLS0_CNTL15_BASE_IDX 1 956#define mmMMMC_VM_MX_L1_TLS0_CNTL16 0x05c1 957#define mmMMMC_VM_MX_L1_TLS0_CNTL16_BASE_IDX 1 958#define mmMMMC_VM_MX_L1_TLS0_CNTL17 0x05c2 959#define mmMMMC_VM_MX_L1_TLS0_CNTL17_BASE_IDX 1 960#define mmMMMC_VM_MX_L1_TLS0_CNTL18 0x05c3 961#define mmMMMC_VM_MX_L1_TLS0_CNTL18_BASE_IDX 1 962#define mmMMMC_VM_MX_L1_TLS0_CNTL19 0x05c4 963#define mmMMMC_VM_MX_L1_TLS0_CNTL19_BASE_IDX 1 964#define mmMMMC_VM_MX_L1_TLS0_CNTL20 0x05c5 965#define mmMMMC_VM_MX_L1_TLS0_CNTL20_BASE_IDX 1 966#define mmMMMC_VM_MX_L1_TLS0_CNTL21 0x05c6 967#define mmMMMC_VM_MX_L1_TLS0_CNTL21_BASE_IDX 1 968#define mmMMMC_VM_MX_L1_TLS0_CNTL22 0x05c7 969#define mmMMMC_VM_MX_L1_TLS0_CNTL22_BASE_IDX 1 970#define mmMMMC_VM_MX_L1_TLS0_CNTL23 0x05c8 971#define mmMMMC_VM_MX_L1_TLS0_CNTL23_BASE_IDX 1 972#define mmMMMC_VM_MX_L1_TLS0_CNTL24 0x05c9 973#define mmMMMC_VM_MX_L1_TLS0_CNTL24_BASE_IDX 1 974#define mmMMMC_VM_MX_L1_TLS0_CNTL25 0x05ca 975#define mmMMMC_VM_MX_L1_TLS0_CNTL25_BASE_IDX 1 976#define mmMMMC_VM_MX_L1_TLS0_CNTL26 0x05cb 977#define mmMMMC_VM_MX_L1_TLS0_CNTL26_BASE_IDX 1 978#define mmMMMC_VM_MX_L1_TLS0_CNTL27 0x05cc 979#define mmMMMC_VM_MX_L1_TLS0_CNTL27_BASE_IDX 1 980#define mmMMMC_VM_MX_L1_TLS0_CNTL28 0x05cd 981#define mmMMMC_VM_MX_L1_TLS0_CNTL28_BASE_IDX 1 982#define mmMMMC_VM_MX_L1_TLS0_CNTL29 0x05ce 983#define mmMMMC_VM_MX_L1_TLS0_CNTL29_BASE_IDX 1 984#define mmMMMC_VM_MX_L1_TLS0_CNTL30 0x05cf 985#define mmMMMC_VM_MX_L1_TLS0_CNTL30_BASE_IDX 1 986#define mmMMMC_VM_MX_L1_TLS0_CNTL31 0x05d0 987#define mmMMMC_VM_MX_L1_TLS0_CNTL31_BASE_IDX 1 988#define mmMMMC_VM_MX_L1_TLS0_CNTL32 0x05d1 989#define mmMMMC_VM_MX_L1_TLS0_CNTL32_BASE_IDX 1 990#define mmMMMC_VM_MX_L1_TLS0_CNTL33 0x05d2 991#define mmMMMC_VM_MX_L1_TLS0_CNTL33_BASE_IDX 1 992#define mmMMMC_VM_MX_L1_TLS0_CNTL34 0x05d3 993#define mmMMMC_VM_MX_L1_TLS0_CNTL34_BASE_IDX 1 994#define mmMMMC_VM_MX_L1_TLS0_CNTL35 0x05d4 995#define mmMMMC_VM_MX_L1_TLS0_CNTL35_BASE_IDX 1 996#define mmMMMC_VM_MX_L1_TLS0_CNTL36 0x05d5 997#define mmMMMC_VM_MX_L1_TLS0_CNTL36_BASE_IDX 1 998#define mmMMMC_VM_MX_L1_TLS0_CNTL37 0x05d6 999#define mmMMMC_VM_MX_L1_TLS0_CNTL37_BASE_IDX 1 1000#define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 0x05d7 1001#define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32_BASE_IDX 1 1002#define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 0x05d8 1003#define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32_BASE_IDX 1 1004#define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 0x05d9 1005#define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32_BASE_IDX 1 1006#define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 0x05da 1007#define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32_BASE_IDX 1 1008#define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 0x05db 1009#define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32_BASE_IDX 1 1010#define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 0x05dc 1011#define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32_BASE_IDX 1 1012#define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 0x05dd 1013#define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32_BASE_IDX 1 1014#define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 0x05de 1015#define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32_BASE_IDX 1 1016#define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 0x05df 1017#define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32_BASE_IDX 1 1018#define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 0x05e0 1019#define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32_BASE_IDX 1 1020#define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 0x05e1 1021#define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32_BASE_IDX 1 1022#define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 0x05e2 1023#define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32_BASE_IDX 1 1024#define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 0x05e3 1025#define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32_BASE_IDX 1 1026#define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 0x05e4 1027#define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32_BASE_IDX 1 1028#define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 0x05e5 1029#define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32_BASE_IDX 1 1030#define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 0x05e6 1031#define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32_BASE_IDX 1 1032#define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 0x05e7 1033#define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32_BASE_IDX 1 1034#define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 0x05e8 1035#define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32_BASE_IDX 1 1036#define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 0x05e9 1037#define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32_BASE_IDX 1 1038#define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 0x05ea 1039#define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32_BASE_IDX 1 1040#define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 0x05eb 1041#define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32_BASE_IDX 1 1042#define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 0x05ec 1043#define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32_BASE_IDX 1 1044#define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 0x05ed 1045#define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32_BASE_IDX 1 1046#define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 0x05ee 1047#define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32_BASE_IDX 1 1048#define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 0x05ef 1049#define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32_BASE_IDX 1 1050#define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 0x05f0 1051#define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32_BASE_IDX 1 1052#define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 0x05f1 1053#define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32_BASE_IDX 1 1054#define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 0x05f2 1055#define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32_BASE_IDX 1 1056#define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 0x05f3 1057#define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32_BASE_IDX 1 1058#define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 0x05f4 1059#define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32_BASE_IDX 1 1060#define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 0x05f5 1061#define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32_BASE_IDX 1 1062#define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 0x05f6 1063#define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32_BASE_IDX 1 1064#define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 0x05f7 1065#define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32_BASE_IDX 1 1066#define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 0x05f8 1067#define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32_BASE_IDX 1 1068#define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 0x05f9 1069#define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32_BASE_IDX 1 1070#define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 0x05fa 1071#define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32_BASE_IDX 1 1072#define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 0x05fb 1073#define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32_BASE_IDX 1 1074#define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 0x05fc 1075#define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32_BASE_IDX 1 1076#define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 0x05fd 1077#define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32_BASE_IDX 1 1078#define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 0x05fe 1079#define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32_BASE_IDX 1 1080#define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 0x05ff 1081#define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32_BASE_IDX 1 1082#define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 0x0600 1083#define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32_BASE_IDX 1 1084#define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 0x0601 1085#define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32_BASE_IDX 1 1086#define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 0x0602 1087#define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32_BASE_IDX 1 1088#define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 0x0603 1089#define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32_BASE_IDX 1 1090#define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 0x0604 1091#define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32_BASE_IDX 1 1092#define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 0x0605 1093#define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32_BASE_IDX 1 1094#define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 0x0606 1095#define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32_BASE_IDX 1 1096#define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 0x0607 1097#define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32_BASE_IDX 1 1098#define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 0x0608 1099#define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32_BASE_IDX 1 1100#define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 0x0609 1101#define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32_BASE_IDX 1 1102#define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 0x060a 1103#define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32_BASE_IDX 1 1104#define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 0x060b 1105#define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32_BASE_IDX 1 1106#define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 0x060c 1107#define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32_BASE_IDX 1 1108#define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 0x060d 1109#define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32_BASE_IDX 1 1110#define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 0x060e 1111#define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32_BASE_IDX 1 1112#define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 0x060f 1113#define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32_BASE_IDX 1 1114#define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 0x0610 1115#define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32_BASE_IDX 1 1116#define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 0x0611 1117#define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32_BASE_IDX 1 1118#define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 0x0612 1119#define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32_BASE_IDX 1 1120#define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 0x0613 1121#define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32_BASE_IDX 1 1122#define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 0x0614 1123#define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32_BASE_IDX 1 1124#define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 0x0615 1125#define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32_BASE_IDX 1 1126#define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 0x0616 1127#define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32_BASE_IDX 1 1128#define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 0x0617 1129#define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32_BASE_IDX 1 1130#define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 0x0618 1131#define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32_BASE_IDX 1 1132#define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 0x0619 1133#define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32_BASE_IDX 1 1134#define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 0x061a 1135#define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32_BASE_IDX 1 1136#define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 0x061b 1137#define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32_BASE_IDX 1 1138#define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 0x061c 1139#define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32_BASE_IDX 1 1140#define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 0x061d 1141#define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32_BASE_IDX 1 1142#define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 0x061e 1143#define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32_BASE_IDX 1 1144#define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 0x061f 1145#define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32_BASE_IDX 1 1146#define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 0x0620 1147#define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32_BASE_IDX 1 1148#define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 0x0621 1149#define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32_BASE_IDX 1 1150#define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 0x0622 1151#define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32_BASE_IDX 1 1152#define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 0x0623 1153#define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32_BASE_IDX 1 1154#define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 0x0624 1155#define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32_BASE_IDX 1 1156#define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 0x0625 1157#define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32_BASE_IDX 1 1158#define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 0x0626 1159#define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32_BASE_IDX 1 1160#define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 0x0627 1161#define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32_BASE_IDX 1 1162#define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 0x0628 1163#define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32_BASE_IDX 1 1164#define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 0x0629 1165#define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32_BASE_IDX 1 1166#define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 0x062a 1167#define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32_BASE_IDX 1 1168#define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 0x062b 1169#define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32_BASE_IDX 1 1170#define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 0x062c 1171#define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32_BASE_IDX 1 1172#define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 0x062d 1173#define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32_BASE_IDX 1 1174#define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 0x062e 1175#define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32_BASE_IDX 1 1176#define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 0x062f 1177#define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32_BASE_IDX 1 1178#define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 0x0630 1179#define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32_BASE_IDX 1 1180#define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 0x0631 1181#define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32_BASE_IDX 1 1182#define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 0x0632 1183#define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32_BASE_IDX 1 1184#define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 0x0633 1185#define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32_BASE_IDX 1 1186#define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 0x0634 1187#define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32_BASE_IDX 1 1188#define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 0x0635 1189#define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32_BASE_IDX 1 1190#define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 0x0636 1191#define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32_BASE_IDX 1 1192#define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 0x0637 1193#define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32_BASE_IDX 1 1194#define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 0x0638 1195#define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32_BASE_IDX 1 1196#define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 0x0639 1197#define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32_BASE_IDX 1 1198#define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 0x063a 1199#define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32_BASE_IDX 1 1200#define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 0x063b 1201#define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32_BASE_IDX 1 1202#define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 0x063c 1203#define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32_BASE_IDX 1 1204#define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 0x063d 1205#define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32_BASE_IDX 1 1206#define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 0x063e 1207#define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32_BASE_IDX 1 1208#define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 0x063f 1209#define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32_BASE_IDX 1 1210#define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 0x0640 1211#define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32_BASE_IDX 1 1212#define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 0x0641 1213#define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32_BASE_IDX 1 1214#define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 0x0642 1215#define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32_BASE_IDX 1 1216#define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 0x0643 1217#define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32_BASE_IDX 1 1218#define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 0x0644 1219#define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32_BASE_IDX 1 1220#define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 0x0645 1221#define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32_BASE_IDX 1 1222#define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 0x0646 1223#define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32_BASE_IDX 1 1224#define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 0x0647 1225#define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32_BASE_IDX 1 1226#define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 0x0648 1227#define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32_BASE_IDX 1 1228#define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 0x0649 1229#define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32_BASE_IDX 1 1230#define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 0x064a 1231#define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32_BASE_IDX 1 1232#define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 0x064b 1233#define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32_BASE_IDX 1 1234#define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 0x064c 1235#define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32_BASE_IDX 1 1236#define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 0x064d 1237#define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32_BASE_IDX 1 1238#define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 0x064e 1239#define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32_BASE_IDX 1 1240#define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 0x064f 1241#define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32_BASE_IDX 1 1242#define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 0x0650 1243#define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32_BASE_IDX 1 1244#define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 0x0651 1245#define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32_BASE_IDX 1 1246#define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 0x0652 1247#define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32_BASE_IDX 1 1248#define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 0x0653 1249#define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32_BASE_IDX 1 1250#define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 0x0654 1251#define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32_BASE_IDX 1 1252#define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 0x0655 1253#define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32_BASE_IDX 1 1254#define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 0x0656 1255#define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32_BASE_IDX 1 1256#define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 0x0657 1257#define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32_BASE_IDX 1 1258#define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 0x0658 1259#define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32_BASE_IDX 1 1260#define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 0x0659 1261#define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32_BASE_IDX 1 1262#define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 0x065a 1263#define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32_BASE_IDX 1 1264#define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 0x065b 1265#define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32_BASE_IDX 1 1266#define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 0x065c 1267#define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32_BASE_IDX 1 1268#define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 0x065d 1269#define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32_BASE_IDX 1 1270#define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 0x065e 1271#define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32_BASE_IDX 1 1272#define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 0x065f 1273#define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32_BASE_IDX 1 1274#define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 0x0660 1275#define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32_BASE_IDX 1 1276#define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 0x0661 1277#define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32_BASE_IDX 1 1278#define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 0x0662 1279#define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32_BASE_IDX 1 1280#define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 0x0663 1281#define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32_BASE_IDX 1 1282#define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 0x0664 1283#define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32_BASE_IDX 1 1284#define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 0x0665 1285#define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32_BASE_IDX 1 1286#define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 0x0666 1287#define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32_BASE_IDX 1 1288#define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 0x0667 1289#define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32_BASE_IDX 1 1290#define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 0x0668 1291#define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32_BASE_IDX 1 1292#define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 0x0669 1293#define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32_BASE_IDX 1 1294#define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 0x066a 1295#define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32_BASE_IDX 1 1296#define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 0x066b 1297#define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32_BASE_IDX 1 1298#define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 0x066c 1299#define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32_BASE_IDX 1 1300#define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 0x066d 1301#define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32_BASE_IDX 1 1302#define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 0x066e 1303#define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32_BASE_IDX 1 1304#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 0x066f 1305#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32_BASE_IDX 1 1306#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 0x0670 1307#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32_BASE_IDX 1 1308#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 0x0671 1309#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32_BASE_IDX 1 1310#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 0x0672 1311#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32_BASE_IDX 1 1312#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS 0x0673 1313#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_BASE_IDX 1 1314#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 0x0674 1315#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 1316#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 0x0675 1317#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 1318#define mmMMVM_L2_SAW_CNTL 0x0676 1319#define mmMMVM_L2_SAW_CNTL_BASE_IDX 1 1320#define mmMMVM_L2_SAW_CNTL2 0x0677 1321#define mmMMVM_L2_SAW_CNTL2_BASE_IDX 1 1322#define mmMMVM_L2_SAW_CNTL3 0x0678 1323#define mmMMVM_L2_SAW_CNTL3_BASE_IDX 1 1324#define mmMMVM_L2_SAW_CNTL4 0x0679 1325#define mmMMVM_L2_SAW_CNTL4_BASE_IDX 1 1326#define mmMMVM_L2_SAW_CONTEXT0_CNTL 0x067a 1327#define mmMMVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX 1 1328#define mmMMVM_L2_SAW_CONTEXT0_CNTL2 0x067b 1329#define mmMMVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX 1 1330#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x067c 1331#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1332#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x067d 1333#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1334#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x067e 1335#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1336#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x067f 1337#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1338#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0680 1339#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1340#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0681 1341#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1342#define mmMMVM_L2_SAW_CONTEXTS_DISABLE 0x0682 1343#define mmMMVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX 1 1344#define mmMMVM_L2_SAW_PIPES_BUSY_LO32 0x0683 1345#define mmMMVM_L2_SAW_PIPES_BUSY_LO32_BASE_IDX 1 1346#define mmMMVM_L2_SAW_PIPES_BUSY_HI32 0x0684 1347#define mmMMVM_L2_SAW_PIPES_BUSY_HI32_BASE_IDX 1 1348#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS 0x0685 1349#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS_BASE_IDX 1 1350#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 0x0686 1351#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32_BASE_IDX 1 1352#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 0x0687 1353#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32_BASE_IDX 1 1354 1355 1356// addressBlock: mmhub_mmutcl2_mmatcl2dec 1357// base address: 0x69b00 1358#define mmMM_ATC_L2_CNTL 0x06c0 1359#define mmMM_ATC_L2_CNTL_BASE_IDX 1 1360#define mmMM_ATC_L2_CNTL2 0x06c1 1361#define mmMM_ATC_L2_CNTL2_BASE_IDX 1 1362#define mmMM_ATC_L2_CACHE_DATA0 0x06c4 1363#define mmMM_ATC_L2_CACHE_DATA0_BASE_IDX 1 1364#define mmMM_ATC_L2_CACHE_DATA1 0x06c5 1365#define mmMM_ATC_L2_CACHE_DATA1_BASE_IDX 1 1366#define mmMM_ATC_L2_CACHE_DATA2 0x06c6 1367#define mmMM_ATC_L2_CACHE_DATA2_BASE_IDX 1 1368#define mmMM_ATC_L2_CNTL3 0x06c7 1369#define mmMM_ATC_L2_CNTL3_BASE_IDX 1 1370#define mmMM_ATC_L2_CNTL4 0x06c8 1371#define mmMM_ATC_L2_CNTL4_BASE_IDX 1 1372#define mmMM_ATC_L2_CNTL5 0x06c9 1373#define mmMM_ATC_L2_CNTL5_BASE_IDX 1 1374#define mmMM_ATC_L2_MM_GROUP_RT_CLASSES 0x06ca 1375#define mmMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 1376#define mmMM_ATC_L2_STATUS 0x06cb 1377#define mmMM_ATC_L2_STATUS_BASE_IDX 1 1378#define mmMM_ATC_L2_STATUS2 0x06cc 1379#define mmMM_ATC_L2_STATUS2_BASE_IDX 1 1380#define mmMM_ATC_L2_MISC_CG 0x06cd 1381#define mmMM_ATC_L2_MISC_CG_BASE_IDX 1 1382#define mmMM_ATC_L2_MEM_POWER_LS 0x06ce 1383#define mmMM_ATC_L2_MEM_POWER_LS_BASE_IDX 1 1384#define mmMM_ATC_L2_CGTT_CLK_CTRL 0x06cf 1385#define mmMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 1386#define mmMM_ATC_L2_SDPPORT_CTRL 0x06d2 1387#define mmMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 1 1388 1389 1390// addressBlock: mmhub_mmutcl2_mmvml2pfdec 1391// base address: 0x69c00 1392#define mmMMVM_L2_CNTL 0x0700 1393#define mmMMVM_L2_CNTL_BASE_IDX 1 1394#define mmMMVM_L2_CNTL2 0x0701 1395#define mmMMVM_L2_CNTL2_BASE_IDX 1 1396#define mmMMVM_L2_CNTL3 0x0702 1397#define mmMMVM_L2_CNTL3_BASE_IDX 1 1398#define mmMMVM_L2_STATUS 0x0703 1399#define mmMMVM_L2_STATUS_BASE_IDX 1 1400#define mmMMVM_DUMMY_PAGE_FAULT_CNTL 0x0704 1401#define mmMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 1402#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0705 1403#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 1404#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0706 1405#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 1406#define mmMMVM_INVALIDATE_CNTL 0x0707 1407#define mmMMVM_INVALIDATE_CNTL_BASE_IDX 1 1408#define mmMMVM_L2_PROTECTION_FAULT_CNTL 0x0708 1409#define mmMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 1410#define mmMMVM_L2_PROTECTION_FAULT_CNTL2 0x0709 1411#define mmMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 1412#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x070a 1413#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 1414#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x070b 1415#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 1416#define mmMMVM_L2_PROTECTION_FAULT_STATUS 0x070c 1417#define mmMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 1418#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x070d 1419#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 1420#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x070e 1421#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 1422#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x070f 1423#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 1424#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0710 1425#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 1426#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0712 1427#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 1428#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0713 1429#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 1430#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0714 1431#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 1432#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0715 1433#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 1434#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0716 1435#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 1436#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0717 1437#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 1438#define mmMMVM_L2_CNTL4 0x0718 1439#define mmMMVM_L2_CNTL4_BASE_IDX 1 1440#define mmMMVM_L2_MM_GROUP_RT_CLASSES 0x0719 1441#define mmMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 1442#define mmMMVM_L2_BANK_SELECT_RESERVED_CID 0x071a 1443#define mmMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 1444#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2 0x071b 1445#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 1446#define mmMMVM_L2_CACHE_PARITY_CNTL 0x071c 1447#define mmMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 1448#define mmMMVM_L2_IH_LOG_CNTL 0x071d 1449#define mmMMVM_L2_IH_LOG_CNTL_BASE_IDX 1 1450#define mmMMVM_L2_IH_LOG_BUSY 0x071e 1451#define mmMMVM_L2_IH_LOG_BUSY_BASE_IDX 1 1452#define mmMMVM_L2_CGTT_CLK_CTRL 0x071f 1453#define mmMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 1 1454#define mmMMVM_L2_CNTL5 0x0720 1455#define mmMMVM_L2_CNTL5_BASE_IDX 1 1456#define mmMMVM_L2_GCR_CNTL 0x0721 1457#define mmMMVM_L2_GCR_CNTL_BASE_IDX 1 1458#define mmMMVM_L2_CGTT_BUSY_CTRL 0x0722 1459#define mmMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 1 1460#define mmMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0723 1461#define mmMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 1 1462#define mmMMVM_L2_PTE_CACHE_DUMP_READ 0x0724 1463#define mmMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 1 1464 1465 1466// addressBlock: mmhub_mmutcl2_mmvml2vcdec 1467// base address: 0x69d00 1468#define mmMMVM_CONTEXT0_CNTL 0x0740 1469#define mmMMVM_CONTEXT0_CNTL_BASE_IDX 1 1470#define mmMMVM_CONTEXT1_CNTL 0x0741 1471#define mmMMVM_CONTEXT1_CNTL_BASE_IDX 1 1472#define mmMMVM_CONTEXT2_CNTL 0x0742 1473#define mmMMVM_CONTEXT2_CNTL_BASE_IDX 1 1474#define mmMMVM_CONTEXT3_CNTL 0x0743 1475#define mmMMVM_CONTEXT3_CNTL_BASE_IDX 1 1476#define mmMMVM_CONTEXT4_CNTL 0x0744 1477#define mmMMVM_CONTEXT4_CNTL_BASE_IDX 1 1478#define mmMMVM_CONTEXT5_CNTL 0x0745 1479#define mmMMVM_CONTEXT5_CNTL_BASE_IDX 1 1480#define mmMMVM_CONTEXT6_CNTL 0x0746 1481#define mmMMVM_CONTEXT6_CNTL_BASE_IDX 1 1482#define mmMMVM_CONTEXT7_CNTL 0x0747 1483#define mmMMVM_CONTEXT7_CNTL_BASE_IDX 1 1484#define mmMMVM_CONTEXT8_CNTL 0x0748 1485#define mmMMVM_CONTEXT8_CNTL_BASE_IDX 1 1486#define mmMMVM_CONTEXT9_CNTL 0x0749 1487#define mmMMVM_CONTEXT9_CNTL_BASE_IDX 1 1488#define mmMMVM_CONTEXT10_CNTL 0x074a 1489#define mmMMVM_CONTEXT10_CNTL_BASE_IDX 1 1490#define mmMMVM_CONTEXT11_CNTL 0x074b 1491#define mmMMVM_CONTEXT11_CNTL_BASE_IDX 1 1492#define mmMMVM_CONTEXT12_CNTL 0x074c 1493#define mmMMVM_CONTEXT12_CNTL_BASE_IDX 1 1494#define mmMMVM_CONTEXT13_CNTL 0x074d 1495#define mmMMVM_CONTEXT13_CNTL_BASE_IDX 1 1496#define mmMMVM_CONTEXT14_CNTL 0x074e 1497#define mmMMVM_CONTEXT14_CNTL_BASE_IDX 1 1498#define mmMMVM_CONTEXT15_CNTL 0x074f 1499#define mmMMVM_CONTEXT15_CNTL_BASE_IDX 1 1500#define mmMMVM_CONTEXTS_DISABLE 0x0750 1501#define mmMMVM_CONTEXTS_DISABLE_BASE_IDX 1 1502#define mmMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0751 1503#define mmMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1504#define mmMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0752 1505#define mmMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1506#define mmMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0753 1507#define mmMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1508#define mmMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0754 1509#define mmMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1510#define mmMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0755 1511#define mmMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1512#define mmMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0756 1513#define mmMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1514#define mmMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0757 1515#define mmMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1516#define mmMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0758 1517#define mmMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1518#define mmMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0759 1519#define mmMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1520#define mmMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075a 1521#define mmMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1522#define mmMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075b 1523#define mmMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1524#define mmMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075c 1525#define mmMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1526#define mmMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075d 1527#define mmMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1528#define mmMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075e 1529#define mmMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1530#define mmMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075f 1531#define mmMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1532#define mmMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0760 1533#define mmMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1534#define mmMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0761 1535#define mmMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1536 1537 1538// addressBlock: mmhub_mmutcl2_mmvml2pldec 1539// base address: 0x6a090 1540#define mmMMMC_VM_L2_PERFCOUNTER0_CFG 0x0824 1541#define mmMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 1542#define mmMMMC_VM_L2_PERFCOUNTER1_CFG 0x0825 1543#define mmMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 1544#define mmMMMC_VM_L2_PERFCOUNTER2_CFG 0x0826 1545#define mmMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 1546#define mmMMMC_VM_L2_PERFCOUNTER3_CFG 0x0827 1547#define mmMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 1548#define mmMMMC_VM_L2_PERFCOUNTER4_CFG 0x0828 1549#define mmMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 1550#define mmMMMC_VM_L2_PERFCOUNTER5_CFG 0x0829 1551#define mmMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 1552#define mmMMMC_VM_L2_PERFCOUNTER6_CFG 0x082a 1553#define mmMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 1554#define mmMMMC_VM_L2_PERFCOUNTER7_CFG 0x082b 1555#define mmMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 1556#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x082c 1557#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1558#define mmMMUTCL2_PERFCOUNTER0_CFG 0x082d 1559#define mmMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 1560#define mmMMUTCL2_PERFCOUNTER1_CFG 0x082e 1561#define mmMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 1562#define mmMMUTCL2_PERFCOUNTER2_CFG 0x082f 1563#define mmMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 1564#define mmMMUTCL2_PERFCOUNTER3_CFG 0x0830 1565#define mmMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 1566#define mmMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x0831 1567#define mmMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1568 1569 1570// addressBlock: mmhub_mmutcl2_mmvml2prdec 1571// base address: 0x6a0e0 1572#define mmMMMC_VM_L2_PERFCOUNTER_LO 0x0838 1573#define mmMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 1574#define mmMMMC_VM_L2_PERFCOUNTER_HI 0x0839 1575#define mmMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 1576#define mmMMUTCL2_PERFCOUNTER_LO 0x083a 1577#define mmMMUTCL2_PERFCOUNTER_LO_BASE_IDX 1 1578#define mmMMUTCL2_PERFCOUNTER_HI 0x083b 1579#define mmMMUTCL2_PERFCOUNTER_HI_BASE_IDX 1 1580 1581 1582// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 1583// base address: 0x6a130 1584#define mmMMMC_VM_FB_SIZE_OFFSET_VF0 0x084c 1585#define mmMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 1586#define mmMMMC_VM_FB_SIZE_OFFSET_VF1 0x084d 1587#define mmMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 1588#define mmMMMC_VM_FB_SIZE_OFFSET_VF2 0x084e 1589#define mmMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 1590#define mmMMMC_VM_FB_SIZE_OFFSET_VF3 0x084f 1591#define mmMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 1592#define mmMMMC_VM_FB_SIZE_OFFSET_VF4 0x0850 1593#define mmMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 1594#define mmMMMC_VM_FB_SIZE_OFFSET_VF5 0x0851 1595#define mmMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 1596#define mmMMMC_VM_FB_SIZE_OFFSET_VF6 0x0852 1597#define mmMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 1598#define mmMMMC_VM_FB_SIZE_OFFSET_VF7 0x0853 1599#define mmMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 1600#define mmMMMC_VM_FB_SIZE_OFFSET_VF8 0x0854 1601#define mmMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 1602#define mmMMMC_VM_FB_SIZE_OFFSET_VF9 0x0855 1603#define mmMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 1604#define mmMMMC_VM_FB_SIZE_OFFSET_VF10 0x0856 1605#define mmMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 1606#define mmMMMC_VM_FB_SIZE_OFFSET_VF11 0x0857 1607#define mmMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 1608#define mmMMMC_VM_FB_SIZE_OFFSET_VF12 0x0858 1609#define mmMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 1610#define mmMMMC_VM_FB_SIZE_OFFSET_VF13 0x0859 1611#define mmMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 1612#define mmMMMC_VM_FB_SIZE_OFFSET_VF14 0x085a 1613#define mmMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 1614#define mmMMMC_VM_FB_SIZE_OFFSET_VF15 0x085b 1615#define mmMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 1616#define mmMMMC_VM_FB_SIZE_OFFSET_VF16 0x085c 1617#define mmMMMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX 1 1618#define mmMMMC_VM_FB_SIZE_OFFSET_VF17 0x085d 1619#define mmMMMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX 1 1620#define mmMMMC_VM_FB_SIZE_OFFSET_VF18 0x085e 1621#define mmMMMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX 1 1622#define mmMMMC_VM_FB_SIZE_OFFSET_VF19 0x085f 1623#define mmMMMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX 1 1624#define mmMMMC_VM_FB_SIZE_OFFSET_VF20 0x0860 1625#define mmMMMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX 1 1626#define mmMMMC_VM_FB_SIZE_OFFSET_VF21 0x0861 1627#define mmMMMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX 1 1628#define mmMMMC_VM_FB_SIZE_OFFSET_VF22 0x0862 1629#define mmMMMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX 1 1630#define mmMMMC_VM_FB_SIZE_OFFSET_VF23 0x0863 1631#define mmMMMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX 1 1632#define mmMMMC_VM_FB_SIZE_OFFSET_VF24 0x0864 1633#define mmMMMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX 1 1634#define mmMMMC_VM_FB_SIZE_OFFSET_VF25 0x0865 1635#define mmMMMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX 1 1636#define mmMMMC_VM_FB_SIZE_OFFSET_VF26 0x0866 1637#define mmMMMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX 1 1638#define mmMMMC_VM_FB_SIZE_OFFSET_VF27 0x0867 1639#define mmMMMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX 1 1640#define mmMMMC_VM_FB_SIZE_OFFSET_VF28 0x0868 1641#define mmMMMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX 1 1642#define mmMMMC_VM_FB_SIZE_OFFSET_VF29 0x0869 1643#define mmMMMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX 1 1644#define mmMMMC_VM_FB_SIZE_OFFSET_VF30 0x086a 1645#define mmMMMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX 1 1646#define mmMMMC_VM_FB_SIZE_OFFSET_VF31 0x086b 1647#define mmMMMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX 1 1648#define mmMMVM_IOMMU_MMIO_CNTRL_1 0x086c 1649#define mmMMVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 1650#define mmMMMC_VM_MARC_BASE_LO_0 0x086d 1651#define mmMMMC_VM_MARC_BASE_LO_0_BASE_IDX 1 1652#define mmMMMC_VM_MARC_BASE_LO_1 0x086e 1653#define mmMMMC_VM_MARC_BASE_LO_1_BASE_IDX 1 1654#define mmMMMC_VM_MARC_BASE_LO_2 0x086f 1655#define mmMMMC_VM_MARC_BASE_LO_2_BASE_IDX 1 1656#define mmMMMC_VM_MARC_BASE_LO_3 0x0870 1657#define mmMMMC_VM_MARC_BASE_LO_3_BASE_IDX 1 1658#define mmMMMC_VM_MARC_BASE_HI_0 0x0871 1659#define mmMMMC_VM_MARC_BASE_HI_0_BASE_IDX 1 1660#define mmMMMC_VM_MARC_BASE_HI_1 0x0872 1661#define mmMMMC_VM_MARC_BASE_HI_1_BASE_IDX 1 1662#define mmMMMC_VM_MARC_BASE_HI_2 0x0873 1663#define mmMMMC_VM_MARC_BASE_HI_2_BASE_IDX 1 1664#define mmMMMC_VM_MARC_BASE_HI_3 0x0874 1665#define mmMMMC_VM_MARC_BASE_HI_3_BASE_IDX 1 1666#define mmMMMC_VM_MARC_RELOC_LO_0 0x0875 1667#define mmMMMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 1668#define mmMMMC_VM_MARC_RELOC_LO_1 0x0876 1669#define mmMMMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 1670#define mmMMMC_VM_MARC_RELOC_LO_2 0x0877 1671#define mmMMMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 1672#define mmMMMC_VM_MARC_RELOC_LO_3 0x0878 1673#define mmMMMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 1674#define mmMMMC_VM_MARC_RELOC_HI_0 0x0879 1675#define mmMMMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 1676#define mmMMMC_VM_MARC_RELOC_HI_1 0x087a 1677#define mmMMMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 1678#define mmMMMC_VM_MARC_RELOC_HI_2 0x087b 1679#define mmMMMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 1680#define mmMMMC_VM_MARC_RELOC_HI_3 0x087c 1681#define mmMMMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 1682#define mmMMMC_VM_MARC_LEN_LO_0 0x087d 1683#define mmMMMC_VM_MARC_LEN_LO_0_BASE_IDX 1 1684#define mmMMMC_VM_MARC_LEN_LO_1 0x087e 1685#define mmMMMC_VM_MARC_LEN_LO_1_BASE_IDX 1 1686#define mmMMMC_VM_MARC_LEN_LO_2 0x087f 1687#define mmMMMC_VM_MARC_LEN_LO_2_BASE_IDX 1 1688#define mmMMMC_VM_MARC_LEN_LO_3 0x0880 1689#define mmMMMC_VM_MARC_LEN_LO_3_BASE_IDX 1 1690#define mmMMMC_VM_MARC_LEN_HI_0 0x0881 1691#define mmMMMC_VM_MARC_LEN_HI_0_BASE_IDX 1 1692#define mmMMMC_VM_MARC_LEN_HI_1 0x0882 1693#define mmMMMC_VM_MARC_LEN_HI_1_BASE_IDX 1 1694#define mmMMMC_VM_MARC_LEN_HI_2 0x0883 1695#define mmMMMC_VM_MARC_LEN_HI_2_BASE_IDX 1 1696#define mmMMMC_VM_MARC_LEN_HI_3 0x0884 1697#define mmMMMC_VM_MARC_LEN_HI_3_BASE_IDX 1 1698#define mmMMVM_IOMMU_CONTROL_REGISTER 0x0885 1699#define mmMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 1700#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0886 1701#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 1702#define mmMMVM_PCIE_ATS_CNTL 0x0887 1703#define mmMMVM_PCIE_ATS_CNTL_BASE_IDX 1 1704#define mmMMVM_PCIE_ATS_CNTL_VF_0 0x0888 1705#define mmMMVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 1706#define mmMMVM_PCIE_ATS_CNTL_VF_1 0x0889 1707#define mmMMVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 1708#define mmMMVM_PCIE_ATS_CNTL_VF_2 0x088a 1709#define mmMMVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 1710#define mmMMVM_PCIE_ATS_CNTL_VF_3 0x088b 1711#define mmMMVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 1712#define mmMMVM_PCIE_ATS_CNTL_VF_4 0x088c 1713#define mmMMVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 1714#define mmMMVM_PCIE_ATS_CNTL_VF_5 0x088d 1715#define mmMMVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 1716#define mmMMVM_PCIE_ATS_CNTL_VF_6 0x088e 1717#define mmMMVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 1718#define mmMMVM_PCIE_ATS_CNTL_VF_7 0x088f 1719#define mmMMVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 1720#define mmMMVM_PCIE_ATS_CNTL_VF_8 0x0890 1721#define mmMMVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 1722#define mmMMVM_PCIE_ATS_CNTL_VF_9 0x0891 1723#define mmMMVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 1724#define mmMMVM_PCIE_ATS_CNTL_VF_10 0x0892 1725#define mmMMVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 1726#define mmMMVM_PCIE_ATS_CNTL_VF_11 0x0893 1727#define mmMMVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 1728#define mmMMVM_PCIE_ATS_CNTL_VF_12 0x0894 1729#define mmMMVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 1730#define mmMMVM_PCIE_ATS_CNTL_VF_13 0x0895 1731#define mmMMVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 1732#define mmMMVM_PCIE_ATS_CNTL_VF_14 0x0896 1733#define mmMMVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 1734#define mmMMVM_PCIE_ATS_CNTL_VF_15 0x0897 1735#define mmMMVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 1736#define mmMMVM_PCIE_ATS_CNTL_VF_16 0x0898 1737#define mmMMVM_PCIE_ATS_CNTL_VF_16_BASE_IDX 1 1738#define mmMMVM_PCIE_ATS_CNTL_VF_17 0x0899 1739#define mmMMVM_PCIE_ATS_CNTL_VF_17_BASE_IDX 1 1740#define mmMMVM_PCIE_ATS_CNTL_VF_18 0x089a 1741#define mmMMVM_PCIE_ATS_CNTL_VF_18_BASE_IDX 1 1742#define mmMMVM_PCIE_ATS_CNTL_VF_19 0x089b 1743#define mmMMVM_PCIE_ATS_CNTL_VF_19_BASE_IDX 1 1744#define mmMMVM_PCIE_ATS_CNTL_VF_20 0x089c 1745#define mmMMVM_PCIE_ATS_CNTL_VF_20_BASE_IDX 1 1746#define mmMMVM_PCIE_ATS_CNTL_VF_21 0x089d 1747#define mmMMVM_PCIE_ATS_CNTL_VF_21_BASE_IDX 1 1748#define mmMMVM_PCIE_ATS_CNTL_VF_22 0x089e 1749#define mmMMVM_PCIE_ATS_CNTL_VF_22_BASE_IDX 1 1750#define mmMMVM_PCIE_ATS_CNTL_VF_23 0x089f 1751#define mmMMVM_PCIE_ATS_CNTL_VF_23_BASE_IDX 1 1752#define mmMMVM_PCIE_ATS_CNTL_VF_24 0x08a0 1753#define mmMMVM_PCIE_ATS_CNTL_VF_24_BASE_IDX 1 1754#define mmMMVM_PCIE_ATS_CNTL_VF_25 0x08a1 1755#define mmMMVM_PCIE_ATS_CNTL_VF_25_BASE_IDX 1 1756#define mmMMVM_PCIE_ATS_CNTL_VF_26 0x08a2 1757#define mmMMVM_PCIE_ATS_CNTL_VF_26_BASE_IDX 1 1758#define mmMMVM_PCIE_ATS_CNTL_VF_27 0x08a3 1759#define mmMMVM_PCIE_ATS_CNTL_VF_27_BASE_IDX 1 1760#define mmMMVM_PCIE_ATS_CNTL_VF_28 0x08a4 1761#define mmMMVM_PCIE_ATS_CNTL_VF_28_BASE_IDX 1 1762#define mmMMVM_PCIE_ATS_CNTL_VF_29 0x08a5 1763#define mmMMVM_PCIE_ATS_CNTL_VF_29_BASE_IDX 1 1764#define mmMMVM_PCIE_ATS_CNTL_VF_30 0x08a6 1765#define mmMMVM_PCIE_ATS_CNTL_VF_30_BASE_IDX 1 1766#define mmMMVM_PCIE_ATS_CNTL_VF_31 0x08a7 1767#define mmMMVM_PCIE_ATS_CNTL_VF_31_BASE_IDX 1 1768 1769 1770// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 1771// base address: 0x6a340 1772#define mmMMMC_VM_NB_MMIOBASE 0x08d0 1773#define mmMMMC_VM_NB_MMIOBASE_BASE_IDX 1 1774#define mmMMMC_VM_NB_MMIOLIMIT 0x08d1 1775#define mmMMMC_VM_NB_MMIOLIMIT_BASE_IDX 1 1776#define mmMMMC_VM_NB_PCI_CTRL 0x08d2 1777#define mmMMMC_VM_NB_PCI_CTRL_BASE_IDX 1 1778#define mmMMMC_VM_NB_PCI_ARB 0x08d3 1779#define mmMMMC_VM_NB_PCI_ARB_BASE_IDX 1 1780#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x08d4 1781#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 1782#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x08d5 1783#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 1784#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x08d6 1785#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 1786#define mmMMMC_VM_FB_OFFSET 0x08d7 1787#define mmMMMC_VM_FB_OFFSET_BASE_IDX 1 1788#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x08d8 1789#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 1790#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x08d9 1791#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 1792#define mmMMMC_VM_STEERING 0x08da 1793#define mmMMMC_VM_STEERING_BASE_IDX 1 1794#define mmMMMC_SHARED_VIRT_RESET_REQ 0x08db 1795#define mmMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 1796#define mmMMMC_MEM_POWER_LS 0x08dc 1797#define mmMMMC_MEM_POWER_LS_BASE_IDX 1 1798#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x08dd 1799#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 1800#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x08de 1801#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 1802#define mmMMMC_VM_APT_CNTL 0x08df 1803#define mmMMMC_VM_APT_CNTL_BASE_IDX 1 1804#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x08e0 1805#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 1 1806#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START 0x08e1 1807#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 1 1808#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END 0x08e2 1809#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 1 1810#define mmMMUTCL2_CGTT_CLK_CTRL 0x08e3 1811#define mmMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 1812#define mmMMMC_SHARED_ACTIVE_FCN_ID 0x08e4 1813#define mmMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 1814#define mmMMMC_SHARED_VIRT_RESET_REQ2 0x08e5 1815#define mmMMMC_SHARED_VIRT_RESET_REQ2_BASE_IDX 1 1816#define mmMMUTCL2_CGTT_BUSY_CTRL 0x08e6 1817#define mmMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 1 1818#define mmMMUTCL2_HARVEST_BYPASS_GROUPS 0x08e7 1819#define mmMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 1 1820 1821 1822// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 1823// base address: 0x6a3b0 1824#define mmMMMC_VM_FB_LOCATION_BASE 0x08ec 1825#define mmMMMC_VM_FB_LOCATION_BASE_BASE_IDX 1 1826#define mmMMMC_VM_FB_LOCATION_TOP 0x08ed 1827#define mmMMMC_VM_FB_LOCATION_TOP_BASE_IDX 1 1828#define mmMMMC_VM_AGP_TOP 0x08ee 1829#define mmMMMC_VM_AGP_TOP_BASE_IDX 1 1830#define mmMMMC_VM_AGP_BOT 0x08ef 1831#define mmMMMC_VM_AGP_BOT_BASE_IDX 1 1832#define mmMMMC_VM_AGP_BASE 0x08f0 1833#define mmMMMC_VM_AGP_BASE_BASE_IDX 1 1834#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x08f1 1835#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 1836#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08f2 1837#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 1838#define mmMMMC_VM_MX_L1_TLB_CNTL 0x08f3 1839#define mmMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 1840 1841 1842// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 1843// base address: 0x6a400 1844#define mmMM_ATC_L2_PERFCOUNTER_LO 0x0900 1845#define mmMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 1846#define mmMM_ATC_L2_PERFCOUNTER_HI 0x0901 1847#define mmMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 1848 1849 1850// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 1851// base address: 0x6a420 1852#define mmMM_ATC_L2_PERFCOUNTER0_CFG 0x0908 1853#define mmMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 1854#define mmMM_ATC_L2_PERFCOUNTER1_CFG 0x0909 1855#define mmMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 1856#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x090a 1857#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1858 1859 1860// addressBlock: mmhub_mmutcl2_mmvml2ptdec 1861// base address: 0x6a500 1862#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0940 1863#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1864#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0941 1865#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1866#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0942 1867#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1868#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0943 1869#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1870#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0944 1871#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1872#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0945 1873#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1874#define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE0 0x0946 1875#define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE0_BASE_IDX 1 1876#define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE1 0x0947 1877#define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE1_BASE_IDX 1 1878#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0948 1879#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1880#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0949 1881#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1882#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x094a 1883#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1884#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x094b 1885#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1886#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x094c 1887#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1888#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x094d 1889#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1890#define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE0 0x094e 1891#define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE0_BASE_IDX 1 1892#define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE1 0x094f 1893#define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE1_BASE_IDX 1 1894#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0950 1895#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1896#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0951 1897#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1898#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0952 1899#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1900#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0953 1901#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1902#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0954 1903#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1904#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0955 1905#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1906#define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE0 0x0956 1907#define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE0_BASE_IDX 1 1908#define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE1 0x0957 1909#define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE1_BASE_IDX 1 1910#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0958 1911#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1912#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0959 1913#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1914#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x095a 1915#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1916#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x095b 1917#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1918#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x095c 1919#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1920#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x095d 1921#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1922#define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE0 0x095e 1923#define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE0_BASE_IDX 1 1924#define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE1 0x095f 1925#define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE1_BASE_IDX 1 1926#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0960 1927#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1928#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0961 1929#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1930#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0962 1931#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1932#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0963 1933#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1934#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0964 1935#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1936#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0965 1937#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1938#define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE0 0x0966 1939#define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE0_BASE_IDX 1 1940#define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE1 0x0967 1941#define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE1_BASE_IDX 1 1942#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0968 1943#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1944#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0969 1945#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1946#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x096a 1947#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1948#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x096b 1949#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1950#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x096c 1951#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1952#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x096d 1953#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1954#define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE0 0x096e 1955#define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE0_BASE_IDX 1 1956#define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE1 0x096f 1957#define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE1_BASE_IDX 1 1958#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0970 1959#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1960#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0971 1961#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1962#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0972 1963#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1964#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0973 1965#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1966#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0974 1967#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1968#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0975 1969#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1970#define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE0 0x0976 1971#define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE0_BASE_IDX 1 1972#define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE1 0x0977 1973#define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE1_BASE_IDX 1 1974#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0978 1975#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1976#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0979 1977#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1978#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x097a 1979#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1980#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x097b 1981#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1982#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x097c 1983#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1984#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x097d 1985#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1986#define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE0 0x097e 1987#define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE0_BASE_IDX 1 1988#define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE1 0x097f 1989#define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE1_BASE_IDX 1 1990#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0980 1991#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1992#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0981 1993#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1994#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0982 1995#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1996#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0983 1997#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1998#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0984 1999#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 2000#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0985 2001#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 2002#define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE0 0x0986 2003#define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE0_BASE_IDX 1 2004#define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE1 0x0987 2005#define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE1_BASE_IDX 1 2006#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0988 2007#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 2008#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0989 2009#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 2010#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x098a 2011#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 2012#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x098b 2013#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 2014#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x098c 2015#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 2016#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x098d 2017#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 2018#define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE0 0x098e 2019#define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE0_BASE_IDX 1 2020#define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE1 0x098f 2021#define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE1_BASE_IDX 1 2022#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0990 2023#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 2024#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0991 2025#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 2026#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0992 2027#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 2028#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0993 2029#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 2030#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0994 2031#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 2032#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0995 2033#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 2034#define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE0 0x0996 2035#define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE0_BASE_IDX 1 2036#define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE1 0x0997 2037#define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE1_BASE_IDX 1 2038#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0998 2039#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 2040#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0999 2041#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 2042#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x099a 2043#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 2044#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x099b 2045#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 2046#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x099c 2047#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 2048#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x099d 2049#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 2050#define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE0 0x099e 2051#define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE0_BASE_IDX 1 2052#define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE1 0x099f 2053#define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE1_BASE_IDX 1 2054#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x09a0 2055#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 2056#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x09a1 2057#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 2058#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x09a2 2059#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 2060#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x09a3 2061#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 2062#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x09a4 2063#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 2064#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x09a5 2065#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 2066#define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE0 0x09a6 2067#define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE0_BASE_IDX 1 2068#define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE1 0x09a7 2069#define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE1_BASE_IDX 1 2070#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x09a8 2071#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 2072#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x09a9 2073#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 2074#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x09aa 2075#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 2076#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x09ab 2077#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 2078#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x09ac 2079#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 2080#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x09ad 2081#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 2082#define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE0 0x09ae 2083#define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE0_BASE_IDX 1 2084#define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE1 0x09af 2085#define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE1_BASE_IDX 1 2086#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x09b0 2087#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 2088#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x09b1 2089#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 2090#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x09b2 2091#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 2092#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x09b3 2093#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 2094#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x09b4 2095#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 2096#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x09b5 2097#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 2098#define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE0 0x09b6 2099#define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE0_BASE_IDX 1 2100#define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE1 0x09b7 2101#define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE1_BASE_IDX 1 2102#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x09b8 2103#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 2104#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x09b9 2105#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 2106#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x09ba 2107#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 2108#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x09bb 2109#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 2110#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x09bc 2111#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 2112#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x09bd 2113#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 2114#define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE0 0x09be 2115#define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE0_BASE_IDX 1 2116#define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE1 0x09bf 2117#define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE1_BASE_IDX 1 2118 2119 2120// addressBlock: mmhub_mmutcl2_mmvml2indec 2121// base address: 0x6a800 2122#define mmMMVM_INVALIDATE_ENG0_SEM 0x0a00 2123#define mmMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 1 2124#define mmMMVM_INVALIDATE_ENG0_REQ 0x0a01 2125#define mmMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 1 2126#define mmMMVM_INVALIDATE_ENG0_ACK 0x0a02 2127#define mmMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 1 2128#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0a03 2129#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 2130#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0a04 2131#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 2132#define mmMMVM_INVALIDATE_ENG0_RESERVE0 0x0a05 2133#define mmMMVM_INVALIDATE_ENG0_RESERVE0_BASE_IDX 1 2134#define mmMMVM_INVALIDATE_ENG0_RESERVE1 0x0a06 2135#define mmMMVM_INVALIDATE_ENG0_RESERVE1_BASE_IDX 1 2136#define mmMMVM_INVALIDATE_ENG0_RESERVE2 0x0a07 2137#define mmMMVM_INVALIDATE_ENG0_RESERVE2_BASE_IDX 1 2138#define mmMMVM_INVALIDATE_ENG1_SEM 0x0a08 2139#define mmMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 1 2140#define mmMMVM_INVALIDATE_ENG1_REQ 0x0a09 2141#define mmMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 1 2142#define mmMMVM_INVALIDATE_ENG1_ACK 0x0a0a 2143#define mmMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 1 2144#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0a0b 2145#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 2146#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0a0c 2147#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 2148#define mmMMVM_INVALIDATE_ENG1_RESERVE0 0x0a0d 2149#define mmMMVM_INVALIDATE_ENG1_RESERVE0_BASE_IDX 1 2150#define mmMMVM_INVALIDATE_ENG1_RESERVE1 0x0a0e 2151#define mmMMVM_INVALIDATE_ENG1_RESERVE1_BASE_IDX 1 2152#define mmMMVM_INVALIDATE_ENG1_RESERVE2 0x0a0f 2153#define mmMMVM_INVALIDATE_ENG1_RESERVE2_BASE_IDX 1 2154#define mmMMVM_INVALIDATE_ENG2_SEM 0x0a10 2155#define mmMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 1 2156#define mmMMVM_INVALIDATE_ENG2_REQ 0x0a11 2157#define mmMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 1 2158#define mmMMVM_INVALIDATE_ENG2_ACK 0x0a12 2159#define mmMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 1 2160#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x0a13 2161#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 2162#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x0a14 2163#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 2164#define mmMMVM_INVALIDATE_ENG2_RESERVE0 0x0a15 2165#define mmMMVM_INVALIDATE_ENG2_RESERVE0_BASE_IDX 1 2166#define mmMMVM_INVALIDATE_ENG2_RESERVE1 0x0a16 2167#define mmMMVM_INVALIDATE_ENG2_RESERVE1_BASE_IDX 1 2168#define mmMMVM_INVALIDATE_ENG2_RESERVE2 0x0a17 2169#define mmMMVM_INVALIDATE_ENG2_RESERVE2_BASE_IDX 1 2170#define mmMMVM_INVALIDATE_ENG3_SEM 0x0a18 2171#define mmMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 1 2172#define mmMMVM_INVALIDATE_ENG3_REQ 0x0a19 2173#define mmMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 1 2174#define mmMMVM_INVALIDATE_ENG3_ACK 0x0a1a 2175#define mmMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 1 2176#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0a1b 2177#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 2178#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0a1c 2179#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 2180#define mmMMVM_INVALIDATE_ENG3_RESERVE0 0x0a1d 2181#define mmMMVM_INVALIDATE_ENG3_RESERVE0_BASE_IDX 1 2182#define mmMMVM_INVALIDATE_ENG3_RESERVE1 0x0a1e 2183#define mmMMVM_INVALIDATE_ENG3_RESERVE1_BASE_IDX 1 2184#define mmMMVM_INVALIDATE_ENG3_RESERVE2 0x0a1f 2185#define mmMMVM_INVALIDATE_ENG3_RESERVE2_BASE_IDX 1 2186#define mmMMVM_INVALIDATE_ENG4_SEM 0x0a20 2187#define mmMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 1 2188#define mmMMVM_INVALIDATE_ENG4_REQ 0x0a21 2189#define mmMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 1 2190#define mmMMVM_INVALIDATE_ENG4_ACK 0x0a22 2191#define mmMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 1 2192#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x0a23 2193#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 2194#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0a24 2195#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 2196#define mmMMVM_INVALIDATE_ENG4_RESERVE0 0x0a25 2197#define mmMMVM_INVALIDATE_ENG4_RESERVE0_BASE_IDX 1 2198#define mmMMVM_INVALIDATE_ENG4_RESERVE1 0x0a26 2199#define mmMMVM_INVALIDATE_ENG4_RESERVE1_BASE_IDX 1 2200#define mmMMVM_INVALIDATE_ENG4_RESERVE2 0x0a27 2201#define mmMMVM_INVALIDATE_ENG4_RESERVE2_BASE_IDX 1 2202#define mmMMVM_INVALIDATE_ENG5_SEM 0x0a28 2203#define mmMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 1 2204#define mmMMVM_INVALIDATE_ENG5_REQ 0x0a29 2205#define mmMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 1 2206#define mmMMVM_INVALIDATE_ENG5_ACK 0x0a2a 2207#define mmMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 1 2208#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0a2b 2209#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 2210#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0a2c 2211#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 2212#define mmMMVM_INVALIDATE_ENG5_RESERVE0 0x0a2d 2213#define mmMMVM_INVALIDATE_ENG5_RESERVE0_BASE_IDX 1 2214#define mmMMVM_INVALIDATE_ENG5_RESERVE1 0x0a2e 2215#define mmMMVM_INVALIDATE_ENG5_RESERVE1_BASE_IDX 1 2216#define mmMMVM_INVALIDATE_ENG5_RESERVE2 0x0a2f 2217#define mmMMVM_INVALIDATE_ENG5_RESERVE2_BASE_IDX 1 2218#define mmMMVM_INVALIDATE_ENG6_SEM 0x0a30 2219#define mmMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 1 2220#define mmMMVM_INVALIDATE_ENG6_REQ 0x0a31 2221#define mmMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 1 2222#define mmMMVM_INVALIDATE_ENG6_ACK 0x0a32 2223#define mmMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 1 2224#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0a33 2225#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 2226#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0a34 2227#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 2228#define mmMMVM_INVALIDATE_ENG6_RESERVE0 0x0a35 2229#define mmMMVM_INVALIDATE_ENG6_RESERVE0_BASE_IDX 1 2230#define mmMMVM_INVALIDATE_ENG6_RESERVE1 0x0a36 2231#define mmMMVM_INVALIDATE_ENG6_RESERVE1_BASE_IDX 1 2232#define mmMMVM_INVALIDATE_ENG6_RESERVE2 0x0a37 2233#define mmMMVM_INVALIDATE_ENG6_RESERVE2_BASE_IDX 1 2234#define mmMMVM_INVALIDATE_ENG7_SEM 0x0a38 2235#define mmMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 1 2236#define mmMMVM_INVALIDATE_ENG7_REQ 0x0a39 2237#define mmMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 1 2238#define mmMMVM_INVALIDATE_ENG7_ACK 0x0a3a 2239#define mmMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 1 2240#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0a3b 2241#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 2242#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0a3c 2243#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 2244#define mmMMVM_INVALIDATE_ENG7_RESERVE0 0x0a3d 2245#define mmMMVM_INVALIDATE_ENG7_RESERVE0_BASE_IDX 1 2246#define mmMMVM_INVALIDATE_ENG7_RESERVE1 0x0a3e 2247#define mmMMVM_INVALIDATE_ENG7_RESERVE1_BASE_IDX 1 2248#define mmMMVM_INVALIDATE_ENG7_RESERVE2 0x0a3f 2249#define mmMMVM_INVALIDATE_ENG7_RESERVE2_BASE_IDX 1 2250#define mmMMVM_INVALIDATE_ENG8_SEM 0x0a40 2251#define mmMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 1 2252#define mmMMVM_INVALIDATE_ENG8_REQ 0x0a41 2253#define mmMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 1 2254#define mmMMVM_INVALIDATE_ENG8_ACK 0x0a42 2255#define mmMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 1 2256#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0a43 2257#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 2258#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0a44 2259#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 2260#define mmMMVM_INVALIDATE_ENG8_RESERVE0 0x0a45 2261#define mmMMVM_INVALIDATE_ENG8_RESERVE0_BASE_IDX 1 2262#define mmMMVM_INVALIDATE_ENG8_RESERVE1 0x0a46 2263#define mmMMVM_INVALIDATE_ENG8_RESERVE1_BASE_IDX 1 2264#define mmMMVM_INVALIDATE_ENG8_RESERVE2 0x0a47 2265#define mmMMVM_INVALIDATE_ENG8_RESERVE2_BASE_IDX 1 2266#define mmMMVM_INVALIDATE_ENG9_SEM 0x0a48 2267#define mmMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 1 2268#define mmMMVM_INVALIDATE_ENG9_REQ 0x0a49 2269#define mmMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 1 2270#define mmMMVM_INVALIDATE_ENG9_ACK 0x0a4a 2271#define mmMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 1 2272#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0a4b 2273#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 2274#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x0a4c 2275#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 2276#define mmMMVM_INVALIDATE_ENG9_RESERVE0 0x0a4d 2277#define mmMMVM_INVALIDATE_ENG9_RESERVE0_BASE_IDX 1 2278#define mmMMVM_INVALIDATE_ENG9_RESERVE1 0x0a4e 2279#define mmMMVM_INVALIDATE_ENG9_RESERVE1_BASE_IDX 1 2280#define mmMMVM_INVALIDATE_ENG9_RESERVE2 0x0a4f 2281#define mmMMVM_INVALIDATE_ENG9_RESERVE2_BASE_IDX 1 2282#define mmMMVM_INVALIDATE_ENG10_SEM 0x0a50 2283#define mmMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 1 2284#define mmMMVM_INVALIDATE_ENG10_REQ 0x0a51 2285#define mmMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 1 2286#define mmMMVM_INVALIDATE_ENG10_ACK 0x0a52 2287#define mmMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 1 2288#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x0a53 2289#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 2290#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x0a54 2291#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 2292#define mmMMVM_INVALIDATE_ENG10_RESERVE0 0x0a55 2293#define mmMMVM_INVALIDATE_ENG10_RESERVE0_BASE_IDX 1 2294#define mmMMVM_INVALIDATE_ENG10_RESERVE1 0x0a56 2295#define mmMMVM_INVALIDATE_ENG10_RESERVE1_BASE_IDX 1 2296#define mmMMVM_INVALIDATE_ENG10_RESERVE2 0x0a57 2297#define mmMMVM_INVALIDATE_ENG10_RESERVE2_BASE_IDX 1 2298#define mmMMVM_INVALIDATE_ENG11_SEM 0x0a58 2299#define mmMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 1 2300#define mmMMVM_INVALIDATE_ENG11_REQ 0x0a59 2301#define mmMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 1 2302#define mmMMVM_INVALIDATE_ENG11_ACK 0x0a5a 2303#define mmMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 1 2304#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x0a5b 2305#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 2306#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x0a5c 2307#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 2308#define mmMMVM_INVALIDATE_ENG11_RESERVE0 0x0a5d 2309#define mmMMVM_INVALIDATE_ENG11_RESERVE0_BASE_IDX 1 2310#define mmMMVM_INVALIDATE_ENG11_RESERVE1 0x0a5e 2311#define mmMMVM_INVALIDATE_ENG11_RESERVE1_BASE_IDX 1 2312#define mmMMVM_INVALIDATE_ENG11_RESERVE2 0x0a5f 2313#define mmMMVM_INVALIDATE_ENG11_RESERVE2_BASE_IDX 1 2314#define mmMMVM_INVALIDATE_ENG12_SEM 0x0a60 2315#define mmMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 1 2316#define mmMMVM_INVALIDATE_ENG12_REQ 0x0a61 2317#define mmMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 1 2318#define mmMMVM_INVALIDATE_ENG12_ACK 0x0a62 2319#define mmMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 1 2320#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x0a63 2321#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 2322#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0a64 2323#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 2324#define mmMMVM_INVALIDATE_ENG12_RESERVE0 0x0a65 2325#define mmMMVM_INVALIDATE_ENG12_RESERVE0_BASE_IDX 1 2326#define mmMMVM_INVALIDATE_ENG12_RESERVE1 0x0a66 2327#define mmMMVM_INVALIDATE_ENG12_RESERVE1_BASE_IDX 1 2328#define mmMMVM_INVALIDATE_ENG12_RESERVE2 0x0a67 2329#define mmMMVM_INVALIDATE_ENG12_RESERVE2_BASE_IDX 1 2330#define mmMMVM_INVALIDATE_ENG13_SEM 0x0a68 2331#define mmMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 1 2332#define mmMMVM_INVALIDATE_ENG13_REQ 0x0a69 2333#define mmMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 1 2334#define mmMMVM_INVALIDATE_ENG13_ACK 0x0a6a 2335#define mmMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 1 2336#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0a6b 2337#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 2338#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0a6c 2339#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 2340#define mmMMVM_INVALIDATE_ENG13_RESERVE0 0x0a6d 2341#define mmMMVM_INVALIDATE_ENG13_RESERVE0_BASE_IDX 1 2342#define mmMMVM_INVALIDATE_ENG13_RESERVE1 0x0a6e 2343#define mmMMVM_INVALIDATE_ENG13_RESERVE1_BASE_IDX 1 2344#define mmMMVM_INVALIDATE_ENG13_RESERVE2 0x0a6f 2345#define mmMMVM_INVALIDATE_ENG13_RESERVE2_BASE_IDX 1 2346#define mmMMVM_INVALIDATE_ENG14_SEM 0x0a70 2347#define mmMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 1 2348#define mmMMVM_INVALIDATE_ENG14_REQ 0x0a71 2349#define mmMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 1 2350#define mmMMVM_INVALIDATE_ENG14_ACK 0x0a72 2351#define mmMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 1 2352#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0a73 2353#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 2354#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0a74 2355#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 2356#define mmMMVM_INVALIDATE_ENG14_RESERVE0 0x0a75 2357#define mmMMVM_INVALIDATE_ENG14_RESERVE0_BASE_IDX 1 2358#define mmMMVM_INVALIDATE_ENG14_RESERVE1 0x0a76 2359#define mmMMVM_INVALIDATE_ENG14_RESERVE1_BASE_IDX 1 2360#define mmMMVM_INVALIDATE_ENG14_RESERVE2 0x0a77 2361#define mmMMVM_INVALIDATE_ENG14_RESERVE2_BASE_IDX 1 2362#define mmMMVM_INVALIDATE_ENG15_SEM 0x0a78 2363#define mmMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 1 2364#define mmMMVM_INVALIDATE_ENG15_REQ 0x0a79 2365#define mmMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 1 2366#define mmMMVM_INVALIDATE_ENG15_ACK 0x0a7a 2367#define mmMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 1 2368#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0a7b 2369#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 2370#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0a7c 2371#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 2372#define mmMMVM_INVALIDATE_ENG15_RESERVE0 0x0a7d 2373#define mmMMVM_INVALIDATE_ENG15_RESERVE0_BASE_IDX 1 2374#define mmMMVM_INVALIDATE_ENG15_RESERVE1 0x0a7e 2375#define mmMMVM_INVALIDATE_ENG15_RESERVE1_BASE_IDX 1 2376#define mmMMVM_INVALIDATE_ENG15_RESERVE2 0x0a7f 2377#define mmMMVM_INVALIDATE_ENG15_RESERVE2_BASE_IDX 1 2378#define mmMMVM_INVALIDATE_ENG16_SEM 0x0a80 2379#define mmMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 1 2380#define mmMMVM_INVALIDATE_ENG16_REQ 0x0a81 2381#define mmMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 1 2382#define mmMMVM_INVALIDATE_ENG16_ACK 0x0a82 2383#define mmMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 1 2384#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0a83 2385#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 2386#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0a84 2387#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 2388#define mmMMVM_INVALIDATE_ENG16_RESERVE0 0x0a85 2389#define mmMMVM_INVALIDATE_ENG16_RESERVE0_BASE_IDX 1 2390#define mmMMVM_INVALIDATE_ENG16_RESERVE1 0x0a86 2391#define mmMMVM_INVALIDATE_ENG16_RESERVE1_BASE_IDX 1 2392#define mmMMVM_INVALIDATE_ENG16_RESERVE2 0x0a87 2393#define mmMMVM_INVALIDATE_ENG16_RESERVE2_BASE_IDX 1 2394#define mmMMVM_INVALIDATE_ENG17_SEM 0x0a88 2395#define mmMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 1 2396#define mmMMVM_INVALIDATE_ENG17_REQ 0x0a89 2397#define mmMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 1 2398#define mmMMVM_INVALIDATE_ENG17_ACK 0x0a8a 2399#define mmMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 1 2400#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0a8b 2401#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 2402#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x0a8c 2403#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 2404#define mmMMVM_INVALIDATE_ENG17_RESERVE0 0x0a8d 2405#define mmMMVM_INVALIDATE_ENG17_RESERVE0_BASE_IDX 1 2406#define mmMMVM_INVALIDATE_ENG17_RESERVE1 0x0a8e 2407#define mmMMVM_INVALIDATE_ENG17_RESERVE1_BASE_IDX 1 2408#define mmMMVM_INVALIDATE_ENG17_RESERVE2 0x0a8f 2409#define mmMMVM_INVALIDATE_ENG17_RESERVE2_BASE_IDX 1 2410 2411 2412// addressBlock: mmhub_mmutcl2_mml2tlbpfdec 2413// base address: 0x6aa90 2414#define mmMML2TLB_TLB0_STATUS 0x0aa5 2415#define mmMML2TLB_TLB0_STATUS_BASE_IDX 1 2416 2417 2418// addressBlock: mmhub_mmutcl2_mml2tlbpldec 2419// base address: 0x6ab00 2420#define mmMML2TLB_PERFCOUNTER0_CFG 0x0ac0 2421#define mmMML2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 2422#define mmMML2TLB_PERFCOUNTER1_CFG 0x0ac1 2423#define mmMML2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 2424#define mmMML2TLB_PERFCOUNTER2_CFG 0x0ac2 2425#define mmMML2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 2426#define mmMML2TLB_PERFCOUNTER3_CFG 0x0ac3 2427#define mmMML2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 2428#define mmMML2TLB_PERFCOUNTER_RSLT_CNTL 0x0ac4 2429#define mmMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 2430 2431 2432// addressBlock: mmhub_mmutcl2_mml2tlbprdec 2433// base address: 0x6ab20 2434#define mmMML2TLB_PERFCOUNTER_LO 0x0ac8 2435#define mmMML2TLB_PERFCOUNTER_LO_BASE_IDX 1 2436#define mmMML2TLB_PERFCOUNTER_HI 0x0ac9 2437#define mmMML2TLB_PERFCOUNTER_HI_BASE_IDX 1 2438 2439#endif
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