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mmhub_1_0_offset.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
1/* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _mmhub_1_0_OFFSET_HEADER 22#define _mmhub_1_0_OFFSET_HEADER 23 24 25 26// addressBlock: mmhub_dagbdec 27// base address: 0x68000 28#define mmDAGB0_RDCLI0 0x0000 29#define mmDAGB0_RDCLI0_BASE_IDX 0 30#define mmDAGB0_RDCLI1 0x0001 31#define mmDAGB0_RDCLI1_BASE_IDX 0 32#define mmDAGB0_RDCLI2 0x0002 33#define mmDAGB0_RDCLI2_BASE_IDX 0 34#define mmDAGB0_RDCLI3 0x0003 35#define mmDAGB0_RDCLI3_BASE_IDX 0 36#define mmDAGB0_RDCLI4 0x0004 37#define mmDAGB0_RDCLI4_BASE_IDX 0 38#define mmDAGB0_RDCLI5 0x0005 39#define mmDAGB0_RDCLI5_BASE_IDX 0 40#define mmDAGB0_RDCLI6 0x0006 41#define mmDAGB0_RDCLI6_BASE_IDX 0 42#define mmDAGB0_RDCLI7 0x0007 43#define mmDAGB0_RDCLI7_BASE_IDX 0 44#define mmDAGB0_RDCLI8 0x0008 45#define mmDAGB0_RDCLI8_BASE_IDX 0 46#define mmDAGB0_RDCLI9 0x0009 47#define mmDAGB0_RDCLI9_BASE_IDX 0 48#define mmDAGB0_RDCLI10 0x000a 49#define mmDAGB0_RDCLI10_BASE_IDX 0 50#define mmDAGB0_RDCLI11 0x000b 51#define mmDAGB0_RDCLI11_BASE_IDX 0 52#define mmDAGB0_RDCLI12 0x000c 53#define mmDAGB0_RDCLI12_BASE_IDX 0 54#define mmDAGB0_RDCLI13 0x000d 55#define mmDAGB0_RDCLI13_BASE_IDX 0 56#define mmDAGB0_RDCLI14 0x000e 57#define mmDAGB0_RDCLI14_BASE_IDX 0 58#define mmDAGB0_RDCLI15 0x000f 59#define mmDAGB0_RDCLI15_BASE_IDX 0 60#define mmDAGB0_RD_CNTL 0x0010 61#define mmDAGB0_RD_CNTL_BASE_IDX 0 62#define mmDAGB0_RD_GMI_CNTL 0x0011 63#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0 64#define mmDAGB0_RD_ADDR_DAGB 0x0012 65#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0 66#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013 67#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 68#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014 69#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 70#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0015 71#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 72#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016 73#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 74#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017 75#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 76#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018 77#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 78#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019 79#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 80#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a 81#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 82#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b 83#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 84#define mmDAGB0_RD_VC0_CNTL 0x001c 85#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0 86#define mmDAGB0_RD_VC1_CNTL 0x001d 87#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0 88#define mmDAGB0_RD_VC2_CNTL 0x001e 89#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0 90#define mmDAGB0_RD_VC3_CNTL 0x001f 91#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0 92#define mmDAGB0_RD_VC4_CNTL 0x0020 93#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0 94#define mmDAGB0_RD_VC5_CNTL 0x0021 95#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0 96#define mmDAGB0_RD_VC6_CNTL 0x0022 97#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0 98#define mmDAGB0_RD_VC7_CNTL 0x0023 99#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0 100#define mmDAGB0_RD_CNTL_MISC 0x0024 101#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 0 102#define mmDAGB0_RD_TLB_CREDIT 0x0025 103#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 0 104#define mmDAGB0_RDCLI_ASK_PENDING 0x0026 105#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 106#define mmDAGB0_RDCLI_GO_PENDING 0x0027 107#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 108#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x0028 109#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 110#define mmDAGB0_RDCLI_TLB_PENDING 0x0029 111#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 112#define mmDAGB0_RDCLI_OARB_PENDING 0x002a 113#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 114#define mmDAGB0_RDCLI_OSD_PENDING 0x002b 115#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 116#define mmDAGB0_WRCLI0 0x002c 117#define mmDAGB0_WRCLI0_BASE_IDX 0 118#define mmDAGB0_WRCLI1 0x002d 119#define mmDAGB0_WRCLI1_BASE_IDX 0 120#define mmDAGB0_WRCLI2 0x002e 121#define mmDAGB0_WRCLI2_BASE_IDX 0 122#define mmDAGB0_WRCLI3 0x002f 123#define mmDAGB0_WRCLI3_BASE_IDX 0 124#define mmDAGB0_WRCLI4 0x0030 125#define mmDAGB0_WRCLI4_BASE_IDX 0 126#define mmDAGB0_WRCLI5 0x0031 127#define mmDAGB0_WRCLI5_BASE_IDX 0 128#define mmDAGB0_WRCLI6 0x0032 129#define mmDAGB0_WRCLI6_BASE_IDX 0 130#define mmDAGB0_WRCLI7 0x0033 131#define mmDAGB0_WRCLI7_BASE_IDX 0 132#define mmDAGB0_WRCLI8 0x0034 133#define mmDAGB0_WRCLI8_BASE_IDX 0 134#define mmDAGB0_WRCLI9 0x0035 135#define mmDAGB0_WRCLI9_BASE_IDX 0 136#define mmDAGB0_WRCLI10 0x0036 137#define mmDAGB0_WRCLI10_BASE_IDX 0 138#define mmDAGB0_WRCLI11 0x0037 139#define mmDAGB0_WRCLI11_BASE_IDX 0 140#define mmDAGB0_WRCLI12 0x0038 141#define mmDAGB0_WRCLI12_BASE_IDX 0 142#define mmDAGB0_WRCLI13 0x0039 143#define mmDAGB0_WRCLI13_BASE_IDX 0 144#define mmDAGB0_WRCLI14 0x003a 145#define mmDAGB0_WRCLI14_BASE_IDX 0 146#define mmDAGB0_WRCLI15 0x003b 147#define mmDAGB0_WRCLI15_BASE_IDX 0 148#define mmDAGB0_WR_CNTL 0x003c 149#define mmDAGB0_WR_CNTL_BASE_IDX 0 150#define mmDAGB0_WR_GMI_CNTL 0x003d 151#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 0 152#define mmDAGB0_WR_ADDR_DAGB 0x003e 153#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 0 154#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x003f 155#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 156#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0040 157#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 158#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0041 159#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 160#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0042 161#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 162#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0043 163#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 164#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0044 165#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 166#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0045 167#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 168#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0046 169#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 170#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0047 171#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 172#define mmDAGB0_WR_DATA_DAGB 0x0048 173#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 0 174#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0049 175#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 176#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004a 177#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 178#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004b 179#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 180#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004c 181#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 182#define mmDAGB0_WR_VC0_CNTL 0x004d 183#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 0 184#define mmDAGB0_WR_VC1_CNTL 0x004e 185#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 0 186#define mmDAGB0_WR_VC2_CNTL 0x004f 187#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 0 188#define mmDAGB0_WR_VC3_CNTL 0x0050 189#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 0 190#define mmDAGB0_WR_VC4_CNTL 0x0051 191#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 0 192#define mmDAGB0_WR_VC5_CNTL 0x0052 193#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 0 194#define mmDAGB0_WR_VC6_CNTL 0x0053 195#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 0 196#define mmDAGB0_WR_VC7_CNTL 0x0054 197#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 0 198#define mmDAGB0_WR_CNTL_MISC 0x0055 199#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 0 200#define mmDAGB0_WR_TLB_CREDIT 0x0056 201#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 0 202#define mmDAGB0_WR_DATA_CREDIT 0x0057 203#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 0 204#define mmDAGB0_WR_MISC_CREDIT 0x0058 205#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 0 206#define mmDAGB0_WRCLI_ASK_PENDING 0x0059 207#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 208#define mmDAGB0_WRCLI_GO_PENDING 0x005a 209#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 210#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x005b 211#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 212#define mmDAGB0_WRCLI_TLB_PENDING 0x005c 213#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 214#define mmDAGB0_WRCLI_OARB_PENDING 0x005d 215#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 216#define mmDAGB0_WRCLI_OSD_PENDING 0x005e 217#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 218#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x005f 219#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 220#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0060 221#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 222#define mmDAGB0_DAGB_DLY 0x0061 223#define mmDAGB0_DAGB_DLY_BASE_IDX 0 224#define mmDAGB0_CNTL_MISC 0x0062 225#define mmDAGB0_CNTL_MISC_BASE_IDX 0 226#define mmDAGB0_CNTL_MISC2 0x0063 227#define mmDAGB0_CNTL_MISC2_BASE_IDX 0 228#define mmDAGB0_FIFO_EMPTY 0x0064 229#define mmDAGB0_FIFO_EMPTY_BASE_IDX 0 230#define mmDAGB0_FIFO_FULL 0x0065 231#define mmDAGB0_FIFO_FULL_BASE_IDX 0 232#define mmDAGB0_WR_CREDITS_FULL 0x0066 233#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 0 234#define mmDAGB0_RD_CREDITS_FULL 0x0067 235#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 0 236#define mmDAGB0_PERFCOUNTER_LO 0x0068 237#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 0 238#define mmDAGB0_PERFCOUNTER_HI 0x0069 239#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 0 240#define mmDAGB0_PERFCOUNTER0_CFG 0x006a 241#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 242#define mmDAGB0_PERFCOUNTER1_CFG 0x006b 243#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 244#define mmDAGB0_PERFCOUNTER2_CFG 0x006c 245#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 246#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x006d 247#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 248#define mmDAGB0_RESERVE0 0x006e 249#define mmDAGB0_RESERVE0_BASE_IDX 0 250#define mmDAGB0_RESERVE1 0x006f 251#define mmDAGB0_RESERVE1_BASE_IDX 0 252#define mmDAGB0_RESERVE2 0x0070 253#define mmDAGB0_RESERVE2_BASE_IDX 0 254#define mmDAGB0_RESERVE3 0x0071 255#define mmDAGB0_RESERVE3_BASE_IDX 0 256#define mmDAGB0_RESERVE4 0x0072 257#define mmDAGB0_RESERVE4_BASE_IDX 0 258#define mmDAGB0_RESERVE5 0x0073 259#define mmDAGB0_RESERVE5_BASE_IDX 0 260#define mmDAGB0_RESERVE6 0x0074 261#define mmDAGB0_RESERVE6_BASE_IDX 0 262#define mmDAGB0_RESERVE7 0x0075 263#define mmDAGB0_RESERVE7_BASE_IDX 0 264#define mmDAGB0_RESERVE8 0x0076 265#define mmDAGB0_RESERVE8_BASE_IDX 0 266#define mmDAGB0_RESERVE9 0x0077 267#define mmDAGB0_RESERVE9_BASE_IDX 0 268#define mmDAGB0_RESERVE10 0x0078 269#define mmDAGB0_RESERVE10_BASE_IDX 0 270#define mmDAGB0_RESERVE11 0x0079 271#define mmDAGB0_RESERVE11_BASE_IDX 0 272#define mmDAGB0_RESERVE12 0x007a 273#define mmDAGB0_RESERVE12_BASE_IDX 0 274#define mmDAGB0_RESERVE13 0x007b 275#define mmDAGB0_RESERVE13_BASE_IDX 0 276#define mmDAGB0_RESERVE14 0x007c 277#define mmDAGB0_RESERVE14_BASE_IDX 0 278#define mmDAGB0_RESERVE15 0x007d 279#define mmDAGB0_RESERVE15_BASE_IDX 0 280#define mmDAGB0_RESERVE16 0x007e 281#define mmDAGB0_RESERVE16_BASE_IDX 0 282#define mmDAGB0_RESERVE17 0x007f 283#define mmDAGB0_RESERVE17_BASE_IDX 0 284#define mmDAGB1_RDCLI0 0x0080 285#define mmDAGB1_RDCLI0_BASE_IDX 0 286#define mmDAGB1_RDCLI1 0x0081 287#define mmDAGB1_RDCLI1_BASE_IDX 0 288#define mmDAGB1_RDCLI2 0x0082 289#define mmDAGB1_RDCLI2_BASE_IDX 0 290#define mmDAGB1_RDCLI3 0x0083 291#define mmDAGB1_RDCLI3_BASE_IDX 0 292#define mmDAGB1_RDCLI4 0x0084 293#define mmDAGB1_RDCLI4_BASE_IDX 0 294#define mmDAGB1_RDCLI5 0x0085 295#define mmDAGB1_RDCLI5_BASE_IDX 0 296#define mmDAGB1_RDCLI6 0x0086 297#define mmDAGB1_RDCLI6_BASE_IDX 0 298#define mmDAGB1_RDCLI7 0x0087 299#define mmDAGB1_RDCLI7_BASE_IDX 0 300#define mmDAGB1_RDCLI8 0x0088 301#define mmDAGB1_RDCLI8_BASE_IDX 0 302#define mmDAGB1_RDCLI9 0x0089 303#define mmDAGB1_RDCLI9_BASE_IDX 0 304#define mmDAGB1_RDCLI10 0x008a 305#define mmDAGB1_RDCLI10_BASE_IDX 0 306#define mmDAGB1_RDCLI11 0x008b 307#define mmDAGB1_RDCLI11_BASE_IDX 0 308#define mmDAGB1_RDCLI12 0x008c 309#define mmDAGB1_RDCLI12_BASE_IDX 0 310#define mmDAGB1_RDCLI13 0x008d 311#define mmDAGB1_RDCLI13_BASE_IDX 0 312#define mmDAGB1_RDCLI14 0x008e 313#define mmDAGB1_RDCLI14_BASE_IDX 0 314#define mmDAGB1_RDCLI15 0x008f 315#define mmDAGB1_RDCLI15_BASE_IDX 0 316#define mmDAGB1_RD_CNTL 0x0090 317#define mmDAGB1_RD_CNTL_BASE_IDX 0 318#define mmDAGB1_RD_GMI_CNTL 0x0091 319#define mmDAGB1_RD_GMI_CNTL_BASE_IDX 0 320#define mmDAGB1_RD_ADDR_DAGB 0x0092 321#define mmDAGB1_RD_ADDR_DAGB_BASE_IDX 0 322#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093 323#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 324#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094 325#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 326#define mmDAGB1_RD_CGTT_CLK_CTRL 0x0095 327#define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0 328#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096 329#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 330#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097 331#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 332#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098 333#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 334#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099 335#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 336#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a 337#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 338#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b 339#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 340#define mmDAGB1_RD_VC0_CNTL 0x009c 341#define mmDAGB1_RD_VC0_CNTL_BASE_IDX 0 342#define mmDAGB1_RD_VC1_CNTL 0x009d 343#define mmDAGB1_RD_VC1_CNTL_BASE_IDX 0 344#define mmDAGB1_RD_VC2_CNTL 0x009e 345#define mmDAGB1_RD_VC2_CNTL_BASE_IDX 0 346#define mmDAGB1_RD_VC3_CNTL 0x009f 347#define mmDAGB1_RD_VC3_CNTL_BASE_IDX 0 348#define mmDAGB1_RD_VC4_CNTL 0x00a0 349#define mmDAGB1_RD_VC4_CNTL_BASE_IDX 0 350#define mmDAGB1_RD_VC5_CNTL 0x00a1 351#define mmDAGB1_RD_VC5_CNTL_BASE_IDX 0 352#define mmDAGB1_RD_VC6_CNTL 0x00a2 353#define mmDAGB1_RD_VC6_CNTL_BASE_IDX 0 354#define mmDAGB1_RD_VC7_CNTL 0x00a3 355#define mmDAGB1_RD_VC7_CNTL_BASE_IDX 0 356#define mmDAGB1_RD_CNTL_MISC 0x00a4 357#define mmDAGB1_RD_CNTL_MISC_BASE_IDX 0 358#define mmDAGB1_RD_TLB_CREDIT 0x00a5 359#define mmDAGB1_RD_TLB_CREDIT_BASE_IDX 0 360#define mmDAGB1_RDCLI_ASK_PENDING 0x00a6 361#define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0 362#define mmDAGB1_RDCLI_GO_PENDING 0x00a7 363#define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX 0 364#define mmDAGB1_RDCLI_GBLSEND_PENDING 0x00a8 365#define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0 366#define mmDAGB1_RDCLI_TLB_PENDING 0x00a9 367#define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0 368#define mmDAGB1_RDCLI_OARB_PENDING 0x00aa 369#define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0 370#define mmDAGB1_RDCLI_OSD_PENDING 0x00ab 371#define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0 372#define mmDAGB1_WRCLI0 0x00ac 373#define mmDAGB1_WRCLI0_BASE_IDX 0 374#define mmDAGB1_WRCLI1 0x00ad 375#define mmDAGB1_WRCLI1_BASE_IDX 0 376#define mmDAGB1_WRCLI2 0x00ae 377#define mmDAGB1_WRCLI2_BASE_IDX 0 378#define mmDAGB1_WRCLI3 0x00af 379#define mmDAGB1_WRCLI3_BASE_IDX 0 380#define mmDAGB1_WRCLI4 0x00b0 381#define mmDAGB1_WRCLI4_BASE_IDX 0 382#define mmDAGB1_WRCLI5 0x00b1 383#define mmDAGB1_WRCLI5_BASE_IDX 0 384#define mmDAGB1_WRCLI6 0x00b2 385#define mmDAGB1_WRCLI6_BASE_IDX 0 386#define mmDAGB1_WRCLI7 0x00b3 387#define mmDAGB1_WRCLI7_BASE_IDX 0 388#define mmDAGB1_WRCLI8 0x00b4 389#define mmDAGB1_WRCLI8_BASE_IDX 0 390#define mmDAGB1_WRCLI9 0x00b5 391#define mmDAGB1_WRCLI9_BASE_IDX 0 392#define mmDAGB1_WRCLI10 0x00b6 393#define mmDAGB1_WRCLI10_BASE_IDX 0 394#define mmDAGB1_WRCLI11 0x00b7 395#define mmDAGB1_WRCLI11_BASE_IDX 0 396#define mmDAGB1_WRCLI12 0x00b8 397#define mmDAGB1_WRCLI12_BASE_IDX 0 398#define mmDAGB1_WRCLI13 0x00b9 399#define mmDAGB1_WRCLI13_BASE_IDX 0 400#define mmDAGB1_WRCLI14 0x00ba 401#define mmDAGB1_WRCLI14_BASE_IDX 0 402#define mmDAGB1_WRCLI15 0x00bb 403#define mmDAGB1_WRCLI15_BASE_IDX 0 404#define mmDAGB1_WR_CNTL 0x00bc 405#define mmDAGB1_WR_CNTL_BASE_IDX 0 406#define mmDAGB1_WR_GMI_CNTL 0x00bd 407#define mmDAGB1_WR_GMI_CNTL_BASE_IDX 0 408#define mmDAGB1_WR_ADDR_DAGB 0x00be 409#define mmDAGB1_WR_ADDR_DAGB_BASE_IDX 0 410#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00bf 411#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 412#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c0 413#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 414#define mmDAGB1_WR_CGTT_CLK_CTRL 0x00c1 415#define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0 416#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c2 417#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 418#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c3 419#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 420#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c4 421#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 422#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c5 423#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 424#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c6 425#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 426#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c7 427#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 428#define mmDAGB1_WR_DATA_DAGB 0x00c8 429#define mmDAGB1_WR_DATA_DAGB_BASE_IDX 0 430#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00c9 431#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 432#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ca 433#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 434#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cb 435#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 436#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00cc 437#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 438#define mmDAGB1_WR_VC0_CNTL 0x00cd 439#define mmDAGB1_WR_VC0_CNTL_BASE_IDX 0 440#define mmDAGB1_WR_VC1_CNTL 0x00ce 441#define mmDAGB1_WR_VC1_CNTL_BASE_IDX 0 442#define mmDAGB1_WR_VC2_CNTL 0x00cf 443#define mmDAGB1_WR_VC2_CNTL_BASE_IDX 0 444#define mmDAGB1_WR_VC3_CNTL 0x00d0 445#define mmDAGB1_WR_VC3_CNTL_BASE_IDX 0 446#define mmDAGB1_WR_VC4_CNTL 0x00d1 447#define mmDAGB1_WR_VC4_CNTL_BASE_IDX 0 448#define mmDAGB1_WR_VC5_CNTL 0x00d2 449#define mmDAGB1_WR_VC5_CNTL_BASE_IDX 0 450#define mmDAGB1_WR_VC6_CNTL 0x00d3 451#define mmDAGB1_WR_VC6_CNTL_BASE_IDX 0 452#define mmDAGB1_WR_VC7_CNTL 0x00d4 453#define mmDAGB1_WR_VC7_CNTL_BASE_IDX 0 454#define mmDAGB1_WR_CNTL_MISC 0x00d5 455#define mmDAGB1_WR_CNTL_MISC_BASE_IDX 0 456#define mmDAGB1_WR_TLB_CREDIT 0x00d6 457#define mmDAGB1_WR_TLB_CREDIT_BASE_IDX 0 458#define mmDAGB1_WR_DATA_CREDIT 0x00d7 459#define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 0 460#define mmDAGB1_WR_MISC_CREDIT 0x00d8 461#define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 0 462#define mmDAGB1_WRCLI_ASK_PENDING 0x00d9 463#define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0 464#define mmDAGB1_WRCLI_GO_PENDING 0x00da 465#define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX 0 466#define mmDAGB1_WRCLI_GBLSEND_PENDING 0x00db 467#define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0 468#define mmDAGB1_WRCLI_TLB_PENDING 0x00dc 469#define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0 470#define mmDAGB1_WRCLI_OARB_PENDING 0x00dd 471#define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0 472#define mmDAGB1_WRCLI_OSD_PENDING 0x00de 473#define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0 474#define mmDAGB1_WRCLI_DBUS_ASK_PENDING 0x00df 475#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 476#define mmDAGB1_WRCLI_DBUS_GO_PENDING 0x00e0 477#define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 478#define mmDAGB1_DAGB_DLY 0x00e1 479#define mmDAGB1_DAGB_DLY_BASE_IDX 0 480#define mmDAGB1_CNTL_MISC 0x00e2 481#define mmDAGB1_CNTL_MISC_BASE_IDX 0 482#define mmDAGB1_CNTL_MISC2 0x00e3 483#define mmDAGB1_CNTL_MISC2_BASE_IDX 0 484#define mmDAGB1_FIFO_EMPTY 0x00e4 485#define mmDAGB1_FIFO_EMPTY_BASE_IDX 0 486#define mmDAGB1_FIFO_FULL 0x00e5 487#define mmDAGB1_FIFO_FULL_BASE_IDX 0 488#define mmDAGB1_WR_CREDITS_FULL 0x00e6 489#define mmDAGB1_WR_CREDITS_FULL_BASE_IDX 0 490#define mmDAGB1_RD_CREDITS_FULL 0x00e7 491#define mmDAGB1_RD_CREDITS_FULL_BASE_IDX 0 492#define mmDAGB1_PERFCOUNTER_LO 0x00e8 493#define mmDAGB1_PERFCOUNTER_LO_BASE_IDX 0 494#define mmDAGB1_PERFCOUNTER_HI 0x00e9 495#define mmDAGB1_PERFCOUNTER_HI_BASE_IDX 0 496#define mmDAGB1_PERFCOUNTER0_CFG 0x00ea 497#define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0 498#define mmDAGB1_PERFCOUNTER1_CFG 0x00eb 499#define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0 500#define mmDAGB1_PERFCOUNTER2_CFG 0x00ec 501#define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0 502#define mmDAGB1_PERFCOUNTER_RSLT_CNTL 0x00ed 503#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 504#define mmDAGB1_RESERVE0 0x00ee 505#define mmDAGB1_RESERVE0_BASE_IDX 0 506#define mmDAGB1_RESERVE1 0x00ef 507#define mmDAGB1_RESERVE1_BASE_IDX 0 508#define mmDAGB1_RESERVE2 0x00f0 509#define mmDAGB1_RESERVE2_BASE_IDX 0 510#define mmDAGB1_RESERVE3 0x00f1 511#define mmDAGB1_RESERVE3_BASE_IDX 0 512#define mmDAGB1_RESERVE4 0x00f2 513#define mmDAGB1_RESERVE4_BASE_IDX 0 514#define mmDAGB1_RESERVE5 0x00f3 515#define mmDAGB1_RESERVE5_BASE_IDX 0 516#define mmDAGB1_RESERVE6 0x00f4 517#define mmDAGB1_RESERVE6_BASE_IDX 0 518#define mmDAGB1_RESERVE7 0x00f5 519#define mmDAGB1_RESERVE7_BASE_IDX 0 520#define mmDAGB1_RESERVE8 0x00f6 521#define mmDAGB1_RESERVE8_BASE_IDX 0 522#define mmDAGB1_RESERVE9 0x00f7 523#define mmDAGB1_RESERVE9_BASE_IDX 0 524#define mmDAGB1_RESERVE10 0x00f8 525#define mmDAGB1_RESERVE10_BASE_IDX 0 526#define mmDAGB1_RESERVE11 0x00f9 527#define mmDAGB1_RESERVE11_BASE_IDX 0 528#define mmDAGB1_RESERVE12 0x00fa 529#define mmDAGB1_RESERVE12_BASE_IDX 0 530#define mmDAGB1_RESERVE13 0x00fb 531#define mmDAGB1_RESERVE13_BASE_IDX 0 532#define mmDAGB1_RESERVE14 0x00fc 533#define mmDAGB1_RESERVE14_BASE_IDX 0 534#define mmDAGB1_RESERVE15 0x00fd 535#define mmDAGB1_RESERVE15_BASE_IDX 0 536#define mmDAGB1_RESERVE16 0x00fe 537#define mmDAGB1_RESERVE16_BASE_IDX 0 538#define mmDAGB1_RESERVE17 0x00ff 539#define mmDAGB1_RESERVE17_BASE_IDX 0 540 541 542// addressBlock: mmhub_ea_mmeadec 543// base address: 0x68400 544#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100 545#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 546#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101 547#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 548#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102 549#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 550#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103 551#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 552#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104 553#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 554#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105 555#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 556#define mmMMEA0_DRAM_RD_LAZY 0x0106 557#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 0 558#define mmMMEA0_DRAM_WR_LAZY 0x0107 559#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 0 560#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108 561#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0 562#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109 563#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0 564#define mmMMEA0_DRAM_PAGE_BURST 0x010a 565#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 0 566#define mmMMEA0_DRAM_RD_PRI_AGE 0x010b 567#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0 568#define mmMMEA0_DRAM_WR_PRI_AGE 0x010c 569#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0 570#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d 571#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0 572#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e 573#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0 574#define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f 575#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0 576#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110 577#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0 578#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111 579#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0 580#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112 581#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0 582#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113 583#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 584#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114 585#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 586#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115 587#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 588#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116 589#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 590#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117 591#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 592#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118 593#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 594#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0132 595#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0 596#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0133 597#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 598#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0134 599#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0 600#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0135 601#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 602#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0136 603#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 604#define mmMMEA0_ADDRNORM_HOLE_CNTL 0x0141 605#define mmMMEA0_ADDRNORM_HOLE_CNTL_BASE_IDX 0 606#define mmMMEA0_ADDRDEC_BANK_CFG 0x0142 607#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0 608#define mmMMEA0_ADDRDEC_MISC_CFG 0x0143 609#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0 610#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0144 611#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 612#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x0145 613#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 614#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x0146 615#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 616#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x0147 617#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 618#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x0148 619#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 620#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x0149 621#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 622#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x014a 623#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 624#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x014b 625#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 626#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x014c 627#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 628#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x014d 629#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 630#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x0158 631#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 632#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0159 633#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 634#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x015a 635#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 636#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x015b 637#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 638#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x015c 639#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 640#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x015d 641#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 642#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x015e 643#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 644#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x015f 645#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 646#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0160 647#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 648#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0161 649#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 650#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0162 651#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 652#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0163 653#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 654#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0164 655#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 656#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x0165 657#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 658#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x0166 659#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 660#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x0167 661#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 662#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0168 663#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 664#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0169 665#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 666#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x016a 667#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 668#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x016b 669#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 670#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x016c 671#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 672#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x016d 673#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 674#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x016e 675#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 676#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x016f 677#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 678#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0170 679#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 680#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x0171 681#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 682#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x0172 683#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 684#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0173 685#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 686#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0174 687#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 688#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x0175 689#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 690#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x0176 691#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 692#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0177 693#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 694#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0178 695#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 696#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0179 697#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 698#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x017a 699#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 700#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x017b 701#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 702#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x017c 703#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 704#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x017d 705#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 706#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x017e 707#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 708#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x017f 709#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 710#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x0180 711#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 712#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x0181 713#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 714#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x0182 715#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 716#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0183 717#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 718#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0184 719#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 720#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0185 721#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 722#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0186 723#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 724#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0187 725#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 726#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01d0 727#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 728#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01d1 729#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 730#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01d2 731#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 732#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01d3 733#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 734#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01d4 735#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0 736#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01d5 737#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0 738#define mmMMEA0_IO_GROUP_BURST 0x01d6 739#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 0 740#define mmMMEA0_IO_RD_PRI_AGE 0x01d7 741#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 0 742#define mmMMEA0_IO_WR_PRI_AGE 0x01d8 743#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 0 744#define mmMMEA0_IO_RD_PRI_QUEUING 0x01d9 745#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0 746#define mmMMEA0_IO_WR_PRI_QUEUING 0x01da 747#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0 748#define mmMMEA0_IO_RD_PRI_FIXED 0x01db 749#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0 750#define mmMMEA0_IO_WR_PRI_FIXED 0x01dc 751#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0 752#define mmMMEA0_IO_RD_PRI_URGENCY 0x01dd 753#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0 754#define mmMMEA0_IO_WR_PRI_URGENCY 0x01de 755#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0 756#define mmMMEA0_IO_RD_PRI_URGENCY_MASK 0x01df 757#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 758#define mmMMEA0_IO_WR_PRI_URGENCY_MASK 0x01e0 759#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 760#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01e1 761#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 762#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01e2 763#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 764#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01e3 765#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 766#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01e4 767#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 768#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01e5 769#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 770#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01e6 771#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 772#define mmMMEA0_SDP_ARB_DRAM 0x01e7 773#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 0 774#define mmMMEA0_SDP_ARB_FINAL 0x01e9 775#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 0 776#define mmMMEA0_SDP_DRAM_PRIORITY 0x01ea 777#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0 778#define mmMMEA0_SDP_IO_PRIORITY 0x01ec 779#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 0 780#define mmMMEA0_SDP_CREDITS 0x01ed 781#define mmMMEA0_SDP_CREDITS_BASE_IDX 0 782#define mmMMEA0_SDP_TAG_RESERVE0 0x01ee 783#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0 784#define mmMMEA0_SDP_TAG_RESERVE1 0x01ef 785#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0 786#define mmMMEA0_SDP_VCC_RESERVE0 0x01f0 787#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0 788#define mmMMEA0_SDP_VCC_RESERVE1 0x01f1 789#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0 790#define mmMMEA0_SDP_VCD_RESERVE0 0x01f2 791#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0 792#define mmMMEA0_SDP_VCD_RESERVE1 0x01f3 793#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0 794#define mmMMEA0_SDP_REQ_CNTL 0x01f4 795#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 0 796#define mmMMEA0_MISC 0x01f5 797#define mmMMEA0_MISC_BASE_IDX 0 798#define mmMMEA0_LATENCY_SAMPLING 0x01f6 799#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 0 800#define mmMMEA0_PERFCOUNTER_LO 0x01f7 801#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 0 802#define mmMMEA0_PERFCOUNTER_HI 0x01f8 803#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 0 804#define mmMMEA0_PERFCOUNTER0_CFG 0x01f9 805#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0 806#define mmMMEA0_PERFCOUNTER1_CFG 0x01fa 807#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 808#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x01fb 809#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 810#define mmMMEA0_EDC_CNT 0x0201 811#define mmMMEA0_EDC_CNT_BASE_IDX 0 812#define mmMMEA0_EDC_CNT2 0x0202 813#define mmMMEA0_EDC_CNT2_BASE_IDX 0 814#define mmMMEA0_DSM_CNTL 0x0203 815#define mmMMEA0_DSM_CNTL_BASE_IDX 0 816#define mmMMEA0_DSM_CNTLA 0x0204 817#define mmMMEA0_DSM_CNTLA_BASE_IDX 0 818#define mmMMEA0_DSM_CNTLB 0x0205 819#define mmMMEA0_DSM_CNTLB_BASE_IDX 0 820#define mmMMEA0_DSM_CNTL2 0x0206 821#define mmMMEA0_DSM_CNTL2_BASE_IDX 0 822#define mmMMEA0_DSM_CNTL2A 0x0207 823#define mmMMEA0_DSM_CNTL2A_BASE_IDX 0 824#define mmMMEA0_DSM_CNTL2B 0x0208 825#define mmMMEA0_DSM_CNTL2B_BASE_IDX 0 826#define mmMMEA0_CGTT_CLK_CTRL 0x020a 827#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 0 828#define mmMMEA0_EDC_MODE 0x020b 829#define mmMMEA0_EDC_MODE_BASE_IDX 0 830#define mmMMEA0_ERR_STATUS 0x020c 831#define mmMMEA0_ERR_STATUS_BASE_IDX 0 832#define mmMMEA0_MISC2 0x020d 833#define mmMMEA0_MISC2_BASE_IDX 0 834#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0240 835#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 836#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0241 837#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 838#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0242 839#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 840#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0243 841#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 842#define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x0244 843#define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 844#define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x0245 845#define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 846#define mmMMEA1_DRAM_RD_LAZY 0x0246 847#define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 0 848#define mmMMEA1_DRAM_WR_LAZY 0x0247 849#define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 0 850#define mmMMEA1_DRAM_RD_CAM_CNTL 0x0248 851#define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0 852#define mmMMEA1_DRAM_WR_CAM_CNTL 0x0249 853#define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0 854#define mmMMEA1_DRAM_PAGE_BURST 0x024a 855#define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 0 856#define mmMMEA1_DRAM_RD_PRI_AGE 0x024b 857#define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0 858#define mmMMEA1_DRAM_WR_PRI_AGE 0x024c 859#define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0 860#define mmMMEA1_DRAM_RD_PRI_QUEUING 0x024d 861#define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0 862#define mmMMEA1_DRAM_WR_PRI_QUEUING 0x024e 863#define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0 864#define mmMMEA1_DRAM_RD_PRI_FIXED 0x024f 865#define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0 866#define mmMMEA1_DRAM_WR_PRI_FIXED 0x0250 867#define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0 868#define mmMMEA1_DRAM_RD_PRI_URGENCY 0x0251 869#define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0 870#define mmMMEA1_DRAM_WR_PRI_URGENCY 0x0252 871#define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0 872#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0253 873#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 874#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0254 875#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 876#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0255 877#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 878#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0256 879#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 880#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0257 881#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 882#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0258 883#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 884#define mmMMEA1_ADDRNORM_BASE_ADDR0 0x0272 885#define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0 886#define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x0273 887#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 888#define mmMMEA1_ADDRNORM_BASE_ADDR1 0x0274 889#define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0 890#define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x0275 891#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 892#define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x0276 893#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 894#define mmMMEA1_ADDRNORM_HOLE_CNTL 0x0281 895#define mmMMEA1_ADDRNORM_HOLE_CNTL_BASE_IDX 0 896#define mmMMEA1_ADDRDEC_BANK_CFG 0x0282 897#define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0 898#define mmMMEA1_ADDRDEC_MISC_CFG 0x0283 899#define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0 900#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0284 901#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 902#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x0285 903#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 904#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x0286 905#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 906#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x0287 907#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 908#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x0288 909#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 910#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x0289 911#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 912#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x028a 913#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 914#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x028b 915#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 916#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x028c 917#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 918#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x028d 919#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 920#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x0298 921#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 922#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x0299 923#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 924#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x029a 925#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 926#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x029b 927#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 928#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x029c 929#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 930#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x029d 931#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 932#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x029e 933#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 934#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x029f 935#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 936#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x02a0 937#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 938#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x02a1 939#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 940#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x02a2 941#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 942#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x02a3 943#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 944#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x02a4 945#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 946#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x02a5 947#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 948#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x02a6 949#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 950#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x02a7 951#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 952#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x02a8 953#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 954#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x02a9 955#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 956#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x02aa 957#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 958#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x02ab 959#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 960#define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x02ac 961#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 962#define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x02ad 963#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 964#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x02ae 965#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 966#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x02af 967#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 968#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x02b0 969#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 970#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x02b1 971#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 972#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x02b2 973#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 974#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x02b3 975#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 976#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x02b4 977#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 978#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x02b5 979#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 980#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x02b6 981#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 982#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x02b7 983#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 984#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x02b8 985#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 986#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x02b9 987#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 988#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x02ba 989#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 990#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x02bb 991#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 992#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x02bc 993#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 994#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x02bd 995#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 996#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x02be 997#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 998#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x02bf 999#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 1000#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x02c0 1001#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 1002#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x02c1 1003#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 1004#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x02c2 1005#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 1006#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x02c3 1007#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 1008#define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x02c4 1009#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 1010#define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x02c5 1011#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 1012#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x02c6 1013#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 1014#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x02c7 1015#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 1016#define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0310 1017#define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 1018#define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0311 1019#define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 1020#define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0312 1021#define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 1022#define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0313 1023#define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 1024#define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0314 1025#define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0 1026#define mmMMEA1_IO_WR_COMBINE_FLUSH 0x0315 1027#define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0 1028#define mmMMEA1_IO_GROUP_BURST 0x0316 1029#define mmMMEA1_IO_GROUP_BURST_BASE_IDX 0 1030#define mmMMEA1_IO_RD_PRI_AGE 0x0317 1031#define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 0 1032#define mmMMEA1_IO_WR_PRI_AGE 0x0318 1033#define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 0 1034#define mmMMEA1_IO_RD_PRI_QUEUING 0x0319 1035#define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0 1036#define mmMMEA1_IO_WR_PRI_QUEUING 0x031a 1037#define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0 1038#define mmMMEA1_IO_RD_PRI_FIXED 0x031b 1039#define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0 1040#define mmMMEA1_IO_WR_PRI_FIXED 0x031c 1041#define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0 1042#define mmMMEA1_IO_RD_PRI_URGENCY 0x031d 1043#define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0 1044#define mmMMEA1_IO_WR_PRI_URGENCY 0x031e 1045#define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0 1046#define mmMMEA1_IO_RD_PRI_URGENCY_MASK 0x031f 1047#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 1048#define mmMMEA1_IO_WR_PRI_URGENCY_MASK 0x0320 1049#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 1050#define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x0321 1051#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 1052#define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x0322 1053#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 1054#define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x0323 1055#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 1056#define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x0324 1057#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 1058#define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x0325 1059#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 1060#define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x0326 1061#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 1062#define mmMMEA1_SDP_ARB_DRAM 0x0327 1063#define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 0 1064#define mmMMEA1_SDP_ARB_FINAL 0x0329 1065#define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 0 1066#define mmMMEA1_SDP_DRAM_PRIORITY 0x032a 1067#define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0 1068#define mmMMEA1_SDP_IO_PRIORITY 0x032c 1069#define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 0 1070#define mmMMEA1_SDP_CREDITS 0x032d 1071#define mmMMEA1_SDP_CREDITS_BASE_IDX 0 1072#define mmMMEA1_SDP_TAG_RESERVE0 0x032e 1073#define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0 1074#define mmMMEA1_SDP_TAG_RESERVE1 0x032f 1075#define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0 1076#define mmMMEA1_SDP_VCC_RESERVE0 0x0330 1077#define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0 1078#define mmMMEA1_SDP_VCC_RESERVE1 0x0331 1079#define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0 1080#define mmMMEA1_SDP_VCD_RESERVE0 0x0332 1081#define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0 1082#define mmMMEA1_SDP_VCD_RESERVE1 0x0333 1083#define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0 1084#define mmMMEA1_SDP_REQ_CNTL 0x0334 1085#define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 0 1086#define mmMMEA1_MISC 0x0335 1087#define mmMMEA1_MISC_BASE_IDX 0 1088#define mmMMEA1_LATENCY_SAMPLING 0x0336 1089#define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 0 1090#define mmMMEA1_PERFCOUNTER_LO 0x0337 1091#define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 0 1092#define mmMMEA1_PERFCOUNTER_HI 0x0338 1093#define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 0 1094#define mmMMEA1_PERFCOUNTER0_CFG 0x0339 1095#define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0 1096#define mmMMEA1_PERFCOUNTER1_CFG 0x033a 1097#define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0 1098#define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x033b 1099#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1100#define mmMMEA1_EDC_CNT 0x0341 1101#define mmMMEA1_EDC_CNT_BASE_IDX 0 1102#define mmMMEA1_EDC_CNT2 0x0342 1103#define mmMMEA1_EDC_CNT2_BASE_IDX 0 1104#define mmMMEA1_DSM_CNTL 0x0343 1105#define mmMMEA1_DSM_CNTL_BASE_IDX 0 1106#define mmMMEA1_DSM_CNTLA 0x0344 1107#define mmMMEA1_DSM_CNTLA_BASE_IDX 0 1108#define mmMMEA1_DSM_CNTLB 0x0345 1109#define mmMMEA1_DSM_CNTLB_BASE_IDX 0 1110#define mmMMEA1_DSM_CNTL2 0x0346 1111#define mmMMEA1_DSM_CNTL2_BASE_IDX 0 1112#define mmMMEA1_DSM_CNTL2A 0x0347 1113#define mmMMEA1_DSM_CNTL2A_BASE_IDX 0 1114#define mmMMEA1_DSM_CNTL2B 0x0348 1115#define mmMMEA1_DSM_CNTL2B_BASE_IDX 0 1116#define mmMMEA1_CGTT_CLK_CTRL 0x034a 1117#define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 0 1118#define mmMMEA1_EDC_MODE 0x034b 1119#define mmMMEA1_EDC_MODE_BASE_IDX 0 1120#define mmMMEA1_ERR_STATUS 0x034c 1121#define mmMMEA1_ERR_STATUS_BASE_IDX 0 1122#define mmMMEA1_MISC2 0x034d 1123#define mmMMEA1_MISC2_BASE_IDX 0 1124 1125 1126// addressBlock: mmhub_pctldec 1127// base address: 0x68e00 1128#define mmPCTL_MISC 0x0380 1129#define mmPCTL_MISC_BASE_IDX 0 1130#define mmPCTL_MMHUB_DEEPSLEEP 0x0381 1131#define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX 0 1132#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 1133#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 1134#define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0383 1135#define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 1136#define mmPCTL_PG_DAGB 0x0384 1137#define mmPCTL_PG_DAGB_BASE_IDX 0 1138#define mmPCTL0_RENG_RAM_INDEX 0x0385 1139#define mmPCTL0_RENG_RAM_INDEX_BASE_IDX 0 1140#define mmPCTL0_RENG_RAM_DATA 0x0386 1141#define mmPCTL0_RENG_RAM_DATA_BASE_IDX 0 1142#define mmPCTL0_RENG_EXECUTE 0x0387 1143#define mmPCTL0_RENG_EXECUTE_BASE_IDX 0 1144#define mmPCTL0_MISC 0x0388 1145#define mmPCTL0_MISC_BASE_IDX 0 1146#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0x0389 1147#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 1148#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0x038a 1149#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 1150#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0x038b 1151#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 1152#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0x038c 1153#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 1154#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x038d 1155#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 1156#define mmPCTL1_RENG_RAM_INDEX 0x038e 1157#define mmPCTL1_RENG_RAM_INDEX_BASE_IDX 0 1158#define mmPCTL1_RENG_RAM_DATA 0x038f 1159#define mmPCTL1_RENG_RAM_DATA_BASE_IDX 0 1160#define mmPCTL1_RENG_EXECUTE 0x0390 1161#define mmPCTL1_RENG_EXECUTE_BASE_IDX 0 1162#define mmPCTL1_MISC 0x0391 1163#define mmPCTL1_MISC_BASE_IDX 0 1164#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0x0392 1165#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 1166#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0x0393 1167#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 1168#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0x0394 1169#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 1170#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0x0395 1171#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 1172#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0396 1173#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 1174#define mmPCTL2_RENG_RAM_INDEX 0x0397 1175#define mmPCTL2_RENG_RAM_INDEX_BASE_IDX 0 1176#define mmPCTL2_RENG_RAM_DATA 0x0398 1177#define mmPCTL2_RENG_RAM_DATA_BASE_IDX 0 1178#define mmPCTL2_RENG_EXECUTE 0x0399 1179#define mmPCTL2_RENG_EXECUTE_BASE_IDX 0 1180#define mmPCTL2_MISC 0x039a 1181#define mmPCTL2_MISC_BASE_IDX 0 1182#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b 1183#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 1184#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c 1185#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 1186#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d 1187#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 1188#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0x039e 1189#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 1190#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x039f 1191#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 1192 1193 1194// addressBlock: mmhub_l1tlb_vml1dec 1195// base address: 0x69600 1196#define mmMC_VM_MX_L1_TLB0_STATUS 0x0588 1197#define mmMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 1198#define mmMC_VM_MX_L1_TLB1_STATUS 0x0589 1199#define mmMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 1200#define mmMC_VM_MX_L1_TLB2_STATUS 0x058a 1201#define mmMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 1202#define mmMC_VM_MX_L1_TLB3_STATUS 0x058b 1203#define mmMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 1204#define mmMC_VM_MX_L1_TLB4_STATUS 0x058c 1205#define mmMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 1206#define mmMC_VM_MX_L1_TLB5_STATUS 0x058d 1207#define mmMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 1208#define mmMC_VM_MX_L1_TLB6_STATUS 0x058e 1209#define mmMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0 1210#define mmMC_VM_MX_L1_TLB7_STATUS 0x058f 1211#define mmMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0 1212 1213 1214// addressBlock: mmhub_l1tlb_vml1pldec 1215// base address: 0x69650 1216#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0594 1217#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 1218#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0595 1219#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 1220#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0596 1221#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 1222#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0597 1223#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 1224#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0598 1225#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1226 1227 1228// addressBlock: mmhub_l1tlb_vml1prdec 1229// base address: 0x69670 1230#define mmMC_VM_MX_L1_PERFCOUNTER_LO 0x059c 1231#define mmMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 1232#define mmMC_VM_MX_L1_PERFCOUNTER_HI 0x059d 1233#define mmMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 1234 1235// Stand Alone Walker Registers 1236#define VMC_TAP_PDE_REQUEST_SNOOP_OFFSET 8 1237#define VMC_TAP_PTE_REQUEST_SNOOP_OFFSET 11 1238#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0606 1239#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1240#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0607 1241#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1242#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0608 1243#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1244#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0609 1245#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1246#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x060a 1247#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1248#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x060b 1249#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1250#define mmVM_L2_SAW_CONTEXT0_CNTL 0x0604 1251#define mmVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX 0 1252#define CONTEXT0_CNTL_ENABLE_OFFSET 0 1253#define CONTEXT0_CNTL_PAGE_TABLE_DEPTH_OFFSET 1 1254#define mmVM_L2_SAW_CONTEXTS_DISABLE 0x060c 1255#define mmVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX 0 1256#define mmVM_L2_SAW_CNTL4 0x0603 1257#define mmVM_L2_SAW_CNTL4_BASE_IDX 0 1258 1259// addressBlock: mmhub_utcl2_atcl2dec 1260// base address: 0x69900 1261#define mmATC_L2_CNTL 0x0640 1262#define mmATC_L2_CNTL_BASE_IDX 0 1263#define mmATC_L2_CNTL2 0x0641 1264#define mmATC_L2_CNTL2_BASE_IDX 0 1265#define mmATC_L2_CACHE_DATA0 0x0644 1266#define mmATC_L2_CACHE_DATA0_BASE_IDX 0 1267#define mmATC_L2_CACHE_DATA1 0x0645 1268#define mmATC_L2_CACHE_DATA1_BASE_IDX 0 1269#define mmATC_L2_CACHE_DATA2 0x0646 1270#define mmATC_L2_CACHE_DATA2_BASE_IDX 0 1271#define mmATC_L2_CNTL3 0x0647 1272#define mmATC_L2_CNTL3_BASE_IDX 0 1273#define mmATC_L2_STATUS 0x0648 1274#define mmATC_L2_STATUS_BASE_IDX 0 1275#define mmATC_L2_STATUS2 0x0649 1276#define mmATC_L2_STATUS2_BASE_IDX 0 1277#define mmATC_L2_MISC_CG 0x064a 1278#define mmATC_L2_MISC_CG_BASE_IDX 0 1279#define mmATC_L2_MEM_POWER_LS 0x064b 1280#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0 1281#define mmATC_L2_CGTT_CLK_CTRL 0x064c 1282#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 1283 1284 1285// addressBlock: mmhub_utcl2_vml2pfdec 1286// base address: 0x69a00 1287#define mmVM_L2_CNTL 0x0680 1288#define mmVM_L2_CNTL_BASE_IDX 0 1289#define mmVM_L2_CNTL2 0x0681 1290#define mmVM_L2_CNTL2_BASE_IDX 0 1291#define mmVM_L2_CNTL3 0x0682 1292#define mmVM_L2_CNTL3_BASE_IDX 0 1293#define mmVM_L2_STATUS 0x0683 1294#define mmVM_L2_STATUS_BASE_IDX 0 1295#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0684 1296#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 1297#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685 1298#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 1299#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686 1300#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 1301#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0687 1302#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 1303#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0688 1304#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 1305#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0689 1306#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 1307#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068a 1308#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 1309#define mmVM_L2_PROTECTION_FAULT_STATUS 0x068b 1310#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 1311#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068c 1312#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 1313#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068d 1314#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 1315#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068e 1316#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 1317#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x068f 1318#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 1319#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0691 1320#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 1321#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0692 1322#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 1323#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0693 1324#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 1325#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0694 1326#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 1327#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0695 1328#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 1329#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0696 1330#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 1331#define mmVM_L2_CNTL4 0x0697 1332#define mmVM_L2_CNTL4_BASE_IDX 0 1333#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0698 1334#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 1335#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0699 1336#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 1337#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x069a 1338#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 1339#define mmVM_L2_CACHE_PARITY_CNTL 0x069b 1340#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 1341#define mmVM_L2_CGTT_CLK_CTRL 0x069e 1342#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 1343 1344 1345// addressBlock: mmhub_utcl2_vml2vcdec 1346// base address: 0x69b00 1347#define mmVM_CONTEXT0_CNTL 0x06c0 1348#define mmVM_CONTEXT0_CNTL_BASE_IDX 0 1349#define mmVM_CONTEXT1_CNTL 0x06c1 1350#define mmVM_CONTEXT1_CNTL_BASE_IDX 0 1351#define mmVM_CONTEXT2_CNTL 0x06c2 1352#define mmVM_CONTEXT2_CNTL_BASE_IDX 0 1353#define mmVM_CONTEXT3_CNTL 0x06c3 1354#define mmVM_CONTEXT3_CNTL_BASE_IDX 0 1355#define mmVM_CONTEXT4_CNTL 0x06c4 1356#define mmVM_CONTEXT4_CNTL_BASE_IDX 0 1357#define mmVM_CONTEXT5_CNTL 0x06c5 1358#define mmVM_CONTEXT5_CNTL_BASE_IDX 0 1359#define mmVM_CONTEXT6_CNTL 0x06c6 1360#define mmVM_CONTEXT6_CNTL_BASE_IDX 0 1361#define mmVM_CONTEXT7_CNTL 0x06c7 1362#define mmVM_CONTEXT7_CNTL_BASE_IDX 0 1363#define mmVM_CONTEXT8_CNTL 0x06c8 1364#define mmVM_CONTEXT8_CNTL_BASE_IDX 0 1365#define mmVM_CONTEXT9_CNTL 0x06c9 1366#define mmVM_CONTEXT9_CNTL_BASE_IDX 0 1367#define mmVM_CONTEXT10_CNTL 0x06ca 1368#define mmVM_CONTEXT10_CNTL_BASE_IDX 0 1369#define mmVM_CONTEXT11_CNTL 0x06cb 1370#define mmVM_CONTEXT11_CNTL_BASE_IDX 0 1371#define mmVM_CONTEXT12_CNTL 0x06cc 1372#define mmVM_CONTEXT12_CNTL_BASE_IDX 0 1373#define mmVM_CONTEXT13_CNTL 0x06cd 1374#define mmVM_CONTEXT13_CNTL_BASE_IDX 0 1375#define mmVM_CONTEXT14_CNTL 0x06ce 1376#define mmVM_CONTEXT14_CNTL_BASE_IDX 0 1377#define mmVM_CONTEXT15_CNTL 0x06cf 1378#define mmVM_CONTEXT15_CNTL_BASE_IDX 0 1379#define mmVM_CONTEXTS_DISABLE 0x06d0 1380#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0 1381#define mmVM_INVALIDATE_ENG0_SEM 0x06d1 1382#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 1383#define mmVM_INVALIDATE_ENG1_SEM 0x06d2 1384#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 1385#define mmVM_INVALIDATE_ENG2_SEM 0x06d3 1386#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 1387#define mmVM_INVALIDATE_ENG3_SEM 0x06d4 1388#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 1389#define mmVM_INVALIDATE_ENG4_SEM 0x06d5 1390#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 1391#define mmVM_INVALIDATE_ENG5_SEM 0x06d6 1392#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 1393#define mmVM_INVALIDATE_ENG6_SEM 0x06d7 1394#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 1395#define mmVM_INVALIDATE_ENG7_SEM 0x06d8 1396#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 1397#define mmVM_INVALIDATE_ENG8_SEM 0x06d9 1398#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 1399#define mmVM_INVALIDATE_ENG9_SEM 0x06da 1400#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 1401#define mmVM_INVALIDATE_ENG10_SEM 0x06db 1402#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 1403#define mmVM_INVALIDATE_ENG11_SEM 0x06dc 1404#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 1405#define mmVM_INVALIDATE_ENG12_SEM 0x06dd 1406#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 1407#define mmVM_INVALIDATE_ENG13_SEM 0x06de 1408#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 1409#define mmVM_INVALIDATE_ENG14_SEM 0x06df 1410#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 1411#define mmVM_INVALIDATE_ENG15_SEM 0x06e0 1412#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 1413#define mmVM_INVALIDATE_ENG16_SEM 0x06e1 1414#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 1415#define mmVM_INVALIDATE_ENG17_SEM 0x06e2 1416#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 1417#define mmVM_INVALIDATE_ENG0_REQ 0x06e3 1418#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 1419#define mmVM_INVALIDATE_ENG1_REQ 0x06e4 1420#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 1421#define mmVM_INVALIDATE_ENG2_REQ 0x06e5 1422#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 1423#define mmVM_INVALIDATE_ENG3_REQ 0x06e6 1424#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 1425#define mmVM_INVALIDATE_ENG4_REQ 0x06e7 1426#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 1427#define mmVM_INVALIDATE_ENG5_REQ 0x06e8 1428#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 1429#define mmVM_INVALIDATE_ENG6_REQ 0x06e9 1430#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 1431#define mmVM_INVALIDATE_ENG7_REQ 0x06ea 1432#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 1433#define mmVM_INVALIDATE_ENG8_REQ 0x06eb 1434#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 1435#define mmVM_INVALIDATE_ENG9_REQ 0x06ec 1436#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 1437#define mmVM_INVALIDATE_ENG10_REQ 0x06ed 1438#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 1439#define mmVM_INVALIDATE_ENG11_REQ 0x06ee 1440#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 1441#define mmVM_INVALIDATE_ENG12_REQ 0x06ef 1442#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 1443#define mmVM_INVALIDATE_ENG13_REQ 0x06f0 1444#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 1445#define mmVM_INVALIDATE_ENG14_REQ 0x06f1 1446#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 1447#define mmVM_INVALIDATE_ENG15_REQ 0x06f2 1448#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 1449#define mmVM_INVALIDATE_ENG16_REQ 0x06f3 1450#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 1451#define mmVM_INVALIDATE_ENG17_REQ 0x06f4 1452#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 1453#define mmVM_INVALIDATE_ENG0_ACK 0x06f5 1454#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 1455#define mmVM_INVALIDATE_ENG1_ACK 0x06f6 1456#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 1457#define mmVM_INVALIDATE_ENG2_ACK 0x06f7 1458#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 1459#define mmVM_INVALIDATE_ENG3_ACK 0x06f8 1460#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 1461#define mmVM_INVALIDATE_ENG4_ACK 0x06f9 1462#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 1463#define mmVM_INVALIDATE_ENG5_ACK 0x06fa 1464#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 1465#define mmVM_INVALIDATE_ENG6_ACK 0x06fb 1466#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 1467#define mmVM_INVALIDATE_ENG7_ACK 0x06fc 1468#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 1469#define mmVM_INVALIDATE_ENG8_ACK 0x06fd 1470#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 1471#define mmVM_INVALIDATE_ENG9_ACK 0x06fe 1472#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 1473#define mmVM_INVALIDATE_ENG10_ACK 0x06ff 1474#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 1475#define mmVM_INVALIDATE_ENG11_ACK 0x0700 1476#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 1477#define mmVM_INVALIDATE_ENG12_ACK 0x0701 1478#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 1479#define mmVM_INVALIDATE_ENG13_ACK 0x0702 1480#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 1481#define mmVM_INVALIDATE_ENG14_ACK 0x0703 1482#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 1483#define mmVM_INVALIDATE_ENG15_ACK 0x0704 1484#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 1485#define mmVM_INVALIDATE_ENG16_ACK 0x0705 1486#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 1487#define mmVM_INVALIDATE_ENG17_ACK 0x0706 1488#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 1489#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707 1490#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 1491#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708 1492#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 1493#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709 1494#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 1495#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a 1496#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 1497#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b 1498#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 1499#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c 1500#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 1501#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d 1502#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 1503#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e 1504#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 1505#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f 1506#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 1507#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710 1508#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 1509#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711 1510#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 1511#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712 1512#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 1513#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713 1514#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 1515#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714 1516#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 1517#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715 1518#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 1519#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716 1520#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 1521#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717 1522#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 1523#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718 1524#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 1525#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719 1526#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 1527#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a 1528#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 1529#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b 1530#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 1531#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c 1532#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 1533#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d 1534#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 1535#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e 1536#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 1537#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f 1538#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 1539#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720 1540#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 1541#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721 1542#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 1543#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722 1544#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 1545#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723 1546#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 1547#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724 1548#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 1549#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725 1550#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 1551#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726 1552#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 1553#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 1554#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 1555#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 1556#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 1557#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729 1558#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 1559#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a 1560#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 1561#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b 1562#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1563#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c 1564#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1565#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d 1566#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1567#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e 1568#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1569#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f 1570#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1571#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730 1572#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1573#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731 1574#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1575#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732 1576#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1577#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733 1578#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1579#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734 1580#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1581#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735 1582#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1583#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736 1584#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1585#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737 1586#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1587#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738 1588#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1589#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739 1590#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1591#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a 1592#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1593#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b 1594#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1595#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c 1596#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1597#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d 1598#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1599#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e 1600#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1601#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f 1602#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1603#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740 1604#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1605#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741 1606#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1607#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742 1608#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1609#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743 1610#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1611#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744 1612#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1613#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745 1614#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1615#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746 1616#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1617#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747 1618#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1619#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748 1620#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1621#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749 1622#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1623#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a 1624#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1625#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b 1626#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1627#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c 1628#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1629#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d 1630#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1631#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e 1632#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1633#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f 1634#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1635#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750 1636#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1637#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751 1638#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1639#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752 1640#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1641#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753 1642#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1643#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754 1644#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1645#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755 1646#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1647#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756 1648#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1649#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757 1650#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1651#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758 1652#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1653#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759 1654#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1655#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a 1656#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1657#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b 1658#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1659#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c 1660#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1661#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d 1662#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1663#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e 1664#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1665#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f 1666#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1667#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760 1668#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1669#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761 1670#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1671#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762 1672#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1673#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763 1674#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1675#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764 1676#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1677#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765 1678#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1679#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766 1680#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1681#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767 1682#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1683#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768 1684#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1685#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769 1686#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1687#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a 1688#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1689#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b 1690#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1691#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c 1692#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1693#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d 1694#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1695#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e 1696#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1697#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f 1698#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1699#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770 1700#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1701#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771 1702#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1703#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772 1704#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1705#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773 1706#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1707#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774 1708#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1709#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775 1710#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1711#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776 1712#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1713#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777 1714#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1715#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778 1716#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1717#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779 1718#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1719#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a 1720#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1721#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b 1722#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1723#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c 1724#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1725#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d 1726#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1727#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e 1728#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1729#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f 1730#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1731#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780 1732#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1733#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781 1734#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1735#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782 1736#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1737#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783 1738#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1739#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784 1740#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1741#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785 1742#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1743#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786 1744#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1745#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787 1746#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1747#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788 1748#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1749#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789 1750#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1751#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a 1752#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1753 1754 1755// addressBlock: mmhub_utcl2_vml2pldec 1756// base address: 0x69e90 1757#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x07a4 1758#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 1759#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x07a5 1760#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 1761#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x07a6 1762#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 1763#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x07a7 1764#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 1765#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x07a8 1766#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 1767#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x07a9 1768#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 1769#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x07aa 1770#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 1771#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x07ab 1772#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 1773#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac 1774#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1775 1776 1777// addressBlock: mmhub_utcl2_vml2prdec 1778// base address: 0x69ee0 1779#define mmMC_VM_L2_PERFCOUNTER_LO 0x07b8 1780#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 1781#define mmMC_VM_L2_PERFCOUNTER_HI 0x07b9 1782#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 1783 1784 1785// addressBlock: mmhub_utcl2_vmsharedhvdec 1786// base address: 0x69f30 1787#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x07cc 1788#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 1789#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x07cd 1790#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 1791#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x07ce 1792#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 1793#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x07cf 1794#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 1795#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x07d0 1796#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 1797#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x07d1 1798#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 1799#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x07d2 1800#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 1801#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x07d3 1802#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 1803#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x07d4 1804#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 1805#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x07d5 1806#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 1807#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x07d6 1808#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 1809#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x07d7 1810#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 1811#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x07d8 1812#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 1813#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x07d9 1814#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 1815#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x07da 1816#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 1817#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x07db 1818#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 1819#define mmVM_IOMMU_MMIO_CNTRL_1 0x07dc 1820#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0 1821#define mmMC_VM_MARC_BASE_LO_0 0x07dd 1822#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 0 1823#define mmMC_VM_MARC_BASE_LO_1 0x07de 1824#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 0 1825#define mmMC_VM_MARC_BASE_LO_2 0x07df 1826#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 0 1827#define mmMC_VM_MARC_BASE_LO_3 0x07e0 1828#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 0 1829#define mmMC_VM_MARC_BASE_HI_0 0x07e1 1830#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 0 1831#define mmMC_VM_MARC_BASE_HI_1 0x07e2 1832#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 0 1833#define mmMC_VM_MARC_BASE_HI_2 0x07e3 1834#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 0 1835#define mmMC_VM_MARC_BASE_HI_3 0x07e4 1836#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 0 1837#define mmMC_VM_MARC_RELOC_LO_0 0x07e5 1838#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 0 1839#define mmMC_VM_MARC_RELOC_LO_1 0x07e6 1840#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 0 1841#define mmMC_VM_MARC_RELOC_LO_2 0x07e7 1842#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 0 1843#define mmMC_VM_MARC_RELOC_LO_3 0x07e8 1844#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 0 1845#define mmMC_VM_MARC_RELOC_HI_0 0x07e9 1846#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 0 1847#define mmMC_VM_MARC_RELOC_HI_1 0x07ea 1848#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 0 1849#define mmMC_VM_MARC_RELOC_HI_2 0x07eb 1850#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 0 1851#define mmMC_VM_MARC_RELOC_HI_3 0x07ec 1852#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 0 1853#define mmMC_VM_MARC_LEN_LO_0 0x07ed 1854#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 0 1855#define mmMC_VM_MARC_LEN_LO_1 0x07ee 1856#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 0 1857#define mmMC_VM_MARC_LEN_LO_2 0x07ef 1858#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 0 1859#define mmMC_VM_MARC_LEN_LO_3 0x07f0 1860#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 0 1861#define mmMC_VM_MARC_LEN_HI_0 0x07f1 1862#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 0 1863#define mmMC_VM_MARC_LEN_HI_1 0x07f2 1864#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 0 1865#define mmMC_VM_MARC_LEN_HI_2 0x07f3 1866#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 0 1867#define mmMC_VM_MARC_LEN_HI_3 0x07f4 1868#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 0 1869#define mmVM_IOMMU_CONTROL_REGISTER 0x07f5 1870#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0 1871#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x07f6 1872#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0 1873#define mmVM_PCIE_ATS_CNTL 0x07f7 1874#define mmVM_PCIE_ATS_CNTL_BASE_IDX 0 1875#define mmVM_PCIE_ATS_CNTL_VF_0 0x07f8 1876#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 1877#define mmVM_PCIE_ATS_CNTL_VF_1 0x07f9 1878#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 1879#define mmVM_PCIE_ATS_CNTL_VF_2 0x07fa 1880#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 1881#define mmVM_PCIE_ATS_CNTL_VF_3 0x07fb 1882#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 1883#define mmVM_PCIE_ATS_CNTL_VF_4 0x07fc 1884#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 1885#define mmVM_PCIE_ATS_CNTL_VF_5 0x07fd 1886#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 1887#define mmVM_PCIE_ATS_CNTL_VF_6 0x07fe 1888#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 1889#define mmVM_PCIE_ATS_CNTL_VF_7 0x07ff 1890#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 1891#define mmVM_PCIE_ATS_CNTL_VF_8 0x0800 1892#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 1893#define mmVM_PCIE_ATS_CNTL_VF_9 0x0801 1894#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 1895#define mmVM_PCIE_ATS_CNTL_VF_10 0x0802 1896#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 1897#define mmVM_PCIE_ATS_CNTL_VF_11 0x0803 1898#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 1899#define mmVM_PCIE_ATS_CNTL_VF_12 0x0804 1900#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 1901#define mmVM_PCIE_ATS_CNTL_VF_13 0x0805 1902#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 1903#define mmVM_PCIE_ATS_CNTL_VF_14 0x0806 1904#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 1905#define mmVM_PCIE_ATS_CNTL_VF_15 0x0807 1906#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 1907#define mmUTCL2_CGTT_CLK_CTRL 0x0808 1908#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 1909 1910 1911// addressBlock: mmhub_utcl2_vmsharedpfdec 1912// base address: 0x6a040 1913#define mmMC_VM_NB_MMIOBASE 0x0810 1914#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0 1915#define mmMC_VM_NB_MMIOLIMIT 0x0811 1916#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0 1917#define mmMC_VM_NB_PCI_CTRL 0x0812 1918#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0 1919#define mmMC_VM_NB_PCI_ARB 0x0813 1920#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0 1921#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0814 1922#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 1923#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0815 1924#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 1925#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0816 1926#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 1927#define mmMC_VM_FB_OFFSET 0x0817 1928#define mmMC_VM_FB_OFFSET_BASE_IDX 0 1929#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0818 1930#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 1931#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0819 1932#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 1933#define mmMC_VM_STEERING 0x081a 1934#define mmMC_VM_STEERING_BASE_IDX 0 1935#define mmMC_SHARED_VIRT_RESET_REQ 0x081b 1936#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 1937#define mmMC_MEM_POWER_LS 0x081c 1938#define mmMC_MEM_POWER_LS_BASE_IDX 0 1939#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x081d 1940#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 1941#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x081e 1942#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 1943#define mmMC_VM_APT_CNTL 0x081f 1944#define mmMC_VM_APT_CNTL_BASE_IDX 0 1945#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0820 1946#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 1947#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0821 1948#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 1949#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0822 1950#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 1951 1952 1953// addressBlock: mmhub_utcl2_vmsharedvcdec 1954// base address: 0x6a0b0 1955#define mmMC_VM_FB_LOCATION_BASE 0x082c 1956#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0 1957#define mmMC_VM_FB_LOCATION_TOP 0x082d 1958#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0 1959#define mmMC_VM_AGP_TOP 0x082e 1960#define mmMC_VM_AGP_TOP_BASE_IDX 0 1961#define mmMC_VM_AGP_BOT 0x082f 1962#define mmMC_VM_AGP_BOT_BASE_IDX 0 1963#define mmMC_VM_AGP_BASE 0x0830 1964#define mmMC_VM_AGP_BASE_BASE_IDX 0 1965#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0831 1966#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 1967#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0832 1968#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 1969#define mmMC_VM_MX_L1_TLB_CNTL 0x0833 1970#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 1971 1972 1973// addressBlock: mmhub_utcl2_atcl2pfcntrdec 1974// base address: 0x6a100 1975#define mmATC_L2_PERFCOUNTER_LO 0x0840 1976#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 0 1977#define mmATC_L2_PERFCOUNTER_HI 0x0841 1978#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 0 1979 1980 1981// addressBlock: mmhub_utcl2_atcl2pfcntldec 1982// base address: 0x6a120 1983#define mmATC_L2_PERFCOUNTER0_CFG 0x0848 1984#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 1985#define mmATC_L2_PERFCOUNTER1_CFG 0x0849 1986#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 1987#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x084a 1988#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1989 1990/* MMEA */ 1991#define mmMMEA0_EDC_CNT_VG20 0x0206 1992#define mmMMEA0_EDC_CNT_VG20_BASE_IDX 0 1993#define mmMMEA0_EDC_CNT2_VG20 0x0207 1994#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX 0 1995#define mmMMEA1_EDC_CNT_VG20 0x0346 1996#define mmMMEA1_EDC_CNT_VG20_BASE_IDX 0 1997#define mmMMEA1_EDC_CNT2_VG20 0x0347 1998#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX 0 1999 2000// addressBlock: mmhub_utcl2_vmsharedpfdec 2001// base address: 0x6a040 2002#define mmMC_VM_XGMI_LFB_CNTL 0x0823 2003#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 2004#define mmMC_VM_XGMI_LFB_SIZE 0x0824 2005#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 2006#endif
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