FILE
gmc_6_0_sh_mask.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h
1/* 2 * 3 * Copyright (C) 2016 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#ifndef GMC_6_0_SH_MASK_H 24#define GMC_6_0_SH_MASK_H 25 26#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L 27#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008 28#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L 29#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010 30#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 31#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000 32#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 33#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002 34#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 35#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001 36#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x00000004L 37#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x00000002 38#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x00004000L 39#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0x0000000e 40#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x00000080L 41#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x00000007 42#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x00000002L 43#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x00000001 44#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x00008000L 45#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0x0000000f 46#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x00000001L 47#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x00000000 48#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x00010000L 49#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x00000010 50#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x00003c00L 51#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0x0000000a 52#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x00000100L 53#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x00000008 54#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x00000020L 55#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x00000005 56#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x00000040L 57#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x00000006 58#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x00000200L 59#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x00000009 60#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x0000003cL 61#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x00000002 62#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x00000001L 63#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x00000000 64#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffffL 65#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x00000000 66#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x03f00000L 67#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x00000014 68#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0000fc00L 69#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0x0000000a 70#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x0000003fL 71#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x00000000 72#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000100L 73#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000008 74#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x00010000L 75#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x00000010 76#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x0000001fL 77#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x00000000 78#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffffL 79#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x00000000 80#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L 81#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x00000010 82#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L 83#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0x0000000f 84#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x0000003fL 85#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x00000000 86#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L 87#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x00000011 88#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0f000000L 89#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x00000018 90#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L 91#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x00000012 92#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00f80000L 93#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x00000013 94#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007c00L 95#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0x0000000a 96#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L 97#define ATC_ATS_STATUS__BUSY__SHIFT 0x00000000 98#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L 99#define ATC_ATS_STATUS__CRASHED__SHIFT 0x00000001 100#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L 101#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000002 102#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffffL 103#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x00000000 104#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x00000003L 105#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x00000000 106#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x00000004L 107#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x00000002 108#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x00000010L 109#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x00000004 110#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L 111#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c 112#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L 113#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014 114#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L 115#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c 116#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L 117#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000 118#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L 119#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004 120#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L 121#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008 122#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L 123#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e 124#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x00000100L 125#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x00000008 126#define ATC_L1RD_STATUS__BUSY_MASK 0x00000001L 127#define ATC_L1RD_STATUS__BUSY__SHIFT 0x00000000 128#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L 129#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001 130#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L 131#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c 132#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L 133#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014 134#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L 135#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c 136#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L 137#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000 138#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L 139#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004 140#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L 141#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008 142#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L 143#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e 144#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x00000100L 145#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x00000008 146#define ATC_L1WR_STATUS__BUSY_MASK 0x00000001L 147#define ATC_L1WR_STATUS__BUSY__SHIFT 0x00000000 148#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L 149#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001 150#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 151#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x00000000 152#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000400L 153#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000a 154#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000030L 155#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x00000004 156#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000800L 157#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000b 158#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x0000003fL 159#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x00000000 160#define ATC_MISC_CG__ENABLE_MASK 0x00040000L 161#define ATC_MISC_CG__ENABLE__SHIFT 0x00000012 162#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 163#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x00000013 164#define ATC_MISC_CG__OFFDLY_MASK 0x00000fc0L 165#define ATC_MISC_CG__OFFDLY__SHIFT 0x00000006 166#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL 167#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000 168#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L 169#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000 170#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL 171#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 172#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL 173#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 174#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL 175#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000 176#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L 177#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000 178#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL 179#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 180#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL 181#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 182#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000ffffL 183#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x00000000 184#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L 185#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x0000001f 186#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000ffffL 187#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x00000000 188#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L 189#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x0000001f 190#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000ffffL 191#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x00000000 192#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L 193#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x0000001f 194#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000ffffL 195#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x00000000 196#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L 197#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x0000001f 198#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000ffffL 199#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x00000000 200#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L 201#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x0000001f 202#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000ffffL 203#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x00000000 204#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L 205#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x0000001f 206#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000ffffL 207#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x00000000 208#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L 209#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x0000001f 210#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000ffffL 211#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x00000000 212#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L 213#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x0000001f 214#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000ffffL 215#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x00000000 216#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L 217#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x0000001f 218#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000ffffL 219#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x00000000 220#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L 221#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x0000001f 222#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000ffffL 223#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x00000000 224#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L 225#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x0000001f 226#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000ffffL 227#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x00000000 228#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L 229#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x0000001f 230#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000ffffL 231#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x00000000 232#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L 233#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x0000001f 234#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000ffffL 235#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x00000000 236#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L 237#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x0000001f 238#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000ffffL 239#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x00000000 240#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L 241#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x0000001f 242#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000ffffL 243#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x00000000 244#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L 245#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x0000001f 246#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L 247#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x00000000 248#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L 249#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0x0000000a 250#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L 251#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0x0000000b 252#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L 253#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0x0000000c 254#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L 255#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0x0000000d 256#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L 257#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0x0000000e 258#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L 259#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0x0000000f 260#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L 261#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x00000001 262#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L 263#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x00000002 264#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L 265#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x00000003 266#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L 267#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x00000004 268#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L 269#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x00000005 270#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L 271#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x00000006 272#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L 273#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x00000007 274#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L 275#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x00000008 276#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L 277#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x00000009 278#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x0000001eL 279#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x00000001 280#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x003ff000L 281#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0x0000000c 282#define DLL_CNTL__DLL_RESET_TIME_MASK 0x000003ffL 283#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x00000000 284#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x01000000L 285#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x00000018 286#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x02000000L 287#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x00000019 288#define DLL_CNTL__PWR2_MODE_MASK 0x04000000L 289#define DLL_CNTL__PWR2_MODE__SHIFT 0x0000001a 290#define GMCON_DEBUG__GFX_CLEAR_MASK 0x00000002L 291#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x00000001 292#define GMCON_DEBUG__GFX_STALL_MASK 0x00000001L 293#define GMCON_DEBUG__GFX_STALL__SHIFT 0x00000000 294#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffcL 295#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x00000002 296#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK 0x00000007L 297#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT 0x00000000 298#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK 0x00000038L 299#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT 0x00000003 300#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x0000fc00L 301#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0x0000000a 302#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x20000000L 303#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x0000001d 304#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x10000000L 305#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x0000001c 306#define GMCON_MISC2__STCTRL_LPT_TARGET_MASK 0x0fff0000L 307#define GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT 0x00000010 308#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0x0000003fL 309#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x00000000 310#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0x00000fc0L 311#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x00000006 312#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00fff000L 313#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x0000000c 314#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x30000000L 315#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0000001c 316#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x08000000L 317#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x0000001b 318#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x00000400L 319#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0x0000000a 320#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00000800L 321#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x0000000b 322#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0x0000f000L 323#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0x0000000c 324#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x02000000L 325#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x00000019 326#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x04000000L 327#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x0000001a 328#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x40000000L 329#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x0000001e 330#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x00060000L 331#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x00000011 332#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x00400000L 333#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x00000016 334#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x00200000L 335#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x00000015 336#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x01000000L 337#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x00000018 338#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x00800000L 339#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x00000017 340#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x00180000L 341#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x00000013 342#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x00010000L 343#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x00000010 344#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000L 345#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x0000001c 346#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x03000000L 347#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x00000018 348#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0x00000fffL 349#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x00000000 350#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0x0c000000L 351#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x0000001a 352#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0x00fff000L 353#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0x0000000c 354#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x00fc0000L 355#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x00000012 356#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0x3f000000L 357#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x00000018 358#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0x00000fc0L 359#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x00000006 360#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x0003f000L 361#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x0000000c 362#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x0000003fL 363#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x00000000 364#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffffL 365#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x00000000 366#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffffL 367#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x00000000 368#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000ffL 369#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x00000000 370#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 371#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0x0000000a 372#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 373#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0x0000000b 374#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 375#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x00000008 376#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 377#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x00000009 378#define GMCON_PGFSM_CONFIG__READ_MASK 0x00002000L 379#define GMCON_PGFSM_CONFIG__READ__SHIFT 0x0000000d 380#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000L 381#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x0000001c 382#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x07ffc000L 383#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0x0000000e 384#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 385#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x0000001b 386#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x00001000L 387#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0x0000000c 388#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0x0f000000L 389#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x00000018 390#define GMCON_PGFSM_READ__READ_VALUE_MASK 0x00ffffffL 391#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x00000000 392#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000L 393#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x0000001c 394#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffffL 395#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x00000000 396#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x003ff000L 397#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0x0000000c 398#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000L 399#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x00000016 400#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 401#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x00000001 402#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000ffcL 403#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x00000002 404#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 405#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x00000000 406#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffffL 407#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x00000000 408#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003ffL 409#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x00000000 410#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000ffffL 411#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x00000000 412#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000L 413#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x00000010 414#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000ffffL 415#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x00000000 416#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000L 417#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x00000010 418#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0x0000ffffL 419#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x00000000 420#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000L 421#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x00000010 422#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0x0000ffffL 423#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x00000000 424#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000L 425#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x00000010 426#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0x0000ffffL 427#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x00000000 428#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000L 429#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x00000010 430#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0x0000000fL 431#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x00000000 432#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0x00000ff0L 433#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x00000004 434#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0x0ffff000L 435#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0x0000000c 436#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x01000000L 437#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x00000018 438#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x02000000L 439#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x00000019 440#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x04000000L 441#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x0000001a 442#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x08000000L 443#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x0000001b 444#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000L 445#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x0000001c 446#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000L 447#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x0000001d 448#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000L 449#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x0000001e 450#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000L 451#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x0000001f 452#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x00010000L 453#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x00000010 454#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x00020000L 455#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x00000011 456#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x00040000L 457#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x00000012 458#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x00080000L 459#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x00000013 460#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x00100000L 461#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x00000014 462#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x00200000L 463#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x00000015 464#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x00400000L 465#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x00000016 466#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x00800000L 467#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x00000017 468#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x00000003L 469#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x00000000 470#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0x0000000cL 471#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x00000002 472#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x00000030L 473#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x00000004 474#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0x000000c0L 475#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x00000006 476#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x00000300L 477#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x00000008 478#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0x00000c00L 479#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0x0000000a 480#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x00003000L 481#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0x0000000c 482#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0x0000c000L 483#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0x0000000e 484#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x01000000L 485#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x00000018 486#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x02000000L 487#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x00000019 488#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x04000000L 489#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x0000001a 490#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x08000000L 491#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x0000001b 492#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000L 493#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x0000001c 494#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000L 495#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x0000001d 496#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000L 497#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x0000001e 498#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000L 499#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x0000001f 500#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x00010000L 501#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x00000010 502#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x00020000L 503#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x00000011 504#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x00040000L 505#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x00000012 506#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x00080000L 507#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x00000013 508#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x00100000L 509#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x00000014 510#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x00200000L 511#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x00000015 512#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x00400000L 513#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x00000016 514#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x00800000L 515#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x00000017 516#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x00000003L 517#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x00000000 518#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0x0000000cL 519#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x00000002 520#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x00000030L 521#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x00000004 522#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0x000000c0L 523#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x00000006 524#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x00000300L 525#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x00000008 526#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0x00000c00L 527#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0x0000000a 528#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x00003000L 529#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0x0000000c 530#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0x0000c000L 531#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0x0000000e 532#define MC_ARB_BANKMAP__BANK0_MASK 0x0000000fL 533#define MC_ARB_BANKMAP__BANK0__SHIFT 0x00000000 534#define MC_ARB_BANKMAP__BANK1_MASK 0x000000f0L 535#define MC_ARB_BANKMAP__BANK1__SHIFT 0x00000004 536#define MC_ARB_BANKMAP__BANK2_MASK 0x00000f00L 537#define MC_ARB_BANKMAP__BANK2__SHIFT 0x00000008 538#define MC_ARB_BANKMAP__BANK3_MASK 0x0000f000L 539#define MC_ARB_BANKMAP__BANK3__SHIFT 0x0000000c 540#define MC_ARB_BANKMAP__RANK_MASK 0x000f0000L 541#define MC_ARB_BANKMAP__RANK__SHIFT 0x00000010 542#define MC_ARB_BURST_TIME__STATE0_MASK 0x0000001fL 543#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x00000000 544#define MC_ARB_BURST_TIME__STATE1_MASK 0x000003e0L 545#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x00000005 546#define MC_ARB_BURST_TIME__STATE2_MASK 0x00007c00L 547#define MC_ARB_BURST_TIME__STATE2__SHIFT 0x0000000a 548#define MC_ARB_BURST_TIME__STATE3_MASK 0x000f8000L 549#define MC_ARB_BURST_TIME__STATE3__SHIFT 0x0000000f 550#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x00002000L 551#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0x0000000d 552#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x00000001L 553#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x00000000 554#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x0000007eL 555#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x00000001 556#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x00001f80L 557#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x00000007 558#define MC_ARB_CG__CG_ARB_REQ_MASK 0x000000ffL 559#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x00000000 560#define MC_ARB_CG__CG_ARB_RESP_MASK 0x0000ff00L 561#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x00000008 562#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0x000000ffL 563#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x00000000 564#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0x0000ff00L 565#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x00000008 566#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0x00ff0000L 567#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x00000010 568#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000L 569#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x00000018 570#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000L 571#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x00000018 572#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0x000000ffL 573#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x00000000 574#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0x0000ff00L 575#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x00000008 576#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0x00ff0000L 577#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x00000010 578#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000L 579#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x00000018 580#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0x000000ffL 581#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x00000000 582#define MC_ARB_DRAM_TIMING2__RP_MASK 0x0000ff00L 583#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x00000008 584#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0x00ff0000L 585#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x00000010 586#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0x000000ffL 587#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x00000000 588#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0x0000ff00L 589#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x00000008 590#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0x00ff0000L 591#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x00000010 592#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000L 593#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x00000018 594#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x00000010L 595#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x00000004 596#define MC_ARB_FED_CNTL__MODE_MASK 0x00000003L 597#define MC_ARB_FED_CNTL__MODE__SHIFT 0x00000000 598#define MC_ARB_FED_CNTL__WR_ERR_MASK 0x0000000cL 599#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x00000002 600#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0x0000000fL 601#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x00000000 602#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0x000000f0L 603#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x00000004 604#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L 605#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a 606#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x00000100L 607#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x00000008 608#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x00000200L 609#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x00000009 610#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0x0000000fL 611#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x00000000 612#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0x000000f0L 613#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x00000004 614#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L 615#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a 616#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x00000100L 617#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x00000008 618#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x00000200L 619#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x00000009 620#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0x000000ffL 621#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x00000000 622#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0x0000ff00L 623#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x00000008 624#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0x00ff0000L 625#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x00000010 626#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000L 627#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x00000018 628#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x00004000L 629#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0x0000000e 630#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x001f8000L 631#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0x0000000f 632#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0x0000ff00L 633#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x00000008 634#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0x00ff0000L 635#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x00000010 636#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000L 637#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x00000018 638#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0x000000ffL 639#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x00000000 640#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x00000018L 641#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x00000003 642#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x00000004L 643#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x00000002 644#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x00000003L 645#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x00000000 646#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x00000020L 647#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x00000005 648#define MC_ARB_GECC2__ECC_MODE_MASK 0x00000006L 649#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x00000001 650#define MC_ARB_GECC2__ENABLE_MASK 0x00000001L 651#define MC_ARB_GECC2__ENABLE__SHIFT 0x00000000 652#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x00000060L 653#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x00000005 654#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0x0000000fL 655#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x00000000 656#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x00000780L 657#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x00000007 658#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x00000018L 659#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x00000003 660#define MC_ARB_GECC2__READ_ERR_MASK 0x00003800L 661#define MC_ARB_GECC2__READ_ERR__SHIFT 0x0000000b 662#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x00000100L 663#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x00000008 664#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x00001000L 665#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0x0000000c 666#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x00000001L 667#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x00000000 668#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x00000010L 669#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x00000004 670#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x00000400L 671#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0x0000000a 672#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x00004000L 673#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0x0000000e 674#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x00000004L 675#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x00000002 676#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x00000040L 677#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x00000006 678#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x00000008L 679#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x00000003 680#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x00000080L 681#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x00000007 682#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x00000800L 683#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0x0000000b 684#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x00000200L 685#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x00000009 686#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x00002000L 687#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0x0000000d 688#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x00000002L 689#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x00000001 690#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x00000020L 691#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x00000005 692#define MC_ARB_LAZY0_RD__GROUP0_MASK 0x000000ffL 693#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x00000000 694#define MC_ARB_LAZY0_RD__GROUP1_MASK 0x0000ff00L 695#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x00000008 696#define MC_ARB_LAZY0_RD__GROUP2_MASK 0x00ff0000L 697#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x00000010 698#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000L 699#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x00000018 700#define MC_ARB_LAZY0_WR__GROUP0_MASK 0x000000ffL 701#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x00000000 702#define MC_ARB_LAZY0_WR__GROUP1_MASK 0x0000ff00L 703#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x00000008 704#define MC_ARB_LAZY0_WR__GROUP2_MASK 0x00ff0000L 705#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x00000010 706#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000L 707#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x00000018 708#define MC_ARB_LAZY1_RD__GROUP4_MASK 0x000000ffL 709#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x00000000 710#define MC_ARB_LAZY1_RD__GROUP5_MASK 0x0000ff00L 711#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x00000008 712#define MC_ARB_LAZY1_RD__GROUP6_MASK 0x00ff0000L 713#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x00000010 714#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000L 715#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x00000018 716#define MC_ARB_LAZY1_WR__GROUP4_MASK 0x000000ffL 717#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x00000000 718#define MC_ARB_LAZY1_WR__GROUP5_MASK 0x0000ff00L 719#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x00000008 720#define MC_ARB_LAZY1_WR__GROUP6_MASK 0x00ff0000L 721#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x00000010 722#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000L 723#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x00000018 724#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0x00e00000L 725#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x00000015 726#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x00040000L 727#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x00000012 728#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x00080000L 729#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x00000013 730#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x00100000L 731#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x00000014 732#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x00010000L 733#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x00000010 734#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0x000000ffL 735#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x00000000 736#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0x0000ff00L 737#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x00000008 738#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x00020000L 739#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x00000011 740#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0x00e00000L 741#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x00000015 742#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x00040000L 743#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x00000012 744#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x00080000L 745#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x00000013 746#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x00100000L 747#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x00000014 748#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x00010000L 749#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x00000010 750#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0x000000ffL 751#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x00000000 752#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0x0000ff00L 753#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x00000008 754#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x00020000L 755#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x00000011 756#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x00010000L 757#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x00000010 758#define MC_ARB_MINCLKS__READ_CLKS_MASK 0x000000ffL 759#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x00000000 760#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0x0000ff00L 761#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x00000008 762#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000L 763#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x0000001d 764#define MC_ARB_MISC2__GECC_MASK 0x00040000L 765#define MC_ARB_MISC2__GECC_RST_MASK 0x00080000L 766#define MC_ARB_MISC2__GECC_RST__SHIFT 0x00000013 767#define MC_ARB_MISC2__GECC__SHIFT 0x00000012 768#define MC_ARB_MISC2__GECC_STATUS_MASK 0x00100000L 769#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x00000014 770#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x00000800L 771#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0x0000000b 772#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x00002000L 773#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0x0000000d 774#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x00001000L 775#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0x0000000c 776#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x0003c000L 777#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0x0000000e 778#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000L 779#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x0000001c 780#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000L 781#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x0000001e 782#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x01e00000L 783#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x00000015 784#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x00000040L 785#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x00000006 786#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x00000080L 787#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x00000007 788#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x00000100L 789#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x00000008 790#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x00000200L 791#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x00000009 792#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x00000400L 793#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0x0000000a 794#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x00000020L 795#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x00000005 796#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000L 797#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x0000001f 798#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0x0e000000L 799#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x00000019 800#define MC_ARB_MISC__CALI_ENABLE_MASK 0x00100000L 801#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x00000014 802#define MC_ARB_MISC__CALI_RATES_MASK 0x00600000L 803#define MC_ARB_MISC__CALI_RATES__SHIFT 0x00000015 804#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x000007f8L 805#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x00000003 806#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x01000000L 807#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x00000018 808#define MC_ARB_MISC__DISPURG_STALL_MASK 0x02000000L 809#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x00000019 810#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000L 811#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x0000001a 812#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x00800000L 813#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x00000017 814#define MC_ARB_MISC__HARSHNESS_MASK 0x0007f800L 815#define MC_ARB_MISC__HARSHNESS__SHIFT 0x0000000b 816#define MC_ARB_MISC__IDLE_RFSH_MASK 0x00000002L 817#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x00000001 818#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x00080000L 819#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x00000013 820#define MC_ARB_MISC__STICKY_RFSH_MASK 0x00000001L 821#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x00000000 822#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x00000004L 823#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x00000002 824#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x00000020L 825#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x00000005 826#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0x00f00000L 827#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x00000014 828#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x00000040L 829#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x00000006 830#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x00040000L 831#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x00000012 832#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x00080000L 833#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x00000013 834#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x00000003L 835#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x00000000 836#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x00000004L 837#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x00000002 838#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x00000008L 839#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x00000003 840#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x00000080L 841#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x00000007 842#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x00000300L 843#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x00000008 844#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x00000400L 845#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0x0000000a 846#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x00000800L 847#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0x0000000b 848#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x00004000L 849#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0x0000000e 850#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x00008000L 851#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0x0000000f 852#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x00001000L 853#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0x0000000c 854#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x00002000L 855#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0x0000000d 856#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x00000010L 857#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x00000004 858#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x00080000L 859#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x00000013 860#define MC_ARB_POP__ENABLE_ARB_MASK 0x00000001L 861#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x00000000 862#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x00040000L 863#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x00000012 864#define MC_ARB_POP__POP_DEPTH_MASK 0x0000003cL 865#define MC_ARB_POP__POP_DEPTH__SHIFT 0x00000002 866#define MC_ARB_POP__QUICK_STOP_MASK 0x00020000L 867#define MC_ARB_POP__QUICK_STOP__SHIFT 0x00000011 868#define MC_ARB_POP__SKID_DEPTH_MASK 0x00007000L 869#define MC_ARB_POP__SKID_DEPTH__SHIFT 0x0000000c 870#define MC_ARB_POP__SPEC_OPEN_MASK 0x00000002L 871#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x00000001 872#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x00018000L 873#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0x0000000f 874#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0x00000fc0L 875#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x00000006 876#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x00000100L 877#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x00000008 878#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x00000003L 879#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x00000000 880#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0x000000c0L 881#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x00000006 882#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x00001000L 883#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0x0000000c 884#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x00000004L 885#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x00000002 886#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x00000038L 887#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x00000003 888#define MC_ARB_REMREQ__RD_WATER_MASK 0x000000ffL 889#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x00000000 890#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0x00f00000L 891#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x00000014 892#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0x000f0000L 893#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x00000010 894#define MC_ARB_REMREQ__WR_WATER_MASK 0x0000ff00L 895#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x00000008 896#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x00000080L 897#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x00000007 898#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x00007f00L 899#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x00000008 900#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x00000040L 901#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x00000006 902#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x00000001L 903#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x00000000 904#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x00000002L 905#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x00000001 906#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x00000020L 907#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x00000005 908#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x00000010L 909#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x00000004 910#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x00000008L 911#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x00000003 912#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x00000004L 913#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x00000002 914#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0x00ff0000L 915#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x00000010 916#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0x0000ff00L 917#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x00000008 918#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0x000000ffL 919#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x00000000 920#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000L 921#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x00000018 922#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0x0000ff00L 923#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x00000008 924#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0x000000ffL 925#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x00000000 926#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0x00ff0000L 927#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x00000010 928#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0x0f000000L 929#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x00000018 930#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x00000800L 931#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0x0000000b 932#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x00000001L 933#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x00000000 934#define MC_ARB_RFSH_CNTL__URG0_MASK 0x0000003eL 935#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x00000001 936#define MC_ARB_RFSH_CNTL__URG1_MASK 0x000007c0L 937#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x00000006 938#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0x000000ffL 939#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x00000000 940#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x00000100L 941#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x00000008 942#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x00000200L 943#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x00000009 944#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x00000400L 945#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0x0000000a 946#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x01000000L 947#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x00000018 948#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x00008000L 949#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0x0000000f 950#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x00010000L 951#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x00000010 952#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x00020000L 953#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x00000011 954#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x00040000L 955#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x00000012 956#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x00080000L 957#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x00000013 958#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x00100000L 959#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x00000014 960#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x00200000L 961#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x00000015 962#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x00400000L 963#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x00000016 964#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x00800000L 965#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x00000017 966#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x00000001L 967#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x00000000 968#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x00000010L 969#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x00000004 970#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x00000020L 971#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x00000005 972#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x02000000L 973#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x00000019 974#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x00000002L 975#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x00000001 976#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0x0000000cL 977#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x00004000L 978#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0x0000000e 979#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x00000002 980#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x00000040L 981#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x00000006 982#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x00003800L 983#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0x0000000b 984#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x00000080L 985#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x00000007 986#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0x000fe000L 987#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0x0000000d 988#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x00001fc0L 989#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x00000006 990#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x0000001fL 991#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x01f00000L 992#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x00000014 993#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000L 994#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x00000019 995#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x00000000 996#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000L 997#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x0000001e 998#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x00000020L 999#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x00000005 1000#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x00002000L 1001#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0x0000000d 1002#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x00001000L 1003#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0x0000000c 1004#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0x00000fc0L 1005#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x00000006 1006#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x0000003fL 1007#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x00000000 1008#define MC_ARB_RTT_DATA__PATTERN_MASK 0x000000ffL 1009#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x00000000 1010#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x00000003L 1011#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x00000000 1012#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0x0000000cL 1013#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x00000002 1014#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0x00000ff0L 1015#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x00000004 1016#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x01fe0000L 1017#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x00000011 1018#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x0001f000L 1019#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0x0000000c 1020#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000L 1021#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x00000019 1022#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x00000100L 1023#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x00000008 1024#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0x000000ffL 1025#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x00000000 1026#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000L 1027#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x00000018 1028#define MC_ARB_SQM_CNTL__RATIO_MASK 0x00ff0000L 1029#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x00000010 1030#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0x0000fe00L 1031#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0x00000009 1032#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x00000006L 1033#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x00000001 1034#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x00000001L 1035#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x00000000 1036#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x00000010L 1037#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x00000004 1038#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x00000008L 1039#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x00000003 1040#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x00000006L 1041#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x00000001 1042#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x00000001L 1043#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x00000000 1044#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x00000010L 1045#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x00000004 1046#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x00000008L 1047#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x00000003 1048#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x00000200L 1049#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x00000009 1050#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x00000400L 1051#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0x0000000a 1052#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x00000800L 1053#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0x0000000b 1054#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x00001000L 1055#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0x0000000c 1056#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x00002000L 1057#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0x0000000d 1058#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x00004000L 1059#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0x0000000e 1060#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0x0000000fL 1061#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x00000000 1062#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x000001f0L 1063#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x00000004 1064#define MC_ARB_WCDR__IDLE_BURST_MASK 0x00001f80L 1065#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x00002000L 1066#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0x0000000d 1067#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x00000007 1068#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x00010000L 1069#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x00000010 1070#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x00000001L 1071#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x00000000 1072#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x0000007cL 1073#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x00000002 1074#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0x0000c000L 1075#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0x0000000e 1076#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x00000002L 1077#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x00000001 1078#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x00020000L 1079#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x00000011 1080#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x02000000L 1081#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x00000019 1082#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x08000000L 1083#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x0000001b 1084#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x04000000L 1085#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x0000001a 1086#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x01c00000L 1087#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x00000016 1088#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x003c0000L 1089#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x00000012 1090#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000L 1091#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x0000001c 1092#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x00000008L 1093#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x00000003 1094#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x00000010L 1095#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x00000004 1096#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x00000020L 1097#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x00000005 1098#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x00000040L 1099#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x00000006 1100#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x00000080L 1101#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x00000007 1102#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x00000100L 1103#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x00000008 1104#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x00000200L 1105#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x00000009 1106#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x00000400L 1107#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a 1108#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x00000004L 1109#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x00000002 1110#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x00000003L 1111#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x00000000 1112#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x00000008L 1113#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x00000003 1114#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x00000010L 1115#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x00000004 1116#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x00000020L 1117#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x00000005 1118#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x00000040L 1119#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x00000006 1120#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x00000080L 1121#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x00000007 1122#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x00000100L 1123#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x00000008 1124#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x00000200L 1125#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x00000009 1126#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x00000400L 1127#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a 1128#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x00000004L 1129#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x00000002 1130#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x00000003L 1131#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x00000000 1132#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x00000003L 1133#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x00000000 1134#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0x0000000cL 1135#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x00000002 1136#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x00000030L 1137#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x00000004 1138#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0x000000c0L 1139#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x00000006 1140#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x00000300L 1141#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x00000008 1142#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0x00000c00L 1143#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0x0000000a 1144#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x00003000L 1145#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0x0000000c 1146#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0x0000c000L 1147#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0x0000000e 1148#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0x00ff0000L 1149#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x00000010 1150#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x00000003L 1151#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x00000000 1152#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0x0000000cL 1153#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x00000002 1154#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x00000030L 1155#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x00000004 1156#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0x000000c0L 1157#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x00000006 1158#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x00000300L 1159#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x00000008 1160#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0x00000c00L 1161#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0x0000000a 1162#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x00003000L 1163#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0x0000000c 1164#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0x0000c000L 1165#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0x0000000e 1166#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0x00ff0000L 1167#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x00000010 1168#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0x000000f0L 1169#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x00000004 1170#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x02000000L 1171#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x00000019 1172#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0x00ffff00L 1173#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x00000008 1174#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x01000000L 1175#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x00000018 1176#define MC_BIST_AUTO_CNTL__MOP_MASK 0x00000003L 1177#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x00000000 1178#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x00000004L 1179#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x00000002 1180#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x00000002L 1181#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x00000001 1182#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x00010000L 1183#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x00000010 1184#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x00020000L 1185#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x00000011 1186#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000L 1187#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x0000001f 1188#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000L 1189#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x0000001c 1190#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000L 1191#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x0000001d 1192#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0x0000fff0L 1193#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x00000004 1194#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0x0ffc0000L 1195#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x00000012 1196#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x00000008L 1197#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x00000003 1198#define MC_BIST_CMD_CNTL__RESET_MASK 0x00000001L 1199#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x00000000 1200#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000L 1201#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x0000001e 1202#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x0000001fL 1203#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x00000100L 1204#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x00000008 1205#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x00000000 1206#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x0001f000L 1207#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x00100000L 1208#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x00000014 1209#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0x0000000c 1210#define MC_BIST_CMP_CNTL__CMP_MASK 0x00030000L 1211#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0x00000ff0L 1212#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x00000004 1213#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0x0000000fL 1214#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x00000000 1215#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x00000010 1216#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x00300000L 1217#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x00000014 1218#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x00002000L 1219#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0x0000000d 1220#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x00040000L 1221#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x00000012 1222#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x00080000L 1223#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x00000013 1224#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x00004000L 1225#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0x0000000e 1226#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x00008000L 1227#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0x0000000f 1228#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x00001000L 1229#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0x0000000c 1230#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000L 1231#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x00000016 1232#define MC_BIST_CNTL__ADR_MODE_MASK 0x00000020L 1233#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x00000005 1234#define MC_BIST_CNTL__DAT_MODE_MASK 0x00000040L 1235#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x00000006 1236#define MC_BIST_CNTL__DONE_MASK 0x40000000L 1237#define MC_BIST_CNTL__DONE__SHIFT 0x0000001e 1238#define MC_BIST_CNTL__ENABLE_D0_MASK 0x00001000L 1239#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0x0000000c 1240#define MC_BIST_CNTL__ENABLE_D1_MASK 0x00002000L 1241#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0x0000000d 1242#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x00004000L 1243#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0x0000000e 1244#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000L 1245#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x0000001f 1246#define MC_BIST_CNTL__LOOP_CNT_MASK 0x0fff0000L 1247#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x00000010 1248#define MC_BIST_CNTL__LOOP_MASK 0x00000c00L 1249#define MC_BIST_CNTL__LOOP__SHIFT 0x0000000a 1250#define MC_BIST_CNTL__MOP_MODE_MASK 0x00000010L 1251#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x00000004 1252#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x00000004L 1253#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x00000002 1254#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x00000008L 1255#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x00000003 1256#define MC_BIST_CNTL__RESET_MASK 0x00000001L 1257#define MC_BIST_CNTL__RESET__SHIFT 0x00000000 1258#define MC_BIST_CNTL__RUN_MASK 0x00000002L 1259#define MC_BIST_CNTL__RUN__SHIFT 0x00000001 1260#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffffL 1261#define MC_BIST_DATA_MASK__MASK__SHIFT 0x00000000 1262#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffffL 1263#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x00000000 1264#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffffL 1265#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x00000000 1266#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffffL 1267#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x00000000 1268#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffffL 1269#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x00000000 1270#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffffL 1271#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x00000000 1272#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffffL 1273#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x00000000 1274#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffffL 1275#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x00000000 1276#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffffL 1277#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x00000000 1278#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x00000040L 1279#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x00000006 1280#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x00000100L 1281#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x00000008 1282#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x00000020L 1283#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x00000005 1284#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x00000080L 1285#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x00000007 1286#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x00000200L 1287#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x00000009 1288#define MC_BIST_DIR_CNTL__EOB_MASK 0x00000008L 1289#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x00000003 1290#define MC_BIST_DIR_CNTL__MOP3_MASK 0x00000400L 1291#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0x0000000a 1292#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x00000010L 1293#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x00000004 1294#define MC_BIST_DIR_CNTL__MOP_MASK 0x00000007L 1295#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x00000000 1296#define MC_BIST_EADDR__BANK_MASK 0x0f000000L 1297#define MC_BIST_EADDR__BANK__SHIFT 0x00000018 1298#define MC_BIST_EADDR__COLH_MASK 0x20000000L 1299#define MC_BIST_EADDR__COLH__SHIFT 0x0000001d 1300#define MC_BIST_EADDR__COL_MASK 0x000003ffL 1301#define MC_BIST_EADDR__COL__SHIFT 0x00000000 1302#define MC_BIST_EADDR__RANK_MASK 0x10000000L 1303#define MC_BIST_EADDR__RANK__SHIFT 0x0000001c 1304#define MC_BIST_EADDR__ROWH_MASK 0xc0000000L 1305#define MC_BIST_EADDR__ROWH__SHIFT 0x0000001e 1306#define MC_BIST_EADDR__ROW_MASK 0x00fffc00L 1307#define MC_BIST_EADDR__ROW__SHIFT 0x0000000a 1308#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0x0f000000L 1309#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x00000018 1310#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000L 1311#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x0000001d 1312#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x000003ffL 1313#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x00000000 1314#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000L 1315#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x0000001c 1316#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000L 1317#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x0000001e 1318#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0x00fffc00L 1319#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0x0000000a 1320#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffffL 1321#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x00000000 1322#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffffL 1323#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x00000000 1324#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffffL 1325#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x00000000 1326#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffffL 1327#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x00000000 1328#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffffL 1329#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x00000000 1330#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffffL 1331#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x00000000 1332#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffffL 1333#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x00000000 1334#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffffL 1335#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x00000000 1336#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffffL 1337#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x00000000 1338#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffffL 1339#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x00000000 1340#define MC_BIST_SADDR__BANK_MASK 0x0f000000L 1341#define MC_BIST_SADDR__BANK__SHIFT 0x00000018 1342#define MC_BIST_SADDR__COLH_MASK 0x20000000L 1343#define MC_BIST_SADDR__COLH__SHIFT 0x0000001d 1344#define MC_BIST_SADDR__COL_MASK 0x000003ffL 1345#define MC_BIST_SADDR__COL__SHIFT 0x00000000 1346#define MC_BIST_SADDR__RANK_MASK 0x10000000L 1347#define MC_BIST_SADDR__RANK__SHIFT 0x0000001c 1348#define MC_BIST_SADDR__ROWH_MASK 0xc0000000L 1349#define MC_BIST_SADDR__ROWH__SHIFT 0x0000001e 1350#define MC_BIST_SADDR__ROW_MASK 0x00fffc00L 1351#define MC_BIST_SADDR__ROW__SHIFT 0x0000000a 1352#define MC_CG_CONFIG__INDEX_MASK 0x003fffc0L 1353#define MC_CG_CONFIG__INDEX__SHIFT 0x00000006 1354#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000L 1355#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0x0000000d 1356#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L 1357#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000 1358#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L 1359#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001 1360#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L 1361#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002 1362#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L 1363#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003 1364#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L 1365#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004 1366#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L 1367#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005 1368#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L 1369#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008 1370#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L 1371#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000 1372#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L 1373#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001 1374#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L 1375#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002 1376#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L 1377#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003 1378#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x00000030L 1379#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004 1380#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffffL 1381#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x00000000 1382#define MC_CITF_CNTL__EXEMPTPM_MASK 0x00000008L 1383#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x00000003 1384#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x00000030L 1385#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x00000004 1386#define MC_CITF_CNTL__IGNOREPM_MASK 0x00000004L 1387#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x00000002 1388#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x00000040L 1389#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x00000006 1390#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x02000000L 1391#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x00000019 1392#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x01000000L 1393#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x00000018 1394#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0x0000ff00L 1395#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x00000008 1396#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0x000000ffL 1397#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x00000000 1398#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0x00ff0000L 1399#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x00000010 1400#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x00010000L 1401#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x00000010 1402#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x00020000L 1403#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x00000011 1404#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0x0000ff00L 1405#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x00000008 1406#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0x000000ffL 1407#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x00000000 1408#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x0000003fL 1409#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x00000000 1410#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0x00000fc0L 1411#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x00000006 1412#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0x000000ffL 1413#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x00000000 1414#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0x0000ff00L 1415#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x00000008 1416#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x0000001eL 1417#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x00000001 1418#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x000003c0L 1419#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x00000006 1420#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x00000020L 1421#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x00000005 1422#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x00000001L 1423#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x00000000 1424#define MC_CITF_DAGB_DLY__CLI_MASK 0x001f0000L 1425#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x00000010 1426#define MC_CITF_DAGB_DLY__DLY_MASK 0x0000001fL 1427#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x00000000 1428#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000L 1429#define MC_CITF_DAGB_DLY__POS__SHIFT 0x00000018 1430#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0x00fc0000L 1431#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x00000012 1432#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x0003f000L 1433#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0x0000000c 1434#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000L 1435#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x00000018 1436#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x0000003fL 1437#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x00000000 1438#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x0000003fL 1439#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x00000000 1440#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0x00000fc0L 1441#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x00000006 1442#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x00040000L 1443#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x00000012 1444#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x00080000L 1445#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x00000013 1446#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0x00000fc0L 1447#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x00000006 1448#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x0000003fL 1449#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x00000000 1450#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x0003f000L 1451#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0x0000000c 1452#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x00040000L 1453#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x00000012 1454#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L 1455#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013 1456#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L 1457#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x00000006 1458#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x0000003fL 1459#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x00000000 1460#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x0003f000L 1461#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c 1462#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x00040000L 1463#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x00000012 1464#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x00080000L 1465#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x00000013 1466#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0x00000fc0L 1467#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x00000006 1468#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x0000003fL 1469#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x00000000 1470#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x0003f000L 1471#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0x0000000c 1472#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0x000001ffL 1473#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x00000000 1474#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x00000040L 1475#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x00000006 1476#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x00001000L 1477#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x0000000c 1478#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x00000080L 1479#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x00000007 1480#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x00002000L 1481#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x0000000d 1482#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x00004000L 1483#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x0000000e 1484#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x00000100L 1485#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x00000008 1486#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x00010000L 1487#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x00000010 1488#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x00000400L 1489#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x0000000a 1490#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x00020000L 1491#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x00000011 1492#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x00008000L 1493#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0x0000000f 1494#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x00040000L 1495#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x00000012 1496#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x00000200L 1497#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x00000009 1498#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x00000800L 1499#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x0000000b 1500#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x00004000L 1501#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0x0000000e 1502#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x0000007fL 1503#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x00000000 1504#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x00003f80L 1505#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x00000007 1506#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x00000001L 1507#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x00000000 1508#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x00000002L 1509#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x00000001 1510#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x00000010L 1511#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x00000004 1512#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x00000020L 1513#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x00000005 1514#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x00000004L 1515#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x00000002 1516#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x00000008L 1517#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x00000003 1518#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x01000000L 1519#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x00000018 1520#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x00000007L 1521#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 1522#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x00000038L 1523#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 1524#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L 1525#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 1526#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L 1527#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 1528#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x00007000L 1529#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c 1530#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x00038000L 1531#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f 1532#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L 1533#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 1534#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L 1535#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 1536#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x01000000L 1537#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x00000018 1538#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x00000007L 1539#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 1540#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x00000038L 1541#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 1542#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L 1543#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 1544#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L 1545#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 1546#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x00007000L 1547#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c 1548#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x00038000L 1549#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f 1550#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L 1551#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 1552#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L 1553#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 1554#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0x00000f00L 1555#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x00000008 1556#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x00000001L 1557#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x00000000 1558#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x00000002L 1559#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x00000001 1560#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x00000004L 1561#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x00000002 1562#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x00000008L 1563#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x00000003 1564#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x00000010L 1565#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x00000004 1566#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x00001000L 1567#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0x0000000c 1568#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000L 1569#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x0000001f 1570#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L 1571#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000 1572#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L 1573#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001 1574#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L 1575#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002 1576#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L 1577#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003 1578#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L 1579#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004 1580#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L 1581#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005 1582#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000L 1583#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x0000001f 1584#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L 1585#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008 1586#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L 1587#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000 1588#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L 1589#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001 1590#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L 1591#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002 1592#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L 1593#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003 1594#define MC_CONFIG__MC_RD_ENABLE_MASK 0x00000030L 1595#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004 1596#define MC_HUB_MISC_DBG__SELECT0_MASK 0x0000000fL 1597#define MC_HUB_MISC_DBG__SELECT0__SHIFT 0x00000000 1598#define MC_HUB_MISC_DBG__SELECT1_MASK 0x000000f0L 1599#define MC_HUB_MISC_DBG__SELECT1__SHIFT 0x00000004 1600#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffffL 1601#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x00000000 1602#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x00040000L 1603#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x00000012 1604#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x00080000L 1605#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x00000013 1606#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0x00000fc0L 1607#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x00000006 1608#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x0000003fL 1609#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x00000000 1610#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x0003f000L 1611#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0x0000000c 1612#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x00000001L 1613#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x00000000 1614#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x00000002L 1615#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x00000001 1616#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x00000400L 1617#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x0000000a 1618#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x00000800L 1619#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x0000000b 1620#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x00000004L 1621#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x00000002 1622#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x00000008L 1623#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x00000003 1624#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x00010000L 1625#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0x00000010 1626#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x00020000L 1627#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0x00000011 1628#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x00040000L 1629#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x00000012 1630#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x00080000L 1631#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x00000013 1632#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x00000040L 1633#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x00000006 1634#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x00000080L 1635#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x00000007 1636#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x00004000L 1637#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0x0000000e 1638#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x00008000L 1639#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0x0000000f 1640#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x00001000L 1641#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0x0000000c 1642#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x00002000L 1643#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0x0000000d 1644#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x01000000L 1645#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x00000018 1646#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x02000000L 1647#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x00000019 1648#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x00100000L 1649#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x00000014 1650#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x00200000L 1651#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x00000015 1652#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x00000003L 1653#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x00000000 1654#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x00000018L 1655#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x00000003 1656#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x00000004L 1657#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x00000002 1658#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x00040000L 1659#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x00000012 1660#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x00080000L 1661#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x00000013 1662#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0x00000fc0L 1663#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x00000006 1664#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x0000003fL 1665#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x00000000 1666#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x0003f000L 1667#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0x0000000c 1668#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x00002000L 1669#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x0000000d 1670#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x00000004L 1671#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x00000002 1672#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x00000008L 1673#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x00000003 1674#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x00000010L 1675#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x00000004 1676#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x00000020L 1677#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x00000005 1678#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x00000100L 1679#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x00000008 1680#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x00000200L 1681#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x00000009 1682#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x00000001L 1683#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x00000000 1684#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x00000040L 1685#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x00000006 1686#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x00000080L 1687#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x00000007 1688#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x00000002L 1689#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x00000001 1690#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x00001000L 1691#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x0000000c 1692#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x00000400L 1693#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0x0000000a 1694#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x00000800L 1695#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x0000000b 1696#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x00040000L 1697#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x00000012 1698#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L 1699#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013 1700#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L 1701#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x00000006 1702#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x0000003fL 1703#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x00000000 1704#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x0003f000L 1705#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c 1706#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x00000200L 1707#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0x00000009 1708#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x0001fc00L 1709#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0x0000000a 1710#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00020000L 1711#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x00000011 1712#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00040000L 1713#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x00000012 1714#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x00000004L 1715#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000002 1716#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x00000008L 1717#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000003 1718#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x00000020L 1719#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x00000005 1720#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x00000040L 1721#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x00000006 1722#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x00000080L 1723#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x00000007 1724#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x00000100L 1725#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x00000008 1726#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L 1727#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004 1728#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x00080000L 1729#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x00000013 1730#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x00000001L 1731#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x00000000 1732#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0x000000ffL 1733#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x00000000 1734#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0x00ff0000L 1735#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x00000010 1736#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000L 1737#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x00000018 1738#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0x000000ffL 1739#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x00000000 1740#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0x0000ff00L 1741#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x00000008 1742#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x00000008L 1743#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 1744#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x00000001L 1745#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x00000000 1746#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x00007800L 1747#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0x0000000b 1748#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x00000003L 1749#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x00000000 1750#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x0000007cL 1751#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x00000002 1752#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x00000780L 1753#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x00000007 1754#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x00000006L 1755#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x00000001 1756#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x00000030L 1757#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x00000004 1758#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x00000040L 1759#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x00000006 1760#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x00008000L 1761#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 1762#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0x000000ffL 1763#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x00000000 1764#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0x000000ffL 1765#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x00000000 1766#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L 1767#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 1768#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x00000001L 1769#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x00000000 1770#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x00007800L 1771#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0x0000000b 1772#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x00000780L 1773#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x00000007 1774#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x00000006L 1775#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x00000001 1776#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x00000030L 1777#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x00000004 1778#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x00000040L 1779#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x00000006 1780#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L 1781#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 1782#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x0003f800L 1783#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0x0000000b 1784#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L 1785#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001 1786#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x00000004L 1787#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x00000002 1788#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x01fc0000L 1789#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x00000012 1790#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x00000001L 1791#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x00000000 1792#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x00000780L 1793#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x00000007 1794#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x00000078L 1795#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x00000003 1796#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000L 1797#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x00000019 1798#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x0003f800L 1799#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0x0000000b 1800#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L 1801#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001 1802#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x00000004L 1803#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x00000002 1804#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x01fc0000L 1805#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x00000012 1806#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x00000001L 1807#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x00000000 1808#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x00000780L 1809#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x00000007 1810#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x00000078L 1811#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x00000003 1812#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000L 1813#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x00000019 1814#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x0003f800L 1815#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0x0000000b 1816#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L 1817#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001 1818#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x00000004L 1819#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x00000002 1820#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x01fc0000L 1821#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x00000012 1822#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x00000001L 1823#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x00000000 1824#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x00000780L 1825#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x00000007 1826#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x00000078L 1827#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x00000003 1828#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000L 1829#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x00000019 1830#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x0003f800L 1831#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0x0000000b 1832#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L 1833#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001 1834#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x00000004L 1835#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x00000002 1836#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x01fc0000L 1837#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x00000012 1838#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x00000001L 1839#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x00000000 1840#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x00000780L 1841#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x00000007 1842#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x00000078L 1843#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x00000003 1844#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000L 1845#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x00000019 1846#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L 1847#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 1848#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x00000001L 1849#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x00000000 1850#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x00007800L 1851#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0x0000000b 1852#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x00000780L 1853#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x00000007 1854#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x00000006L 1855#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x00000001 1856#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x00000030L 1857#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x00000004 1858#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x00000040L 1859#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x00000006 1860#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L 1861#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 1862#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L 1863#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003 1864#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x00000001L 1865#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x00000000 1866#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x00007800L 1867#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0x0000000b 1868#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x00000780L 1869#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x00000007 1870#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x00000006L 1871#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x00000001 1872#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x00000030L 1873#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x00000004 1874#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x00000040L 1875#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x00000006 1876#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L 1877#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 1878#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L 1879#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003 1880#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x00000001L 1881#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x00000000 1882#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x00007800L 1883#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0x0000000b 1884#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x00000780L 1885#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x00000007 1886#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x00000006L 1887#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x00000001 1888#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x00000030L 1889#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x00000004 1890#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x00000040L 1891#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x00000006 1892#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L 1893#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 1894#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x0000007fL 1895#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x00000000 1896#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x00007f00L 1897#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x00000008 1898#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x00000080L 1899#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x00000007 1900#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L 1901#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003 1902#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x00000001L 1903#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x00000000 1904#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x00007800L 1905#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0x0000000b 1906#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x00000780L 1907#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x00000007 1908#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x00000006L 1909#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x00000001 1910#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x00000030L 1911#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x00000004 1912#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x00000040L 1913#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x00000006 1914#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L 1915#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 1916#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L 1917#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007 1918#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x00000040L 1919#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006 1920#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x00000020L 1921#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x00000005 1922#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L 1923#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a 1924#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x00000200L 1925#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009 1926#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x00000100L 1927#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0x00000008 1928#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L 1929#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001 1930#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L 1931#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002 1932#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L 1933#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003 1934#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L 1935#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004 1936#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x00000800L 1937#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0x0000000b 1938#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x00000001L 1939#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x00000000 1940#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L 1941#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 1942#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x00000001L 1943#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x00000000 1944#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x00007800L 1945#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0x0000000b 1946#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x00000780L 1947#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x00000007 1948#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x00000006L 1949#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x00000001 1950#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x00000030L 1951#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x00000004 1952#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x00000040L 1953#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x00000006 1954#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L 1955#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 1956#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L 1957#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003 1958#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x00000001L 1959#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x00000000 1960#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x00007800L 1961#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0x0000000b 1962#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x00000780L 1963#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x00000007 1964#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x00000006L 1965#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x00000001 1966#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x00000030L 1967#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x00000004 1968#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x00000040L 1969#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x00000006 1970#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L 1971#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 1972#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x00010000L 1973#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x00000010 1974#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L 1975#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003 1976#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x00000001L 1977#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x00000000 1978#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x00007800L 1979#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0x0000000b 1980#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x00000780L 1981#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x00000007 1982#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x00000006L 1983#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x00000001 1984#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x00000030L 1985#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x00000004 1986#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x00000040L 1987#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x00000006 1988#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L 1989#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 1990#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L 1991#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003 1992#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x00000001L 1993#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x00000000 1994#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x00007800L 1995#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0x0000000b 1996#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x00000780L 1997#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x00000007 1998#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x00000006L 1999#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x00000001 2000#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x00000030L 2001#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x00000004 2002#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x00000040L 2003#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x00000006 2004#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L 2005#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2006#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x00000008L 2007#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 2008#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x00000001L 2009#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x00000000 2010#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x00007800L 2011#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0x0000000b 2012#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x00000780L 2013#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x00000007 2014#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x00000006L 2015#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x00000001 2016#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x00000030L 2017#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x00000004 2018#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x00000040L 2019#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x00000006 2020#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x00008000L 2021#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2022#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L 2023#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 2024#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L 2025#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 2026#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L 2027#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 2028#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L 2029#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 2030#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L 2031#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c 2032#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L 2033#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f 2034#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L 2035#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 2036#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L 2037#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 2038#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L 2039#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003 2040#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x00000001L 2041#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x00000000 2042#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x00007800L 2043#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0x0000000b 2044#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x00000780L 2045#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x00000007 2046#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x00000006L 2047#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x00000001 2048#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x00000030L 2049#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x00000004 2050#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x00000040L 2051#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006 2052#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L 2053#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2054#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x001f0000L 2055#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x00000010 2056#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x0000003fL 2057#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x00000000 2058#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000L 2059#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x00000018 2060#define MC_HUB_WDP_BP__ENABLE_MASK 0x00000001L 2061#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x00000000 2062#define MC_HUB_WDP_BP__RDRET_MASK 0x0003fffeL 2063#define MC_HUB_WDP_BP__RDRET__SHIFT 0x00000001 2064#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000L 2065#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x00000012 2066#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x00001fe0L 2067#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x00000005 2068#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00002000L 2069#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x0000000d 2070#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00004000L 2071#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x0000000e 2072#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x00008000L 2073#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0x0000000f 2074#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x00040000L 2075#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x00000012 2076#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x00010000L 2077#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x00000010 2078#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x00000002L 2079#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000001 2080#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x00000004L 2081#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000002 2082#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x00000008L 2083#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x00000003 2084#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x00020000L 2085#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x00000011 2086#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x00080000L 2087#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x00000013 2088#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L 2089#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004 2090#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x00100000L 2091#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x00000014 2092#define MC_HUB_WDP_CREDITS__STOR0_MASK 0x00ff0000L 2093#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x00000010 2094#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000L 2095#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x00000018 2096#define MC_HUB_WDP_CREDITS__VM0_MASK 0x000000ffL 2097#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x00000000 2098#define MC_HUB_WDP_CREDITS__VM1_MASK 0x0000ff00L 2099#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x00000008 2100#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x00000001L 2101#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x00000000 2102#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x00000002L 2103#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x00000001 2104#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0x000000f0L 2105#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x00000004 2106#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0x0000000fL 2107#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x00000000 2108#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x00010000L 2109#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x00000010 2110#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0x0000ff00L 2111#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x00000008 2112#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0x000000f0L 2113#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x00000004 2114#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0x0000000fL 2115#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x00000000 2116#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x00010000L 2117#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x00000010 2118#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0x0000ff00L 2119#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x00000008 2120#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L 2121#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 2122#define MC_HUB_WDP_HDP__ENABLE_MASK 0x00000001L 2123#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x00000000 2124#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x00007800L 2125#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0x0000000b 2126#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x00000780L 2127#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x00000007 2128#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x00000006L 2129#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x00000001 2130#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x00000030L 2131#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x00000004 2132#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x00000040L 2133#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x00000006 2134#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L 2135#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2136#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x00000008L 2137#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x00000003 2138#define MC_HUB_WDP_IH__ENABLE_MASK 0x00000001L 2139#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x00000000 2140#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x00007800L 2141#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0x0000000b 2142#define MC_HUB_WDP_IH__MAXBURST_MASK 0x00000780L 2143#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x00000007 2144#define MC_HUB_WDP_IH__PRESCALE_MASK 0x00000006L 2145#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x00000001 2146#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x00000030L 2147#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x00000004 2148#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x00000040L 2149#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x00000006 2150#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x00008000L 2151#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2152#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x00001f80L 2153#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x00000007 2154#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000L 2155#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x00000018 2156#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L 2157#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001 2158#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x00000001L 2159#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x00000000 2160#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x0001e000L 2161#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0x0000000d 2162#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x00000078L 2163#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x00000003 2164#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x00000004L 2165#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x00000002 2166#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0x00fe0000L 2167#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x00000011 2168#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x00001f80L 2169#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x00000007 2170#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000L 2171#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x00000018 2172#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L 2173#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001 2174#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x00000001L 2175#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x00000000 2176#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x0001e000L 2177#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0x0000000d 2178#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x00000078L 2179#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x00000003 2180#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x00000004L 2181#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x00000002 2182#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0x00fe0000L 2183#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x00000011 2184#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x00001f80L 2185#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x00000007 2186#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000L 2187#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x00000018 2188#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L 2189#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001 2190#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x00000001L 2191#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x00000000 2192#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x0001e000L 2193#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0x0000000d 2194#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x00000078L 2195#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x00000003 2196#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x00000004L 2197#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x00000002 2198#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0x00fe0000L 2199#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x00000011 2200#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x00001f80L 2201#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x00000007 2202#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000L 2203#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x00000018 2204#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L 2205#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001 2206#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x00000001L 2207#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x00000000 2208#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x0001e000L 2209#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0x0000000d 2210#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x00000078L 2211#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x00000003 2212#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x00000004L 2213#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x00000002 2214#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0x00fe0000L 2215#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x00000011 2216#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L 2217#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 2218#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x00000001L 2219#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x00000000 2220#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x00007800L 2221#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0x0000000b 2222#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x00000780L 2223#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x00000007 2224#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x00000006L 2225#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x00000001 2226#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x00000030L 2227#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x00000004 2228#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x00000040L 2229#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x00000006 2230#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L 2231#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2232#define MC_HUB_WDP_MGPU2__CID2_MASK 0x000000ffL 2233#define MC_HUB_WDP_MGPU2__CID2__SHIFT 0x00000000 2234#define MC_HUB_WDP_MGPU__CID_MASK 0x0000ff00L 2235#define MC_HUB_WDP_MGPU__CID__SHIFT 0x00000008 2236#define MC_HUB_WDP_MGPU__ENABLE_MASK 0x00800000L 2237#define MC_HUB_WDP_MGPU__ENABLE__SHIFT 0x00000017 2238#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME_MASK 0x007f0000L 2239#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME__SHIFT 0x00000010 2240#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME_MASK 0x7f000000L 2241#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME__SHIFT 0x00000018 2242#define MC_HUB_WDP_MGPU__STOR_MASK 0x000000ffL 2243#define MC_HUB_WDP_MGPU__STOR__SHIFT 0x00000000 2244#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L 2245#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003 2246#define MC_HUB_WDP_RLC__ENABLE_MASK 0x00000001L 2247#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x00000000 2248#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x00007800L 2249#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0x0000000b 2250#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x00000780L 2251#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x00000007 2252#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x00000006L 2253#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x00000001 2254#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x00000030L 2255#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x00000004 2256#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x00000040L 2257#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x00000006 2258#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L 2259#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2260#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L 2261#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003 2262#define MC_HUB_WDP_SEM__ENABLE_MASK 0x00000001L 2263#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x00000000 2264#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x00007800L 2265#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0x0000000b 2266#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x00000780L 2267#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x00000007 2268#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x00000006L 2269#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x00000001 2270#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x00000030L 2271#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x00000004 2272#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x00000040L 2273#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x00000006 2274#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L 2275#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2276#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x00000008L 2277#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x00000003 2278#define MC_HUB_WDP_SH0__ENABLE_MASK 0x00000001L 2279#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x00000000 2280#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x00007800L 2281#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0x0000000b 2282#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x00000780L 2283#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x00000007 2284#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x00000006L 2285#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x00000001 2286#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x00000030L 2287#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x00000004 2288#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x00000040L 2289#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x00000006 2290#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x00008000L 2291#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2292#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x00000008L 2293#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x00000003 2294#define MC_HUB_WDP_SH1__ENABLE_MASK 0x00000001L 2295#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x00000000 2296#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x00007800L 2297#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0x0000000b 2298#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x00000780L 2299#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x00000007 2300#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x00000006L 2301#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x00000001 2302#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x00000030L 2303#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x00000004 2304#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x00000040L 2305#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x00000006 2306#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x00008000L 2307#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2308#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x000001fcL 2309#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x00000002 2310#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x00000003L 2311#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x00000000 2312#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L 2313#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003 2314#define MC_HUB_WDP_SMU__ENABLE_MASK 0x00000001L 2315#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x00000000 2316#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x00007800L 2317#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0x0000000b 2318#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x00000780L 2319#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x00000007 2320#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x00000006L 2321#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x00000001 2322#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x00000030L 2323#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x00000004 2324#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x00000040L 2325#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x00000006 2326#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L 2327#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2328#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L 2329#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007 2330#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x00000040L 2331#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006 2332#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x00000020L 2333#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x00000005 2334#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L 2335#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a 2336#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x00000200L 2337#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009 2338#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x00000100L 2339#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x00000008 2340#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L 2341#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001 2342#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x00000800L 2343#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x0000000b 2344#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L 2345#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002 2346#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x00001000L 2347#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0x0000000c 2348#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L 2349#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003 2350#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x00002000L 2351#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0x0000000d 2352#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L 2353#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004 2354#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x00004000L 2355#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0x0000000e 2356#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x00000001L 2357#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x00000000 2358#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L 2359#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 2360#define MC_HUB_WDP_UMC__ENABLE_MASK 0x00000001L 2361#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x00000000 2362#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x00007800L 2363#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0x0000000b 2364#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x00000780L 2365#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x00000007 2366#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x00000006L 2367#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x00000001 2368#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x00000030L 2369#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x00000004 2370#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x00000040L 2371#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x00000006 2372#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L 2373#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2374#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L 2375#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003 2376#define MC_HUB_WDP_UVD__ENABLE_MASK 0x00000001L 2377#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x00000000 2378#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x00007800L 2379#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0x0000000b 2380#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x00000780L 2381#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x00000007 2382#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x00000006L 2383#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x00000001 2384#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x00000030L 2385#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x00000004 2386#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x00000040L 2387#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x00000006 2388#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L 2389#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2390#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x00010000L 2391#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x00000010 2392#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L 2393#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003 2394#define MC_HUB_WDP_VCE__ENABLE_MASK 0x00000001L 2395#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x00000000 2396#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x00007800L 2397#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0x0000000b 2398#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x00000780L 2399#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x00000007 2400#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x00000006L 2401#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x00000001 2402#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x00000030L 2403#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x00000004 2404#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x00000040L 2405#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x00000006 2406#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L 2407#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2408#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L 2409#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003 2410#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x00000001L 2411#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x00000000 2412#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x00007800L 2413#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0x0000000b 2414#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x00000780L 2415#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x00000007 2416#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x00000006L 2417#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x00000001 2418#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x00000030L 2419#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x00000004 2420#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x00000040L 2421#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x00000006 2422#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L 2423#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2424#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L 2425#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 2426#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L 2427#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 2428#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L 2429#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 2430#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L 2431#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 2432#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L 2433#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c 2434#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L 2435#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f 2436#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L 2437#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 2438#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L 2439#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 2440#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x00000008L 2441#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x00000003 2442#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L 2443#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010 2444#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x00000001L 2445#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x00000000 2446#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x00007800L 2447#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0x0000000b 2448#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x00000780L 2449#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x00000007 2450#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L 2451#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003 2452#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L 2453#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010 2454#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x00000001L 2455#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x00000000 2456#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x00007800L 2457#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0x0000000b 2458#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x00000780L 2459#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x00000007 2460#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x00000006L 2461#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x00000001 2462#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x00000030L 2463#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x00000004 2464#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x00000040L 2465#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006 2466#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L 2467#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2468#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x00000006L 2469#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x00000001 2470#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x00000030L 2471#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x00000004 2472#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x00000040L 2473#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x00000006 2474#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x00008000L 2475#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2476#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x00000008L 2477#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 2478#define MC_HUB_WDP_XDP__ENABLE_MASK 0x00000001L 2479#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x00000000 2480#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x00007800L 2481#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0x0000000b 2482#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x00000780L 2483#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x00000007 2484#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x00000006L 2485#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x00000001 2486#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x00000030L 2487#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x00000004 2488#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x00000040L 2489#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x00000006 2490#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x00008000L 2491#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 2492#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x00200000L 2493#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x00000015 2494#define MC_HUB_WRRET_CNTL__BP_MASK 0x001ffffeL 2495#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x00000001 2496#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000L 2497#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x00000016 2498#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000L 2499#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x0000001e 2500#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000L 2501#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x0000001f 2502#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x00000001L 2503#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x00000000 2504#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0x000000feL 2505#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x00000001 2506#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x00000001L 2507#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x00000000 2508#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0x000000feL 2509#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x00000001 2510#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x00000001L 2511#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x00000000 2512#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0x000000feL 2513#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x00000001 2514#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x00000001L 2515#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x00000000 2516#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0x000000feL 2517#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x00000001 2518#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x00000001L 2519#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x00000000 2520#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x00000001L 2521#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x00000000 2522#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x00000002L 2523#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x00000001 2524#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x00000004L 2525#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x00000002 2526#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x00000008L 2527#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x00000003 2528#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000L 2529#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x0000001f 2530#define MC_IMP_CNTL__CAL_VREF_MASK 0x007f0000L 2531#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x00000040L 2532#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x00000006 2533#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x00000020L 2534#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x00000005 2535#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x00000010 2536#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000L 2537#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x0000001d 2538#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000L 2539#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x0000001e 2540#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x00000200L 2541#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x00000009 2542#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0x0000e000L 2543#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0x0000000d 2544#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x0000001fL 2545#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x00000000 2546#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x00000100L 2547#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x00000008 2548#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000L 2549#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x0000001f 2550#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000L 2551#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x0000001c 2552#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000L 2553#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x0000001e 2554#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000L 2555#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x0000001d 2556#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0x0fff0000L 2557#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x00000010 2558#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0x0000ff00L 2559#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x00000008 2560#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0x000000ffL 2561#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x00000000 2562#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0x0000ff00L 2563#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x00000008 2564#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0x000000ffL 2565#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x00000000 2566#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000L 2567#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x00000018 2568#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0x00ff0000L 2569#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x00000010 2570#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000L 2571#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x00000018 2572#define MC_IMP_STATUS__NSTR_CAL_MASK 0x00ff0000L 2573#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x00000010 2574#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0x0000ff00L 2575#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x00000008 2576#define MC_IMP_STATUS__PSTR_CAL_MASK 0x000000ffL 2577#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x00000000 2578#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0x0c000000L 2579#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x0000001a 2580#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000L 2581#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x0000001c 2582#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000L 2583#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x0000001d 2584#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0x00000fc0L 2585#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x00000006 2586#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x0000003fL 2587#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x00000000 2588#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x0003f000L 2589#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0x0000000c 2590#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x01000000L 2591#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x00000018 2592#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x02000000L 2593#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x00000019 2594#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0x0c000000L 2595#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x0000001a 2596#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000L 2597#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x0000001c 2598#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000L 2599#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x0000001d 2600#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0x00000fc0L 2601#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x00000006 2602#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x0000003fL 2603#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x00000000 2604#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x0003f000L 2605#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0x0000000c 2606#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x01000000L 2607#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x00000018 2608#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x02000000L 2609#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x00000019 2610#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0x000000ffL 2611#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x00000000 2612#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0x0000ff00L 2613#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x00000008 2614#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0x00ff0000L 2615#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x00000010 2616#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000L 2617#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x00000018 2618#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0x000000ffL 2619#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x00000000 2620#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0x0000ff00L 2621#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x00000008 2622#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0x00ff0000L 2623#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x00000010 2624#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000L 2625#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x00000018 2626#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x00000001L 2627#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x00000000 2628#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x00000002L 2629#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x00000001 2630#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x00000004L 2631#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x00000002 2632#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x00000008L 2633#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x00000003 2634#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x00000010L 2635#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x00000004 2636#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x00000020L 2637#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x00000005 2638#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x00000040L 2639#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x00000006 2640#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x00000080L 2641#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x00000007 2642#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x00000001L 2643#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x00000000 2644#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x00000002L 2645#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x00000001 2646#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x00000004L 2647#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x00000002 2648#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x00000008L 2649#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x00000003 2650#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x00000010L 2651#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x00000004 2652#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x00000020L 2653#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x00000005 2654#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x00000040L 2655#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x00000006 2656#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x00000080L 2657#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x00000007 2658#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x00400000L 2659#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x00000016 2660#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x00800000L 2661#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x00000017 2662#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000L 2663#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x0000001c 2664#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000L 2665#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x0000001d 2666#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x00100000L 2667#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x00000014 2668#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x00200000L 2669#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x00000015 2670#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000L 2671#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x0000001e 2672#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000L 2673#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x0000001f 2674#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x00000400L 2675#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0x0000000a 2676#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x00000800L 2677#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0x0000000b 2678#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x00000100L 2679#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x00000008 2680#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x00000200L 2681#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x00000009 2682#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0x0000f000L 2683#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0x0000000c 2684#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0x000f0000L 2685#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x00000010 2686#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0x0000000fL 2687#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x00000000 2688#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0x000000f0L 2689#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x00000004 2690#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x04000000L 2691#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x0000001a 2692#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x08000000L 2693#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x0000001b 2694#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x01000000L 2695#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x00000018 2696#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x02000000L 2697#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x00000019 2698#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x00400000L 2699#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x00000016 2700#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x00800000L 2701#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x00000017 2702#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000L 2703#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x0000001c 2704#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000L 2705#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x0000001d 2706#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x00100000L 2707#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x00000014 2708#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x00200000L 2709#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x00000015 2710#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000L 2711#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x0000001e 2712#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000L 2713#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x0000001f 2714#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x00000400L 2715#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0x0000000a 2716#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x00000800L 2717#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0x0000000b 2718#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x00000100L 2719#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x00000008 2720#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x00000200L 2721#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x00000009 2722#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0x0000f000L 2723#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0x0000000c 2724#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0x000f0000L 2725#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x00000010 2726#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0x0000000fL 2727#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x00000000 2728#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0x000000f0L 2729#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x00000004 2730#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x04000000L 2731#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x0000001a 2732#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x08000000L 2733#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x0000001b 2734#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x01000000L 2735#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x00000018 2736#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x02000000L 2737#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x00000019 2738#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0x000000ffL 2739#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x00000000 2740#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 2741#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x00000008 2742#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 2743#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x00000010 2744#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000L 2745#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x00000018 2746#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0x000000ffL 2747#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x00000000 2748#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 2749#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x00000008 2750#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 2751#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x00000010 2752#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000L 2753#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x00000018 2754#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0x000000ffL 2755#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x00000000 2756#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0x0000ff00L 2757#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x00000008 2758#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0x00ff0000L 2759#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x00000010 2760#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000L 2761#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x00000018 2762#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0x000000ffL 2763#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x00000000 2764#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0x0000ff00L 2765#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x00000008 2766#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0x00ff0000L 2767#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x00000010 2768#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000L 2769#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x00000018 2770#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0x000000ffL 2771#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x00000000 2772#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 2773#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x00000008 2774#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 2775#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x00000010 2776#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000L 2777#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x00000018 2778#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0x000000ffL 2779#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x00000000 2780#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 2781#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x00000008 2782#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 2783#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x00000010 2784#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000L 2785#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x00000018 2786#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0x000000ffL 2787#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x00000000 2788#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 2789#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x00000008 2790#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 2791#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x00000010 2792#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000L 2793#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x00000018 2794#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0x000000ffL 2795#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x00000000 2796#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 2797#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x00000008 2798#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 2799#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x00000010 2800#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000L 2801#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x00000018 2802#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 2803#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 2804#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 2805#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 2806#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 2807#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 2808#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000L 2809#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 2810#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 2811#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 2812#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 2813#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 2814#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 2815#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 2816#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000L 2817#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 2818#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 2819#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 2820#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 2821#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 2822#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 2823#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 2824#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000L 2825#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 2826#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 2827#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 2828#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 2829#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 2830#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 2831#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 2832#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000L 2833#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 2834#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0x000000ffL 2835#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x00000000 2836#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 2837#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x00000008 2838#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 2839#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x00000010 2840#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000L 2841#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x00000018 2842#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0x000000ffL 2843#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x00000000 2844#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 2845#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x00000008 2846#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 2847#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x00000010 2848#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000L 2849#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x00000018 2850#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0x000000ffL 2851#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x00000000 2852#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0x0000ff00L 2853#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x00000008 2854#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0x00ff0000L 2855#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x00000010 2856#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000L 2857#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x00000018 2858#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0x000000ffL 2859#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x00000000 2860#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0x0000ff00L 2861#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x00000008 2862#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0x00ff0000L 2863#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x00000010 2864#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000L 2865#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x00000018 2866#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0x000000ffL 2867#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x00000000 2868#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 2869#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x00000008 2870#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 2871#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x00000010 2872#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000L 2873#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x00000018 2874#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0x000000ffL 2875#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x00000000 2876#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 2877#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x00000008 2878#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 2879#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x00000010 2880#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000L 2881#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x00000018 2882#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0x000000ffL 2883#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x00000000 2884#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0x0000ff00L 2885#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x00000008 2886#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0x00ff0000L 2887#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x00000010 2888#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000L 2889#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x00000018 2890#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0x000000ffL 2891#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x00000000 2892#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0x0000ff00L 2893#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x00000008 2894#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0x00ff0000L 2895#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x00000010 2896#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000L 2897#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x00000018 2898#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0x000000ffL 2899#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x00000000 2900#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 2901#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x00000008 2902#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 2903#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x00000010 2904#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000L 2905#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x00000018 2906#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0x000000ffL 2907#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x00000000 2908#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 2909#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x00000008 2910#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 2911#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x00000010 2912#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000L 2913#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x00000018 2914#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 2915#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 2916#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 2917#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 2918#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 2919#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 2920#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000L 2921#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 2922#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 2923#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 2924#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 2925#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 2926#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 2927#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 2928#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000L 2929#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 2930#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 2931#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 2932#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 2933#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 2934#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 2935#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 2936#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000L 2937#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 2938#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 2939#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 2940#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 2941#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 2942#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 2943#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 2944#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000L 2945#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 2946#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0x000000ffL 2947#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x00000000 2948#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 2949#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x00000008 2950#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 2951#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x00000010 2952#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000L 2953#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x00000018 2954#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0x000000ffL 2955#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x00000000 2956#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 2957#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x00000008 2958#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 2959#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x00000010 2960#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000L 2961#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x00000018 2962#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0x000000ffL 2963#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x00000000 2964#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0x0000ff00L 2965#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x00000008 2966#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0x00ff0000L 2967#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x00000010 2968#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000L 2969#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x00000018 2970#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0x000000ffL 2971#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x00000000 2972#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0x0000ff00L 2973#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x00000008 2974#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0x00ff0000L 2975#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x00000010 2976#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000L 2977#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x00000018 2978#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0x000000ffL 2979#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x00000000 2980#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 2981#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x00000008 2982#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 2983#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x00000010 2984#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000L 2985#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x00000018 2986#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0x000000ffL 2987#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x00000000 2988#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 2989#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x00000008 2990#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 2991#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x00000010 2992#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000L 2993#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x00000018 2994#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0x000000ffL 2995#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x00000000 2996#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0x0000ff00L 2997#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x00000008 2998#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0x00ff0000L 2999#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x00000010 3000#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000L 3001#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x00000018 3002#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0x000000ffL 3003#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x00000000 3004#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0x0000ff00L 3005#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x00000008 3006#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0x00ff0000L 3007#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x00000010 3008#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000L 3009#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x00000018 3010#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0x000000ffL 3011#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x00000000 3012#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 3013#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x00000008 3014#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 3015#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x00000010 3016#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000L 3017#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x00000018 3018#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0x000000ffL 3019#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x00000000 3020#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 3021#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x00000008 3022#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 3023#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x00000010 3024#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000L 3025#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x00000018 3026#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 3027#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 3028#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 3029#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 3030#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 3031#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 3032#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000L 3033#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 3034#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 3035#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 3036#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 3037#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 3038#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 3039#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 3040#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000L 3041#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 3042#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 3043#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 3044#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 3045#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 3046#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 3047#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 3048#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000L 3049#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 3050#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 3051#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 3052#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 3053#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 3054#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 3055#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 3056#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000L 3057#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 3058#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0x000000ffL 3059#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x00000000 3060#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 3061#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x00000008 3062#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 3063#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x00000010 3064#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000L 3065#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x00000018 3066#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0x000000ffL 3067#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x00000000 3068#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 3069#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x00000008 3070#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 3071#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x00000010 3072#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000L 3073#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x00000018 3074#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0x000000ffL 3075#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x00000000 3076#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0x0000ff00L 3077#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x00000008 3078#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0x00ff0000L 3079#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x00000010 3080#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000L 3081#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x00000018 3082#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0x000000ffL 3083#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x00000000 3084#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0x0000ff00L 3085#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x00000008 3086#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0x00ff0000L 3087#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x00000010 3088#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000L 3089#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x00000018 3090#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0x000000ffL 3091#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x00000000 3092#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 3093#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x00000008 3094#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 3095#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x00000010 3096#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000L 3097#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x00000018 3098#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0x000000ffL 3099#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x00000000 3100#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 3101#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x00000008 3102#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 3103#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x00000010 3104#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000L 3105#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x00000018 3106#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0x000000ffL 3107#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x00000000 3108#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0x0000ff00L 3109#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x00000008 3110#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0x00ff0000L 3111#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x00000010 3112#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000L 3113#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x00000018 3114#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0x000000ffL 3115#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x00000000 3116#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0x0000ff00L 3117#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x00000008 3118#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0x00ff0000L 3119#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x00000010 3120#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000L 3121#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x00000018 3122#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0x000000ffL 3123#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x00000000 3124#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 3125#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x00000008 3126#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 3127#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x00000010 3128#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000L 3129#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x00000018 3130#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0x000000ffL 3131#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x00000000 3132#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 3133#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x00000008 3134#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 3135#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x00000010 3136#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000L 3137#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x00000018 3138#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 3139#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 3140#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 3141#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 3142#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 3143#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 3144#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000L 3145#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 3146#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 3147#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 3148#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 3149#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 3150#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 3151#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 3152#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000L 3153#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 3154#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 3155#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 3156#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 3157#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 3158#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 3159#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 3160#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000L 3161#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 3162#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 3163#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 3164#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 3165#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 3166#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 3167#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 3168#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000L 3169#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 3170#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0x000000ffL 3171#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x00000000 3172#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 3173#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x00000008 3174#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 3175#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x00000010 3176#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000L 3177#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x00000018 3178#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0x000000ffL 3179#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x00000000 3180#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 3181#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x00000008 3182#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 3183#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x00000010 3184#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000L 3185#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x00000018 3186#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0x000000ffL 3187#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x00000000 3188#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0x0000ff00L 3189#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x00000008 3190#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0x00ff0000L 3191#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x00000010 3192#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000L 3193#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x00000018 3194#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0x000000ffL 3195#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x00000000 3196#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0x0000ff00L 3197#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x00000008 3198#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0x00ff0000L 3199#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x00000010 3200#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000L 3201#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x00000018 3202#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0x000000ffL 3203#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x00000000 3204#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 3205#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x00000008 3206#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 3207#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x00000010 3208#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000L 3209#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x00000018 3210#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0x000000ffL 3211#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x00000000 3212#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 3213#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x00000008 3214#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 3215#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x00000010 3216#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000L 3217#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x00000018 3218#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0x000000ffL 3219#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x00000000 3220#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0x0000ff00L 3221#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x00000008 3222#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0x00ff0000L 3223#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x00000010 3224#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000L 3225#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x00000018 3226#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0x000000ffL 3227#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x00000000 3228#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0x0000ff00L 3229#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x00000008 3230#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0x00ff0000L 3231#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x00000010 3232#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000L 3233#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x00000018 3234#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0x000000ffL 3235#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x00000000 3236#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 3237#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x00000008 3238#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 3239#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x00000010 3240#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000L 3241#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x00000018 3242#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0x000000ffL 3243#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x00000000 3244#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 3245#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x00000008 3246#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 3247#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x00000010 3248#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000L 3249#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x00000018 3250#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0x000000ffL 3251#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x00000000 3252#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 3253#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x00000008 3254#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 3255#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x00000010 3256#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000L 3257#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x00000018 3258#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0x000000ffL 3259#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x00000000 3260#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 3261#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x00000008 3262#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 3263#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x00000010 3264#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000L 3265#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x00000018 3266#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0x000000ffL 3267#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x00000000 3268#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 3269#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x00000008 3270#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 3271#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x00000010 3272#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000L 3273#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x00000018 3274#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0x000000ffL 3275#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x00000000 3276#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 3277#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x00000008 3278#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 3279#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x00000010 3280#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000L 3281#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x00000018 3282#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 3283#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 3284#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 3285#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 3286#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 3287#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 3288#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000L 3289#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 3290#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 3291#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 3292#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 3293#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 3294#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 3295#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 3296#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000L 3297#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 3298#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 3299#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 3300#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 3301#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 3302#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 3303#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 3304#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000L 3305#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 3306#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 3307#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 3308#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 3309#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 3310#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 3311#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 3312#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000L 3313#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 3314#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0x000000ffL 3315#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x00000000 3316#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 3317#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x00000008 3318#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 3319#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x00000010 3320#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000L 3321#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x00000018 3322#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0x000000ffL 3323#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x00000000 3324#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 3325#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x00000008 3326#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 3327#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x00000010 3328#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000L 3329#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x00000018 3330#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0x000000ffL 3331#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x00000000 3332#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0x0000ff00L 3333#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x00000008 3334#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0x00ff0000L 3335#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x00000010 3336#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000L 3337#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x00000018 3338#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0x000000ffL 3339#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x00000000 3340#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0x0000ff00L 3341#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x00000008 3342#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0x00ff0000L 3343#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x00000010 3344#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000L 3345#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x00000018 3346#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL 3347#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 3348#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L 3349#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 3350#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L 3351#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 3352#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L 3353#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 3354#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL 3355#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 3356#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L 3357#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 3358#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L 3359#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 3360#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L 3361#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 3362#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0x000000ffL 3363#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x00000000 3364#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 3365#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x00000008 3366#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 3367#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x00000010 3368#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000L 3369#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x00000018 3370#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0x000000ffL 3371#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x00000000 3372#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 3373#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x00000008 3374#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 3375#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x00000010 3376#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000L 3377#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x00000018 3378#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0x000000ffL 3379#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x00000000 3380#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0x0000ff00L 3381#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x00000008 3382#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0x00ff0000L 3383#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x00000010 3384#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000L 3385#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x00000018 3386#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0x000000ffL 3387#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x00000000 3388#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0x0000ff00L 3389#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x00000008 3390#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0x00ff0000L 3391#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x00000010 3392#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000L 3393#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x00000018 3394#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0x000000ffL 3395#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x00000000 3396#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 3397#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x00000008 3398#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 3399#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x00000010 3400#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000L 3401#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x00000018 3402#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0x000000ffL 3403#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x00000000 3404#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 3405#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x00000008 3406#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 3407#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x00000010 3408#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000L 3409#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x00000018 3410#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0x000000ffL 3411#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x00000000 3412#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 3413#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x00000008 3414#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 3415#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x00000010 3416#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000L 3417#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x00000018 3418#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0x000000ffL 3419#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x00000000 3420#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 3421#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x00000008 3422#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 3423#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x00000010 3424#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000L 3425#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x00000018 3426#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0x000000ffL 3427#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x00000000 3428#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 3429#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x00000008 3430#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 3431#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x00000010 3432#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000L 3433#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x00000018 3434#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0x000000ffL 3435#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x00000000 3436#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 3437#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x00000008 3438#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 3439#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x00000010 3440#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000L 3441#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x00000018 3442#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 3443#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 3444#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 3445#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 3446#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 3447#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 3448#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 3449#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 3450#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 3451#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 3452#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 3453#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 3454#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 3455#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 3456#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 3457#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 3458#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 3459#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 3460#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 3461#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 3462#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 3463#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 3464#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000L 3465#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 3466#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 3467#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 3468#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 3469#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 3470#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 3471#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 3472#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000L 3473#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 3474#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 3475#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 3476#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 3477#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 3478#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 3479#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 3480#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000L 3481#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 3482#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 3483#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 3484#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 3485#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 3486#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 3487#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 3488#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000L 3489#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 3490#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0x000000ffL 3491#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x00000000 3492#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 3493#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x00000008 3494#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 3495#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x00000010 3496#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000L 3497#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x00000018 3498#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0x000000ffL 3499#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x00000000 3500#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 3501#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x00000008 3502#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 3503#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x00000010 3504#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000L 3505#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x00000018 3506#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0x000000ffL 3507#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x00000000 3508#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0x0000ff00L 3509#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x00000008 3510#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0x00ff0000L 3511#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x00000010 3512#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000L 3513#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x00000018 3514#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0x000000ffL 3515#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x00000000 3516#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0x0000ff00L 3517#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x00000008 3518#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0x00ff0000L 3519#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x00000010 3520#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000L 3521#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x00000018 3522#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL 3523#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 3524#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L 3525#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 3526#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L 3527#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 3528#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L 3529#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 3530#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL 3531#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 3532#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L 3533#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 3534#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L 3535#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 3536#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L 3537#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 3538#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL 3539#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 3540#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L 3541#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 3542#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L 3543#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 3544#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L 3545#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 3546#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL 3547#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 3548#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L 3549#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 3550#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L 3551#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 3552#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L 3553#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 3554#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL 3555#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 3556#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L 3557#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 3558#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L 3559#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 3560#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L 3561#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 3562#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL 3563#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 3564#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L 3565#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 3566#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L 3567#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 3568#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L 3569#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 3570#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL 3571#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 3572#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L 3573#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 3574#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L 3575#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 3576#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L 3577#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 3578#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL 3579#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 3580#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L 3581#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 3582#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L 3583#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 3584#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L 3585#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 3586#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL 3587#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 3588#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L 3589#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 3590#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L 3591#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 3592#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L 3593#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 3594#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL 3595#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 3596#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L 3597#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 3598#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L 3599#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 3600#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L 3601#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 3602#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0x000000ffL 3603#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 3604#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 3605#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 3606#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 3607#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 3608#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000L 3609#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 3610#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0x000000ffL 3611#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 3612#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 3613#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 3614#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 3615#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 3616#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000L 3617#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 3618#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0x000000ffL 3619#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x00000000 3620#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0x0000ff00L 3621#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x00000008 3622#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0x00ff0000L 3623#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x00000010 3624#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000L 3625#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x00000018 3626#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0x000000ffL 3627#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x00000000 3628#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0x0000ff00L 3629#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x00000008 3630#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0x00ff0000L 3631#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x00000010 3632#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000L 3633#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x00000018 3634#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0x000000ffL 3635#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 3636#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 3637#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 3638#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 3639#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 3640#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000L 3641#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 3642#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0x000000ffL 3643#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 3644#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 3645#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 3646#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 3647#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 3648#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000L 3649#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 3650#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0x000000ffL 3651#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 3652#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 3653#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 3654#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 3655#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 3656#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000L 3657#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 3658#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0x000000ffL 3659#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 3660#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 3661#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 3662#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 3663#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 3664#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000L 3665#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 3666#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0x000000ffL 3667#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 3668#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 3669#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 3670#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 3671#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 3672#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000L 3673#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 3674#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0x000000ffL 3675#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 3676#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 3677#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 3678#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 3679#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 3680#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000L 3681#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 3682#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 3683#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 3684#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 3685#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 3686#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 3687#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 3688#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 3689#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 3690#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 3691#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 3692#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 3693#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 3694#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 3695#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 3696#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 3697#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 3698#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 3699#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 3700#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 3701#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 3702#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 3703#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 3704#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000L 3705#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 3706#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 3707#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 3708#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 3709#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 3710#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 3711#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 3712#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000L 3713#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 3714#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 3715#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 3716#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 3717#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 3718#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 3719#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 3720#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000L 3721#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 3722#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 3723#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 3724#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 3725#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 3726#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 3727#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 3728#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000L 3729#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 3730#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0x000000ffL 3731#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 3732#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 3733#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 3734#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 3735#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 3736#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000L 3737#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 3738#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0x000000ffL 3739#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 3740#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 3741#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 3742#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 3743#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 3744#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000L 3745#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 3746#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0x000000ffL 3747#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x00000000 3748#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0x0000ff00L 3749#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x00000008 3750#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0x00ff0000L 3751#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x00000010 3752#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000L 3753#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x00000018 3754#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0x000000ffL 3755#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x00000000 3756#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0x0000ff00L 3757#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x00000008 3758#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0x00ff0000L 3759#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x00000010 3760#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000L 3761#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x00000018 3762#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0x000000ffL 3763#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 3764#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 3765#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 3766#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 3767#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 3768#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000L 3769#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 3770#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0x000000ffL 3771#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 3772#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 3773#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 3774#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 3775#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 3776#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000L 3777#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 3778#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0x000000ffL 3779#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x00000000 3780#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0x0000ff00L 3781#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x00000008 3782#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0x00ff0000L 3783#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x00000010 3784#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000L 3785#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x00000018 3786#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0x000000ffL 3787#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x00000000 3788#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0x0000ff00L 3789#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x00000008 3790#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0x00ff0000L 3791#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x00000010 3792#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000L 3793#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x00000018 3794#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0x000000ffL 3795#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 3796#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 3797#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 3798#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 3799#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 3800#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000L 3801#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 3802#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0x000000ffL 3803#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 3804#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 3805#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 3806#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 3807#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 3808#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000L 3809#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 3810#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0x000000ffL 3811#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 3812#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 3813#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 3814#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 3815#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 3816#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000L 3817#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 3818#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0x000000ffL 3819#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 3820#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 3821#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 3822#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 3823#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 3824#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000L 3825#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 3826#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0x000000ffL 3827#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 3828#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 3829#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 3830#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 3831#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 3832#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000L 3833#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 3834#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0x000000ffL 3835#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 3836#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 3837#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 3838#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 3839#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 3840#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000L 3841#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 3842#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 3843#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 3844#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 3845#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 3846#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 3847#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 3848#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 3849#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 3850#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 3851#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 3852#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 3853#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 3854#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 3855#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 3856#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 3857#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 3858#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 3859#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 3860#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 3861#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 3862#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 3863#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 3864#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000L 3865#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 3866#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 3867#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 3868#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 3869#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 3870#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 3871#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 3872#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000L 3873#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 3874#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 3875#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 3876#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 3877#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 3878#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 3879#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 3880#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000L 3881#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 3882#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 3883#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 3884#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 3885#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 3886#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 3887#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 3888#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000L 3889#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 3890#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0x000000ffL 3891#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 3892#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 3893#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 3894#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 3895#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 3896#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000L 3897#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 3898#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0x000000ffL 3899#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 3900#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 3901#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 3902#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 3903#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 3904#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000L 3905#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 3906#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0x000000ffL 3907#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x00000000 3908#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0x0000ff00L 3909#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x00000008 3910#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0x00ff0000L 3911#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x00000010 3912#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000L 3913#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x00000018 3914#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0x000000ffL 3915#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x00000000 3916#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0x0000ff00L 3917#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x00000008 3918#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0x00ff0000L 3919#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x00000010 3920#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000L 3921#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x00000018 3922#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL 3923#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 3924#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L 3925#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 3926#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L 3927#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 3928#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L 3929#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 3930#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL 3931#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 3932#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L 3933#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 3934#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L 3935#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 3936#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L 3937#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 3938#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0x000000ffL 3939#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 3940#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 3941#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 3942#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 3943#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 3944#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000L 3945#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 3946#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0x000000ffL 3947#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 3948#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 3949#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 3950#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 3951#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 3952#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000L 3953#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 3954#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0x000000ffL 3955#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x00000000 3956#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0x0000ff00L 3957#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x00000008 3958#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0x00ff0000L 3959#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x00000010 3960#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000L 3961#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x00000018 3962#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0x000000ffL 3963#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x00000000 3964#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0x0000ff00L 3965#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x00000008 3966#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0x00ff0000L 3967#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x00000010 3968#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000L 3969#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x00000018 3970#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0x000000ffL 3971#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 3972#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 3973#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 3974#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 3975#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 3976#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000L 3977#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 3978#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0x000000ffL 3979#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 3980#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 3981#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 3982#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 3983#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 3984#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000L 3985#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 3986#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0x000000ffL 3987#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 3988#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 3989#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 3990#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 3991#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 3992#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000L 3993#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 3994#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0x000000ffL 3995#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 3996#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 3997#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 3998#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 3999#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 4000#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000L 4001#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 4002#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0x000000ffL 4003#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 4004#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 4005#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 4006#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 4007#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 4008#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000L 4009#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 4010#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0x000000ffL 4011#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 4012#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 4013#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 4014#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 4015#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 4016#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000L 4017#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 4018#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 4019#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 4020#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 4021#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 4022#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 4023#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 4024#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 4025#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 4026#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 4027#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 4028#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 4029#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 4030#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 4031#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 4032#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 4033#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 4034#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 4035#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 4036#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 4037#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 4038#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 4039#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 4040#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000L 4041#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 4042#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 4043#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 4044#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 4045#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 4046#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 4047#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 4048#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000L 4049#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 4050#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 4051#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 4052#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 4053#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 4054#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 4055#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 4056#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000L 4057#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 4058#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 4059#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 4060#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 4061#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 4062#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 4063#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 4064#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000L 4065#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 4066#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0x000000ffL 4067#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 4068#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 4069#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 4070#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 4071#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 4072#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000L 4073#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 4074#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0x000000ffL 4075#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 4076#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 4077#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 4078#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 4079#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 4080#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000L 4081#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 4082#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0x000000ffL 4083#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x00000000 4084#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0x0000ff00L 4085#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x00000008 4086#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0x00ff0000L 4087#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x00000010 4088#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000L 4089#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x00000018 4090#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0x000000ffL 4091#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x00000000 4092#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0x0000ff00L 4093#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x00000008 4094#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0x00ff0000L 4095#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x00000010 4096#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000L 4097#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x00000018 4098#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0x000000ffL 4099#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 4100#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 4101#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 4102#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 4103#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 4104#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000L 4105#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 4106#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0x000000ffL 4107#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 4108#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 4109#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 4110#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 4111#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 4112#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000L 4113#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 4114#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0x000000ffL 4115#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x00000000 4116#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0x0000ff00L 4117#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x00000008 4118#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0x00ff0000L 4119#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x00000010 4120#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000L 4121#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x00000018 4122#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0x000000ffL 4123#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x00000000 4124#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0x0000ff00L 4125#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x00000008 4126#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0x00ff0000L 4127#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x00000010 4128#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000L 4129#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x00000018 4130#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0x000000ffL 4131#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 4132#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 4133#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 4134#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 4135#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 4136#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000L 4137#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 4138#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0x000000ffL 4139#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 4140#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 4141#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 4142#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 4143#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 4144#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000L 4145#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 4146#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0x000000ffL 4147#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 4148#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 4149#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 4150#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 4151#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 4152#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000L 4153#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 4154#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0x000000ffL 4155#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 4156#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 4157#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 4158#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 4159#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 4160#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000L 4161#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 4162#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0x000000ffL 4163#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 4164#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 4165#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 4166#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 4167#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 4168#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000L 4169#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 4170#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0x000000ffL 4171#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 4172#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 4173#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 4174#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 4175#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 4176#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000L 4177#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 4178#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 4179#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 4180#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 4181#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 4182#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 4183#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 4184#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 4185#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 4186#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 4187#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 4188#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 4189#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 4190#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 4191#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 4192#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 4193#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 4194#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 4195#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 4196#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 4197#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 4198#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 4199#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 4200#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000L 4201#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 4202#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 4203#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 4204#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 4205#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 4206#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 4207#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 4208#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000L 4209#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 4210#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 4211#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 4212#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 4213#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 4214#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 4215#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 4216#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000L 4217#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 4218#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 4219#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 4220#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 4221#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 4222#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 4223#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 4224#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000L 4225#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 4226#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0x000000ffL 4227#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 4228#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 4229#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 4230#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 4231#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 4232#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000L 4233#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 4234#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0x000000ffL 4235#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 4236#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 4237#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 4238#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 4239#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 4240#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000L 4241#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 4242#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0x000000ffL 4243#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x00000000 4244#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0x0000ff00L 4245#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x00000008 4246#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0x00ff0000L 4247#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x00000010 4248#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000L 4249#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x00000018 4250#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0x000000ffL 4251#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x00000000 4252#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0x0000ff00L 4253#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x00000008 4254#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0x00ff0000L 4255#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x00000010 4256#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000L 4257#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x00000018 4258#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL 4259#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 4260#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L 4261#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 4262#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L 4263#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 4264#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L 4265#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 4266#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL 4267#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 4268#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L 4269#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 4270#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L 4271#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 4272#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L 4273#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 4274#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0x000000ffL 4275#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 4276#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 4277#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 4278#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 4279#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 4280#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000L 4281#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 4282#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0x000000ffL 4283#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 4284#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 4285#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 4286#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 4287#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 4288#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000L 4289#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 4290#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0x000000ffL 4291#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x00000000 4292#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0x0000ff00L 4293#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x00000008 4294#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0x00ff0000L 4295#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x00000010 4296#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000L 4297#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x00000018 4298#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0x000000ffL 4299#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x00000000 4300#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0x0000ff00L 4301#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x00000008 4302#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0x00ff0000L 4303#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x00000010 4304#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000L 4305#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x00000018 4306#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0x000000ffL 4307#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 4308#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 4309#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 4310#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 4311#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 4312#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000L 4313#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 4314#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0x000000ffL 4315#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 4316#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 4317#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 4318#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 4319#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 4320#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000L 4321#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 4322#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0x000000ffL 4323#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 4324#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 4325#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 4326#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 4327#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 4328#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000L 4329#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 4330#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0x000000ffL 4331#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 4332#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 4333#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 4334#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 4335#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 4336#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000L 4337#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 4338#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0x000000ffL 4339#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 4340#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 4341#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 4342#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 4343#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 4344#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000L 4345#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 4346#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0x000000ffL 4347#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 4348#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 4349#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 4350#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 4351#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 4352#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000L 4353#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 4354#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 4355#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 4356#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 4357#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 4358#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 4359#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 4360#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 4361#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 4362#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 4363#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 4364#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 4365#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 4366#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 4367#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 4368#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 4369#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 4370#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 4371#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 4372#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 4373#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 4374#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 4375#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 4376#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000L 4377#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 4378#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 4379#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 4380#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 4381#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 4382#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 4383#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 4384#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000L 4385#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 4386#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 4387#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 4388#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 4389#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 4390#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 4391#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 4392#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000L 4393#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 4394#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 4395#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 4396#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 4397#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 4398#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 4399#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 4400#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000L 4401#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 4402#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0x000000ffL 4403#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 4404#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 4405#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 4406#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 4407#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 4408#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000L 4409#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 4410#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0x000000ffL 4411#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 4412#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 4413#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 4414#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 4415#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 4416#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000L 4417#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 4418#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0x000000ffL 4419#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x00000000 4420#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0x0000ff00L 4421#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x00000008 4422#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0x00ff0000L 4423#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x00000010 4424#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000L 4425#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x00000018 4426#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0x000000ffL 4427#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x00000000 4428#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0x0000ff00L 4429#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x00000008 4430#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0x00ff0000L 4431#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x00000010 4432#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000L 4433#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x00000018 4434#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0x000000ffL 4435#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 4436#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 4437#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 4438#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 4439#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 4440#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000L 4441#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 4442#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0x000000ffL 4443#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 4444#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 4445#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 4446#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 4447#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 4448#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000L 4449#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 4450#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0x000000ffL 4451#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x00000000 4452#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0x0000ff00L 4453#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x00000008 4454#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0x00ff0000L 4455#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x00000010 4456#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000L 4457#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x00000018 4458#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0x000000ffL 4459#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x00000000 4460#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0x0000ff00L 4461#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x00000008 4462#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0x00ff0000L 4463#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x00000010 4464#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000L 4465#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x00000018 4466#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0x000000ffL 4467#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 4468#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 4469#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 4470#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 4471#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 4472#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000L 4473#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 4474#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0x000000ffL 4475#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 4476#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 4477#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 4478#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 4479#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 4480#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000L 4481#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 4482#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0x000000ffL 4483#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 4484#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 4485#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 4486#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 4487#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 4488#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000L 4489#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 4490#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0x000000ffL 4491#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 4492#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 4493#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 4494#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 4495#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 4496#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000L 4497#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 4498#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0x000000ffL 4499#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 4500#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 4501#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 4502#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 4503#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 4504#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000L 4505#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 4506#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0x000000ffL 4507#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 4508#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 4509#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 4510#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 4511#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 4512#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000L 4513#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 4514#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 4515#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 4516#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 4517#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 4518#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 4519#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 4520#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 4521#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 4522#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 4523#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 4524#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 4525#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 4526#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 4527#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 4528#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 4529#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 4530#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 4531#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 4532#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 4533#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 4534#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 4535#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 4536#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000L 4537#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 4538#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 4539#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 4540#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 4541#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 4542#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 4543#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 4544#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000L 4545#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 4546#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 4547#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 4548#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 4549#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 4550#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 4551#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 4552#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000L 4553#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 4554#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 4555#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 4556#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 4557#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 4558#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 4559#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 4560#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000L 4561#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 4562#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0x000000ffL 4563#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 4564#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 4565#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 4566#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 4567#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 4568#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000L 4569#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 4570#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0x000000ffL 4571#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 4572#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 4573#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 4574#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 4575#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 4576#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000L 4577#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 4578#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0x000000ffL 4579#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x00000000 4580#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0x0000ff00L 4581#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x00000008 4582#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0x00ff0000L 4583#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x00000010 4584#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000L 4585#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x00000018 4586#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0x000000ffL 4587#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x00000000 4588#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0x0000ff00L 4589#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x00000008 4590#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0x00ff0000L 4591#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x00000010 4592#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000L 4593#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x00000018 4594#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL 4595#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 4596#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L 4597#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 4598#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L 4599#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 4600#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L 4601#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 4602#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL 4603#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 4604#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L 4605#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 4606#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L 4607#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 4608#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L 4609#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 4610#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0x000000ffL 4611#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 4612#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 4613#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 4614#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 4615#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 4616#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000L 4617#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 4618#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0x000000ffL 4619#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 4620#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 4621#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 4622#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 4623#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 4624#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000L 4625#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 4626#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0x000000ffL 4627#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x00000000 4628#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0x0000ff00L 4629#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x00000008 4630#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0x00ff0000L 4631#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x00000010 4632#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000L 4633#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x00000018 4634#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0x000000ffL 4635#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x00000000 4636#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0x0000ff00L 4637#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x00000008 4638#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0x00ff0000L 4639#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x00000010 4640#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000L 4641#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x00000018 4642#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0x000000ffL 4643#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 4644#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 4645#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 4646#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 4647#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 4648#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000L 4649#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 4650#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0x000000ffL 4651#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 4652#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 4653#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 4654#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 4655#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 4656#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000L 4657#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 4658#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0x000000ffL 4659#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 4660#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 4661#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 4662#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 4663#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 4664#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000L 4665#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 4666#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0x000000ffL 4667#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 4668#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 4669#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 4670#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 4671#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 4672#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000L 4673#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 4674#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0x000000ffL 4675#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 4676#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 4677#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 4678#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 4679#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 4680#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000L 4681#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 4682#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0x000000ffL 4683#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 4684#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 4685#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 4686#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 4687#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 4688#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000L 4689#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 4690#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 4691#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 4692#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 4693#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 4694#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 4695#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 4696#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 4697#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 4698#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 4699#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 4700#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 4701#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 4702#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 4703#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 4704#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 4705#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 4706#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 4707#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 4708#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 4709#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 4710#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 4711#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 4712#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000L 4713#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 4714#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 4715#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 4716#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 4717#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 4718#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 4719#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 4720#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000L 4721#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 4722#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 4723#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 4724#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 4725#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 4726#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 4727#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 4728#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000L 4729#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 4730#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 4731#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 4732#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 4733#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 4734#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 4735#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 4736#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000L 4737#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 4738#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0x000000ffL 4739#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 4740#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 4741#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 4742#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 4743#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 4744#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000L 4745#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 4746#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0x000000ffL 4747#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 4748#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 4749#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 4750#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 4751#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 4752#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000L 4753#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 4754#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0x000000ffL 4755#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x00000000 4756#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0x0000ff00L 4757#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x00000008 4758#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0x00ff0000L 4759#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x00000010 4760#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000L 4761#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x00000018 4762#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0x000000ffL 4763#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x00000000 4764#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0x0000ff00L 4765#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x00000008 4766#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0x00ff0000L 4767#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x00000010 4768#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000L 4769#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x00000018 4770#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0x000000ffL 4771#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 4772#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 4773#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 4774#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 4775#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 4776#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000L 4777#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 4778#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0x000000ffL 4779#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 4780#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 4781#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 4782#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 4783#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 4784#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000L 4785#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 4786#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0x000000ffL 4787#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x00000000 4788#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0x0000ff00L 4789#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x00000008 4790#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0x00ff0000L 4791#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x00000010 4792#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000L 4793#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x00000018 4794#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0x000000ffL 4795#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x00000000 4796#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0x0000ff00L 4797#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x00000008 4798#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0x00ff0000L 4799#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x00000010 4800#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000L 4801#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x00000018 4802#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0x000000ffL 4803#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 4804#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 4805#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 4806#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 4807#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 4808#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000L 4809#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 4810#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0x000000ffL 4811#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 4812#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 4813#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 4814#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 4815#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 4816#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000L 4817#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 4818#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0x000000ffL 4819#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 4820#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 4821#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 4822#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 4823#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 4824#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000L 4825#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 4826#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0x000000ffL 4827#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 4828#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 4829#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 4830#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 4831#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 4832#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000L 4833#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 4834#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0x000000ffL 4835#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 4836#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 4837#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 4838#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 4839#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 4840#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000L 4841#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 4842#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0x000000ffL 4843#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 4844#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 4845#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 4846#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 4847#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 4848#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000L 4849#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 4850#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 4851#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 4852#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 4853#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 4854#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 4855#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 4856#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 4857#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 4858#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 4859#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 4860#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 4861#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 4862#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 4863#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 4864#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 4865#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 4866#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 4867#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 4868#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 4869#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 4870#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 4871#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 4872#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000L 4873#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 4874#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 4875#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 4876#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 4877#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 4878#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 4879#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 4880#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000L 4881#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 4882#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 4883#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 4884#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 4885#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 4886#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 4887#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 4888#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000L 4889#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 4890#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 4891#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 4892#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 4893#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 4894#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 4895#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 4896#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000L 4897#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 4898#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0x000000ffL 4899#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 4900#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 4901#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 4902#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 4903#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 4904#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000L 4905#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 4906#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0x000000ffL 4907#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 4908#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 4909#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 4910#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 4911#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 4912#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000L 4913#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 4914#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0x000000ffL 4915#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x00000000 4916#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0x0000ff00L 4917#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x00000008 4918#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0x00ff0000L 4919#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x00000010 4920#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000L 4921#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x00000018 4922#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0x000000ffL 4923#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x00000000 4924#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0x0000ff00L 4925#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x00000008 4926#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0x00ff0000L 4927#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x00000010 4928#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000L 4929#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x00000018 4930#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL 4931#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 4932#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L 4933#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 4934#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L 4935#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 4936#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L 4937#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 4938#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL 4939#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 4940#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L 4941#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 4942#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L 4943#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 4944#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L 4945#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 4946#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0x000000ffL 4947#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x00000000 4948#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 4949#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x00000008 4950#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 4951#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x00000010 4952#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000L 4953#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x00000018 4954#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0x000000ffL 4955#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x00000000 4956#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 4957#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x00000008 4958#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 4959#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x00000010 4960#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000L 4961#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x00000018 4962#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0x000000ffL 4963#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x00000000 4964#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0x0000ff00L 4965#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x00000008 4966#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0x00ff0000L 4967#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x00000010 4968#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000L 4969#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x00000018 4970#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0x000000ffL 4971#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x00000000 4972#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0x0000ff00L 4973#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x00000008 4974#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0x00ff0000L 4975#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x00000010 4976#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000L 4977#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x00000018 4978#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0x000000ffL 4979#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x00000000 4980#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 4981#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x00000008 4982#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 4983#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x00000010 4984#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000L 4985#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x00000018 4986#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0x000000ffL 4987#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x00000000 4988#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 4989#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x00000008 4990#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 4991#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x00000010 4992#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000L 4993#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x00000018 4994#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL 4995#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 4996#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L 4997#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 4998#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L 4999#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 5000#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L 5001#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 5002#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL 5003#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 5004#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L 5005#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 5006#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L 5007#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 5008#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L 5009#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 5010#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0x000000ffL 5011#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x00000000 5012#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 5013#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x00000008 5014#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 5015#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x00000010 5016#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000L 5017#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x00000018 5018#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0x000000ffL 5019#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x00000000 5020#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 5021#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x00000008 5022#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 5023#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x00000010 5024#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000L 5025#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x00000018 5026#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL 5027#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 5028#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L 5029#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 5030#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L 5031#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 5032#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L 5033#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 5034#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL 5035#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 5036#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L 5037#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 5038#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L 5039#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 5040#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L 5041#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 5042#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0x000000ffL 5043#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x00000000 5044#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 5045#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x00000008 5046#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 5047#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x00000010 5048#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000L 5049#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x00000018 5050#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0x000000ffL 5051#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x00000000 5052#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 5053#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x00000008 5054#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 5055#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x00000010 5056#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000L 5057#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x00000018 5058#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 5059#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 5060#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 5061#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 5062#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 5063#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 5064#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 5065#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 5066#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 5067#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 5068#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 5069#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 5070#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 5071#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 5072#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 5073#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 5074#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 5075#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 5076#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 5077#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 5078#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 5079#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 5080#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000L 5081#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 5082#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 5083#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 5084#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 5085#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 5086#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 5087#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 5088#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000L 5089#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 5090#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 5091#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 5092#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 5093#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 5094#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 5095#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 5096#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000L 5097#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 5098#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 5099#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 5100#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 5101#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 5102#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 5103#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 5104#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000L 5105#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 5106#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0x000000ffL 5107#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x00000000 5108#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 5109#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x00000008 5110#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 5111#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x00000010 5112#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000L 5113#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x00000018 5114#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0x000000ffL 5115#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x00000000 5116#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 5117#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x00000008 5118#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 5119#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x00000010 5120#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000L 5121#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x00000018 5122#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0x000000ffL 5123#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x00000000 5124#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0x0000ff00L 5125#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x00000008 5126#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0x00ff0000L 5127#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x00000010 5128#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000L 5129#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x00000018 5130#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0x000000ffL 5131#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x00000000 5132#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0x0000ff00L 5133#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x00000008 5134#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0x00ff0000L 5135#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x00000010 5136#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000L 5137#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x00000018 5138#define MC_IO_DEBUG_UP_0__VALUE0_MASK 0x000000ffL 5139#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x00000000 5140#define MC_IO_DEBUG_UP_0__VALUE1_MASK 0x0000ff00L 5141#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x00000008 5142#define MC_IO_DEBUG_UP_0__VALUE2_MASK 0x00ff0000L 5143#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x00000010 5144#define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000L 5145#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x00000018 5146#define MC_IO_DEBUG_UP_100__VALUE0_MASK 0x000000ffL 5147#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x00000000 5148#define MC_IO_DEBUG_UP_100__VALUE1_MASK 0x0000ff00L 5149#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x00000008 5150#define MC_IO_DEBUG_UP_100__VALUE2_MASK 0x00ff0000L 5151#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x00000010 5152#define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000L 5153#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x00000018 5154#define MC_IO_DEBUG_UP_101__VALUE0_MASK 0x000000ffL 5155#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x00000000 5156#define MC_IO_DEBUG_UP_101__VALUE1_MASK 0x0000ff00L 5157#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x00000008 5158#define MC_IO_DEBUG_UP_101__VALUE2_MASK 0x00ff0000L 5159#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x00000010 5160#define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000L 5161#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x00000018 5162#define MC_IO_DEBUG_UP_102__VALUE0_MASK 0x000000ffL 5163#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x00000000 5164#define MC_IO_DEBUG_UP_102__VALUE1_MASK 0x0000ff00L 5165#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x00000008 5166#define MC_IO_DEBUG_UP_102__VALUE2_MASK 0x00ff0000L 5167#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x00000010 5168#define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000L 5169#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x00000018 5170#define MC_IO_DEBUG_UP_103__VALUE0_MASK 0x000000ffL 5171#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x00000000 5172#define MC_IO_DEBUG_UP_103__VALUE1_MASK 0x0000ff00L 5173#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x00000008 5174#define MC_IO_DEBUG_UP_103__VALUE2_MASK 0x00ff0000L 5175#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x00000010 5176#define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000L 5177#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x00000018 5178#define MC_IO_DEBUG_UP_104__VALUE0_MASK 0x000000ffL 5179#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x00000000 5180#define MC_IO_DEBUG_UP_104__VALUE1_MASK 0x0000ff00L 5181#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x00000008 5182#define MC_IO_DEBUG_UP_104__VALUE2_MASK 0x00ff0000L 5183#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x00000010 5184#define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000L 5185#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x00000018 5186#define MC_IO_DEBUG_UP_105__VALUE0_MASK 0x000000ffL 5187#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x00000000 5188#define MC_IO_DEBUG_UP_105__VALUE1_MASK 0x0000ff00L 5189#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x00000008 5190#define MC_IO_DEBUG_UP_105__VALUE2_MASK 0x00ff0000L 5191#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x00000010 5192#define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000L 5193#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x00000018 5194#define MC_IO_DEBUG_UP_106__VALUE0_MASK 0x000000ffL 5195#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x00000000 5196#define MC_IO_DEBUG_UP_106__VALUE1_MASK 0x0000ff00L 5197#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x00000008 5198#define MC_IO_DEBUG_UP_106__VALUE2_MASK 0x00ff0000L 5199#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x00000010 5200#define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000L 5201#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x00000018 5202#define MC_IO_DEBUG_UP_107__VALUE0_MASK 0x000000ffL 5203#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x00000000 5204#define MC_IO_DEBUG_UP_107__VALUE1_MASK 0x0000ff00L 5205#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x00000008 5206#define MC_IO_DEBUG_UP_107__VALUE2_MASK 0x00ff0000L 5207#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x00000010 5208#define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000L 5209#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x00000018 5210#define MC_IO_DEBUG_UP_108__VALUE0_MASK 0x000000ffL 5211#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x00000000 5212#define MC_IO_DEBUG_UP_108__VALUE1_MASK 0x0000ff00L 5213#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x00000008 5214#define MC_IO_DEBUG_UP_108__VALUE2_MASK 0x00ff0000L 5215#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x00000010 5216#define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000L 5217#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x00000018 5218#define MC_IO_DEBUG_UP_109__VALUE0_MASK 0x000000ffL 5219#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x00000000 5220#define MC_IO_DEBUG_UP_109__VALUE1_MASK 0x0000ff00L 5221#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x00000008 5222#define MC_IO_DEBUG_UP_109__VALUE2_MASK 0x00ff0000L 5223#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x00000010 5224#define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000L 5225#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x00000018 5226#define MC_IO_DEBUG_UP_10__VALUE0_MASK 0x000000ffL 5227#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x00000000 5228#define MC_IO_DEBUG_UP_10__VALUE1_MASK 0x0000ff00L 5229#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x00000008 5230#define MC_IO_DEBUG_UP_10__VALUE2_MASK 0x00ff0000L 5231#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x00000010 5232#define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000L 5233#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x00000018 5234#define MC_IO_DEBUG_UP_110__VALUE0_MASK 0x000000ffL 5235#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x00000000 5236#define MC_IO_DEBUG_UP_110__VALUE1_MASK 0x0000ff00L 5237#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x00000008 5238#define MC_IO_DEBUG_UP_110__VALUE2_MASK 0x00ff0000L 5239#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x00000010 5240#define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000L 5241#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x00000018 5242#define MC_IO_DEBUG_UP_111__VALUE0_MASK 0x000000ffL 5243#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x00000000 5244#define MC_IO_DEBUG_UP_111__VALUE1_MASK 0x0000ff00L 5245#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x00000008 5246#define MC_IO_DEBUG_UP_111__VALUE2_MASK 0x00ff0000L 5247#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x00000010 5248#define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000L 5249#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x00000018 5250#define MC_IO_DEBUG_UP_112__VALUE0_MASK 0x000000ffL 5251#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x00000000 5252#define MC_IO_DEBUG_UP_112__VALUE1_MASK 0x0000ff00L 5253#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x00000008 5254#define MC_IO_DEBUG_UP_112__VALUE2_MASK 0x00ff0000L 5255#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x00000010 5256#define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000L 5257#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x00000018 5258#define MC_IO_DEBUG_UP_113__VALUE0_MASK 0x000000ffL 5259#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x00000000 5260#define MC_IO_DEBUG_UP_113__VALUE1_MASK 0x0000ff00L 5261#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x00000008 5262#define MC_IO_DEBUG_UP_113__VALUE2_MASK 0x00ff0000L 5263#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x00000010 5264#define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000L 5265#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x00000018 5266#define MC_IO_DEBUG_UP_114__VALUE0_MASK 0x000000ffL 5267#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x00000000 5268#define MC_IO_DEBUG_UP_114__VALUE1_MASK 0x0000ff00L 5269#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x00000008 5270#define MC_IO_DEBUG_UP_114__VALUE2_MASK 0x00ff0000L 5271#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x00000010 5272#define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000L 5273#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x00000018 5274#define MC_IO_DEBUG_UP_115__VALUE0_MASK 0x000000ffL 5275#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x00000000 5276#define MC_IO_DEBUG_UP_115__VALUE1_MASK 0x0000ff00L 5277#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x00000008 5278#define MC_IO_DEBUG_UP_115__VALUE2_MASK 0x00ff0000L 5279#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x00000010 5280#define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000L 5281#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x00000018 5282#define MC_IO_DEBUG_UP_116__VALUE0_MASK 0x000000ffL 5283#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x00000000 5284#define MC_IO_DEBUG_UP_116__VALUE1_MASK 0x0000ff00L 5285#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x00000008 5286#define MC_IO_DEBUG_UP_116__VALUE2_MASK 0x00ff0000L 5287#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x00000010 5288#define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000L 5289#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x00000018 5290#define MC_IO_DEBUG_UP_117__VALUE0_MASK 0x000000ffL 5291#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x00000000 5292#define MC_IO_DEBUG_UP_117__VALUE1_MASK 0x0000ff00L 5293#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x00000008 5294#define MC_IO_DEBUG_UP_117__VALUE2_MASK 0x00ff0000L 5295#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x00000010 5296#define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000L 5297#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x00000018 5298#define MC_IO_DEBUG_UP_118__VALUE0_MASK 0x000000ffL 5299#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x00000000 5300#define MC_IO_DEBUG_UP_118__VALUE1_MASK 0x0000ff00L 5301#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x00000008 5302#define MC_IO_DEBUG_UP_118__VALUE2_MASK 0x00ff0000L 5303#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x00000010 5304#define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000L 5305#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x00000018 5306#define MC_IO_DEBUG_UP_119__VALUE0_MASK 0x000000ffL 5307#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x00000000 5308#define MC_IO_DEBUG_UP_119__VALUE1_MASK 0x0000ff00L 5309#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x00000008 5310#define MC_IO_DEBUG_UP_119__VALUE2_MASK 0x00ff0000L 5311#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x00000010 5312#define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000L 5313#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x00000018 5314#define MC_IO_DEBUG_UP_11__VALUE0_MASK 0x000000ffL 5315#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x00000000 5316#define MC_IO_DEBUG_UP_11__VALUE1_MASK 0x0000ff00L 5317#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x00000008 5318#define MC_IO_DEBUG_UP_11__VALUE2_MASK 0x00ff0000L 5319#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x00000010 5320#define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000L 5321#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x00000018 5322#define MC_IO_DEBUG_UP_120__VALUE0_MASK 0x000000ffL 5323#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x00000000 5324#define MC_IO_DEBUG_UP_120__VALUE1_MASK 0x0000ff00L 5325#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x00000008 5326#define MC_IO_DEBUG_UP_120__VALUE2_MASK 0x00ff0000L 5327#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x00000010 5328#define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000L 5329#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x00000018 5330#define MC_IO_DEBUG_UP_121__VALUE0_MASK 0x000000ffL 5331#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x00000000 5332#define MC_IO_DEBUG_UP_121__VALUE1_MASK 0x0000ff00L 5333#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x00000008 5334#define MC_IO_DEBUG_UP_121__VALUE2_MASK 0x00ff0000L 5335#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x00000010 5336#define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000L 5337#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x00000018 5338#define MC_IO_DEBUG_UP_122__VALUE0_MASK 0x000000ffL 5339#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x00000000 5340#define MC_IO_DEBUG_UP_122__VALUE1_MASK 0x0000ff00L 5341#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x00000008 5342#define MC_IO_DEBUG_UP_122__VALUE2_MASK 0x00ff0000L 5343#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x00000010 5344#define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000L 5345#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x00000018 5346#define MC_IO_DEBUG_UP_123__VALUE0_MASK 0x000000ffL 5347#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x00000000 5348#define MC_IO_DEBUG_UP_123__VALUE1_MASK 0x0000ff00L 5349#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x00000008 5350#define MC_IO_DEBUG_UP_123__VALUE2_MASK 0x00ff0000L 5351#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x00000010 5352#define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000L 5353#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x00000018 5354#define MC_IO_DEBUG_UP_124__VALUE0_MASK 0x000000ffL 5355#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x00000000 5356#define MC_IO_DEBUG_UP_124__VALUE1_MASK 0x0000ff00L 5357#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x00000008 5358#define MC_IO_DEBUG_UP_124__VALUE2_MASK 0x00ff0000L 5359#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x00000010 5360#define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000L 5361#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x00000018 5362#define MC_IO_DEBUG_UP_125__VALUE0_MASK 0x000000ffL 5363#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x00000000 5364#define MC_IO_DEBUG_UP_125__VALUE1_MASK 0x0000ff00L 5365#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x00000008 5366#define MC_IO_DEBUG_UP_125__VALUE2_MASK 0x00ff0000L 5367#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x00000010 5368#define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000L 5369#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x00000018 5370#define MC_IO_DEBUG_UP_126__VALUE0_MASK 0x000000ffL 5371#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x00000000 5372#define MC_IO_DEBUG_UP_126__VALUE1_MASK 0x0000ff00L 5373#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x00000008 5374#define MC_IO_DEBUG_UP_126__VALUE2_MASK 0x00ff0000L 5375#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x00000010 5376#define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000L 5377#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x00000018 5378#define MC_IO_DEBUG_UP_127__VALUE0_MASK 0x000000ffL 5379#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x00000000 5380#define MC_IO_DEBUG_UP_127__VALUE1_MASK 0x0000ff00L 5381#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x00000008 5382#define MC_IO_DEBUG_UP_127__VALUE2_MASK 0x00ff0000L 5383#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x00000010 5384#define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000L 5385#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x00000018 5386#define MC_IO_DEBUG_UP_128__VALUE0_MASK 0x000000ffL 5387#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x00000000 5388#define MC_IO_DEBUG_UP_128__VALUE1_MASK 0x0000ff00L 5389#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x00000008 5390#define MC_IO_DEBUG_UP_128__VALUE2_MASK 0x00ff0000L 5391#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x00000010 5392#define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000L 5393#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x00000018 5394#define MC_IO_DEBUG_UP_129__VALUE0_MASK 0x000000ffL 5395#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x00000000 5396#define MC_IO_DEBUG_UP_129__VALUE1_MASK 0x0000ff00L 5397#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x00000008 5398#define MC_IO_DEBUG_UP_129__VALUE2_MASK 0x00ff0000L 5399#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x00000010 5400#define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000L 5401#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x00000018 5402#define MC_IO_DEBUG_UP_12__VALUE0_MASK 0x000000ffL 5403#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x00000000 5404#define MC_IO_DEBUG_UP_12__VALUE1_MASK 0x0000ff00L 5405#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x00000008 5406#define MC_IO_DEBUG_UP_12__VALUE2_MASK 0x00ff0000L 5407#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x00000010 5408#define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000L 5409#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x00000018 5410#define MC_IO_DEBUG_UP_130__VALUE0_MASK 0x000000ffL 5411#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x00000000 5412#define MC_IO_DEBUG_UP_130__VALUE1_MASK 0x0000ff00L 5413#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x00000008 5414#define MC_IO_DEBUG_UP_130__VALUE2_MASK 0x00ff0000L 5415#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x00000010 5416#define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000L 5417#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x00000018 5418#define MC_IO_DEBUG_UP_131__VALUE0_MASK 0x000000ffL 5419#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x00000000 5420#define MC_IO_DEBUG_UP_131__VALUE1_MASK 0x0000ff00L 5421#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x00000008 5422#define MC_IO_DEBUG_UP_131__VALUE2_MASK 0x00ff0000L 5423#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x00000010 5424#define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000L 5425#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x00000018 5426#define MC_IO_DEBUG_UP_132__VALUE0_MASK 0x000000ffL 5427#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x00000000 5428#define MC_IO_DEBUG_UP_132__VALUE1_MASK 0x0000ff00L 5429#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x00000008 5430#define MC_IO_DEBUG_UP_132__VALUE2_MASK 0x00ff0000L 5431#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x00000010 5432#define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000L 5433#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x00000018 5434#define MC_IO_DEBUG_UP_133__VALUE0_MASK 0x000000ffL 5435#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x00000000 5436#define MC_IO_DEBUG_UP_133__VALUE1_MASK 0x0000ff00L 5437#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x00000008 5438#define MC_IO_DEBUG_UP_133__VALUE2_MASK 0x00ff0000L 5439#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x00000010 5440#define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000L 5441#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x00000018 5442#define MC_IO_DEBUG_UP_134__VALUE0_MASK 0x000000ffL 5443#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x00000000 5444#define MC_IO_DEBUG_UP_134__VALUE1_MASK 0x0000ff00L 5445#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x00000008 5446#define MC_IO_DEBUG_UP_134__VALUE2_MASK 0x00ff0000L 5447#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x00000010 5448#define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000L 5449#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x00000018 5450#define MC_IO_DEBUG_UP_135__VALUE0_MASK 0x000000ffL 5451#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x00000000 5452#define MC_IO_DEBUG_UP_135__VALUE1_MASK 0x0000ff00L 5453#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x00000008 5454#define MC_IO_DEBUG_UP_135__VALUE2_MASK 0x00ff0000L 5455#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x00000010 5456#define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000L 5457#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x00000018 5458#define MC_IO_DEBUG_UP_136__VALUE0_MASK 0x000000ffL 5459#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x00000000 5460#define MC_IO_DEBUG_UP_136__VALUE1_MASK 0x0000ff00L 5461#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x00000008 5462#define MC_IO_DEBUG_UP_136__VALUE2_MASK 0x00ff0000L 5463#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x00000010 5464#define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000L 5465#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x00000018 5466#define MC_IO_DEBUG_UP_137__VALUE0_MASK 0x000000ffL 5467#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x00000000 5468#define MC_IO_DEBUG_UP_137__VALUE1_MASK 0x0000ff00L 5469#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x00000008 5470#define MC_IO_DEBUG_UP_137__VALUE2_MASK 0x00ff0000L 5471#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x00000010 5472#define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000L 5473#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x00000018 5474#define MC_IO_DEBUG_UP_138__VALUE0_MASK 0x000000ffL 5475#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x00000000 5476#define MC_IO_DEBUG_UP_138__VALUE1_MASK 0x0000ff00L 5477#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x00000008 5478#define MC_IO_DEBUG_UP_138__VALUE2_MASK 0x00ff0000L 5479#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x00000010 5480#define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000L 5481#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x00000018 5482#define MC_IO_DEBUG_UP_139__VALUE0_MASK 0x000000ffL 5483#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x00000000 5484#define MC_IO_DEBUG_UP_139__VALUE1_MASK 0x0000ff00L 5485#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x00000008 5486#define MC_IO_DEBUG_UP_139__VALUE2_MASK 0x00ff0000L 5487#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x00000010 5488#define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000L 5489#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x00000018 5490#define MC_IO_DEBUG_UP_13__VALUE0_MASK 0x000000ffL 5491#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x00000000 5492#define MC_IO_DEBUG_UP_13__VALUE1_MASK 0x0000ff00L 5493#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x00000008 5494#define MC_IO_DEBUG_UP_13__VALUE2_MASK 0x00ff0000L 5495#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x00000010 5496#define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000L 5497#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x00000018 5498#define MC_IO_DEBUG_UP_140__VALUE0_MASK 0x000000ffL 5499#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x00000000 5500#define MC_IO_DEBUG_UP_140__VALUE1_MASK 0x0000ff00L 5501#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x00000008 5502#define MC_IO_DEBUG_UP_140__VALUE2_MASK 0x00ff0000L 5503#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x00000010 5504#define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000L 5505#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x00000018 5506#define MC_IO_DEBUG_UP_141__VALUE0_MASK 0x000000ffL 5507#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x00000000 5508#define MC_IO_DEBUG_UP_141__VALUE1_MASK 0x0000ff00L 5509#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x00000008 5510#define MC_IO_DEBUG_UP_141__VALUE2_MASK 0x00ff0000L 5511#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x00000010 5512#define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000L 5513#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x00000018 5514#define MC_IO_DEBUG_UP_142__VALUE0_MASK 0x000000ffL 5515#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x00000000 5516#define MC_IO_DEBUG_UP_142__VALUE1_MASK 0x0000ff00L 5517#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x00000008 5518#define MC_IO_DEBUG_UP_142__VALUE2_MASK 0x00ff0000L 5519#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x00000010 5520#define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000L 5521#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x00000018 5522#define MC_IO_DEBUG_UP_143__VALUE0_MASK 0x000000ffL 5523#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x00000000 5524#define MC_IO_DEBUG_UP_143__VALUE1_MASK 0x0000ff00L 5525#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x00000008 5526#define MC_IO_DEBUG_UP_143__VALUE2_MASK 0x00ff0000L 5527#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x00000010 5528#define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000L 5529#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x00000018 5530#define MC_IO_DEBUG_UP_144__VALUE0_MASK 0x000000ffL 5531#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x00000000 5532#define MC_IO_DEBUG_UP_144__VALUE1_MASK 0x0000ff00L 5533#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x00000008 5534#define MC_IO_DEBUG_UP_144__VALUE2_MASK 0x00ff0000L 5535#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x00000010 5536#define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000L 5537#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x00000018 5538#define MC_IO_DEBUG_UP_145__VALUE0_MASK 0x000000ffL 5539#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x00000000 5540#define MC_IO_DEBUG_UP_145__VALUE1_MASK 0x0000ff00L 5541#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x00000008 5542#define MC_IO_DEBUG_UP_145__VALUE2_MASK 0x00ff0000L 5543#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x00000010 5544#define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000L 5545#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x00000018 5546#define MC_IO_DEBUG_UP_146__VALUE0_MASK 0x000000ffL 5547#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x00000000 5548#define MC_IO_DEBUG_UP_146__VALUE1_MASK 0x0000ff00L 5549#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x00000008 5550#define MC_IO_DEBUG_UP_146__VALUE2_MASK 0x00ff0000L 5551#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x00000010 5552#define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000L 5553#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x00000018 5554#define MC_IO_DEBUG_UP_147__VALUE0_MASK 0x000000ffL 5555#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x00000000 5556#define MC_IO_DEBUG_UP_147__VALUE1_MASK 0x0000ff00L 5557#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x00000008 5558#define MC_IO_DEBUG_UP_147__VALUE2_MASK 0x00ff0000L 5559#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x00000010 5560#define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000L 5561#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x00000018 5562#define MC_IO_DEBUG_UP_148__VALUE0_MASK 0x000000ffL 5563#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x00000000 5564#define MC_IO_DEBUG_UP_148__VALUE1_MASK 0x0000ff00L 5565#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x00000008 5566#define MC_IO_DEBUG_UP_148__VALUE2_MASK 0x00ff0000L 5567#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x00000010 5568#define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000L 5569#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x00000018 5570#define MC_IO_DEBUG_UP_149__VALUE0_MASK 0x000000ffL 5571#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x00000000 5572#define MC_IO_DEBUG_UP_149__VALUE1_MASK 0x0000ff00L 5573#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x00000008 5574#define MC_IO_DEBUG_UP_149__VALUE2_MASK 0x00ff0000L 5575#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x00000010 5576#define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000L 5577#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x00000018 5578#define MC_IO_DEBUG_UP_14__VALUE0_MASK 0x000000ffL 5579#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x00000000 5580#define MC_IO_DEBUG_UP_14__VALUE1_MASK 0x0000ff00L 5581#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x00000008 5582#define MC_IO_DEBUG_UP_14__VALUE2_MASK 0x00ff0000L 5583#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x00000010 5584#define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000L 5585#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x00000018 5586#define MC_IO_DEBUG_UP_150__VALUE0_MASK 0x000000ffL 5587#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x00000000 5588#define MC_IO_DEBUG_UP_150__VALUE1_MASK 0x0000ff00L 5589#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x00000008 5590#define MC_IO_DEBUG_UP_150__VALUE2_MASK 0x00ff0000L 5591#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x00000010 5592#define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000L 5593#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x00000018 5594#define MC_IO_DEBUG_UP_151__VALUE0_MASK 0x000000ffL 5595#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x00000000 5596#define MC_IO_DEBUG_UP_151__VALUE1_MASK 0x0000ff00L 5597#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x00000008 5598#define MC_IO_DEBUG_UP_151__VALUE2_MASK 0x00ff0000L 5599#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x00000010 5600#define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000L 5601#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x00000018 5602#define MC_IO_DEBUG_UP_152__VALUE0_MASK 0x000000ffL 5603#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x00000000 5604#define MC_IO_DEBUG_UP_152__VALUE1_MASK 0x0000ff00L 5605#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x00000008 5606#define MC_IO_DEBUG_UP_152__VALUE2_MASK 0x00ff0000L 5607#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x00000010 5608#define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000L 5609#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x00000018 5610#define MC_IO_DEBUG_UP_153__VALUE0_MASK 0x000000ffL 5611#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x00000000 5612#define MC_IO_DEBUG_UP_153__VALUE1_MASK 0x0000ff00L 5613#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x00000008 5614#define MC_IO_DEBUG_UP_153__VALUE2_MASK 0x00ff0000L 5615#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x00000010 5616#define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000L 5617#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x00000018 5618#define MC_IO_DEBUG_UP_154__VALUE0_MASK 0x000000ffL 5619#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x00000000 5620#define MC_IO_DEBUG_UP_154__VALUE1_MASK 0x0000ff00L 5621#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x00000008 5622#define MC_IO_DEBUG_UP_154__VALUE2_MASK 0x00ff0000L 5623#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x00000010 5624#define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000L 5625#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x00000018 5626#define MC_IO_DEBUG_UP_155__VALUE0_MASK 0x000000ffL 5627#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x00000000 5628#define MC_IO_DEBUG_UP_155__VALUE1_MASK 0x0000ff00L 5629#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x00000008 5630#define MC_IO_DEBUG_UP_155__VALUE2_MASK 0x00ff0000L 5631#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x00000010 5632#define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000L 5633#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x00000018 5634#define MC_IO_DEBUG_UP_156__VALUE0_MASK 0x000000ffL 5635#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x00000000 5636#define MC_IO_DEBUG_UP_156__VALUE1_MASK 0x0000ff00L 5637#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x00000008 5638#define MC_IO_DEBUG_UP_156__VALUE2_MASK 0x00ff0000L 5639#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x00000010 5640#define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000L 5641#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x00000018 5642#define MC_IO_DEBUG_UP_157__VALUE0_MASK 0x000000ffL 5643#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x00000000 5644#define MC_IO_DEBUG_UP_157__VALUE1_MASK 0x0000ff00L 5645#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x00000008 5646#define MC_IO_DEBUG_UP_157__VALUE2_MASK 0x00ff0000L 5647#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x00000010 5648#define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000L 5649#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x00000018 5650#define MC_IO_DEBUG_UP_158__VALUE0_MASK 0x000000ffL 5651#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x00000000 5652#define MC_IO_DEBUG_UP_158__VALUE1_MASK 0x0000ff00L 5653#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x00000008 5654#define MC_IO_DEBUG_UP_158__VALUE2_MASK 0x00ff0000L 5655#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x00000010 5656#define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000L 5657#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x00000018 5658#define MC_IO_DEBUG_UP_159__VALUE0_MASK 0x000000ffL 5659#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x00000000 5660#define MC_IO_DEBUG_UP_159__VALUE1_MASK 0x0000ff00L 5661#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x00000008 5662#define MC_IO_DEBUG_UP_159__VALUE2_MASK 0x00ff0000L 5663#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x00000010 5664#define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000L 5665#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x00000018 5666#define MC_IO_DEBUG_UP_15__VALUE0_MASK 0x000000ffL 5667#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x00000000 5668#define MC_IO_DEBUG_UP_15__VALUE1_MASK 0x0000ff00L 5669#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x00000008 5670#define MC_IO_DEBUG_UP_15__VALUE2_MASK 0x00ff0000L 5671#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x00000010 5672#define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000L 5673#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x00000018 5674#define MC_IO_DEBUG_UP_16__VALUE0_MASK 0x000000ffL 5675#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x00000000 5676#define MC_IO_DEBUG_UP_16__VALUE1_MASK 0x0000ff00L 5677#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x00000008 5678#define MC_IO_DEBUG_UP_16__VALUE2_MASK 0x00ff0000L 5679#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x00000010 5680#define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000L 5681#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x00000018 5682#define MC_IO_DEBUG_UP_17__VALUE0_MASK 0x000000ffL 5683#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x00000000 5684#define MC_IO_DEBUG_UP_17__VALUE1_MASK 0x0000ff00L 5685#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x00000008 5686#define MC_IO_DEBUG_UP_17__VALUE2_MASK 0x00ff0000L 5687#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x00000010 5688#define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000L 5689#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x00000018 5690#define MC_IO_DEBUG_UP_18__VALUE0_MASK 0x000000ffL 5691#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x00000000 5692#define MC_IO_DEBUG_UP_18__VALUE1_MASK 0x0000ff00L 5693#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x00000008 5694#define MC_IO_DEBUG_UP_18__VALUE2_MASK 0x00ff0000L 5695#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x00000010 5696#define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000L 5697#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x00000018 5698#define MC_IO_DEBUG_UP_19__VALUE0_MASK 0x000000ffL 5699#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x00000000 5700#define MC_IO_DEBUG_UP_19__VALUE1_MASK 0x0000ff00L 5701#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x00000008 5702#define MC_IO_DEBUG_UP_19__VALUE2_MASK 0x00ff0000L 5703#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x00000010 5704#define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000L 5705#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x00000018 5706#define MC_IO_DEBUG_UP_1__VALUE0_MASK 0x000000ffL 5707#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x00000000 5708#define MC_IO_DEBUG_UP_1__VALUE1_MASK 0x0000ff00L 5709#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x00000008 5710#define MC_IO_DEBUG_UP_1__VALUE2_MASK 0x00ff0000L 5711#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x00000010 5712#define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000L 5713#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x00000018 5714#define MC_IO_DEBUG_UP_20__VALUE0_MASK 0x000000ffL 5715#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x00000000 5716#define MC_IO_DEBUG_UP_20__VALUE1_MASK 0x0000ff00L 5717#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x00000008 5718#define MC_IO_DEBUG_UP_20__VALUE2_MASK 0x00ff0000L 5719#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x00000010 5720#define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000L 5721#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x00000018 5722#define MC_IO_DEBUG_UP_21__VALUE0_MASK 0x000000ffL 5723#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x00000000 5724#define MC_IO_DEBUG_UP_21__VALUE1_MASK 0x0000ff00L 5725#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x00000008 5726#define MC_IO_DEBUG_UP_21__VALUE2_MASK 0x00ff0000L 5727#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x00000010 5728#define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000L 5729#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x00000018 5730#define MC_IO_DEBUG_UP_22__VALUE0_MASK 0x000000ffL 5731#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x00000000 5732#define MC_IO_DEBUG_UP_22__VALUE1_MASK 0x0000ff00L 5733#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x00000008 5734#define MC_IO_DEBUG_UP_22__VALUE2_MASK 0x00ff0000L 5735#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x00000010 5736#define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000L 5737#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x00000018 5738#define MC_IO_DEBUG_UP_23__VALUE0_MASK 0x000000ffL 5739#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x00000000 5740#define MC_IO_DEBUG_UP_23__VALUE1_MASK 0x0000ff00L 5741#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x00000008 5742#define MC_IO_DEBUG_UP_23__VALUE2_MASK 0x00ff0000L 5743#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x00000010 5744#define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000L 5745#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x00000018 5746#define MC_IO_DEBUG_UP_24__VALUE0_MASK 0x000000ffL 5747#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x00000000 5748#define MC_IO_DEBUG_UP_24__VALUE1_MASK 0x0000ff00L 5749#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x00000008 5750#define MC_IO_DEBUG_UP_24__VALUE2_MASK 0x00ff0000L 5751#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x00000010 5752#define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000L 5753#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x00000018 5754#define MC_IO_DEBUG_UP_25__VALUE0_MASK 0x000000ffL 5755#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x00000000 5756#define MC_IO_DEBUG_UP_25__VALUE1_MASK 0x0000ff00L 5757#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x00000008 5758#define MC_IO_DEBUG_UP_25__VALUE2_MASK 0x00ff0000L 5759#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x00000010 5760#define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000L 5761#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x00000018 5762#define MC_IO_DEBUG_UP_26__VALUE0_MASK 0x000000ffL 5763#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x00000000 5764#define MC_IO_DEBUG_UP_26__VALUE1_MASK 0x0000ff00L 5765#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x00000008 5766#define MC_IO_DEBUG_UP_26__VALUE2_MASK 0x00ff0000L 5767#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x00000010 5768#define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000L 5769#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x00000018 5770#define MC_IO_DEBUG_UP_27__VALUE0_MASK 0x000000ffL 5771#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x00000000 5772#define MC_IO_DEBUG_UP_27__VALUE1_MASK 0x0000ff00L 5773#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x00000008 5774#define MC_IO_DEBUG_UP_27__VALUE2_MASK 0x00ff0000L 5775#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x00000010 5776#define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000L 5777#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x00000018 5778#define MC_IO_DEBUG_UP_28__VALUE0_MASK 0x000000ffL 5779#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x00000000 5780#define MC_IO_DEBUG_UP_28__VALUE1_MASK 0x0000ff00L 5781#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x00000008 5782#define MC_IO_DEBUG_UP_28__VALUE2_MASK 0x00ff0000L 5783#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x00000010 5784#define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000L 5785#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x00000018 5786#define MC_IO_DEBUG_UP_29__VALUE0_MASK 0x000000ffL 5787#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x00000000 5788#define MC_IO_DEBUG_UP_29__VALUE1_MASK 0x0000ff00L 5789#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x00000008 5790#define MC_IO_DEBUG_UP_29__VALUE2_MASK 0x00ff0000L 5791#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x00000010 5792#define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000L 5793#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x00000018 5794#define MC_IO_DEBUG_UP_2__VALUE0_MASK 0x000000ffL 5795#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x00000000 5796#define MC_IO_DEBUG_UP_2__VALUE1_MASK 0x0000ff00L 5797#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x00000008 5798#define MC_IO_DEBUG_UP_2__VALUE2_MASK 0x00ff0000L 5799#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x00000010 5800#define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000L 5801#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x00000018 5802#define MC_IO_DEBUG_UP_30__VALUE0_MASK 0x000000ffL 5803#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x00000000 5804#define MC_IO_DEBUG_UP_30__VALUE1_MASK 0x0000ff00L 5805#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x00000008 5806#define MC_IO_DEBUG_UP_30__VALUE2_MASK 0x00ff0000L 5807#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x00000010 5808#define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000L 5809#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x00000018 5810#define MC_IO_DEBUG_UP_31__VALUE0_MASK 0x000000ffL 5811#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x00000000 5812#define MC_IO_DEBUG_UP_31__VALUE1_MASK 0x0000ff00L 5813#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x00000008 5814#define MC_IO_DEBUG_UP_31__VALUE2_MASK 0x00ff0000L 5815#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x00000010 5816#define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000L 5817#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x00000018 5818#define MC_IO_DEBUG_UP_32__VALUE0_MASK 0x000000ffL 5819#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x00000000 5820#define MC_IO_DEBUG_UP_32__VALUE1_MASK 0x0000ff00L 5821#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x00000008 5822#define MC_IO_DEBUG_UP_32__VALUE2_MASK 0x00ff0000L 5823#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x00000010 5824#define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000L 5825#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x00000018 5826#define MC_IO_DEBUG_UP_33__VALUE0_MASK 0x000000ffL 5827#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x00000000 5828#define MC_IO_DEBUG_UP_33__VALUE1_MASK 0x0000ff00L 5829#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x00000008 5830#define MC_IO_DEBUG_UP_33__VALUE2_MASK 0x00ff0000L 5831#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x00000010 5832#define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000L 5833#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x00000018 5834#define MC_IO_DEBUG_UP_34__VALUE0_MASK 0x000000ffL 5835#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x00000000 5836#define MC_IO_DEBUG_UP_34__VALUE1_MASK 0x0000ff00L 5837#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x00000008 5838#define MC_IO_DEBUG_UP_34__VALUE2_MASK 0x00ff0000L 5839#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x00000010 5840#define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000L 5841#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x00000018 5842#define MC_IO_DEBUG_UP_35__VALUE0_MASK 0x000000ffL 5843#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x00000000 5844#define MC_IO_DEBUG_UP_35__VALUE1_MASK 0x0000ff00L 5845#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x00000008 5846#define MC_IO_DEBUG_UP_35__VALUE2_MASK 0x00ff0000L 5847#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x00000010 5848#define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000L 5849#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x00000018 5850#define MC_IO_DEBUG_UP_36__VALUE0_MASK 0x000000ffL 5851#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x00000000 5852#define MC_IO_DEBUG_UP_36__VALUE1_MASK 0x0000ff00L 5853#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x00000008 5854#define MC_IO_DEBUG_UP_36__VALUE2_MASK 0x00ff0000L 5855#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x00000010 5856#define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000L 5857#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x00000018 5858#define MC_IO_DEBUG_UP_37__VALUE0_MASK 0x000000ffL 5859#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x00000000 5860#define MC_IO_DEBUG_UP_37__VALUE1_MASK 0x0000ff00L 5861#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x00000008 5862#define MC_IO_DEBUG_UP_37__VALUE2_MASK 0x00ff0000L 5863#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x00000010 5864#define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000L 5865#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x00000018 5866#define MC_IO_DEBUG_UP_38__VALUE0_MASK 0x000000ffL 5867#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x00000000 5868#define MC_IO_DEBUG_UP_38__VALUE1_MASK 0x0000ff00L 5869#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x00000008 5870#define MC_IO_DEBUG_UP_38__VALUE2_MASK 0x00ff0000L 5871#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x00000010 5872#define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000L 5873#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x00000018 5874#define MC_IO_DEBUG_UP_39__VALUE0_MASK 0x000000ffL 5875#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x00000000 5876#define MC_IO_DEBUG_UP_39__VALUE1_MASK 0x0000ff00L 5877#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x00000008 5878#define MC_IO_DEBUG_UP_39__VALUE2_MASK 0x00ff0000L 5879#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x00000010 5880#define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000L 5881#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x00000018 5882#define MC_IO_DEBUG_UP_3__VALUE0_MASK 0x000000ffL 5883#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x00000000 5884#define MC_IO_DEBUG_UP_3__VALUE1_MASK 0x0000ff00L 5885#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x00000008 5886#define MC_IO_DEBUG_UP_3__VALUE2_MASK 0x00ff0000L 5887#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x00000010 5888#define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000L 5889#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x00000018 5890#define MC_IO_DEBUG_UP_40__VALUE0_MASK 0x000000ffL 5891#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x00000000 5892#define MC_IO_DEBUG_UP_40__VALUE1_MASK 0x0000ff00L 5893#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x00000008 5894#define MC_IO_DEBUG_UP_40__VALUE2_MASK 0x00ff0000L 5895#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x00000010 5896#define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000L 5897#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x00000018 5898#define MC_IO_DEBUG_UP_41__VALUE0_MASK 0x000000ffL 5899#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x00000000 5900#define MC_IO_DEBUG_UP_41__VALUE1_MASK 0x0000ff00L 5901#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x00000008 5902#define MC_IO_DEBUG_UP_41__VALUE2_MASK 0x00ff0000L 5903#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x00000010 5904#define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000L 5905#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x00000018 5906#define MC_IO_DEBUG_UP_42__VALUE0_MASK 0x000000ffL 5907#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x00000000 5908#define MC_IO_DEBUG_UP_42__VALUE1_MASK 0x0000ff00L 5909#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x00000008 5910#define MC_IO_DEBUG_UP_42__VALUE2_MASK 0x00ff0000L 5911#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x00000010 5912#define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000L 5913#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x00000018 5914#define MC_IO_DEBUG_UP_43__VALUE0_MASK 0x000000ffL 5915#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x00000000 5916#define MC_IO_DEBUG_UP_43__VALUE1_MASK 0x0000ff00L 5917#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x00000008 5918#define MC_IO_DEBUG_UP_43__VALUE2_MASK 0x00ff0000L 5919#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x00000010 5920#define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000L 5921#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x00000018 5922#define MC_IO_DEBUG_UP_44__VALUE0_MASK 0x000000ffL 5923#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x00000000 5924#define MC_IO_DEBUG_UP_44__VALUE1_MASK 0x0000ff00L 5925#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x00000008 5926#define MC_IO_DEBUG_UP_44__VALUE2_MASK 0x00ff0000L 5927#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x00000010 5928#define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000L 5929#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x00000018 5930#define MC_IO_DEBUG_UP_45__VALUE0_MASK 0x000000ffL 5931#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x00000000 5932#define MC_IO_DEBUG_UP_45__VALUE1_MASK 0x0000ff00L 5933#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x00000008 5934#define MC_IO_DEBUG_UP_45__VALUE2_MASK 0x00ff0000L 5935#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x00000010 5936#define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000L 5937#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x00000018 5938#define MC_IO_DEBUG_UP_46__VALUE0_MASK 0x000000ffL 5939#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x00000000 5940#define MC_IO_DEBUG_UP_46__VALUE1_MASK 0x0000ff00L 5941#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x00000008 5942#define MC_IO_DEBUG_UP_46__VALUE2_MASK 0x00ff0000L 5943#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x00000010 5944#define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000L 5945#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x00000018 5946#define MC_IO_DEBUG_UP_47__VALUE0_MASK 0x000000ffL 5947#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x00000000 5948#define MC_IO_DEBUG_UP_47__VALUE1_MASK 0x0000ff00L 5949#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x00000008 5950#define MC_IO_DEBUG_UP_47__VALUE2_MASK 0x00ff0000L 5951#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x00000010 5952#define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000L 5953#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x00000018 5954#define MC_IO_DEBUG_UP_48__VALUE0_MASK 0x000000ffL 5955#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x00000000 5956#define MC_IO_DEBUG_UP_48__VALUE1_MASK 0x0000ff00L 5957#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x00000008 5958#define MC_IO_DEBUG_UP_48__VALUE2_MASK 0x00ff0000L 5959#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x00000010 5960#define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000L 5961#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x00000018 5962#define MC_IO_DEBUG_UP_49__VALUE0_MASK 0x000000ffL 5963#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x00000000 5964#define MC_IO_DEBUG_UP_49__VALUE1_MASK 0x0000ff00L 5965#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x00000008 5966#define MC_IO_DEBUG_UP_49__VALUE2_MASK 0x00ff0000L 5967#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x00000010 5968#define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000L 5969#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x00000018 5970#define MC_IO_DEBUG_UP_4__VALUE0_MASK 0x000000ffL 5971#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x00000000 5972#define MC_IO_DEBUG_UP_4__VALUE1_MASK 0x0000ff00L 5973#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x00000008 5974#define MC_IO_DEBUG_UP_4__VALUE2_MASK 0x00ff0000L 5975#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x00000010 5976#define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000L 5977#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x00000018 5978#define MC_IO_DEBUG_UP_50__VALUE0_MASK 0x000000ffL 5979#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x00000000 5980#define MC_IO_DEBUG_UP_50__VALUE1_MASK 0x0000ff00L 5981#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x00000008 5982#define MC_IO_DEBUG_UP_50__VALUE2_MASK 0x00ff0000L 5983#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x00000010 5984#define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000L 5985#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x00000018 5986#define MC_IO_DEBUG_UP_51__VALUE0_MASK 0x000000ffL 5987#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x00000000 5988#define MC_IO_DEBUG_UP_51__VALUE1_MASK 0x0000ff00L 5989#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x00000008 5990#define MC_IO_DEBUG_UP_51__VALUE2_MASK 0x00ff0000L 5991#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x00000010 5992#define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000L 5993#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x00000018 5994#define MC_IO_DEBUG_UP_52__VALUE0_MASK 0x000000ffL 5995#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x00000000 5996#define MC_IO_DEBUG_UP_52__VALUE1_MASK 0x0000ff00L 5997#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x00000008 5998#define MC_IO_DEBUG_UP_52__VALUE2_MASK 0x00ff0000L 5999#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x00000010 6000#define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000L 6001#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x00000018 6002#define MC_IO_DEBUG_UP_53__VALUE0_MASK 0x000000ffL 6003#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x00000000 6004#define MC_IO_DEBUG_UP_53__VALUE1_MASK 0x0000ff00L 6005#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x00000008 6006#define MC_IO_DEBUG_UP_53__VALUE2_MASK 0x00ff0000L 6007#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x00000010 6008#define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000L 6009#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x00000018 6010#define MC_IO_DEBUG_UP_54__VALUE0_MASK 0x000000ffL 6011#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x00000000 6012#define MC_IO_DEBUG_UP_54__VALUE1_MASK 0x0000ff00L 6013#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x00000008 6014#define MC_IO_DEBUG_UP_54__VALUE2_MASK 0x00ff0000L 6015#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x00000010 6016#define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000L 6017#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x00000018 6018#define MC_IO_DEBUG_UP_55__VALUE0_MASK 0x000000ffL 6019#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x00000000 6020#define MC_IO_DEBUG_UP_55__VALUE1_MASK 0x0000ff00L 6021#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x00000008 6022#define MC_IO_DEBUG_UP_55__VALUE2_MASK 0x00ff0000L 6023#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x00000010 6024#define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000L 6025#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x00000018 6026#define MC_IO_DEBUG_UP_56__VALUE0_MASK 0x000000ffL 6027#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x00000000 6028#define MC_IO_DEBUG_UP_56__VALUE1_MASK 0x0000ff00L 6029#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x00000008 6030#define MC_IO_DEBUG_UP_56__VALUE2_MASK 0x00ff0000L 6031#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x00000010 6032#define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000L 6033#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x00000018 6034#define MC_IO_DEBUG_UP_57__VALUE0_MASK 0x000000ffL 6035#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x00000000 6036#define MC_IO_DEBUG_UP_57__VALUE1_MASK 0x0000ff00L 6037#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x00000008 6038#define MC_IO_DEBUG_UP_57__VALUE2_MASK 0x00ff0000L 6039#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x00000010 6040#define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000L 6041#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x00000018 6042#define MC_IO_DEBUG_UP_58__VALUE0_MASK 0x000000ffL 6043#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x00000000 6044#define MC_IO_DEBUG_UP_58__VALUE1_MASK 0x0000ff00L 6045#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x00000008 6046#define MC_IO_DEBUG_UP_58__VALUE2_MASK 0x00ff0000L 6047#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x00000010 6048#define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000L 6049#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x00000018 6050#define MC_IO_DEBUG_UP_59__VALUE0_MASK 0x000000ffL 6051#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x00000000 6052#define MC_IO_DEBUG_UP_59__VALUE1_MASK 0x0000ff00L 6053#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x00000008 6054#define MC_IO_DEBUG_UP_59__VALUE2_MASK 0x00ff0000L 6055#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x00000010 6056#define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000L 6057#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x00000018 6058#define MC_IO_DEBUG_UP_5__VALUE0_MASK 0x000000ffL 6059#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x00000000 6060#define MC_IO_DEBUG_UP_5__VALUE1_MASK 0x0000ff00L 6061#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x00000008 6062#define MC_IO_DEBUG_UP_5__VALUE2_MASK 0x00ff0000L 6063#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x00000010 6064#define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000L 6065#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x00000018 6066#define MC_IO_DEBUG_UP_60__VALUE0_MASK 0x000000ffL 6067#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x00000000 6068#define MC_IO_DEBUG_UP_60__VALUE1_MASK 0x0000ff00L 6069#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x00000008 6070#define MC_IO_DEBUG_UP_60__VALUE2_MASK 0x00ff0000L 6071#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x00000010 6072#define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000L 6073#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x00000018 6074#define MC_IO_DEBUG_UP_61__VALUE0_MASK 0x000000ffL 6075#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x00000000 6076#define MC_IO_DEBUG_UP_61__VALUE1_MASK 0x0000ff00L 6077#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x00000008 6078#define MC_IO_DEBUG_UP_61__VALUE2_MASK 0x00ff0000L 6079#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x00000010 6080#define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000L 6081#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x00000018 6082#define MC_IO_DEBUG_UP_62__VALUE0_MASK 0x000000ffL 6083#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x00000000 6084#define MC_IO_DEBUG_UP_62__VALUE1_MASK 0x0000ff00L 6085#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x00000008 6086#define MC_IO_DEBUG_UP_62__VALUE2_MASK 0x00ff0000L 6087#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x00000010 6088#define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000L 6089#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x00000018 6090#define MC_IO_DEBUG_UP_63__VALUE0_MASK 0x000000ffL 6091#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x00000000 6092#define MC_IO_DEBUG_UP_63__VALUE1_MASK 0x0000ff00L 6093#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x00000008 6094#define MC_IO_DEBUG_UP_63__VALUE2_MASK 0x00ff0000L 6095#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x00000010 6096#define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000L 6097#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x00000018 6098#define MC_IO_DEBUG_UP_64__VALUE0_MASK 0x000000ffL 6099#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x00000000 6100#define MC_IO_DEBUG_UP_64__VALUE1_MASK 0x0000ff00L 6101#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x00000008 6102#define MC_IO_DEBUG_UP_64__VALUE2_MASK 0x00ff0000L 6103#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x00000010 6104#define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000L 6105#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x00000018 6106#define MC_IO_DEBUG_UP_65__VALUE0_MASK 0x000000ffL 6107#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x00000000 6108#define MC_IO_DEBUG_UP_65__VALUE1_MASK 0x0000ff00L 6109#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x00000008 6110#define MC_IO_DEBUG_UP_65__VALUE2_MASK 0x00ff0000L 6111#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x00000010 6112#define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000L 6113#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x00000018 6114#define MC_IO_DEBUG_UP_66__VALUE0_MASK 0x000000ffL 6115#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x00000000 6116#define MC_IO_DEBUG_UP_66__VALUE1_MASK 0x0000ff00L 6117#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x00000008 6118#define MC_IO_DEBUG_UP_66__VALUE2_MASK 0x00ff0000L 6119#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x00000010 6120#define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000L 6121#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x00000018 6122#define MC_IO_DEBUG_UP_67__VALUE0_MASK 0x000000ffL 6123#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x00000000 6124#define MC_IO_DEBUG_UP_67__VALUE1_MASK 0x0000ff00L 6125#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x00000008 6126#define MC_IO_DEBUG_UP_67__VALUE2_MASK 0x00ff0000L 6127#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x00000010 6128#define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000L 6129#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x00000018 6130#define MC_IO_DEBUG_UP_68__VALUE0_MASK 0x000000ffL 6131#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x00000000 6132#define MC_IO_DEBUG_UP_68__VALUE1_MASK 0x0000ff00L 6133#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x00000008 6134#define MC_IO_DEBUG_UP_68__VALUE2_MASK 0x00ff0000L 6135#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x00000010 6136#define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000L 6137#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x00000018 6138#define MC_IO_DEBUG_UP_69__VALUE0_MASK 0x000000ffL 6139#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x00000000 6140#define MC_IO_DEBUG_UP_69__VALUE1_MASK 0x0000ff00L 6141#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x00000008 6142#define MC_IO_DEBUG_UP_69__VALUE2_MASK 0x00ff0000L 6143#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x00000010 6144#define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000L 6145#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x00000018 6146#define MC_IO_DEBUG_UP_6__VALUE0_MASK 0x000000ffL 6147#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x00000000 6148#define MC_IO_DEBUG_UP_6__VALUE1_MASK 0x0000ff00L 6149#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x00000008 6150#define MC_IO_DEBUG_UP_6__VALUE2_MASK 0x00ff0000L 6151#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x00000010 6152#define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000L 6153#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x00000018 6154#define MC_IO_DEBUG_UP_70__VALUE0_MASK 0x000000ffL 6155#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x00000000 6156#define MC_IO_DEBUG_UP_70__VALUE1_MASK 0x0000ff00L 6157#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x00000008 6158#define MC_IO_DEBUG_UP_70__VALUE2_MASK 0x00ff0000L 6159#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x00000010 6160#define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000L 6161#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x00000018 6162#define MC_IO_DEBUG_UP_71__VALUE0_MASK 0x000000ffL 6163#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x00000000 6164#define MC_IO_DEBUG_UP_71__VALUE1_MASK 0x0000ff00L 6165#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x00000008 6166#define MC_IO_DEBUG_UP_71__VALUE2_MASK 0x00ff0000L 6167#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x00000010 6168#define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000L 6169#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x00000018 6170#define MC_IO_DEBUG_UP_72__VALUE0_MASK 0x000000ffL 6171#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x00000000 6172#define MC_IO_DEBUG_UP_72__VALUE1_MASK 0x0000ff00L 6173#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x00000008 6174#define MC_IO_DEBUG_UP_72__VALUE2_MASK 0x00ff0000L 6175#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x00000010 6176#define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000L 6177#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x00000018 6178#define MC_IO_DEBUG_UP_73__VALUE0_MASK 0x000000ffL 6179#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x00000000 6180#define MC_IO_DEBUG_UP_73__VALUE1_MASK 0x0000ff00L 6181#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x00000008 6182#define MC_IO_DEBUG_UP_73__VALUE2_MASK 0x00ff0000L 6183#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x00000010 6184#define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000L 6185#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x00000018 6186#define MC_IO_DEBUG_UP_74__VALUE0_MASK 0x000000ffL 6187#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x00000000 6188#define MC_IO_DEBUG_UP_74__VALUE1_MASK 0x0000ff00L 6189#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x00000008 6190#define MC_IO_DEBUG_UP_74__VALUE2_MASK 0x00ff0000L 6191#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x00000010 6192#define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000L 6193#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x00000018 6194#define MC_IO_DEBUG_UP_75__VALUE0_MASK 0x000000ffL 6195#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x00000000 6196#define MC_IO_DEBUG_UP_75__VALUE1_MASK 0x0000ff00L 6197#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x00000008 6198#define MC_IO_DEBUG_UP_75__VALUE2_MASK 0x00ff0000L 6199#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x00000010 6200#define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000L 6201#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x00000018 6202#define MC_IO_DEBUG_UP_76__VALUE0_MASK 0x000000ffL 6203#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x00000000 6204#define MC_IO_DEBUG_UP_76__VALUE1_MASK 0x0000ff00L 6205#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x00000008 6206#define MC_IO_DEBUG_UP_76__VALUE2_MASK 0x00ff0000L 6207#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x00000010 6208#define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000L 6209#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x00000018 6210#define MC_IO_DEBUG_UP_77__VALUE0_MASK 0x000000ffL 6211#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x00000000 6212#define MC_IO_DEBUG_UP_77__VALUE1_MASK 0x0000ff00L 6213#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x00000008 6214#define MC_IO_DEBUG_UP_77__VALUE2_MASK 0x00ff0000L 6215#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x00000010 6216#define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000L 6217#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x00000018 6218#define MC_IO_DEBUG_UP_78__VALUE0_MASK 0x000000ffL 6219#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x00000000 6220#define MC_IO_DEBUG_UP_78__VALUE1_MASK 0x0000ff00L 6221#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x00000008 6222#define MC_IO_DEBUG_UP_78__VALUE2_MASK 0x00ff0000L 6223#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x00000010 6224#define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000L 6225#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x00000018 6226#define MC_IO_DEBUG_UP_79__VALUE0_MASK 0x000000ffL 6227#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x00000000 6228#define MC_IO_DEBUG_UP_79__VALUE1_MASK 0x0000ff00L 6229#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x00000008 6230#define MC_IO_DEBUG_UP_79__VALUE2_MASK 0x00ff0000L 6231#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x00000010 6232#define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000L 6233#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x00000018 6234#define MC_IO_DEBUG_UP_7__VALUE0_MASK 0x000000ffL 6235#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x00000000 6236#define MC_IO_DEBUG_UP_7__VALUE1_MASK 0x0000ff00L 6237#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x00000008 6238#define MC_IO_DEBUG_UP_7__VALUE2_MASK 0x00ff0000L 6239#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x00000010 6240#define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000L 6241#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x00000018 6242#define MC_IO_DEBUG_UP_80__VALUE0_MASK 0x000000ffL 6243#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x00000000 6244#define MC_IO_DEBUG_UP_80__VALUE1_MASK 0x0000ff00L 6245#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x00000008 6246#define MC_IO_DEBUG_UP_80__VALUE2_MASK 0x00ff0000L 6247#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x00000010 6248#define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000L 6249#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x00000018 6250#define MC_IO_DEBUG_UP_81__VALUE0_MASK 0x000000ffL 6251#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x00000000 6252#define MC_IO_DEBUG_UP_81__VALUE1_MASK 0x0000ff00L 6253#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x00000008 6254#define MC_IO_DEBUG_UP_81__VALUE2_MASK 0x00ff0000L 6255#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x00000010 6256#define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000L 6257#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x00000018 6258#define MC_IO_DEBUG_UP_82__VALUE0_MASK 0x000000ffL 6259#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x00000000 6260#define MC_IO_DEBUG_UP_82__VALUE1_MASK 0x0000ff00L 6261#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x00000008 6262#define MC_IO_DEBUG_UP_82__VALUE2_MASK 0x00ff0000L 6263#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x00000010 6264#define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000L 6265#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x00000018 6266#define MC_IO_DEBUG_UP_83__VALUE0_MASK 0x000000ffL 6267#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x00000000 6268#define MC_IO_DEBUG_UP_83__VALUE1_MASK 0x0000ff00L 6269#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x00000008 6270#define MC_IO_DEBUG_UP_83__VALUE2_MASK 0x00ff0000L 6271#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x00000010 6272#define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000L 6273#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x00000018 6274#define MC_IO_DEBUG_UP_84__VALUE0_MASK 0x000000ffL 6275#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x00000000 6276#define MC_IO_DEBUG_UP_84__VALUE1_MASK 0x0000ff00L 6277#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x00000008 6278#define MC_IO_DEBUG_UP_84__VALUE2_MASK 0x00ff0000L 6279#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x00000010 6280#define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000L 6281#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x00000018 6282#define MC_IO_DEBUG_UP_85__VALUE0_MASK 0x000000ffL 6283#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x00000000 6284#define MC_IO_DEBUG_UP_85__VALUE1_MASK 0x0000ff00L 6285#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x00000008 6286#define MC_IO_DEBUG_UP_85__VALUE2_MASK 0x00ff0000L 6287#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x00000010 6288#define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000L 6289#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x00000018 6290#define MC_IO_DEBUG_UP_86__VALUE0_MASK 0x000000ffL 6291#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x00000000 6292#define MC_IO_DEBUG_UP_86__VALUE1_MASK 0x0000ff00L 6293#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x00000008 6294#define MC_IO_DEBUG_UP_86__VALUE2_MASK 0x00ff0000L 6295#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x00000010 6296#define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000L 6297#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x00000018 6298#define MC_IO_DEBUG_UP_87__VALUE0_MASK 0x000000ffL 6299#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x00000000 6300#define MC_IO_DEBUG_UP_87__VALUE1_MASK 0x0000ff00L 6301#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x00000008 6302#define MC_IO_DEBUG_UP_87__VALUE2_MASK 0x00ff0000L 6303#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x00000010 6304#define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000L 6305#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x00000018 6306#define MC_IO_DEBUG_UP_88__VALUE0_MASK 0x000000ffL 6307#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x00000000 6308#define MC_IO_DEBUG_UP_88__VALUE1_MASK 0x0000ff00L 6309#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x00000008 6310#define MC_IO_DEBUG_UP_88__VALUE2_MASK 0x00ff0000L 6311#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x00000010 6312#define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000L 6313#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x00000018 6314#define MC_IO_DEBUG_UP_89__VALUE0_MASK 0x000000ffL 6315#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x00000000 6316#define MC_IO_DEBUG_UP_89__VALUE1_MASK 0x0000ff00L 6317#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x00000008 6318#define MC_IO_DEBUG_UP_89__VALUE2_MASK 0x00ff0000L 6319#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x00000010 6320#define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000L 6321#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x00000018 6322#define MC_IO_DEBUG_UP_8__VALUE0_MASK 0x000000ffL 6323#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x00000000 6324#define MC_IO_DEBUG_UP_8__VALUE1_MASK 0x0000ff00L 6325#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x00000008 6326#define MC_IO_DEBUG_UP_8__VALUE2_MASK 0x00ff0000L 6327#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x00000010 6328#define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000L 6329#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x00000018 6330#define MC_IO_DEBUG_UP_90__VALUE0_MASK 0x000000ffL 6331#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x00000000 6332#define MC_IO_DEBUG_UP_90__VALUE1_MASK 0x0000ff00L 6333#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x00000008 6334#define MC_IO_DEBUG_UP_90__VALUE2_MASK 0x00ff0000L 6335#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x00000010 6336#define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000L 6337#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x00000018 6338#define MC_IO_DEBUG_UP_91__VALUE0_MASK 0x000000ffL 6339#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x00000000 6340#define MC_IO_DEBUG_UP_91__VALUE1_MASK 0x0000ff00L 6341#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x00000008 6342#define MC_IO_DEBUG_UP_91__VALUE2_MASK 0x00ff0000L 6343#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x00000010 6344#define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000L 6345#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x00000018 6346#define MC_IO_DEBUG_UP_92__VALUE0_MASK 0x000000ffL 6347#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x00000000 6348#define MC_IO_DEBUG_UP_92__VALUE1_MASK 0x0000ff00L 6349#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x00000008 6350#define MC_IO_DEBUG_UP_92__VALUE2_MASK 0x00ff0000L 6351#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x00000010 6352#define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000L 6353#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x00000018 6354#define MC_IO_DEBUG_UP_93__VALUE0_MASK 0x000000ffL 6355#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x00000000 6356#define MC_IO_DEBUG_UP_93__VALUE1_MASK 0x0000ff00L 6357#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x00000008 6358#define MC_IO_DEBUG_UP_93__VALUE2_MASK 0x00ff0000L 6359#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x00000010 6360#define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000L 6361#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x00000018 6362#define MC_IO_DEBUG_UP_94__VALUE0_MASK 0x000000ffL 6363#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x00000000 6364#define MC_IO_DEBUG_UP_94__VALUE1_MASK 0x0000ff00L 6365#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x00000008 6366#define MC_IO_DEBUG_UP_94__VALUE2_MASK 0x00ff0000L 6367#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x00000010 6368#define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000L 6369#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x00000018 6370#define MC_IO_DEBUG_UP_95__VALUE0_MASK 0x000000ffL 6371#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x00000000 6372#define MC_IO_DEBUG_UP_95__VALUE1_MASK 0x0000ff00L 6373#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x00000008 6374#define MC_IO_DEBUG_UP_95__VALUE2_MASK 0x00ff0000L 6375#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x00000010 6376#define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000L 6377#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x00000018 6378#define MC_IO_DEBUG_UP_96__VALUE0_MASK 0x000000ffL 6379#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x00000000 6380#define MC_IO_DEBUG_UP_96__VALUE1_MASK 0x0000ff00L 6381#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x00000008 6382#define MC_IO_DEBUG_UP_96__VALUE2_MASK 0x00ff0000L 6383#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x00000010 6384#define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000L 6385#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x00000018 6386#define MC_IO_DEBUG_UP_97__VALUE0_MASK 0x000000ffL 6387#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x00000000 6388#define MC_IO_DEBUG_UP_97__VALUE1_MASK 0x0000ff00L 6389#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x00000008 6390#define MC_IO_DEBUG_UP_97__VALUE2_MASK 0x00ff0000L 6391#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x00000010 6392#define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000L 6393#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x00000018 6394#define MC_IO_DEBUG_UP_98__VALUE0_MASK 0x000000ffL 6395#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x00000000 6396#define MC_IO_DEBUG_UP_98__VALUE1_MASK 0x0000ff00L 6397#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x00000008 6398#define MC_IO_DEBUG_UP_98__VALUE2_MASK 0x00ff0000L 6399#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x00000010 6400#define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000L 6401#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x00000018 6402#define MC_IO_DEBUG_UP_99__VALUE0_MASK 0x000000ffL 6403#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x00000000 6404#define MC_IO_DEBUG_UP_99__VALUE1_MASK 0x0000ff00L 6405#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x00000008 6406#define MC_IO_DEBUG_UP_99__VALUE2_MASK 0x00ff0000L 6407#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x00000010 6408#define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000L 6409#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x00000018 6410#define MC_IO_DEBUG_UP_9__VALUE0_MASK 0x000000ffL 6411#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x00000000 6412#define MC_IO_DEBUG_UP_9__VALUE1_MASK 0x0000ff00L 6413#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x00000008 6414#define MC_IO_DEBUG_UP_9__VALUE2_MASK 0x00ff0000L 6415#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x00000010 6416#define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000L 6417#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x00000018 6418#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL 6419#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 6420#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L 6421#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 6422#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L 6423#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 6424#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L 6425#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 6426#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL 6427#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 6428#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L 6429#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 6430#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L 6431#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 6432#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L 6433#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 6434#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0x000000ffL 6435#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x00000000 6436#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 6437#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x00000008 6438#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 6439#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x00000010 6440#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000L 6441#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x00000018 6442#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0x000000ffL 6443#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x00000000 6444#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 6445#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x00000008 6446#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 6447#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x00000010 6448#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000L 6449#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x00000018 6450#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0x000000ffL 6451#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x00000000 6452#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0x0000ff00L 6453#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x00000008 6454#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0x00ff0000L 6455#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x00000010 6456#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000L 6457#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x00000018 6458#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0x000000ffL 6459#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x00000000 6460#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0x0000ff00L 6461#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x00000008 6462#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0x00ff0000L 6463#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x00000010 6464#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000L 6465#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x00000018 6466#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0x000000ffL 6467#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x00000000 6468#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 6469#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x00000008 6470#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 6471#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x00000010 6472#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000L 6473#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x00000018 6474#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0x000000ffL 6475#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x00000000 6476#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 6477#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x00000008 6478#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 6479#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x00000010 6480#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000L 6481#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x00000018 6482#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL 6483#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 6484#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L 6485#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 6486#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L 6487#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 6488#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L 6489#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 6490#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL 6491#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 6492#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L 6493#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 6494#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L 6495#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 6496#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L 6497#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 6498#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0x000000ffL 6499#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x00000000 6500#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 6501#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x00000008 6502#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 6503#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x00000010 6504#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000L 6505#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x00000018 6506#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0x000000ffL 6507#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x00000000 6508#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 6509#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x00000008 6510#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 6511#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x00000010 6512#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000L 6513#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x00000018 6514#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL 6515#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 6516#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L 6517#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 6518#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L 6519#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 6520#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L 6521#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 6522#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL 6523#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 6524#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L 6525#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 6526#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L 6527#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 6528#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L 6529#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 6530#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0x000000ffL 6531#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x00000000 6532#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 6533#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x00000008 6534#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 6535#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x00000010 6536#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000L 6537#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x00000018 6538#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0x000000ffL 6539#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x00000000 6540#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 6541#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x00000008 6542#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 6543#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x00000010 6544#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000L 6545#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x00000018 6546#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 6547#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 6548#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 6549#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 6550#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 6551#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 6552#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 6553#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 6554#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 6555#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 6556#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 6557#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 6558#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 6559#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 6560#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 6561#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 6562#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 6563#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 6564#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 6565#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 6566#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 6567#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 6568#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000L 6569#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 6570#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 6571#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 6572#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 6573#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 6574#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 6575#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 6576#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000L 6577#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 6578#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 6579#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 6580#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 6581#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 6582#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 6583#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 6584#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000L 6585#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 6586#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 6587#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 6588#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 6589#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 6590#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 6591#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 6592#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000L 6593#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 6594#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0x000000ffL 6595#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x00000000 6596#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 6597#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x00000008 6598#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 6599#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x00000010 6600#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000L 6601#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x00000018 6602#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0x000000ffL 6603#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x00000000 6604#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 6605#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x00000008 6606#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 6607#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x00000010 6608#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000L 6609#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x00000018 6610#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0x000000ffL 6611#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x00000000 6612#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0x0000ff00L 6613#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x00000008 6614#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0x00ff0000L 6615#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x00000010 6616#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000L 6617#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x00000018 6618#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0x000000ffL 6619#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x00000000 6620#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0x0000ff00L 6621#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x00000008 6622#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0x00ff0000L 6623#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x00000010 6624#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000L 6625#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x00000018 6626#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0x000000ffL 6627#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x00000000 6628#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0x0000ff00L 6629#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x00000008 6630#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0x00ff0000L 6631#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x00000010 6632#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000L 6633#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x00000018 6634#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0x000000ffL 6635#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x00000000 6636#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0x0000ff00L 6637#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x00000008 6638#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0x00ff0000L 6639#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x00000010 6640#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000L 6641#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x00000018 6642#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0x000000ffL 6643#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x00000000 6644#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0x0000ff00L 6645#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x00000008 6646#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0x00ff0000L 6647#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x00000010 6648#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000L 6649#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x00000018 6650#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0x000000ffL 6651#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x00000000 6652#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0x0000ff00L 6653#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x00000008 6654#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0x00ff0000L 6655#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x00000010 6656#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000L 6657#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x00000018 6658#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0x000000ffL 6659#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x00000000 6660#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0x0000ff00L 6661#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x00000008 6662#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0x00ff0000L 6663#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x00000010 6664#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000L 6665#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x00000018 6666#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0x000000ffL 6667#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x00000000 6668#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0x0000ff00L 6669#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x00000008 6670#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0x00ff0000L 6671#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x00000010 6672#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000L 6673#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x00000018 6674#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0x000000ffL 6675#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x00000000 6676#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0x0000ff00L 6677#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x00000008 6678#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0x00ff0000L 6679#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x00000010 6680#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000L 6681#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x00000018 6682#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0x000000ffL 6683#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x00000000 6684#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0x0000ff00L 6685#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x00000008 6686#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0x00ff0000L 6687#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x00000010 6688#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000L 6689#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x00000018 6690#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0x000000ffL 6691#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x00000000 6692#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0x0000ff00L 6693#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x00000008 6694#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0x00ff0000L 6695#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x00000010 6696#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000L 6697#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x00000018 6698#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0x000000ffL 6699#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x00000000 6700#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0x0000ff00L 6701#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x00000008 6702#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0x00ff0000L 6703#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x00000010 6704#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000L 6705#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x00000018 6706#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL 6707#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 6708#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L 6709#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 6710#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L 6711#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 6712#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L 6713#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 6714#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL 6715#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 6716#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L 6717#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 6718#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L 6719#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 6720#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L 6721#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 6722#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0x000000ffL 6723#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 6724#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L 6725#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 6726#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L 6727#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 6728#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000L 6729#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 6730#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0x000000ffL 6731#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 6732#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L 6733#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 6734#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L 6735#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 6736#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000L 6737#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 6738#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0x000000ffL 6739#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 6740#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L 6741#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 6742#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L 6743#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 6744#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000L 6745#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 6746#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0x000000ffL 6747#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 6748#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L 6749#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 6750#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L 6751#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 6752#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000L 6753#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 6754#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0x000000ffL 6755#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x00000000 6756#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0x0000ff00L 6757#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x00000008 6758#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0x00ff0000L 6759#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x00000010 6760#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000L 6761#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x00000018 6762#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0x000000ffL 6763#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x00000000 6764#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0x0000ff00L 6765#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x00000008 6766#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0x00ff0000L 6767#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x00000010 6768#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000L 6769#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x00000018 6770#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0x000000ffL 6771#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x00000000 6772#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0x0000ff00L 6773#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x00000008 6774#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0x00ff0000L 6775#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x00000010 6776#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000L 6777#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x00000018 6778#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0x000000ffL 6779#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x00000000 6780#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0x0000ff00L 6781#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x00000008 6782#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0x00ff0000L 6783#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x00000010 6784#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000L 6785#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x00000018 6786#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0x0c000000L 6787#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x0000001a 6788#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000L 6789#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x0000001c 6790#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000L 6791#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x0000001d 6792#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0x00000fc0L 6793#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x00000006 6794#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0x00fc0000L 6795#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x00000012 6796#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x0000003fL 6797#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x00000000 6798#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x0003f000L 6799#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0x0000000c 6800#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x01000000L 6801#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x00000018 6802#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x02000000L 6803#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x00000019 6804#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0x0c000000L 6805#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x0000001a 6806#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000L 6807#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x0000001c 6808#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000L 6809#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x0000001d 6810#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0x00000fc0L 6811#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x00000006 6812#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0x00fc0000L 6813#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x00000012 6814#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x0000003fL 6815#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x00000000 6816#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x0003f000L 6817#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0x0000000c 6818#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x01000000L 6819#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x00000018 6820#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x02000000L 6821#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x00000019 6822#define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000L 6823#define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x00000018 6824#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000L 6825#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x0000001f 6826#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000L 6827#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x0000001e 6828#define MC_IO_PAD_CNTL__ATBSEL_MASK 0x00f00000L 6829#define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x00000014 6830#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x00100000L 6831#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x00000014 6832#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0x00c00000L 6833#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x00000016 6834#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x03000000L 6835#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x00000018 6836#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x00200000L 6837#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x00000015 6838#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x00000010L 6839#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x00000004 6840#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x00000004L 6841#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x00000002 6842#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x00000008L 6843#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x00000003 6844#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000L 6845#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x0000001d 6846#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x00002000L 6847#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0x0000000d 6848#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x00001000L 6849#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0x0000000c 6850#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x00000800L 6851#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0x0000000b 6852#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x00000400L 6853#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0x0000000a 6854#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000L 6855#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x0000001e 6856#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x00000200L 6857#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x00000009 6858#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x00000080L 6859#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x00000007 6860#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x00000100L 6861#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x00000008 6862#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x08000000L 6863#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x0000001b 6864#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000L 6865#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x0000001f 6866#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000L 6867#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x0000001c 6868#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x00004000L 6869#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0x0000000e 6870#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0x000f8000L 6871#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0x0000000f 6872#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x00100000L 6873#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x00000014 6874#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0x00c00000L 6875#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x00000016 6876#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x03000000L 6877#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x00000018 6878#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x00200000L 6879#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x00000015 6880#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x00000010L 6881#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x00000004 6882#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x00000004L 6883#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x00000002 6884#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x00000008L 6885#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x00000003 6886#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x00000001L 6887#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x00000000 6888#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x00000002L 6889#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x00000001 6890#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000L 6891#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x0000001d 6892#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x00002000L 6893#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0x0000000d 6894#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x00001000L 6895#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0x0000000c 6896#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x00000800L 6897#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0x0000000b 6898#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x00000400L 6899#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0x0000000a 6900#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000L 6901#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x0000001e 6902#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x00000200L 6903#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x00000009 6904#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x00000080L 6905#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x00000007 6906#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x00000100L 6907#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x00000008 6908#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x00000020L 6909#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x00000005 6910#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x00000040L 6911#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x00000006 6912#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x08000000L 6913#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x0000001b 6914#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000L 6915#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x0000001f 6916#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000L 6917#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x0000001c 6918#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x00004000L 6919#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0x0000000e 6920#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0x000f8000L 6921#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0x0000000f 6922#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0x0000ff00L 6923#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x00000008 6924#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0x000000ffL 6925#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x00000000 6926#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x00040000L 6927#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x00000012 6928#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x00080000L 6929#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x00000013 6930#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x00020000L 6931#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x00000011 6932#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x00010000L 6933#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x00000010 6934#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000L 6935#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x0000001c 6936#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0x0e000000L 6937#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x00000019 6938#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0x0000000fL 6939#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x00000000 6940#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0x000000f0L 6941#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x00000004 6942#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0x0000ff00L 6943#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x00000008 6944#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x00040000L 6945#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x00000012 6946#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x00010000L 6947#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x00000010 6948#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x00020000L 6949#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x00000011 6950#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000L 6951#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x0000001c 6952#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0x0e000000L 6953#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x00000019 6954#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0x0000000fL 6955#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x00000000 6956#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0x000000f0L 6957#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x00000004 6958#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0x0000ff00L 6959#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x00000008 6960#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x00040000L 6961#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x00000012 6962#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x00010000L 6963#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x00000010 6964#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x00020000L 6965#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x00000011 6966#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000L 6967#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x0000001c 6968#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0x0e000000L 6969#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x00000019 6970#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0x0000000fL 6971#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x00000000 6972#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0x000000f0L 6973#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x00000004 6974#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0x0000ff00L 6975#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x00000008 6976#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x00040000L 6977#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x00000012 6978#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x00010000L 6979#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x00000010 6980#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x00020000L 6981#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x00000011 6982#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000L 6983#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x0000001c 6984#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0x0e000000L 6985#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x00000019 6986#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0x0000000fL 6987#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x00000000 6988#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0x000000f0L 6989#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x00000004 6990#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0x0000ff00L 6991#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x00000008 6992#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x00040000L 6993#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x00000012 6994#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x00010000L 6995#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x00000010 6996#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x00020000L 6997#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x00000011 6998#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x00700000L 6999#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x00000014 7000#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x07000000L 7001#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x00000018 7002#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000L 7003#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x0000001c 7004#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000L 7005#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x0000001e 7006#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x00000004L 7007#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x00000002 7008#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000L 7009#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x0000001d 7010#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x00000003L 7011#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x00000000 7012#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x00000030L 7013#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x00000004 7014#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x00000080L 7015#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x00000007 7016#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x00000040L 7017#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x00000006 7018#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0x000c0000L 7019#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x00000012 7020#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0x00000f00L 7021#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x00000008 7022#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0x0000f000L 7023#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0x0000000c 7024#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x00000008L 7025#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x00000003 7026#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x00010000L 7027#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x00000010 7028#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x00700000L 7029#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x00000014 7030#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x07000000L 7031#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x00000018 7032#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000L 7033#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x0000001c 7034#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000L 7035#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x0000001e 7036#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x00000004L 7037#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x00000002 7038#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000L 7039#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x0000001d 7040#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x00000003L 7041#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x00000000 7042#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x00000030L 7043#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x00000004 7044#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x00000080L 7045#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x00000007 7046#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x00000040L 7047#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x00000006 7048#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0x000c0000L 7049#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x00000012 7050#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0x00000f00L 7051#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x00000008 7052#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0x0000f000L 7053#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0x0000000c 7054#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x00000008L 7055#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x00000003 7056#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x00010000L 7057#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x00000010 7058#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x00700000L 7059#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x00000014 7060#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x07000000L 7061#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x00000018 7062#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000L 7063#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x0000001c 7064#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000L 7065#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x0000001e 7066#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x00000004L 7067#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x00000002 7068#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000L 7069#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x0000001d 7070#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x00000003L 7071#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x00000000 7072#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x00000030L 7073#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x00000004 7074#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x00000080L 7075#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x00000007 7076#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x00000040L 7077#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x00000006 7078#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0x000c0000L 7079#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x00000012 7080#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0x00000f00L 7081#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x00000008 7082#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0x0000f000L 7083#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0x0000000c 7084#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x00000008L 7085#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x00000003 7086#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x00010000L 7087#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x00000010 7088#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x00700000L 7089#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x00000014 7090#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x07000000L 7091#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x00000018 7092#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000L 7093#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x0000001c 7094#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000L 7095#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x0000001e 7096#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x00000004L 7097#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x00000002 7098#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000L 7099#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x0000001d 7100#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x00000003L 7101#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x00000000 7102#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x00000030L 7103#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x00000004 7104#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x00000080L 7105#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x00000007 7106#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x00000040L 7107#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x00000006 7108#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0x000c0000L 7109#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x00000012 7110#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0x00000f00L 7111#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x00000008 7112#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0x0000f000L 7113#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0x0000000c 7114#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x00000008L 7115#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x00000003 7116#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x00010000L 7117#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x00000010 7118#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x00000003L 7119#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x00000000 7120#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000L 7121#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x0000001e 7122#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000L 7123#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x0000001f 7124#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0x0000000cL 7125#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x00000002 7126#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x00000040L 7127#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x00000006 7128#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x00000010L 7129#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x00000004 7130#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x00700000L 7131#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x00000014 7132#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0x000f0000L 7133#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x00000010 7134#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0x0000e000L 7135#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0x0000000d 7136#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0x00000f00L 7137#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x00000008 7138#define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x00000020L 7139#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x00000005 7140#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x01000000L 7141#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x00000018 7142#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x00001000L 7143#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0x0000000c 7144#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000L 7145#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x0000001b 7146#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x04000000L 7147#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x0000001a 7148#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x00000080L 7149#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x00000007 7150#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x02000000L 7151#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x00000019 7152#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x00800000L 7153#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x00000017 7154#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x00000003L 7155#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x00000000 7156#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000L 7157#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x0000001e 7158#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000L 7159#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x0000001f 7160#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0x0000000cL 7161#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x00000002 7162#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x00000040L 7163#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x00000006 7164#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x00000010L 7165#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x00000004 7166#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x00700000L 7167#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x00000014 7168#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0x000f0000L 7169#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x00000010 7170#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0x0000e000L 7171#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0x0000000d 7172#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0x00000f00L 7173#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x00000008 7174#define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x00000020L 7175#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x00000005 7176#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x01000000L 7177#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x00000018 7178#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x00001000L 7179#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0x0000000c 7180#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000L 7181#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x0000001b 7182#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x04000000L 7183#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x0000001a 7184#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x00000080L 7185#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x00000007 7186#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x02000000L 7187#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x00000019 7188#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x00800000L 7189#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x00000017 7190#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x00000003L 7191#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x00000000 7192#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0x0000000cL 7193#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x00000002 7194#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x02000000L 7195#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x00000019 7196#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x00000040L 7197#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x00000006 7198#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x00000010L 7199#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x00000004 7200#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0x00f00000L 7201#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x00000014 7202#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0x0000f000L 7203#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0x0000000c 7204#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0x000f0000L 7205#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x00000010 7206#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x08000000L 7207#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x0000001b 7208#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0x00000f00L 7209#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x00000008 7210#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x00000020L 7211#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x00000005 7212#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x01000000L 7213#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x00000018 7214#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000L 7215#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x0000001c 7216#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x04000000L 7217#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x0000001a 7218#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x00000080L 7219#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x00000007 7220#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x00000003L 7221#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x00000000 7222#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0x0000000cL 7223#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x00000002 7224#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x02000000L 7225#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x00000019 7226#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x00000040L 7227#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x00000006 7228#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x00000010L 7229#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x00000004 7230#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0x00f00000L 7231#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x00000014 7232#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0x0000f000L 7233#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0x0000000c 7234#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0x000f0000L 7235#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x00000010 7236#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x08000000L 7237#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x0000001b 7238#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0x00000f00L 7239#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x00000008 7240#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x00000020L 7241#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x00000005 7242#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x01000000L 7243#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x00000018 7244#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000L 7245#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x0000001c 7246#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x04000000L 7247#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x0000001a 7248#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x00000080L 7249#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x00000007 7250#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x00000003L 7251#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x00000000 7252#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0x0000000cL 7253#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x00000002 7254#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x02000000L 7255#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x00000019 7256#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x00000040L 7257#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x00000006 7258#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x00000010L 7259#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x00000004 7260#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0x00f00000L 7261#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x00000014 7262#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0x0000f000L 7263#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0x0000000c 7264#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0x000f0000L 7265#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x00000010 7266#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x08000000L 7267#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x0000001b 7268#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0x00000f00L 7269#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x00000008 7270#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x00000020L 7271#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x00000005 7272#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x01000000L 7273#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x00000018 7274#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000L 7275#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x0000001c 7276#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x04000000L 7277#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x0000001a 7278#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x00000080L 7279#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x00000007 7280#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x00000003L 7281#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x00000000 7282#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0x0000000cL 7283#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x00000002 7284#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x02000000L 7285#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x00000019 7286#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x00000040L 7287#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x00000006 7288#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x00000010L 7289#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x00000004 7290#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0x00f00000L 7291#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x00000014 7292#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0x0000f000L 7293#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0x0000000c 7294#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0x000f0000L 7295#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x00000010 7296#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x08000000L 7297#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x0000001b 7298#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0x00000f00L 7299#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x00000008 7300#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x00000020L 7301#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x00000005 7302#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x01000000L 7303#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x00000018 7304#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000L 7305#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x0000001c 7306#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x04000000L 7307#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x0000001a 7308#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x00000080L 7309#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x00000007 7310#define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x00000040L 7311#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x01000000L 7312#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x00000018 7313#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000006 7314#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x0000001fL 7315#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x00000000 7316#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00000080L 7317#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000007 7318#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x00000100L 7319#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x00000008 7320#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x00010000L 7321#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x00000010 7322#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x00000200L 7323#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x00000009 7324#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x00020000L 7325#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x00000011 7326#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000fc0L 7327#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000006 7328#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003fL 7329#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000000 7330#define MC_NPL_STATUS__D0_NDELAY_MASK 0x0000000cL 7331#define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x00000002 7332#define MC_NPL_STATUS__D0_NEARLY_MASK 0x00000020L 7333#define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x00000005 7334#define MC_NPL_STATUS__D0_PDELAY_MASK 0x00000003L 7335#define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x00000000 7336#define MC_NPL_STATUS__D0_PEARLY_MASK 0x00000010L 7337#define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x00000004 7338#define MC_NPL_STATUS__D1_NDELAY_MASK 0x00000300L 7339#define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x00000008 7340#define MC_NPL_STATUS__D1_NEARLY_MASK 0x00000800L 7341#define MC_NPL_STATUS__D1_NEARLY__SHIFT 0x0000000b 7342#define MC_NPL_STATUS__D1_PDELAY_MASK 0x000000c0L 7343#define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x00000006 7344#define MC_NPL_STATUS__D1_PEARLY_MASK 0x00000400L 7345#define MC_NPL_STATUS__D1_PEARLY__SHIFT 0x0000000a 7346#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x00040000L 7347#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x00000012 7348#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x00080000L 7349#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x00000013 7350#define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x0000007fL 7351#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x00000000 7352#define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x00001000L 7353#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0x0000000c 7354#define MC_PHY_TIMING_2__RXC0_INV_MASK 0x00000100L 7355#define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x00000008 7356#define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x00002000L 7357#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0x0000000d 7358#define MC_PHY_TIMING_2__RXC1_INV_MASK 0x00000200L 7359#define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x00000009 7360#define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x00004000L 7361#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0x0000000e 7362#define MC_PHY_TIMING_2__TXC0_INV_MASK 0x00000400L 7363#define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0x0000000a 7364#define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x00008000L 7365#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0x0000000f 7366#define MC_PHY_TIMING_2__TXC1_INV_MASK 0x00000800L 7367#define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0x0000000b 7368#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x00010000L 7369#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x00000010 7370#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x00020000L 7371#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x00000011 7372#define MC_PHY_TIMING_2__WR_DLY_MASK 0x00f00000L 7373#define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x00000014 7374#define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0x0000000fL 7375#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x00000000 7376#define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0x000000f0L 7377#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x00000004 7378#define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0x00000f00L 7379#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x00000008 7380#define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0x0000f000L 7381#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0x0000000c 7382#define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x00070000L 7383#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x00000010 7384#define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0x00f00000L 7385#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x00000014 7386#define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x07000000L 7387#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x00000018 7388#define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000L 7389#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x0000001c 7390#define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0x0000000fL 7391#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x00000000 7392#define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0x000000f0L 7393#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x00000004 7394#define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0x00000f00L 7395#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x00000008 7396#define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0x0000f000L 7397#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0x0000000c 7398#define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x00070000L 7399#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x00000010 7400#define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0x00f00000L 7401#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x00000014 7402#define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x07000000L 7403#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x00000018 7404#define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000L 7405#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x0000001c 7406#define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000L 7407#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x00000018 7408#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x00000800L 7409#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0x0000000b 7410#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0x000f0000L 7411#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x00000010 7412#define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x00002000L 7413#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0x0000000d 7414#define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x00001000L 7415#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0x0000000c 7416#define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x00000002L 7417#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x00000001 7418#define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x00400000L 7419#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x00000016 7420#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x00000400L 7421#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0x0000000a 7422#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x00008000L 7423#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0x0000000f 7424#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x00800000L 7425#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x00000017 7426#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x00000100L 7427#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x00000008 7428#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x00000200L 7429#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x00000009 7430#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x00004000L 7431#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0x0000000e 7432#define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x00000001L 7433#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x00000000 7434#define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x00000004L 7435#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x00000002 7436#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x00100000L 7437#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x00000014 7438#define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0x000000f0L 7439#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x00000004 7440#define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x00200000L 7441#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x00000015 7442#define MC_PMG_AUTO_CMD__ADR_MASK 0x0001ffffL 7443#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000L 7444#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x0000001d 7445#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000L 7446#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x0000001c 7447#define MC_PMG_AUTO_CMD__ADR__SHIFT 0x00000000 7448#define MC_PMG_CFG__DPM_WAKE_MASK 0x00000400L 7449#define MC_PMG_CFG__DPM_WAKE__SHIFT 0x0000000a 7450#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x00400000L 7451#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x00000016 7452#define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0x000f0000L 7453#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x00000010 7454#define MC_PMG_CFG__PREA_SRX_MASK 0x00002000L 7455#define MC_PMG_CFG__PREA_SRX__SHIFT 0x0000000d 7456#define MC_PMG_CFG__RFS_SRX_MASK 0x00001000L 7457#define MC_PMG_CFG__RFS_SRX__SHIFT 0x0000000c 7458#define MC_PMG_CFG__RST_EMRS_MASK 0x00000004L 7459#define MC_PMG_CFG__RST_EMRS__SHIFT 0x00000002 7460#define MC_PMG_CFG__RST_MRS1_MASK 0x00000100L 7461#define MC_PMG_CFG__RST_MRS1__SHIFT 0x00000008 7462#define MC_PMG_CFG__RST_MRS2_MASK 0x00000200L 7463#define MC_PMG_CFG__RST_MRS2__SHIFT 0x00000009 7464#define MC_PMG_CFG__RST_MRS_MASK 0x00000002L 7465#define MC_PMG_CFG__RST_MRS__SHIFT 0x00000001 7466#define MC_PMG_CFG__RXPDNB_MASK 0x02000000L 7467#define MC_PMG_CFG__RXPDNB__SHIFT 0x00000019 7468#define MC_PMG_CFG__SYC_CLK_MASK 0x00000001L 7469#define MC_PMG_CFG__SYC_CLK__SHIFT 0x00000000 7470#define MC_PMG_CFG__TRI_MIO_MASK 0x00000008L 7471#define MC_PMG_CFG__TRI_MIO__SHIFT 0x00000003 7472#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x00100000L 7473#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x00000014 7474#define MC_PMG_CFG__XSR_TMR_MASK 0x000000f0L 7475#define MC_PMG_CFG__XSR_TMR__SHIFT 0x00000004 7476#define MC_PMG_CFG__YCLK_ON_MASK 0x00200000L 7477#define MC_PMG_CFG__YCLK_ON__SHIFT 0x00000015 7478#define MC_PMG_CFG__ZQCL_SEND_MASK 0x0c000000L 7479#define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x0000001a 7480#define MC_PMG_CMD_EMRS__ADR_MASK 0x0000ffffL 7481#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000L 7482#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x0000001d 7483#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000L 7484#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x0000001c 7485#define MC_PMG_CMD_EMRS__ADR__SHIFT 0x00000000 7486#define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x00080000L 7487#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x00000013 7488#define MC_PMG_CMD_EMRS__CSB_MASK 0x00600000L 7489#define MC_PMG_CMD_EMRS__CSB__SHIFT 0x00000015 7490#define MC_PMG_CMD_EMRS__END_MASK 0x00100000L 7491#define MC_PMG_CMD_EMRS__END__SHIFT 0x00000014 7492#define MC_PMG_CMD_EMRS__MOP_MASK 0x00070000L 7493#define MC_PMG_CMD_EMRS__MOP__SHIFT 0x00000010 7494#define MC_PMG_CMD_MRS1__ADR_MASK 0x0000ffffL 7495#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000L 7496#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x0000001d 7497#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000L 7498#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x0000001c 7499#define MC_PMG_CMD_MRS1__ADR__SHIFT 0x00000000 7500#define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x00080000L 7501#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x00000013 7502#define MC_PMG_CMD_MRS1__CSB_MASK 0x00600000L 7503#define MC_PMG_CMD_MRS1__CSB__SHIFT 0x00000015 7504#define MC_PMG_CMD_MRS1__END_MASK 0x00100000L 7505#define MC_PMG_CMD_MRS1__END__SHIFT 0x00000014 7506#define MC_PMG_CMD_MRS1__MOP_MASK 0x00070000L 7507#define MC_PMG_CMD_MRS1__MOP__SHIFT 0x00000010 7508#define MC_PMG_CMD_MRS2__ADR_MASK 0x0000ffffL 7509#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000L 7510#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x0000001d 7511#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000L 7512#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x0000001c 7513#define MC_PMG_CMD_MRS2__ADR__SHIFT 0x00000000 7514#define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x00080000L 7515#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x00000013 7516#define MC_PMG_CMD_MRS2__CSB_MASK 0x00600000L 7517#define MC_PMG_CMD_MRS2__CSB__SHIFT 0x00000015 7518#define MC_PMG_CMD_MRS2__END_MASK 0x00100000L 7519#define MC_PMG_CMD_MRS2__END__SHIFT 0x00000014 7520#define MC_PMG_CMD_MRS2__MOP_MASK 0x00070000L 7521#define MC_PMG_CMD_MRS2__MOP__SHIFT 0x00000010 7522#define MC_PMG_CMD_MRS__ADR_MASK 0x0000ffffL 7523#define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000L 7524#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x0000001d 7525#define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000L 7526#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x0000001c 7527#define MC_PMG_CMD_MRS__ADR__SHIFT 0x00000000 7528#define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x00080000L 7529#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x00000013 7530#define MC_PMG_CMD_MRS__CSB_MASK 0x00600000L 7531#define MC_PMG_CMD_MRS__CSB__SHIFT 0x00000015 7532#define MC_PMG_CMD_MRS__END_MASK 0x00100000L 7533#define MC_PMG_CMD_MRS__END__SHIFT 0x00000014 7534#define MC_PMG_CMD_MRS__MOP_MASK 0x00070000L 7535#define MC_PMG_CMD_MRS__MOP__SHIFT 0x00000010 7536#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x00000008L 7537#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x00000003 7538#define MC_RD_CB__ENABLE_MASK 0x00000001L 7539#define MC_RD_CB__ENABLE__SHIFT 0x00000000 7540#define MC_RD_CB__LAZY_TIMER_MASK 0x00007800L 7541#define MC_RD_CB__LAZY_TIMER__SHIFT 0x0000000b 7542#define MC_RD_CB__MAX_BURST_MASK 0x00000780L 7543#define MC_RD_CB__MAX_BURST__SHIFT 0x00000007 7544#define MC_RD_CB__PRESCALE_MASK 0x00000006L 7545#define MC_RD_CB__PRESCALE__SHIFT 0x00000001 7546#define MC_RD_CB__STALL_MODE_MASK 0x00000030L 7547#define MC_RD_CB__STALL_MODE__SHIFT 0x00000004 7548#define MC_RD_CB__STALL_OVERRIDE_MASK 0x00000040L 7549#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x00000006 7550#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x00008000L 7551#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 7552#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x00000008L 7553#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x00000003 7554#define MC_RD_DB__ENABLE_MASK 0x00000001L 7555#define MC_RD_DB__ENABLE__SHIFT 0x00000000 7556#define MC_RD_DB__LAZY_TIMER_MASK 0x00007800L 7557#define MC_RD_DB__LAZY_TIMER__SHIFT 0x0000000b 7558#define MC_RD_DB__MAX_BURST_MASK 0x00000780L 7559#define MC_RD_DB__MAX_BURST__SHIFT 0x00000007 7560#define MC_RD_DB__PRESCALE_MASK 0x00000006L 7561#define MC_RD_DB__PRESCALE__SHIFT 0x00000001 7562#define MC_RD_DB__STALL_MODE_MASK 0x00000030L 7563#define MC_RD_DB__STALL_MODE__SHIFT 0x00000004 7564#define MC_RD_DB__STALL_OVERRIDE_MASK 0x00000040L 7565#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x00000006 7566#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x00008000L 7567#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 7568#define MC_RD_GRP_EXT__DBSTEN0_MASK 0x0000000fL 7569#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x00000000 7570#define MC_RD_GRP_EXT__TC0_MASK 0x000000f0L 7571#define MC_RD_GRP_EXT__TC0__SHIFT 0x00000004 7572#define MC_RD_GRP_GFX__CP_MASK 0x0000000fL 7573#define MC_RD_GRP_GFX__CP__SHIFT 0x00000000 7574#define MC_RD_GRP_GFX__XDMAM_MASK 0x000f0000L 7575#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x00000010 7576#define MC_RD_GRP_LCL__CB0_MASK 0x0000f000L 7577#define MC_RD_GRP_LCL__CB0__SHIFT 0x0000000c 7578#define MC_RD_GRP_LCL__CBCMASK0_MASK 0x000f0000L 7579#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x00000010 7580#define MC_RD_GRP_LCL__CBFMASK0_MASK 0x00f00000L 7581#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x00000014 7582#define MC_RD_GRP_LCL__DB0_MASK 0x0f000000L 7583#define MC_RD_GRP_LCL__DB0__SHIFT 0x00000018 7584#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000L 7585#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x0000001c 7586#define MC_RD_GRP_OTH__HDP_MASK 0x00000f00L 7587#define MC_RD_GRP_OTH__HDP__SHIFT 0x00000008 7588#define MC_RD_GRP_OTH__SEM_MASK 0x0000f000L 7589#define MC_RD_GRP_OTH__SEM__SHIFT 0x0000000c 7590#define MC_RD_GRP_OTH__UMC_MASK 0x000f0000L 7591#define MC_RD_GRP_OTH__UMC__SHIFT 0x00000010 7592#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0x0000000fL 7593#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x00000000 7594#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0x0f000000L 7595#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x00000018 7596#define MC_RD_GRP_OTH__UVD_MASK 0x00f00000L 7597#define MC_RD_GRP_OTH__UVD__SHIFT 0x00000014 7598#define MC_RD_GRP_SYS__DMIF_MASK 0x0000f000L 7599#define MC_RD_GRP_SYS__DMIF__SHIFT 0x0000000c 7600#define MC_RD_GRP_SYS__MCIF_MASK 0x000f0000L 7601#define MC_RD_GRP_SYS__MCIF__SHIFT 0x00000010 7602#define MC_RD_GRP_SYS__RLC_MASK 0x0000000fL 7603#define MC_RD_GRP_SYS__RLC__SHIFT 0x00000000 7604#define MC_RD_GRP_SYS__SMU_MASK 0x00f00000L 7605#define MC_RD_GRP_SYS__SMU__SHIFT 0x00000014 7606#define MC_RD_GRP_SYS__VCE_MASK 0x0f000000L 7607#define MC_RD_GRP_SYS__VCE__SHIFT 0x00000018 7608#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000L 7609#define MC_RD_GRP_SYS__VCEU__SHIFT 0x0000001c 7610#define MC_RD_GRP_SYS__VMC_MASK 0x000000f0L 7611#define MC_RD_GRP_SYS__VMC__SHIFT 0x00000004 7612#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x00000008L 7613#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x00000003 7614#define MC_RD_HUB__ENABLE_MASK 0x00000001L 7615#define MC_RD_HUB__ENABLE__SHIFT 0x00000000 7616#define MC_RD_HUB__LAZY_TIMER_MASK 0x00007800L 7617#define MC_RD_HUB__LAZY_TIMER__SHIFT 0x0000000b 7618#define MC_RD_HUB__MAX_BURST_MASK 0x00000780L 7619#define MC_RD_HUB__MAX_BURST__SHIFT 0x00000007 7620#define MC_RD_HUB__PRESCALE_MASK 0x00000006L 7621#define MC_RD_HUB__PRESCALE__SHIFT 0x00000001 7622#define MC_RD_HUB__STALL_MODE_MASK 0x00000030L 7623#define MC_RD_HUB__STALL_MODE__SHIFT 0x00000004 7624#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x00000040L 7625#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x00000006 7626#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x00008000L 7627#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 7628#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x00000008L 7629#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x00000003 7630#define MC_RD_TC0__ENABLE_MASK 0x00000001L 7631#define MC_RD_TC0__ENABLE__SHIFT 0x00000000 7632#define MC_RD_TC0__LAZY_TIMER_MASK 0x00007800L 7633#define MC_RD_TC0__LAZY_TIMER__SHIFT 0x0000000b 7634#define MC_RD_TC0__MAX_BURST_MASK 0x00000780L 7635#define MC_RD_TC0__MAX_BURST__SHIFT 0x00000007 7636#define MC_RD_TC0__PRESCALE_MASK 0x00000006L 7637#define MC_RD_TC0__PRESCALE__SHIFT 0x00000001 7638#define MC_RD_TC0__STALL_MODE_MASK 0x00000030L 7639#define MC_RD_TC0__STALL_MODE__SHIFT 0x00000004 7640#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x00000040L 7641#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x00000006 7642#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x00008000L 7643#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 7644#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x00000008L 7645#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x00000003 7646#define MC_RD_TC1__ENABLE_MASK 0x00000001L 7647#define MC_RD_TC1__ENABLE__SHIFT 0x00000000 7648#define MC_RD_TC1__LAZY_TIMER_MASK 0x00007800L 7649#define MC_RD_TC1__LAZY_TIMER__SHIFT 0x0000000b 7650#define MC_RD_TC1__MAX_BURST_MASK 0x00000780L 7651#define MC_RD_TC1__MAX_BURST__SHIFT 0x00000007 7652#define MC_RD_TC1__PRESCALE_MASK 0x00000006L 7653#define MC_RD_TC1__PRESCALE__SHIFT 0x00000001 7654#define MC_RD_TC1__STALL_MODE_MASK 0x00000030L 7655#define MC_RD_TC1__STALL_MODE__SHIFT 0x00000004 7656#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x00000040L 7657#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x00000006 7658#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x00008000L 7659#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 7660#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0x00ff0000L 7661#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x00000010 7662#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x0000ff00L 7663#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x00000008 7664#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x000000ffL 7665#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x00000000 7666#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0x000000ffL 7667#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x00000000 7668#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0x0000ff00L 7669#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x00000008 7670#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000L 7671#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x00000010 7672#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000ffffL 7673#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x00000000 7674#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x0000003eL 7675#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x00000001 7676#define MC_RPB_CID_QUEUE_EX__START_MASK 0x00000001L 7677#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x00000000 7678#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0x000000ffL 7679#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x00000000 7680#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x00000c00L 7681#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0x0000000a 7682#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00000300L 7683#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x00000008 7684#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0x000000ffL 7685#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x00000000 7686#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00001800L 7687#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0x0000000b 7688#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x00002000L 7689#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000100L 7690#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x00000008 7691#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x0000000d 7692#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00000600L 7693#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x00000009 7694#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x00010000L 7695#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x00000010 7696#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x00020000L 7697#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x00000011 7698#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x00008000L 7699#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0x0000000f 7700#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000L 7701#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x00000014 7702#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0x000fff00L 7703#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x00000008 7704#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0x000000ffL 7705#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x00000000 7706#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000ff00L 7707#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x00000008 7708#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000ffL 7709#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x00000000 7710#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0x0000ff00L 7711#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x00000008 7712#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0x000000ffL 7713#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x00000000 7714#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L 7715#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x00000003 7716#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L 7717#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x00000002 7718#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001e0L 7719#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x00000005 7720#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003e00L 7721#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x00000009 7722#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007c000L 7723#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0x0000000e 7724#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00f80000L 7725#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x00000013 7726#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000L 7727#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x00000018 7728#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 7729#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000 7730#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L 7731#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x00000004 7732#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffffL 7733#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x00000000 7734#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x000000ffL 7735#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000 7736#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x0000ff00L 7737#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000008 7738#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x00ff0000L 7739#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x00000010 7740#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000L 7741#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000018 7742#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x00000080L 7743#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x00000007 7744#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x00000001L 7745#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x00000000 7746#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x00000078L 7747#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x00000003 7748#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x00000006L 7749#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x00000001 7750#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x000000ffL 7751#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000 7752#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x0000ff00L 7753#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000008 7754#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x00ff0000L 7755#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x00000010 7756#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000L 7757#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000018 7758#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x00000007L 7759#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x00000000 7760#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x00000038L 7761#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x00000003 7762#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x000001c0L 7763#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x00000006 7764#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0x00000e00L 7765#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x00000009 7766#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x00007000L 7767#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0x0000000c 7768#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x00038000L 7769#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0x0000000f 7770#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x001c0000L 7771#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x00000012 7772#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0x00e00000L 7773#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x00000015 7774#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x00000007L 7775#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x00000000 7776#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x00000038L 7777#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x00000003 7778#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x000001c0L 7779#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x00000006 7780#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0x00000e00L 7781#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x00000009 7782#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x00007000L 7783#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0x0000000c 7784#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x00038000L 7785#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0x0000000f 7786#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x001c0000L 7787#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x00000012 7788#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0x00e00000L 7789#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x00000015 7790#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x00000007L 7791#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x00000000 7792#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x00000038L 7793#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x00000003 7794#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x000001c0L 7795#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x00000006 7796#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0x00000e00L 7797#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x00000009 7798#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x00007000L 7799#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0x0000000c 7800#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x00038000L 7801#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0x0000000f 7802#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x001c0000L 7803#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x00000012 7804#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0x00e00000L 7805#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x00000015 7806#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x00000007L 7807#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x00000000 7808#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x00000038L 7809#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x00000003 7810#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x000001c0L 7811#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x00000006 7812#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0x00000e00L 7813#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x00000009 7814#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x00007000L 7815#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0x0000000c 7816#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x00038000L 7817#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0x0000000f 7818#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x001c0000L 7819#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x00000012 7820#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0x00e00000L 7821#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x00000015 7822#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x00000007L 7823#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x00000000 7824#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x00000038L 7825#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x00000003 7826#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x000001c0L 7827#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x00000006 7828#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0x00000e00L 7829#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x00000009 7830#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x00007000L 7831#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0x0000000c 7832#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x00038000L 7833#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0x0000000f 7834#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x001c0000L 7835#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x00000012 7836#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0x00e00000L 7837#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x00000015 7838#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x00000007L 7839#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x00000000 7840#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x00000038L 7841#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x00000003 7842#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x000001c0L 7843#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x00000006 7844#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0x00000e00L 7845#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x00000009 7846#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x00007000L 7847#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0x0000000c 7848#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x00038000L 7849#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0x0000000f 7850#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x001c0000L 7851#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x00000012 7852#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0x00e00000L 7853#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x00000015 7854#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x00000007L 7855#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x00000000 7856#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x00000038L 7857#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x00000003 7858#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x000001c0L 7859#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x00000006 7860#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0x00000e00L 7861#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x00000009 7862#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x00007000L 7863#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0x0000000c 7864#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x00038000L 7865#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0x0000000f 7866#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x001c0000L 7867#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x00000012 7868#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0x00e00000L 7869#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x00000015 7870#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x00000007L 7871#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x00000000 7872#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x00000038L 7873#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x00000003 7874#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x000001c0L 7875#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x00000006 7876#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0x00000e00L 7877#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x00000009 7878#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x00007000L 7879#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0x0000000c 7880#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x00038000L 7881#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0x0000000f 7882#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x001c0000L 7883#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x00000012 7884#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0x00e00000L 7885#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x00000015 7886#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x00000003L 7887#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x00000000 7888#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0x0000000cL 7889#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x00000002 7890#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x00000030L 7891#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x00000004 7892#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0x000000c0L 7893#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x00000006 7894#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x00000003L 7895#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x00000000 7896#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0x0000000cL 7897#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x00000002 7898#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x00000030L 7899#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x00000004 7900#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0x000000c0L 7901#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x00000006 7902#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0x00000e00L 7903#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x00000009 7904#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000L 7905#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x00000018 7906#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0x0000000cL 7907#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x00000002 7908#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x00000003L 7909#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x00000000 7910#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0x0000f000L 7911#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0x0000000c 7912#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x000001f0L 7913#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x00000004 7914#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x001f0000L 7915#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x00000010 7916#define MC_SEQ_CAS_TIMING__TCCDL_MASK 0x00000e00L 7917#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x00000009 7918#define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000L 7919#define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x00000018 7920#define MC_SEQ_CAS_TIMING__TNOPR_MASK 0x0000000cL 7921#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x00000002 7922#define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x00000003L 7923#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x00000000 7924#define MC_SEQ_CAS_TIMING__TR2R_MASK 0x0000f000L 7925#define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0x0000000c 7926#define MC_SEQ_CAS_TIMING__TR2W_MASK 0x000001f0L 7927#define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x00000004 7928#define MC_SEQ_CAS_TIMING__TW2R_MASK 0x001f0000L 7929#define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x00000010 7930#define MC_SEQ_CG__CG_SEQ_REQ_MASK 0x000000ffL 7931#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x00000000 7932#define MC_SEQ_CG__CG_SEQ_RESP_MASK 0x0000ff00L 7933#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x00000008 7934#define MC_SEQ_CG__SEQ_CG_REQ_MASK 0x00ff0000L 7935#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x00000010 7936#define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000L 7937#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x00000018 7938#define MC_SEQ_CMD__ADR_MASK 0x0000ffffL 7939#define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000L 7940#define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x0000001d 7941#define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000L 7942#define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x0000001c 7943#define MC_SEQ_CMD__ADR__SHIFT 0x00000000 7944#define MC_SEQ_CMD__CHAN0_MASK 0x01000000L 7945#define MC_SEQ_CMD__CHAN0__SHIFT 0x00000018 7946#define MC_SEQ_CMD__CHAN1_MASK 0x02000000L 7947#define MC_SEQ_CMD__CHAN1__SHIFT 0x00000019 7948#define MC_SEQ_CMD__CSB_MASK 0x00600000L 7949#define MC_SEQ_CMD__CSB__SHIFT 0x00000015 7950#define MC_SEQ_CMD__END_MASK 0x00100000L 7951#define MC_SEQ_CMD__END__SHIFT 0x00000014 7952#define MC_SEQ_CMD__MOP_MASK 0x000f0000L 7953#define MC_SEQ_CMD__MOP__SHIFT 0x00000010 7954#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x00000300L 7955#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x00000008 7956#define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0x0000fc00L 7957#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0x0000000a 7958#define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x003f0000L 7959#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x00000010 7960#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0x0f000000L 7961#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x00000018 7962#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000L 7963#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x0000001c 7964#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x00400000L 7965#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x00000016 7966#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x00800000L 7967#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x00000017 7968#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0x00f00000L 7969#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x00000014 7970#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0x0f000000L 7971#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x00000018 7972#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000L 7973#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x0000001c 7974#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x00040000L 7975#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x00000012 7976#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x00020000L 7977#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x00000011 7978#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x00000300L 7979#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x00000008 7980#define MC_SEQ_CNTL__DAT_INV_MASK 0x00000040L 7981#define MC_SEQ_CNTL__DAT_INV__SHIFT 0x00000006 7982#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0x0000000cL 7983#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x00000002 7984#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x00000003L 7985#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x00000000 7986#define MC_SEQ_CNTL__MSK_DF1_MASK 0x00000080L 7987#define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x00000007 7988#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x00008000L 7989#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0x0000000f 7990#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x00004000L 7991#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0x0000000e 7992#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x00010000L 7993#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x00000010 7994#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x00080000L 7995#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x00000013 7996#define MC_SEQ_CNTL__SAFE_MODE_MASK 0x00000030L 7997#define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x00000004 7998#define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x04000000L 7999#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x0000001a 8000#define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x02000000L 8001#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x00000019 8002#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x00000004L 8003#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x00000002 8004#define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x00000002L 8005#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x00000001 8006#define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x00000001L 8007#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x00000000 8008#define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x00002000L 8009#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0x0000000d 8010#define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x00000008L 8011#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x00000003 8012#define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000L 8013#define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x0000001f 8014#define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x00000010L 8015#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x00000004 8016#define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000L 8017#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x0000001c 8018#define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x08000000L 8019#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x0000001b 8020#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000L 8021#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x0000001d 8022#define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x00004000L 8023#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0x0000000e 8024#define MC_SEQ_DRAM_2__DLL_EST_MASK 0x00001000L 8025#define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0x0000000c 8026#define MC_SEQ_DRAM_2__DQM_EST_MASK 0x00000080L 8027#define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x00000007 8028#define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x01000000L 8029#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x00000018 8030#define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x00000800L 8031#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0x0000000b 8032#define MC_SEQ_DRAM_2__PLL_CNT_MASK 0x00ff0000L 8033#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x00000010 8034#define MC_SEQ_DRAM_2__PLL_EST_MASK 0x00000400L 8035#define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0x0000000a 8036#define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x00000040L 8037#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x00000006 8038#define MC_SEQ_DRAM_2__RD_DQS_MASK 0x00000100L 8039#define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x00000008 8040#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000L 8041#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x0000001e 8042#define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x00008000L 8043#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0x0000000f 8044#define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x00000020L 8045#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x00000005 8046#define MC_SEQ_DRAM_2__WR_DQS_MASK 0x00000200L 8047#define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x00000009 8048#define MC_SEQ_DRAM__ADR_2CK_MASK 0x00000001L 8049#define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x00000000 8050#define MC_SEQ_DRAM__ADR_DF1_MASK 0x00000004L 8051#define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x00000002 8052#define MC_SEQ_DRAM__ADR_MUX_MASK 0x00000002L 8053#define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x00000001 8054#define MC_SEQ_DRAM__AP8_MASK 0x00000008L 8055#define MC_SEQ_DRAM__AP8__SHIFT 0x00000003 8056#define MC_SEQ_DRAM__BO4_MASK 0x00004000L 8057#define MC_SEQ_DRAM__BO4__SHIFT 0x0000000e 8058#define MC_SEQ_DRAM__CKE_ACT_MASK 0x00002000L 8059#define MC_SEQ_DRAM__CKE_ACT__SHIFT 0x0000000d 8060#define MC_SEQ_DRAM__CKE_DYN_MASK 0x00001000L 8061#define MC_SEQ_DRAM__CKE_DYN__SHIFT 0x0000000c 8062#define MC_SEQ_DRAM__DAT_DF1_MASK 0x00000010L 8063#define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x00000004 8064#define MC_SEQ_DRAM__DAT_INV_MASK 0x01000000L 8065#define MC_SEQ_DRAM__DAT_INV__SHIFT 0x00000018 8066#define MC_SEQ_DRAM__DLL_CLR_MASK 0x00008000L 8067#define MC_SEQ_DRAM__DLL_CLR__SHIFT 0x0000000f 8068#define MC_SEQ_DRAM__DLL_CNT_MASK 0x00ff0000L 8069#define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x00000010 8070#define MC_SEQ_DRAM__DQM_ACT_MASK 0x00000080L 8071#define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x00000007 8072#define MC_SEQ_DRAM__DQM_DF1_MASK 0x00000040L 8073#define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x00000006 8074#define MC_SEQ_DRAM__DQS_DF1_MASK 0x00000020L 8075#define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x00000005 8076#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000L 8077#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x00000010 8078#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0x0000ffffL 8079#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x00000000 8080#define MC_SEQ_DRAM__INV_ACM_MASK 0x02000000L 8081#define MC_SEQ_DRAM__INV_ACM__SHIFT 0x00000019 8082#define MC_SEQ_DRAM__ODT_ACT_MASK 0x08000000L 8083#define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x0000001b 8084#define MC_SEQ_DRAM__ODT_ENB_MASK 0x04000000L 8085#define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x0000001a 8086#define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000L 8087#define MC_SEQ_DRAM__RST_CTL__SHIFT 0x0000001c 8088#define MC_SEQ_DRAM__STB_CNT_MASK 0x00000f00L 8089#define MC_SEQ_DRAM__STB_CNT__SHIFT 0x00000008 8090#define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000L 8091#define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x0000001e 8092#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000L 8093#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x0000001d 8094#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x00000100L 8095#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x00000008 8096#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x00000200L 8097#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x00000009 8098#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x00000030L 8099#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x00000004 8100#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0x000000c0L 8101#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x00000006 8102#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x00007000L 8103#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0x0000000c 8104#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x00030000L 8105#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x00000010 8106#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0x000c0000L 8107#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x00000012 8108#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x00000003L 8109#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x00000000 8110#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0x00000c00L 8111#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0x0000000a 8112#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0x0000000cL 8113#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x00000002 8114#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffffL 8115#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x00000000 8116#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x000001ffL 8117#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x00000000 8118#define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffffL 8119#define MC_SEQ_IO_RDBI__MASK__SHIFT 0x00000000 8120#define MC_SEQ_IO_REDC__EDC_MASK 0xffffffffL 8121#define MC_SEQ_IO_REDC__EDC__SHIFT 0x00000000 8122#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000L 8123#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x00000018 8124#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0x00000fffL 8125#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x00000000 8126#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0x00fff000L 8127#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0x0000000c 8128#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000L 8129#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x00000018 8130#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0x00000fffL 8131#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x00000000 8132#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0x00fff000L 8133#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0x0000000c 8134#define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffffL 8135#define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x00000000 8136#define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffffL 8137#define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x00000000 8138#define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffffL 8139#define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x00000000 8140#define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffffL 8141#define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x00000000 8142#define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffffL 8143#define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x00000000 8144#define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffffL 8145#define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x00000000 8146#define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffffL 8147#define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x00000000 8148#define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffffL 8149#define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x00000000 8150#define MC_SEQ_MISC0__VALUE_MASK 0xffffffffL 8151#define MC_SEQ_MISC0__VALUE__SHIFT 0x00000000 8152#define MC_SEQ_MISC1__VALUE_MASK 0xffffffffL 8153#define MC_SEQ_MISC1__VALUE__SHIFT 0x00000000 8154#define MC_SEQ_MISC3__VALUE_MASK 0xffffffffL 8155#define MC_SEQ_MISC3__VALUE__SHIFT 0x00000000 8156#define MC_SEQ_MISC4__VALUE_MASK 0xffffffffL 8157#define MC_SEQ_MISC4__VALUE__SHIFT 0x00000000 8158#define MC_SEQ_MISC5__VALUE_MASK 0xffffffffL 8159#define MC_SEQ_MISC5__VALUE__SHIFT 0x00000000 8160#define MC_SEQ_MISC6__VALUE_MASK 0xffffffffL 8161#define MC_SEQ_MISC6__VALUE__SHIFT 0x00000000 8162#define MC_SEQ_MISC7__VALUE_MASK 0xffffffffL 8163#define MC_SEQ_MISC7__VALUE__SHIFT 0x00000000 8164#define MC_SEQ_MISC8__VALUE_MASK 0xffffffffL 8165#define MC_SEQ_MISC8__VALUE__SHIFT 0x00000000 8166#define MC_SEQ_MISC9__VALUE_MASK 0xffffffffL 8167#define MC_SEQ_MISC9__VALUE__SHIFT 0x00000000 8168#define MC_SEQ_MISC_TIMING2__FAW_MASK 0x00001f00L 8169#define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x00000008 8170#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x00001f00L 8171#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x00000008 8172#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x00000007L 8173#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x00000000 8174#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x00000070L 8175#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x00000004 8176#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0x00e00000L 8177#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x00000015 8178#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0x0f000000L 8179#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x00000018 8180#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0x0000e000L 8181#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0x0000000d 8182#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000L 8183#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x0000001c 8184#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x001f0000L 8185#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x00000010 8186#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x00000007L 8187#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x00000000 8188#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x00000070L 8189#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x00000004 8190#define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x01e00000L 8191#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x00000015 8192#define MC_SEQ_MISC_TIMING2__TREDC_MASK 0x0000e000L 8193#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0x0000000d 8194#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000L 8195#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x0000001c 8196#define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x001f0000L 8197#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x00000010 8198#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000L 8199#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x00000014 8200#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0x000f8000L 8201#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x00003f00L 8202#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x00000008 8203#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0x0000000f 8204#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x0000003fL 8205#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x00000000 8206#define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000L 8207#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x00000014 8208#define MC_SEQ_MISC_TIMING__TRP_MASK 0x000f8000L 8209#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x00003f00L 8210#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x00000008 8211#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0x0000000f 8212#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x0000003fL 8213#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x00000000 8214#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x00000001L 8215#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x00000000 8216#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x00000020L 8217#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x00000005 8218#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x00000002L 8219#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x00000001 8220#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x00000004L 8221#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x00000002 8222#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x00000008L 8223#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x00000003 8224#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x00000010L 8225#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x00000004 8226#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x00000040L 8227#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x00000006 8228#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x00000080L 8229#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x00000007 8230#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x00000001L 8231#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x00000000 8232#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x00000100L 8233#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x00000008 8234#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x00000200L 8235#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x00000009 8236#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x00000400L 8237#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0x0000000a 8238#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x00000800L 8239#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0x0000000b 8240#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x00001000L 8241#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0x0000000c 8242#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x00002000L 8243#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0x0000000d 8244#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x00004000L 8245#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0x0000000e 8246#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x00008000L 8247#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0x0000000f 8248#define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000L 8249#define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x0000001e 8250#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffffL 8251#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x00000000 8252#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffffL 8253#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x00000000 8254#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffffL 8255#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x00000000 8256#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffffL 8257#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x00000000 8258#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffffL 8259#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x00000000 8260#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffffL 8261#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x00000000 8262#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffffL 8263#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x00000000 8264#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffffL 8265#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x00000000 8266#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffffL 8267#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x00000000 8268#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0x0000000fL 8269#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x00000000 8270#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0x000000f0L 8271#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x00000004 8272#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0x00000f00L 8273#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x00000008 8274#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0x0000f000L 8275#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0x0000000c 8276#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0x000f0000L 8277#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x00000010 8278#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0x00f00000L 8279#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x00000014 8280#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0x0f000000L 8281#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x00000018 8282#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000L 8283#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x0000001c 8284#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0x0000ffffL 8285#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000L 8286#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x0000001d 8287#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000L 8288#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x0000001c 8289#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x00000000 8290#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x00080000L 8291#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x00000013 8292#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x00600000L 8293#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x00000015 8294#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x00100000L 8295#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x00000014 8296#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x00070000L 8297#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x00000010 8298#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0x0000ffffL 8299#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000L 8300#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x0000001d 8301#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000L 8302#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x0000001c 8303#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x00000000 8304#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x00080000L 8305#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x00000013 8306#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x00600000L 8307#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x00000015 8308#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x00100000L 8309#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x00000014 8310#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x00070000L 8311#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x00000010 8312#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0x0000ffffL 8313#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000L 8314#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x0000001d 8315#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000L 8316#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x0000001c 8317#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x00000000 8318#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x00080000L 8319#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x00000013 8320#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x00600000L 8321#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x00000015 8322#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x00100000L 8323#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x00000014 8324#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x00070000L 8325#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x00000010 8326#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0x0000ffffL 8327#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000L 8328#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x0000001d 8329#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000L 8330#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x0000001c 8331#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x00000000 8332#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x00080000L 8333#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x00000013 8334#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x00600000L 8335#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x00000015 8336#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x00100000L 8337#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x00000014 8338#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x00070000L 8339#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x00000010 8340#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x00040000L 8341#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x00000012 8342#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x00000300L 8343#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x00000008 8344#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0x000000c0L 8345#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x00000006 8346#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x00003c00L 8347#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0x0000000a 8348#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x00000001L 8349#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x00000000 8350#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x00020000L 8351#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x00000011 8352#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x00000002L 8353#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x00000001 8354#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x0000003cL 8355#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x00000002 8356#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x00010000L 8357#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x00000010 8358#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000L 8359#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x0000001f 8360#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x00010000L 8361#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x00000010 8362#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x00000020L 8363#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x00000005 8364#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x00000002L 8365#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x00000001 8366#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x00000010L 8367#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x00000004 8368#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x00000001L 8369#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x00000000 8370#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x00000040L 8371#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x00000006 8372#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x00000004L 8373#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x00000002 8374#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x00000080L 8375#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x00000007 8376#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x00000008L 8377#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x00000003 8378#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x00002000L 8379#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0x0000000d 8380#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x00000200L 8381#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x00000009 8382#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x00001000L 8383#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0x0000000c 8384#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x00000100L 8385#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x00000008 8386#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x00004000L 8387#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0x0000000e 8388#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x00000400L 8389#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0x0000000a 8390#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x00008000L 8391#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0x0000000f 8392#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x00000800L 8393#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0x0000000b 8394#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000L 8395#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x0000001f 8396#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x00010000L 8397#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x00000010 8398#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x00000020L 8399#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x00000005 8400#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x00000002L 8401#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x00000001 8402#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x00000010L 8403#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x00000004 8404#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x00000001L 8405#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x00000000 8406#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x00000040L 8407#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x00000006 8408#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x00000004L 8409#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x00000002 8410#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x00000080L 8411#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x00000007 8412#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x00000008L 8413#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x00000003 8414#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x00002000L 8415#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0x0000000d 8416#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x00000200L 8417#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x00000009 8418#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x00001000L 8419#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0x0000000c 8420#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x00000100L 8421#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x00000008 8422#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x00004000L 8423#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0x0000000e 8424#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x00000400L 8425#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0x0000000a 8426#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x00008000L 8427#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0x0000000f 8428#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x00000800L 8429#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0x0000000b 8430#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x001c0000L 8431#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x00000012 8432#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000L 8433#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x00000018 8434#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x0003f000L 8435#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0x00000f00L 8436#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x00800000L 8437#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x00000017 8438#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x00000008 8439#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0x0000000c 8440#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x00000007L 8441#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x00000000 8442#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x00000070L 8443#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x00000004 8444#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x001c0000L 8445#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x00000012 8446#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000L 8447#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x00000018 8448#define MC_SEQ_PMG_TIMING__TCKE_MASK 0x0003f000L 8449#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0x00000f00L 8450#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x00800000L 8451#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x00000017 8452#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x00000008 8453#define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0x0000000c 8454#define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x00000007L 8455#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x00000000 8456#define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x00000070L 8457#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x00000004 8458#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0x000f8000L 8459#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0x0000000f 8460#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x00007c00L 8461#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0x0000000a 8462#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x000003e0L 8463#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x00000005 8464#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x0000001fL 8465#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x00000000 8466#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000L 8467#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x00000018 8468#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0x00f00000L 8469#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x00000014 8470#define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0x000f8000L 8471#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0x0000000f 8472#define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x00007c00L 8473#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0x0000000a 8474#define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x000003e0L 8475#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x00000005 8476#define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x0000001fL 8477#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x00000000 8478#define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000L 8479#define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x00000018 8480#define MC_SEQ_RAS_TIMING__TRRD_MASK 0x00f00000L 8481#define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x00000014 8482#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x01f00000L 8483#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x00000014 8484#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000L 8485#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x00000019 8486#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x00000007L 8487#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x00000000 8488#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0x000000f8L 8489#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x00000003 8490#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0x0000f000L 8491#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0x0000000c 8492#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x00000300L 8493#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x00000008 8494#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0x00000c00L 8495#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0x0000000a 8496#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x00010000L 8497#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x00000010 8498#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x00020000L 8499#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x00000011 8500#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x01f00000L 8501#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x00000014 8502#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000L 8503#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x00000019 8504#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x00000007L 8505#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x00000000 8506#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0x000000f8L 8507#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x00000003 8508#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0x0000f000L 8509#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0x0000000c 8510#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x00000300L 8511#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x00000008 8512#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0x00000c00L 8513#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0x0000000a 8514#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x00010000L 8515#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x00000010 8516#define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x00020000L 8517#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x00000011 8518#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x01f00000L 8519#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x00000014 8520#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000L 8521#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x00000019 8522#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x00000007L 8523#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x00000000 8524#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0x000000f8L 8525#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x00000003 8526#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0x0000f000L 8527#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0x0000000c 8528#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x00000300L 8529#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x00000008 8530#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0x00000c00L 8531#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0x0000000a 8532#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x00010000L 8533#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x00000010 8534#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x00020000L 8535#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x00000011 8536#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x01f00000L 8537#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x00000014 8538#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000L 8539#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x00000019 8540#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x00000007L 8541#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x00000000 8542#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0x000000f8L 8543#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x00000003 8544#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0x0000f000L 8545#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0x0000000c 8546#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x00000300L 8547#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x00000008 8548#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0x00000c00L 8549#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0x0000000a 8550#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x00010000L 8551#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x00000010 8552#define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x00020000L 8553#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x00000011 8554#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xffffffffL 8555#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x00000000 8556#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffffL 8557#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x00000000 8558#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffffL 8559#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x00000000 8560#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0x0000000fL 8561#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x00000000 8562#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0x000000f0L 8563#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x00000004 8564#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0x00000f00L 8565#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x00000008 8566#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0x0000f000L 8567#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0x0000000c 8568#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0x000f0000L 8569#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x00000010 8570#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0x00f00000L 8571#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x00000014 8572#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0x0f000000L 8573#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x00000018 8574#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000L 8575#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x0000001c 8576#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0x0000000fL 8577#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x00000000 8578#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0x000000f0L 8579#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x00000004 8580#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0x00000f00L 8581#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x00000008 8582#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0x0000f000L 8583#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0x0000000c 8584#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0x000f0000L 8585#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x00000010 8586#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0x00f00000L 8587#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x00000014 8588#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0x0f000000L 8589#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x00000018 8590#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000L 8591#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x0000001c 8592#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0x0000000fL 8593#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x00000000 8594#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0x000000f0L 8595#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x00000004 8596#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0x00000f00L 8597#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x00000008 8598#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0x0000f000L 8599#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0x0000000c 8600#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0x000f0000L 8601#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x00000010 8602#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0x00f00000L 8603#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x00000014 8604#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0x0f000000L 8605#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x00000018 8606#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000L 8607#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x0000001c 8608#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0x0000000fL 8609#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x00000000 8610#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0x000000f0L 8611#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x00000004 8612#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0x00000f00L 8613#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x00000008 8614#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0x0000f000L 8615#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0x0000000c 8616#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0x000f0000L 8617#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x00000010 8618#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0x00f00000L 8619#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x00000014 8620#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0x0f000000L 8621#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x00000018 8622#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000L 8623#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x0000001c 8624#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0x0000000fL 8625#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x00000000 8626#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0x000000f0L 8627#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x00000004 8628#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0x00000f00L 8629#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x00000008 8630#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0x0000f000L 8631#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0x0000000c 8632#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0x000f0000L 8633#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x00000010 8634#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0x00f00000L 8635#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x00000014 8636#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0x0f000000L 8637#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x00000018 8638#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000L 8639#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x0000001c 8640#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0x0000000fL 8641#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x00000000 8642#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0x000000f0L 8643#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x00000004 8644#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0x00000f00L 8645#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x00000008 8646#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0x0000f000L 8647#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0x0000000c 8648#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0x000f0000L 8649#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x00000010 8650#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0x00f00000L 8651#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x00000014 8652#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0x0f000000L 8653#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x00000018 8654#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000L 8655#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x0000001c 8656#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0x0000000fL 8657#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x00000000 8658#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0x000000f0L 8659#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x00000004 8660#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0x00000f00L 8661#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x00000008 8662#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0x0000f000L 8663#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0x0000000c 8664#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0x000f0000L 8665#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x00000010 8666#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0x00f00000L 8667#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x00000014 8668#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0x0f000000L 8669#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x00000018 8670#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000L 8671#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x0000001c 8672#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0x0000000fL 8673#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x00000000 8674#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0x000000f0L 8675#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x00000004 8676#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0x00000f00L 8677#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x00000008 8678#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0x0000f000L 8679#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0x0000000c 8680#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0x000f0000L 8681#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x00000010 8682#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0x00f00000L 8683#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x00000014 8684#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0x0f000000L 8685#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x00000018 8686#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000L 8687#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x0000001c 8688#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0x0000000fL 8689#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x00000000 8690#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0x000000f0L 8691#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x00000004 8692#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0x00000f00L 8693#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x00000008 8694#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0x0000f000L 8695#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0x0000000c 8696#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0x0000000fL 8697#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x00000000 8698#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0x000000f0L 8699#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x00000004 8700#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0x00000f00L 8701#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x00000008 8702#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0x0000f000L 8703#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0x0000000c 8704#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0x0000000fL 8705#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x00000000 8706#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0x000000f0L 8707#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x00000004 8708#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0x00000f00L 8709#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x00000008 8710#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0x0000f000L 8711#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0x0000000c 8712#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0x000f0000L 8713#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x00000010 8714#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0x00f00000L 8715#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x00000014 8716#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0x0f000000L 8717#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x00000018 8718#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000L 8719#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x0000001c 8720#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0x0000000fL 8721#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x00000000 8722#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0x000000f0L 8723#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x00000004 8724#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0x00000f00L 8725#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x00000008 8726#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0x0000f000L 8727#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0x0000000c 8728#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0x000f0000L 8729#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x00000010 8730#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0x00f00000L 8731#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x00000014 8732#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0x0f000000L 8733#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x00000018 8734#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000L 8735#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x0000001c 8736#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x00000004L 8737#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x00000002 8738#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x00000008L 8739#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x00000003 8740#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x01f00000L 8741#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x00000014 8742#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x00010000L 8743#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x00000010 8744#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x00000001L 8745#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x00000000 8746#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x00000002L 8747#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x00000001 8748#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x00000100L 8749#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x00000008 8750#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x02000000L 8751#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x00000019 8752#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x00004000L 8753#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0x0000000e 8754#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x00001000L 8755#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0x0000000c 8756#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x00000200L 8757#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x00000009 8758#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x04000000L 8759#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x0000001a 8760#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x00008000L 8761#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0x0000000f 8762#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x00002000L 8763#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0x0000000d 8764#define MC_SEQ_STATUS_M__SLF_D0_MASK 0x00000010L 8765#define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x00000004 8766#define MC_SEQ_STATUS_M__SLF_D1_MASK 0x00000020L 8767#define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x00000005 8768#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x00000040L 8769#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x00000006 8770#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x00000080L 8771#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x00000007 8772#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x00000010L 8773#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x00000004 8774#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x00000001L 8775#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x00000000 8776#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x00000100L 8777#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x00000008 8778#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x00000020L 8779#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x00000005 8780#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x00000002L 8781#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x00000001 8782#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x00000200L 8783#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x00000009 8784#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x00000080L 8785#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x00000007 8786#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x00000040L 8787#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x00000006 8788#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000L 8789#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x00000017 8790#define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x00000020L 8791#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x00000005 8792#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x00000010L 8793#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x00000004 8794#define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x00000008L 8795#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x00000003 8796#define MC_SEQ_SUP_CNTL__RUN_MASK 0x00000001L 8797#define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x00000000 8798#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x00000002L 8799#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x00000001 8800#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x00000004L 8801#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x00000002 8802#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffffL 8803#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x00000000 8804#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffffL 8805#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x00000000 8806#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffffL 8807#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x00000000 8808#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffffL 8809#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x00000000 8810#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffffL 8811#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x00000000 8812#define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffffL 8813#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x00000000 8814#define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffffL 8815#define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x00000000 8816#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffffL 8817#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x00000000 8818#define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffffL 8819#define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x00000000 8820#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x04000000L 8821#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x0000001a 8822#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x02000000L 8823#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x00000019 8824#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x00380000L 8825#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x00000013 8826#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0x0000f000L 8827#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0x0000000c 8828#define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000L 8829#define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x0000001f 8830#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x00000002L 8831#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x00000001 8832#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x00000004L 8833#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x00000002 8834#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x00040000L 8835#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x00000012 8836#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x00000080L 8837#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x00000007 8838#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x00400000L 8839#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x00000016 8840#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x00010000L 8841#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x00000010 8842#define MC_SEQ_TCG_CNTL__MOP_MASK 0x00000f00L 8843#define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x00000008 8844#define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x00000070L 8845#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x00000004 8846#define MC_SEQ_TCG_CNTL__RESET_MASK 0x00000001L 8847#define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x00000000 8848#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x00020000L 8849#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x00000011 8850#define MC_SEQ_TCG_CNTL__START_MASK 0x00000008L 8851#define MC_SEQ_TCG_CNTL__START__SHIFT 0x00000003 8852#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x00800000L 8853#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x00000017 8854#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x01000000L 8855#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x00000018 8856#define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffffL 8857#define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x00000000 8858#define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffffL 8859#define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x00000000 8860#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x00040000L 8861#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 8862#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x00080000L 8863#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 8864#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L 8865#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 8866#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L 8867#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 8868#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x00000001L 8869#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x00000000 8870#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L 8871#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 8872#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L 8873#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a 8874#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x01000000L 8875#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x00000018 8876#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x00000004L 8877#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x00000002 8878#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x00000010L 8879#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x00000004 8880#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x00000002L 8881#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x00000001 8882#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L 8883#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 8884#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L 8885#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b 8886#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x02000000L 8887#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x00000019 8888#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x00000008L 8889#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x00000003 8890#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x00000020L 8891#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x00000005 8892#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x00800000L 8893#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x00000017 8894#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x00100000L 8895#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x00000014 8896#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L 8897#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 8898#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x04000000L 8899#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x0000001a 8900#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x00002000L 8901#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0x0000000d 8902#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L 8903#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 8904#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L 8905#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c 8906#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x00020000L 8907#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x00000011 8908#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x00008000L 8909#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0x0000000f 8910#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x00004000L 8911#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0x0000000e 8912#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffffL 8913#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x00000000 8914#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x00000100L 8915#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x00000008 8916#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x00000001L 8917#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x00000000 8918#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x00000200L 8919#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x00000009 8920#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x00000002L 8921#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x00000001 8922#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x00000004L 8923#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x00000002 8924#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x00000030L 8925#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x00000004 8926#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x00000008L 8927#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x00000003 8928#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000L 8929#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x00000010 8930#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0x0000ffffL 8931#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x00000000 8932#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x000003e0L 8933#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x00000005 8934#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0x000f8000L 8935#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0x0000000f 8936#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x00007c00L 8937#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0x0000000a 8938#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x0000001fL 8939#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x00000000 8940#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x00040000L 8941#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 8942#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x00080000L 8943#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 8944#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L 8945#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 8946#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L 8947#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 8948#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x00010000L 8949#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x00000010 8950#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x00000001L 8951#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x00000000 8952#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L 8953#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 8954#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L 8955#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a 8956#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x01000000L 8957#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x00000018 8958#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x00000004L 8959#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x00000002 8960#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x00000010L 8961#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x00000004 8962#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x00000002L 8963#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x00000001 8964#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L 8965#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 8966#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L 8967#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b 8968#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x02000000L 8969#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x00000019 8970#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x00000008L 8971#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x00000003 8972#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x00000020L 8973#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x00000005 8974#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x00800000L 8975#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x00000017 8976#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x00100000L 8977#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x00000014 8978#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L 8979#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 8980#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x04000000L 8981#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x0000001a 8982#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x00002000L 8983#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0x0000000d 8984#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L 8985#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 8986#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L 8987#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c 8988#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x00020000L 8989#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x00000011 8990#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x00008000L 8991#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0x0000000f 8992#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x00004000L 8993#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0x0000000e 8994#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x00000100L 8995#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x00000008 8996#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x00000400L 8997#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0x0000000a 8998#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x00100000L 8999#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x00000014 9000#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x00000200L 9001#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x00000009 9002#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x00000800L 9003#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0x0000000b 9004#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x01000000L 9005#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x00000018 9006#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x04000000L 9007#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x0000001a 9008#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x02000000L 9009#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x00000019 9010#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x08000000L 9011#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x0000001b 9012#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x00000001L 9013#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x00000000 9014#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x00000004L 9015#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x00000002 9016#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x00000002L 9017#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x00000001 9018#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x00000008L 9019#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x00000003 9020#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000L 9021#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x0000001d 9022#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x00010000L 9023#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x00000010 9024#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x00040000L 9025#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x00000012 9026#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x00020000L 9027#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x00000011 9028#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x00080000L 9029#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x00000013 9030#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x00000010L 9031#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x00000004 9032#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x00000040L 9033#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x00000006 9034#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x00000020L 9035#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x00000005 9036#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x00000080L 9037#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x00000007 9038#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x00200000L 9039#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x00000015 9040#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x00400000L 9041#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x00000016 9042#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000L 9043#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x0000001c 9044#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000L 9045#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x0000001e 9046#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000L 9047#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x0000001f 9048#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x00001000L 9049#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0x0000000c 9050#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x00004000L 9051#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0x0000000e 9052#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x00002000L 9053#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0x0000000d 9054#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x00008000L 9055#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0x0000000f 9056#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x00040000L 9057#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 9058#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x00080000L 9059#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 9060#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L 9061#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 9062#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L 9063#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 9064#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x00000001L 9065#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x00000000 9066#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L 9067#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 9068#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L 9069#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a 9070#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x01000000L 9071#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x00000018 9072#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x00000004L 9073#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x00000002 9074#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x00000010L 9075#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x00000004 9076#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x00000002L 9077#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x00000001 9078#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L 9079#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 9080#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L 9081#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b 9082#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x02000000L 9083#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x00000019 9084#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x00000008L 9085#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x00000003 9086#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x00000020L 9087#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x00000005 9088#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x00800000L 9089#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x00000017 9090#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x00100000L 9091#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x00000014 9092#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L 9093#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 9094#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x04000000L 9095#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x0000001a 9096#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x00002000L 9097#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0x0000000d 9098#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L 9099#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 9100#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L 9101#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c 9102#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x00020000L 9103#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x00000011 9104#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x00008000L 9105#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0x0000000f 9106#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x00004000L 9107#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0x0000000e 9108#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x00040000L 9109#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 9110#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x00080000L 9111#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 9112#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L 9113#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 9114#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L 9115#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 9116#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x00000001L 9117#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x00000000 9118#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L 9119#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 9120#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L 9121#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a 9122#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x01000000L 9123#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x00000018 9124#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x00000004L 9125#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x00000002 9126#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x00000010L 9127#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x00000004 9128#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x00000002L 9129#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x00000001 9130#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L 9131#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 9132#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L 9133#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b 9134#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x02000000L 9135#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x00000019 9136#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x00000008L 9137#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x00000003 9138#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x00000020L 9139#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x00000005 9140#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x00800000L 9141#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x00000017 9142#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x00100000L 9143#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x00000014 9144#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L 9145#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 9146#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x04000000L 9147#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x0000001a 9148#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x00002000L 9149#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0x0000000d 9150#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L 9151#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 9152#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L 9153#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c 9154#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x00020000L 9155#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x00000011 9156#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x00008000L 9157#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0x0000000f 9158#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x00004000L 9159#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0x0000000e 9160#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0x0000ff00L 9161#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x00000008 9162#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0x00ff0000L 9163#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x00000010 9164#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000L 9165#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x00000018 9166#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0x000000f0L 9167#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x00000004 9168#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0x0000000fL 9169#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x00000000 9170#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x00000002L 9171#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x00000001 9172#define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x00000020L 9173#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x00000005 9174#define MC_SEQ_TSM_CTRL__DONE_MASK 0x00000004L 9175#define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x00000002 9176#define MC_SEQ_TSM_CTRL__ERR_MASK 0x00000008L 9177#define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x00000003 9178#define MC_SEQ_TSM_CTRL__INVERT_MASK 0x00000040L 9179#define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x00000006 9180#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x00000080L 9181#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x00000007 9182#define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000L 9183#define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x00000010 9184#define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x00000400L 9185#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0x0000000a 9186#define MC_SEQ_TSM_CTRL__START_MASK 0x00000001L 9187#define MC_SEQ_TSM_CTRL__START__SHIFT 0x00000000 9188#define MC_SEQ_TSM_CTRL__STEP_MASK 0x00000010L 9189#define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x00000004 9190#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x00000300L 9191#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x00000008 9192#define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffffL 9193#define MC_SEQ_TSM_DBI__DBI__SHIFT 0x00000000 9194#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffffL 9195#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x00000000 9196#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x0000001fL 9197#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x00000000 9198#define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffffL 9199#define MC_SEQ_TSM_EDC__EDC__SHIFT 0x00000000 9200#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000L 9201#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x00000018 9202#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0x000000f0L 9203#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x00000004 9204#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0x0000ff00L 9205#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x00000008 9206#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0x000f0000L 9207#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x00000010 9208#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0x0000000fL 9209#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x00000000 9210#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000L 9211#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x00000010 9212#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0x000000f0L 9213#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x00000004 9214#define MC_SEQ_TSM_GCNT__TESTS_MASK 0x0000ff00L 9215#define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x00000008 9216#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0x0000000fL 9217#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x00000000 9218#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0x000f0000L 9219#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x00000010 9220#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0x0000ffffL 9221#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x00000000 9222#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0x000000f0L 9223#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x00000004 9224#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0x0f000000L 9225#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x00000018 9226#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0x00f00000L 9227#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x00000014 9228#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0x000f0000L 9229#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x00000010 9230#define MC_SEQ_TSM_NCNT__TESTS_MASK 0x0000ff00L 9231#define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x00000008 9232#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0x0000000fL 9233#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x00000000 9234#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000L 9235#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x00000010 9236#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0x000000f0L 9237#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x00000004 9238#define MC_SEQ_TSM_OCNT__TESTS_MASK 0x0000ff00L 9239#define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x00000008 9240#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0x0000000fL 9241#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x00000000 9242#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0x00ff0000L 9243#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x00000010 9244#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000L 9245#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x00000018 9246#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0x000000f0L 9247#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x00000004 9248#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0x0000000fL 9249#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x00000000 9250#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0x0000ff00L 9251#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x00000008 9252#define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffffL 9253#define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x00000000 9254#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0x0000000fL 9255#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x00000000 9256#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0x000000f0L 9257#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x00000004 9258#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0x00000f00L 9259#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x00000008 9260#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0x0000f000L 9261#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0x0000000c 9262#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0x000f0000L 9263#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x00000010 9264#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0x00f00000L 9265#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x00000014 9266#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0x0f000000L 9267#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x00000018 9268#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000L 9269#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x0000001c 9270#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0x0000000fL 9271#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x00000000 9272#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0x000000f0L 9273#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x00000004 9274#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0x00000f00L 9275#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x00000008 9276#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0x0000f000L 9277#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0x0000000c 9278#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0x000f0000L 9279#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x00000010 9280#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0x00f00000L 9281#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x00000014 9282#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0x0f000000L 9283#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x00000018 9284#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000L 9285#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x0000001c 9286#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0x0000000fL 9287#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x00000000 9288#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0x000000f0L 9289#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x00000004 9290#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0x00000f00L 9291#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x00000008 9292#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0x0000f000L 9293#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0x0000000c 9294#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0x000f0000L 9295#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x00000010 9296#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0x00f00000L 9297#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x00000014 9298#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0x0f000000L 9299#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x00000018 9300#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000L 9301#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x0000001c 9302#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0x0000000fL 9303#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x00000000 9304#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0x000000f0L 9305#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x00000004 9306#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0x00000f00L 9307#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x00000008 9308#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0x0000f000L 9309#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0x0000000c 9310#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0x000f0000L 9311#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x00000010 9312#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0x00f00000L 9313#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x00000014 9314#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0x0f000000L 9315#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x00000018 9316#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000L 9317#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x0000001c 9318#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0x0000000fL 9319#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x00000000 9320#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0x000000f0L 9321#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x00000004 9322#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0x00000f00L 9323#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x00000008 9324#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0x0000f000L 9325#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0x0000000c 9326#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0x000f0000L 9327#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x00000010 9328#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0x00f00000L 9329#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x00000014 9330#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0x0f000000L 9331#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x00000018 9332#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000L 9333#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x0000001c 9334#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0x0000000fL 9335#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x00000000 9336#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0x000000f0L 9337#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x00000004 9338#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0x00000f00L 9339#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x00000008 9340#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0x0000f000L 9341#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0x0000000c 9342#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0x000f0000L 9343#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x00000010 9344#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0x00f00000L 9345#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x00000014 9346#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0x0f000000L 9347#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x00000018 9348#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000L 9349#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x0000001c 9350#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0x0000000fL 9351#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x00000000 9352#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0x000000f0L 9353#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x00000004 9354#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0x00000f00L 9355#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x00000008 9356#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0x0000f000L 9357#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0x0000000c 9358#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0x000f0000L 9359#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x00000010 9360#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0x00f00000L 9361#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x00000014 9362#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0x0f000000L 9363#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x00000018 9364#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000L 9365#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x0000001c 9366#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0x0000000fL 9367#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x00000000 9368#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0x000000f0L 9369#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x00000004 9370#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0x00000f00L 9371#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x00000008 9372#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0x0000f000L 9373#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0x0000000c 9374#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0x000f0000L 9375#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x00000010 9376#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0x00f00000L 9377#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x00000014 9378#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0x0f000000L 9379#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x00000018 9380#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000L 9381#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x0000001c 9382#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0x0000000fL 9383#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x00000000 9384#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0x000000f0L 9385#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x00000004 9386#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0x00000f00L 9387#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x00000008 9388#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0x0000f000L 9389#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0x0000000c 9390#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0x0000000fL 9391#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x00000000 9392#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0x000000f0L 9393#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x00000004 9394#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0x00000f00L 9395#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x00000008 9396#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0x0000f000L 9397#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0x0000000c 9398#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0x0000000fL 9399#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x00000000 9400#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0x000000f0L 9401#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x00000004 9402#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0x00000f00L 9403#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x00000008 9404#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0x0000f000L 9405#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0x0000000c 9406#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0x000f0000L 9407#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x00000010 9408#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0x00f00000L 9409#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x00000014 9410#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0x0f000000L 9411#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x00000018 9412#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000L 9413#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x0000001c 9414#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0x0000000fL 9415#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x00000000 9416#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0x000000f0L 9417#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x00000004 9418#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0x00000f00L 9419#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x00000008 9420#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0x0000f000L 9421#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0x0000000c 9422#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0x000f0000L 9423#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x00000010 9424#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0x00f00000L 9425#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x00000014 9426#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0x0f000000L 9427#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x00000018 9428#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000L 9429#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x0000001c 9430#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0x0000000fL 9431#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x00000000 9432#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0x000000f0L 9433#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x00000004 9434#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0x00000f00L 9435#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x00000008 9436#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0x0000f000L 9437#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0x0000000c 9438#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0x0000000fL 9439#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x00000000 9440#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0x000000f0L 9441#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x00000004 9442#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0x00000f00L 9443#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x00000008 9444#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0x0000f000L 9445#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0x0000000c 9446#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffffL 9447#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x00000000 9448#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffffL 9449#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x00000000 9450#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x00004000L 9451#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0x0000000e 9452#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x00100000L 9453#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x00000014 9454#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x00200000L 9455#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x00000015 9456#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0x0f000000L 9457#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x00000018 9458#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000L 9459#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x0000001c 9460#define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x00002000L 9461#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0x0000000d 9462#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x00008000L 9463#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0x0000000f 9464#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0x000f0000L 9465#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x00000010 9466#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0x000000ffL 9467#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x00000000 9468#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0x00000f00L 9469#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x00000008 9470#define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x00001000L 9471#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0x0000000c 9472#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x00000001L 9473#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x00000000 9474#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x00000008L 9475#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x00000003 9476#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x00000002L 9477#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x00000001 9478#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x00000010L 9479#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x00000004 9480#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x00000001L 9481#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x00000000 9482#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x00000008L 9483#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x00000003 9484#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x00000002L 9485#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x00000001 9486#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x00000010L 9487#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x00000004 9488#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x00000004L 9489#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x00000002 9490#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x00000020L 9491#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x00000005 9492#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x00000040L 9493#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x00000006 9494#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x00000004L 9495#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x00000002 9496#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x00000020L 9497#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x00000005 9498#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x00000040L 9499#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x00000006 9500#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x00000400L 9501#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0x0000000a 9502#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000L 9503#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x0000001d 9504#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x00000800L 9505#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0x0000000b 9506#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000L 9507#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x0000001e 9508#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x00000200L 9509#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x00000009 9510#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0x0000000fL 9511#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x00000000 9512#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0x000000f0L 9513#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x00000004 9514#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x00000100L 9515#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x00000008 9516#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x00000400L 9517#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0x0000000a 9518#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000L 9519#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x0000001d 9520#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x00000800L 9521#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0x0000000b 9522#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000L 9523#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x0000001e 9524#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x00000200L 9525#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x00000009 9526#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0x0000000fL 9527#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x00000000 9528#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0x000000f0L 9529#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x00000004 9530#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x00000100L 9531#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x00000008 9532#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0x0f000000L 9533#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x00000018 9534#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000L 9535#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x0000001c 9536#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0x0000f000L 9537#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0x0000000c 9538#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0x000f0000L 9539#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x00000010 9540#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x00300000L 9541#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x00000014 9542#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0x0f000000L 9543#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x00000018 9544#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000L 9545#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x0000001c 9546#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0x0000f000L 9547#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0x0000000c 9548#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0x000f0000L 9549#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x00000010 9550#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x00300000L 9551#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x00000014 9552#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x00000400L 9553#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0x0000000a 9554#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000L 9555#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x0000001d 9556#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x00000800L 9557#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0x0000000b 9558#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000L 9559#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x0000001e 9560#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x00000200L 9561#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x00000009 9562#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0x0000000fL 9563#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x00000000 9564#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0x000000f0L 9565#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x00000004 9566#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x00000100L 9567#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x00000008 9568#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x00000400L 9569#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0x0000000a 9570#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000L 9571#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x0000001d 9572#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x00000800L 9573#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0x0000000b 9574#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000L 9575#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x0000001e 9576#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x00000200L 9577#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x00000009 9578#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0x0000000fL 9579#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x00000000 9580#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0x000000f0L 9581#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x00000004 9582#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x00000100L 9583#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x00000008 9584#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0x0f000000L 9585#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x00000018 9586#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000L 9587#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x0000001c 9588#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0x0000f000L 9589#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0x0000000c 9590#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0x000f0000L 9591#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x00000010 9592#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x00300000L 9593#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x00000014 9594#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0x0f000000L 9595#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x00000018 9596#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000L 9597#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x0000001c 9598#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0x0000f000L 9599#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0x0000000c 9600#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0x000f0000L 9601#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x00000010 9602#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x00300000L 9603#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x00000014 9604#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x00000007L 9605#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x00000000 9606#define MC_SHARED_CHMAP__CHAN0_MASK 0x0000000fL 9607#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x00000000 9608#define MC_SHARED_CHMAP__CHAN1_MASK 0x000000f0L 9609#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x00000004 9610#define MC_SHARED_CHMAP__CHAN2_MASK 0x00000f00L 9611#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x00000008 9612#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0x0000f000L 9613#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0x0000000c 9614#define MC_SHARED_CHREMAP__CHAN0_MASK 0x00000007L 9615#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x00000000 9616#define MC_SHARED_CHREMAP__CHAN1_MASK 0x00000038L 9617#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x00000003 9618#define MC_SHARED_CHREMAP__CHAN2_MASK 0x000001c0L 9619#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x00000006 9620#define MC_SHARED_CHREMAP__CHAN3_MASK 0x00000e00L 9621#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0x00000009 9622#define MC_SHARED_CHREMAP__CHAN4_MASK 0x00007000L 9623#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x0000000c 9624#define MC_SHARED_CHREMAP__CHAN5_MASK 0x00038000L 9625#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x0000000f 9626#define MC_SHARED_CHREMAP__CHAN6_MASK 0x001c0000L 9627#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x00000012 9628#define MC_SHARED_CHREMAP__CHAN7_MASK 0x00e00000L 9629#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x00000015 9630#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0x000000ffL 9631#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x00000000 9632#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0x0000ff00L 9633#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x00000008 9634#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0x00ff0000L 9635#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x00000010 9636#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000L 9637#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x00000018 9638#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0x000000ffL 9639#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x00000000 9640#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0x0000ff00L 9641#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x00000008 9642#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0x00ff0000L 9643#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x00000010 9644#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000L 9645#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x00000018 9646#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000L 9647#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x00000010 9648#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0x0000ffffL 9649#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x00000000 9650#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000L 9651#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x00000010 9652#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0x0000ffffL 9653#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x00000000 9654#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffffL 9655#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x00000000 9656#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffffL 9657#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x00000000 9658#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0x0000000fL 9659#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x00000000 9660#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0x000000f0L 9661#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x00000004 9662#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000L 9663#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x0000001c 9664#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000L 9665#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x0000001d 9666#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000L 9667#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x0000001e 9668#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0x0000f000L 9669#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0x0000000c 9670#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0x00000f00L 9671#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x00000008 9672#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0x0000000fL 9673#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x00000000 9674#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0x000000f0L 9675#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x00000004 9676#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000L 9677#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x0000001c 9678#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000L 9679#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x0000001d 9680#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000L 9681#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x0000001e 9682#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0x0000f000L 9683#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0x0000000c 9684#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0x00000f00L 9685#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x00000008 9686#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000L 9687#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x0000001c 9688#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x03ff0000L 9689#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x00000010 9690#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x00000400L 9691#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0x0000000a 9692#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x00000002L 9693#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x00000001 9694#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x00000100L 9695#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x00000008 9696#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x00000001L 9697#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x00000000 9698#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x00000030L 9699#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x00000004 9700#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x00000200L 9701#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x00000009 9702#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x00000800L 9703#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0x0000000b 9704#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000L 9705#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x0000001c 9706#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x03ff0000L 9707#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x00000010 9708#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x00000400L 9709#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0x0000000a 9710#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x00000002L 9711#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x00000001 9712#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x00000100L 9713#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x00000008 9714#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x00000001L 9715#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x00000000 9716#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x00000030L 9717#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x00000004 9718#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x00000200L 9719#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x00000009 9720#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x00000800L 9721#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0x0000000b 9722#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0x000000ffL 9723#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x00000000 9724#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0x0000ff00L 9725#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x00000008 9726#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0x00ff0000L 9727#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x00000010 9728#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000L 9729#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x00000018 9730#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0x000000ffL 9731#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x00000000 9732#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0x0000ff00L 9733#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x00000008 9734#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0x00ff0000L 9735#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x00000010 9736#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000L 9737#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x00000018 9738#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0x000000ffL 9739#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x00000000 9740#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0x0000ff00L 9741#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x00000008 9742#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0x00ff0000L 9743#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x00000010 9744#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000L 9745#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x00000018 9746#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0x000000ffL 9747#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x00000000 9748#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0x0000ff00L 9749#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x00000008 9750#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0x00ff0000L 9751#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x00000010 9752#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000L 9753#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x00000018 9754#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0x000000ffL 9755#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x00000000 9756#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0x0000ff00L 9757#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x00000008 9758#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0x00ff0000L 9759#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x00000010 9760#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000L 9761#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x00000018 9762#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0x000000ffL 9763#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x00000000 9764#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0x0000ff00L 9765#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x00000008 9766#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0x00ff0000L 9767#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x00000010 9768#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000L 9769#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x00000018 9770#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0x000000ffL 9771#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x00000000 9772#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0x0000ff00L 9773#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x00000008 9774#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0x00ff0000L 9775#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x00000010 9776#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000L 9777#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x00000018 9778#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0x000000ffL 9779#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x00000000 9780#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0x0000ff00L 9781#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x00000008 9782#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0x00ff0000L 9783#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x00000010 9784#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000L 9785#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x00000018 9786#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0x000000ffL 9787#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x00000000 9788#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0x0000ff00L 9789#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x00000008 9790#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0x00ff0000L 9791#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x00000010 9792#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000L 9793#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x00000018 9794#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0x000000ffL 9795#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x00000000 9796#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0x0000ff00L 9797#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x00000008 9798#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0x00ff0000L 9799#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x00000010 9800#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000L 9801#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x00000018 9802#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0x000000ffL 9803#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x00000000 9804#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0x0000ff00L 9805#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x00000008 9806#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0x00ff0000L 9807#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x00000010 9808#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000L 9809#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x00000018 9810#define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffffL 9811#define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x00000000 9812#define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffffL 9813#define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x00000000 9814#define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffffL 9815#define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x00000000 9816#define MC_TSM_DEBUG_MISC__FLAG_MASK 0x000000ffL 9817#define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x00000000 9818#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0x00000f00L 9819#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x00000008 9820#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0x0000f000L 9821#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0x0000000c 9822#define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffffL 9823#define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x00000000 9824#define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffffL 9825#define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x00000000 9826#define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffffL 9827#define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x00000000 9828#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x0003ffffL 9829#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x00000000 9830#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x0003ffffL 9831#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x00000000 9832#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x0003ffffL 9833#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x00000000 9834#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x00000100L 9835#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x00000008 9836#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x00000200L 9837#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x00000009 9838#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x00000003L 9839#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x00000000 9840#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0x0000000cL 9841#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x00000002 9842#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x00000030L 9843#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x00000004 9844#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0x000000c0L 9845#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x00000006 9846#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL 9847#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 9848#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL 9849#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 9850#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL 9851#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 9852#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL 9853#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 9854#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL 9855#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 9856#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL 9857#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 9858#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL 9859#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 9860#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL 9861#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 9862#define MC_VM_FB_LOCATION__FB_BASE_MASK 0x0000ffffL 9863#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x00000000 9864#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000L 9865#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x00000010 9866#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x0003ffffL 9867#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x00000000 9868#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L 9869#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c 9870#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L 9871#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 9872#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L 9873#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 9874#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L 9875#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f 9876#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L 9877#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 9878#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 9879#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x00000000 9880#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 9881#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x00000000 9882#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L 9883#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c 9884#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L 9885#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 9886#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L 9887#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 9888#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L 9889#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f 9890#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L 9891#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 9892#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 9893#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x00000000 9894#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L 9895#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c 9896#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L 9897#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 9898#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L 9899#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 9900#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L 9901#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f 9902#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L 9903#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 9904#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 9905#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x00000000 9906#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x0000003fL 9907#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x00000000 9908#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L 9909#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c 9910#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L 9911#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 9912#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L 9913#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 9914#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L 9915#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f 9916#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L 9917#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 9918#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 9919#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x00000000 9920#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L 9921#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c 9922#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L 9923#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 9924#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L 9925#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 9926#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L 9927#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f 9928#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L 9929#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 9930#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 9931#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x00000000 9932#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L 9933#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c 9934#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L 9935#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 9936#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L 9937#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 9938#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L 9939#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f 9940#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L 9941#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 9942#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 9943#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x00000000 9944#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L 9945#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c 9946#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L 9947#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 9948#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L 9949#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 9950#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L 9951#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f 9952#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L 9953#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 9954#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 9955#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x00000000 9956#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x0000003fL 9957#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x00000000 9958#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 9959#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x00000007 9960#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 9961#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x00000006 9962#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x00000002L 9963#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x00000001 9964#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 9965#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x00000000 9966#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 9967#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x00000003 9968#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 9969#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x00000005 9970#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 9971#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 9972#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 9973#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 9974#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 9975#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 9976#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x00000008L 9977#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x00000003 9978#define MC_WR_CB__ENABLE_MASK 0x00000001L 9979#define MC_WR_CB__ENABLE__SHIFT 0x00000000 9980#define MC_WR_CB__LAZY_TIMER_MASK 0x00007800L 9981#define MC_WR_CB__LAZY_TIMER__SHIFT 0x0000000b 9982#define MC_WR_CB__MAX_BURST_MASK 0x00000780L 9983#define MC_WR_CB__MAX_BURST__SHIFT 0x00000007 9984#define MC_WR_CB__PRESCALE_MASK 0x00000006L 9985#define MC_WR_CB__PRESCALE__SHIFT 0x00000001 9986#define MC_WR_CB__STALL_MODE_MASK 0x00000030L 9987#define MC_WR_CB__STALL_MODE__SHIFT 0x00000004 9988#define MC_WR_CB__STALL_OVERRIDE_MASK 0x00000040L 9989#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x00000006 9990#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x00008000L 9991#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 9992#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x00000008L 9993#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x00000003 9994#define MC_WR_DB__ENABLE_MASK 0x00000001L 9995#define MC_WR_DB__ENABLE__SHIFT 0x00000000 9996#define MC_WR_DB__LAZY_TIMER_MASK 0x00007800L 9997#define MC_WR_DB__LAZY_TIMER__SHIFT 0x0000000b 9998#define MC_WR_DB__MAX_BURST_MASK 0x00000780L 9999#define MC_WR_DB__MAX_BURST__SHIFT 0x00000007 10000#define MC_WR_DB__PRESCALE_MASK 0x00000006L 10001#define MC_WR_DB__PRESCALE__SHIFT 0x00000001 10002#define MC_WR_DB__STALL_MODE_MASK 0x00000030L 10003#define MC_WR_DB__STALL_MODE__SHIFT 0x00000004 10004#define MC_WR_DB__STALL_OVERRIDE_MASK 0x00000040L 10005#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x00000006 10006#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x00008000L 10007#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 10008#define MC_WR_GRP_EXT__DBSTEN0_MASK 0x0000000fL 10009#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x00000000 10010#define MC_WR_GRP_EXT__TC0_MASK 0x000000f0L 10011#define MC_WR_GRP_EXT__TC0__SHIFT 0x00000004 10012#define MC_WR_GRP_GFX__CP_MASK 0x0000000fL 10013#define MC_WR_GRP_GFX__CP__SHIFT 0x00000000 10014#define MC_WR_GRP_GFX__XDMA_MASK 0x0000f000L 10015#define MC_WR_GRP_GFX__XDMAM_MASK 0x000f0000L 10016#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x00000010 10017#define MC_WR_GRP_GFX__XDMA__SHIFT 0x0000000c 10018#define MC_WR_GRP_LCL__CB0_MASK 0x0000000fL 10019#define MC_WR_GRP_LCL__CB0__SHIFT 0x00000000 10020#define MC_WR_GRP_LCL__CBCMASK0_MASK 0x000000f0L 10021#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x00000004 10022#define MC_WR_GRP_LCL__CBFMASK0_MASK 0x00000f00L 10023#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x00000008 10024#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000L 10025#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x0000001c 10026#define MC_WR_GRP_LCL__DB0_MASK 0x0000f000L 10027#define MC_WR_GRP_LCL__DB0__SHIFT 0x0000000c 10028#define MC_WR_GRP_LCL__DBHTILE0_MASK 0x000f0000L 10029#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x00000010 10030#define MC_WR_GRP_LCL__SX0_MASK 0x00f00000L 10031#define MC_WR_GRP_LCL__SX0__SHIFT 0x00000014 10032#define MC_WR_GRP_OTH__HDP_MASK 0x00000f00L 10033#define MC_WR_GRP_OTH__HDP__SHIFT 0x00000008 10034#define MC_WR_GRP_OTH__SEM_MASK 0x0000f000L 10035#define MC_WR_GRP_OTH__SEM__SHIFT 0x0000000c 10036#define MC_WR_GRP_OTH__UMC_MASK 0x000f0000L 10037#define MC_WR_GRP_OTH__UMC__SHIFT 0x00000010 10038#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0x0000000fL 10039#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x00000000 10040#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000L 10041#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x0000001c 10042#define MC_WR_GRP_OTH__UVD_MASK 0x00f00000L 10043#define MC_WR_GRP_OTH__UVD__SHIFT 0x00000014 10044#define MC_WR_GRP_OTH__XDP_MASK 0x0f000000L 10045#define MC_WR_GRP_OTH__XDP__SHIFT 0x00000018 10046#define MC_WR_GRP_SYS__IH_MASK 0x0000000fL 10047#define MC_WR_GRP_SYS__IH__SHIFT 0x00000000 10048#define MC_WR_GRP_SYS__MCIF_MASK 0x000000f0L 10049#define MC_WR_GRP_SYS__MCIF__SHIFT 0x00000004 10050#define MC_WR_GRP_SYS__RLC_MASK 0x00000f00L 10051#define MC_WR_GRP_SYS__RLC__SHIFT 0x00000008 10052#define MC_WR_GRP_SYS__SMU_MASK 0x00f00000L 10053#define MC_WR_GRP_SYS__SMU__SHIFT 0x00000014 10054#define MC_WR_GRP_SYS__VCE_MASK 0x0f000000L 10055#define MC_WR_GRP_SYS__VCE__SHIFT 0x00000018 10056#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000L 10057#define MC_WR_GRP_SYS__VCEU__SHIFT 0x0000001c 10058#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x00000008L 10059#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x00000003 10060#define MC_WR_HUB__ENABLE_MASK 0x00000001L 10061#define MC_WR_HUB__ENABLE__SHIFT 0x00000000 10062#define MC_WR_HUB__LAZY_TIMER_MASK 0x00007800L 10063#define MC_WR_HUB__LAZY_TIMER__SHIFT 0x0000000b 10064#define MC_WR_HUB__MAX_BURST_MASK 0x00000780L 10065#define MC_WR_HUB__MAX_BURST__SHIFT 0x00000007 10066#define MC_WR_HUB__PRESCALE_MASK 0x00000006L 10067#define MC_WR_HUB__PRESCALE__SHIFT 0x00000001 10068#define MC_WR_HUB__STALL_MODE_MASK 0x00000030L 10069#define MC_WR_HUB__STALL_MODE__SHIFT 0x00000004 10070#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x00000040L 10071#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x00000006 10072#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x00008000L 10073#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 10074#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x00000008L 10075#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x00000003 10076#define MC_WR_TC0__ENABLE_MASK 0x00000001L 10077#define MC_WR_TC0__ENABLE__SHIFT 0x00000000 10078#define MC_WR_TC0__LAZY_TIMER_MASK 0x00007800L 10079#define MC_WR_TC0__LAZY_TIMER__SHIFT 0x0000000b 10080#define MC_WR_TC0__MAX_BURST_MASK 0x00000780L 10081#define MC_WR_TC0__MAX_BURST__SHIFT 0x00000007 10082#define MC_WR_TC0__PRESCALE_MASK 0x00000006L 10083#define MC_WR_TC0__PRESCALE__SHIFT 0x00000001 10084#define MC_WR_TC0__STALL_MODE_MASK 0x00000030L 10085#define MC_WR_TC0__STALL_MODE__SHIFT 0x00000004 10086#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x00000040L 10087#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x00000006 10088#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x00008000L 10089#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 10090#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x00000008L 10091#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x00000003 10092#define MC_WR_TC1__ENABLE_MASK 0x00000001L 10093#define MC_WR_TC1__ENABLE__SHIFT 0x00000000 10094#define MC_WR_TC1__LAZY_TIMER_MASK 0x00007800L 10095#define MC_WR_TC1__LAZY_TIMER__SHIFT 0x0000000b 10096#define MC_WR_TC1__MAX_BURST_MASK 0x00000780L 10097#define MC_WR_TC1__MAX_BURST__SHIFT 0x00000007 10098#define MC_WR_TC1__PRESCALE_MASK 0x00000006L 10099#define MC_WR_TC1__PRESCALE__SHIFT 0x00000001 10100#define MC_WR_TC1__STALL_MODE_MASK 0x00000030L 10101#define MC_WR_TC1__STALL_MODE__SHIFT 0x00000004 10102#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x00000040L 10103#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x00000006 10104#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x00008000L 10105#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f 10106#define MC_XBAR_ADDR_DEC__GECC_MASK 0x00000002L 10107#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x00000001 10108#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x00000001L 10109#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x00000000 10110#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x00000008L 10111#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x00000003 10112#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x00000004L 10113#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x00000002 10114#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x00000004L 10115#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x00000002 10116#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x00000002L 10117#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x00000001 10118#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x00000001L 10119#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x00000000 10120#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0x0000000fL 10121#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x00000000 10122#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0x000000f0L 10123#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x00000004 10124#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0x00000f00L 10125#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x00000008 10126#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0x0000f000L 10127#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0x0000000c 10128#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0x000f0000L 10129#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x00000010 10130#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0x00f00000L 10131#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x00000014 10132#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0x0f000000L 10133#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x00000018 10134#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000L 10135#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x0000001c 10136#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x00000003L 10137#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x00000000 10138#define MC_XBAR_CHTRIREMAP__CH1_MASK 0x0000000cL 10139#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x00000002 10140#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x00000030L 10141#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x00000004 10142#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000L 10143#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x0000001c 10144#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x03000000L 10145#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x00000018 10146#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0x00000fffL 10147#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x00000000 10148#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0x0c000000L 10149#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x0000001a 10150#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0x00fff000L 10151#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0x0000000c 10152#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0x0000ff00L 10153#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x00000008 10154#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x00ff0000L 10155#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x00000010 10156#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x000000ffL 10157#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x00000000 10158#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0x000000ffL 10159#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x00000000 10160#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0x0000ff00L 10161#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x00000008 10162#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0x00ff0000L 10163#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x00000010 10164#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000L 10165#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x00000018 10166#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0x000000ffL 10167#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x00000000 10168#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0x0000ff00L 10169#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x00000008 10170#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0x00ff0000L 10171#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x00000010 10172#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000L 10173#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x00000018 10174#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffffL 10175#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x00000000 10176#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffffL 10177#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x00000000 10178#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffffL 10179#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x00000000 10180#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffffL 10181#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x00000000 10182#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0x000000ffL 10183#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x00000000 10184#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0x0000ff00L 10185#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x00000008 10186#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0x00ff0000L 10187#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x00000010 10188#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000L 10189#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x00000018 10190#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0x000000ffL 10191#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x00000000 10192#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0x0000ff00L 10193#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x00000008 10194#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0x00ff0000L 10195#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x00000010 10196#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000L 10197#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x00000018 10198#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0x000000ffL 10199#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x00000000 10200#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0x0000ff00L 10201#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x00000008 10202#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0x00ff0000L 10203#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x00000010 10204#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000L 10205#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x00000018 10206#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0x00ff0000L 10207#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x00000010 10208#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0x000000ffL 10209#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x00000000 10210#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0x0000ff00L 10211#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x00000008 10212#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0x000000ffL 10213#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x00000000 10214#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0x0000ff00L 10215#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x00000008 10216#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0x00ff0000L 10217#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x00000010 10218#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000L 10219#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x00000018 10220#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0x000000ffL 10221#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x00000000 10222#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0x0000ff00L 10223#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x00000008 10224#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x00000002L 10225#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x00000001 10226#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x00000001L 10227#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x00000000 10228#define MC_XBAR_SPARE0__BIT_MASK 0xffffffffL 10229#define MC_XBAR_SPARE0__BIT__SHIFT 0x00000000 10230#define MC_XBAR_SPARE1__BIT_MASK 0xffffffffL 10231#define MC_XBAR_SPARE1__BIT__SHIFT 0x00000000 10232#define MC_XBAR_TWOCHAN__CH0_MASK 0x00000006L 10233#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x00000001 10234#define MC_XBAR_TWOCHAN__CH1_MASK 0x00000018L 10235#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x00000003 10236#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x00000001L 10237#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x00000000 10238#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0x000000ffL 10239#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x00000000 10240#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0x0000ff00L 10241#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x00000008 10242#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0x00ff0000L 10243#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x00000010 10244#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000L 10245#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x00000018 10246#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0x000000ffL 10247#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x00000000 10248#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0x0000ff00L 10249#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x00000008 10250#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0x00ff0000L 10251#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x00000010 10252#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000L 10253#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x00000018 10254#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0x000000ffL 10255#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x00000000 10256#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0x0000ff00L 10257#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x00000008 10258#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003c00L 10259#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0x0000000a 10260#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L 10261#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x00000004 10262#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L 10263#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x00000007 10264#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003c000L 10265#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0x0000000e 10266#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000fL 10267#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x00000000 10268#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x00003c00L 10269#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0x0000000a 10270#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x00000070L 10271#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x00000004 10272#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x00000380L 10273#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x00000007 10274#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x0003c000L 10275#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0x0000000e 10276#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0x0000000fL 10277#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x00000000 10278#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x00003c00L 10279#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0x0000000a 10280#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x00000070L 10281#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x00000004 10282#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x00000380L 10283#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x00000007 10284#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x0003c000L 10285#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0x0000000e 10286#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0x0000000fL 10287#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x00000000 10288#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x00003c00L 10289#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0x0000000a 10290#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x00000070L 10291#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x00000004 10292#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x00000380L 10293#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x00000007 10294#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x0003c000L 10295#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0x0000000e 10296#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0x0000000fL 10297#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x00000000 10298#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x00003c00L 10299#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0x0000000a 10300#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x00000070L 10301#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x00000004 10302#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x00000380L 10303#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x00000007 10304#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x0003c000L 10305#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0x0000000e 10306#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0x0000000fL 10307#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x00000000 10308#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x00003c00L 10309#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0x0000000a 10310#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x00000070L 10311#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x00000004 10312#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x00000380L 10313#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x00000007 10314#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x0003c000L 10315#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0x0000000e 10316#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0x0000000fL 10317#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x00000000 10318#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x00003c00L 10319#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0x0000000a 10320#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x00000070L 10321#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x00000004 10322#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x00000380L 10323#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x00000007 10324#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x0003c000L 10325#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0x0000000e 10326#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0x0000000fL 10327#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x00000000 10328#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x00003c00L 10329#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0x0000000a 10330#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x00000070L 10331#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x00000004 10332#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x00000380L 10333#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x00000007 10334#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x0003c000L 10335#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0x0000000e 10336#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0x0000000fL 10337#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x00000000 10338#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x00003c00L 10339#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0x0000000a 10340#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x00000070L 10341#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x00000004 10342#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x00000380L 10343#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x00000007 10344#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x0003c000L 10345#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0x0000000e 10346#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0x0000000fL 10347#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x00000000 10348#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x00003c00L 10349#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0x0000000a 10350#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x00000070L 10351#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x00000004 10352#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x00000380L 10353#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x00000007 10354#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x0003c000L 10355#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0x0000000e 10356#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0x0000000fL 10357#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x00000000 10358#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x00003c00L 10359#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0x0000000a 10360#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x00000070L 10361#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x00000004 10362#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x00000380L 10363#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x00000007 10364#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x0003c000L 10365#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0x0000000e 10366#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0x0000000fL 10367#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x00000000 10368#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003c00L 10369#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0x0000000a 10370#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L 10371#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x00000004 10372#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L 10373#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x00000007 10374#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003c000L 10375#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0x0000000e 10376#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000fL 10377#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x00000000 10378#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x00003c00L 10379#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0x0000000a 10380#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x00000070L 10381#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x00000004 10382#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x00000380L 10383#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x00000007 10384#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x0003c000L 10385#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0x0000000e 10386#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0x0000000fL 10387#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x00000000 10388#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x00003c00L 10389#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0x0000000a 10390#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x00000070L 10391#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x00000004 10392#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x00000380L 10393#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x00000007 10394#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x0003c000L 10395#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0x0000000e 10396#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0x0000000fL 10397#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x00000000 10398#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x00003c00L 10399#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0x0000000a 10400#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x00000070L 10401#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x00000004 10402#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x00000380L 10403#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x00000007 10404#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x0003c000L 10405#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0x0000000e 10406#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0x0000000fL 10407#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x00000000 10408#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x00003c00L 10409#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0x0000000a 10410#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x00000070L 10411#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x00000004 10412#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x00000380L 10413#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x00000007 10414#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x0003c000L 10415#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0x0000000e 10416#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0x0000000fL 10417#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x00000000 10418#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x00003c00L 10419#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0x0000000a 10420#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x00000070L 10421#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x00000004 10422#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x00000380L 10423#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x00000007 10424#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x0003c000L 10425#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0x0000000e 10426#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0x0000000fL 10427#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x00000000 10428#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x00003c00L 10429#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0x0000000a 10430#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x00000070L 10431#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x00000004 10432#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x00000380L 10433#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x00000007 10434#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x0003c000L 10435#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0x0000000e 10436#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0x0000000fL 10437#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x00000000 10438#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x00003c00L 10439#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0x0000000a 10440#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x00000070L 10441#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x00000004 10442#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x00000380L 10443#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x00000007 10444#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x0003c000L 10445#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0x0000000e 10446#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0x0000000fL 10447#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x00000000 10448#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x00003c00L 10449#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0x0000000a 10450#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x00000070L 10451#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x00000004 10452#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x00000380L 10453#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x00000007 10454#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x0003c000L 10455#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0x0000000e 10456#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0x0000000fL 10457#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x00000000 10458#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x00003c00L 10459#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0x0000000a 10460#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x00000070L 10461#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x00000004 10462#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x00000380L 10463#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x00000007 10464#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x0003c000L 10465#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0x0000000e 10466#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0x0000000fL 10467#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x00000000 10468#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x00003c00L 10469#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0x0000000a 10470#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x00000070L 10471#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x00000004 10472#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x00000380L 10473#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x00000007 10474#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x0003c000L 10475#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0x0000000e 10476#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0x0000000fL 10477#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x00000000 10478#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003c00L 10479#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0x0000000a 10480#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L 10481#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x00000004 10482#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L 10483#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x00000007 10484#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003c000L 10485#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0x0000000e 10486#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000fL 10487#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x00000000 10488#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x00003c00L 10489#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0x0000000a 10490#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x00000070L 10491#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x00000004 10492#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x00000380L 10493#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x00000007 10494#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x0003c000L 10495#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0x0000000e 10496#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0x0000000fL 10497#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x00000000 10498#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x00003c00L 10499#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0x0000000a 10500#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x00000070L 10501#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x00000004 10502#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x00000380L 10503#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x00000007 10504#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x0003c000L 10505#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0x0000000e 10506#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0x0000000fL 10507#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x00000000 10508#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x00003c00L 10509#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0x0000000a 10510#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x00000070L 10511#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x00000004 10512#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x00000380L 10513#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x00000007 10514#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x0003c000L 10515#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0x0000000e 10516#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0x0000000fL 10517#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x00000000 10518#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x00003c00L 10519#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0x0000000a 10520#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x00000070L 10521#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x00000004 10522#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x00000380L 10523#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x00000007 10524#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x0003c000L 10525#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0x0000000e 10526#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0x0000000fL 10527#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x00000000 10528#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x00003c00L 10529#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0x0000000a 10530#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x00000070L 10531#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x00000004 10532#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x00000380L 10533#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x00000007 10534#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x0003c000L 10535#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0x0000000e 10536#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0x0000000fL 10537#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x00000000 10538#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x00003c00L 10539#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0x0000000a 10540#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x00000070L 10541#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x00000004 10542#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x00000380L 10543#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x00000007 10544#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x0003c000L 10545#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0x0000000e 10546#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0x0000000fL 10547#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x00000000 10548#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x00003c00L 10549#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0x0000000a 10550#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x00000070L 10551#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x00000004 10552#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x00000380L 10553#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x00000007 10554#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x0003c000L 10555#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0x0000000e 10556#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0x0000000fL 10557#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x00000000 10558#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003c00L 10559#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0x0000000a 10560#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L 10561#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x00000004 10562#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L 10563#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x00000007 10564#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003c000L 10565#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0x0000000e 10566#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000fL 10567#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x00000000 10568#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003c00L 10569#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0x0000000a 10570#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L 10571#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x00000004 10572#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L 10573#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x00000007 10574#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003c000L 10575#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0x0000000e 10576#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000fL 10577#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x00000000 10578#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003c00L 10579#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0x0000000a 10580#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L 10581#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x00000004 10582#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L 10583#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x00000007 10584#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003c000L 10585#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0x0000000e 10586#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000fL 10587#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x00000000 10588#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003c00L 10589#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0x0000000a 10590#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L 10591#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x00000004 10592#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L 10593#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x00000007 10594#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003c000L 10595#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0x0000000e 10596#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000fL 10597#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x00000000 10598#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003c00L 10599#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0x0000000a 10600#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L 10601#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x00000004 10602#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L 10603#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x00000007 10604#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003c000L 10605#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0x0000000e 10606#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000fL 10607#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x00000000 10608#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x00003c00L 10609#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0x0000000a 10610#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x00000070L 10611#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x00000004 10612#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x00000380L 10613#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x00000007 10614#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x0003c000L 10615#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0x0000000e 10616#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0x0000000fL 10617#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x00000000 10618#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x00003c00L 10619#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0x0000000a 10620#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x00000070L 10621#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x00000004 10622#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x00000380L 10623#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x00000007 10624#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x0003c000L 10625#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0x0000000e 10626#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0x0000000fL 10627#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x00000000 10628#define MC_XPB_CLG_EXTRA__CMP0_MASK 0x000000ffL 10629#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x00000000 10630#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x01fe0000L 10631#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x00000011 10632#define MC_XPB_CLG_EXTRA__MSK0_MASK 0x0000ff00L 10633#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x00000008 10634#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0x000000ffL 10635#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x00000000 10636#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x01fe0000L 10637#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x00000011 10638#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0x0000ff00L 10639#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x00000008 10640#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x00010000L 10641#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x00000010 10642#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x02000000L 10643#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x00000019 10644#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x00010000L 10645#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x00000010 10646#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x02000000L 10647#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x00000019 10648#define MC_XPB_CLK_GAT__ENABLE_MASK 0x00040000L 10649#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x00000012 10650#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L 10651#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x00000013 10652#define MC_XPB_CLK_GAT__OFFDLY_MASK 0x00000fc0L 10653#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x00000006 10654#define MC_XPB_CLK_GAT__ONDLY_MASK 0x0000003fL 10655#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x00000000 10656#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x0003f000L 10657#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0x0000000c 10658#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000ffL 10659#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x00000000 10660#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L 10661#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x00000019 10662#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L 10663#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x0000001a 10664#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L 10665#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x00000017 10666#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L 10667#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x00000018 10668#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000ff00L 10669#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x00000008 10670#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000ffL 10671#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x00000000 10672#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L 10673#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x0000001e 10674#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L 10675#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x0000001f 10676#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007f0000L 10677#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x00000010 10678#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L 10679#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x0000001b 10680#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L 10681#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x0000001d 10682#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L 10683#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x00000012 10684#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L 10685#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x00000011 10686#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L 10687#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x00000010 10688#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L 10689#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0x0000000f 10690#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07f80000L 10691#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x00000013 10692#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000ffL 10693#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x00000000 10694#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007f00L 10695#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x00000008 10696#define MC_XPB_LB_ADDR__CMP0_MASK 0x000003ffL 10697#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x00000000 10698#define MC_XPB_LB_ADDR__CMP1_MASK 0x03f00000L 10699#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x00000014 10700#define MC_XPB_LB_ADDR__MASK0_MASK 0x000ffc00L 10701#define MC_XPB_LB_ADDR__MASK0__SHIFT 0x0000000a 10702#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000L 10703#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x0000001a 10704#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000ffffL 10705#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x00000000 10706#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0x000000ffL 10707#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x00000000 10708#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0x0000ff00L 10709#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x00000008 10710#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0x00ff0000L 10711#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x00000010 10712#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000L 10713#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x00000018 10714#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L 10715#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x0000001f 10716#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000L 10717#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x00000010 10718#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L 10719#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0x0000000e 10720#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000fL 10721#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x00000000 10722#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000f00L 10723#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x00000008 10724#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000f0L 10725#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x00000004 10726#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x00008000L 10727#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0x0000000f 10728#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L 10729#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0x0000000d 10730#define MC_XPB_P2P_BAR0__VALID_MASK 0x00001000L 10731#define MC_XPB_P2P_BAR0__VALID__SHIFT 0x0000000c 10732#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000L 10733#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x00000010 10734#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L 10735#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0x0000000e 10736#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000fL 10737#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x00000000 10738#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000f00L 10739#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x00000008 10740#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000f0L 10741#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x00000004 10742#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x00008000L 10743#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0x0000000f 10744#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L 10745#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0x0000000d 10746#define MC_XPB_P2P_BAR1__VALID_MASK 0x00001000L 10747#define MC_XPB_P2P_BAR1__VALID__SHIFT 0x0000000c 10748#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000L 10749#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x00000010 10750#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L 10751#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0x0000000e 10752#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000fL 10753#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x00000000 10754#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000f00L 10755#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x00000008 10756#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000f0L 10757#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x00000004 10758#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x00008000L 10759#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0x0000000f 10760#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L 10761#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0x0000000d 10762#define MC_XPB_P2P_BAR2__VALID_MASK 0x00001000L 10763#define MC_XPB_P2P_BAR2__VALID__SHIFT 0x0000000c 10764#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000L 10765#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x00000010 10766#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L 10767#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0x0000000e 10768#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000fL 10769#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x00000000 10770#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000f00L 10771#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x00000008 10772#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000f0L 10773#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x00000004 10774#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x00008000L 10775#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0x0000000f 10776#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L 10777#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0x0000000d 10778#define MC_XPB_P2P_BAR3__VALID_MASK 0x00001000L 10779#define MC_XPB_P2P_BAR3__VALID__SHIFT 0x0000000c 10780#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000L 10781#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x00000010 10782#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L 10783#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0x0000000e 10784#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000fL 10785#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x00000000 10786#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000f00L 10787#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x00000008 10788#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000f0L 10789#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x00000004 10790#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x00008000L 10791#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0x0000000f 10792#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L 10793#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0x0000000d 10794#define MC_XPB_P2P_BAR4__VALID_MASK 0x00001000L 10795#define MC_XPB_P2P_BAR4__VALID__SHIFT 0x0000000c 10796#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000L 10797#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x00000010 10798#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L 10799#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0x0000000e 10800#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000fL 10801#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x00000000 10802#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000f00L 10803#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x00000008 10804#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000f0L 10805#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x00000004 10806#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x00008000L 10807#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0x0000000f 10808#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L 10809#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0x0000000d 10810#define MC_XPB_P2P_BAR5__VALID_MASK 0x00001000L 10811#define MC_XPB_P2P_BAR5__VALID__SHIFT 0x0000000c 10812#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000L 10813#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x00000010 10814#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L 10815#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0x0000000e 10816#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000fL 10817#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x00000000 10818#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000f00L 10819#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x00000008 10820#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000f0L 10821#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x00000004 10822#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x00008000L 10823#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0x0000000f 10824#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L 10825#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0x0000000d 10826#define MC_XPB_P2P_BAR6__VALID_MASK 0x00001000L 10827#define MC_XPB_P2P_BAR6__VALID__SHIFT 0x0000000c 10828#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000L 10829#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x00000010 10830#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L 10831#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0x0000000e 10832#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000fL 10833#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x00000000 10834#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000f00L 10835#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x00000008 10836#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000f0L 10837#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x00000004 10838#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x00008000L 10839#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0x0000000f 10840#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L 10841#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0x0000000d 10842#define MC_XPB_P2P_BAR7__VALID_MASK 0x00001000L 10843#define MC_XPB_P2P_BAR7__VALID__SHIFT 0x0000000c 10844#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000fL 10845#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x00000000 10846#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L 10847#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0x0000000c 10848#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L 10849#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x00000008 10850#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L 10851#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0x0000000b 10852#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L 10853#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0x0000000a 10854#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L 10855#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x00000004 10856#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L 10857#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x00000007 10858#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L 10859#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x00000006 10860#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L 10861#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x00000009 10862#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0x00000f00L 10863#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x00000008 10864#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0x0000f000L 10865#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0x0000000c 10866#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0x000000ffL 10867#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x00000000 10868#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0fffff00L 10869#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x00000008 10870#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000ffL 10871#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x00000000 10872#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0fffff00L 10873#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x00000008 10874#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000ffL 10875#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x00000000 10876#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000L 10877#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x00000010 10878#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L 10879#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0x0000000e 10880#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000f00L 10881#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x00000008 10882#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L 10883#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0x0000000f 10884#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0x000000ffL 10885#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x00000000 10886#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L 10887#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0x0000000d 10888#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L 10889#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0x0000000c 10890#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x07fffffcL 10891#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x00000002 10892#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x00000002L 10893#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x00000001 10894#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L 10895#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x00000000 10896#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x07fffffcL 10897#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x00000002 10898#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x00000002L 10899#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x00000001 10900#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L 10901#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x00000000 10902#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x07fffffcL 10903#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x00000002 10904#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x00000002L 10905#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x00000001 10906#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L 10907#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x00000000 10908#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x07fffffcL 10909#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x00000002 10910#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x00000002L 10911#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x00000001 10912#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L 10913#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x00000000 10914#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x07fffffcL 10915#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x00000002 10916#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x00000002L 10917#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x00000001 10918#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L 10919#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x00000000 10920#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x07fffffcL 10921#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x00000002 10922#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x00000002L 10923#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x00000001 10924#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L 10925#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x00000000 10926#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x07fffffcL 10927#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x00000002 10928#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x00000002L 10929#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x00000001 10930#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L 10931#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x00000000 10932#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x07fffffcL 10933#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x00000002 10934#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x00000002L 10935#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x00000001 10936#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L 10937#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x00000000 10938#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x07fffffcL 10939#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x00000002 10940#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x00000002L 10941#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x00000001 10942#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L 10943#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x00000000 10944#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x07fffffcL 10945#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x00000002 10946#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x00000002L 10947#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x00000001 10948#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L 10949#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x00000000 10950#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003fL 10951#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x00000000 10952#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000fc0L 10953#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x00000006 10954#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003f000L 10955#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0x0000000c 10956#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L 10957#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x00000017 10958#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L 10959#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x00000000 10960#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000feL 10961#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000001 10962#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L 10963#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x00000015 10964#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L 10965#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0x0000000f 10966#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L 10967#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x00000011 10968#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L 10969#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x00000013 10970#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007f00L 10971#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000008 10972#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L 10973#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x00000016 10974#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L 10975#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x00000010 10976#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L 10977#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x00000012 10978#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L 10979#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x00000014 10980#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000L 10981#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x00000018 10982#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L 10983#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a 10984#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL 10985#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001 10986#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L 10987#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 10988#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018 10989#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014 10990#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L 10991#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x00000000 10992#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L 10993#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019 10994#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L 10995#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a 10996#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL 10997#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001 10998#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L 10999#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 11000#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018 11001#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014 11002#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L 11003#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x00000000 11004#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L 11005#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019 11006#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L 11007#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a 11008#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL 11009#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001 11010#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L 11011#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 11012#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018 11013#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014 11014#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L 11015#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x00000000 11016#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L 11017#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019 11018#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L 11019#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a 11020#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL 11021#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001 11022#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L 11023#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 11024#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018 11025#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014 11026#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L 11027#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x00000000 11028#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L 11029#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019 11030#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000L 11031#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x0000001a 11032#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000ffffeL 11033#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x00000001 11034#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00f00000L 11035#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L 11036#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x00000018 11037#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x00000014 11038#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L 11039#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x00000000 11040#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L 11041#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x00000019 11042#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000L 11043#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x0000001a 11044#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000ffffeL 11045#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x00000001 11046#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00f00000L 11047#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L 11048#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x00000018 11049#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x00000014 11050#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L 11051#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x00000000 11052#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L 11053#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x00000019 11054#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000L 11055#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x0000001a 11056#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000ffffeL 11057#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x00000001 11058#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00f00000L 11059#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L 11060#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x00000018 11061#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x00000014 11062#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L 11063#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x00000000 11064#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L 11065#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x00000019 11066#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000L 11067#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x0000001a 11068#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000ffffeL 11069#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x00000001 11070#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00f00000L 11071#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L 11072#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x00000018 11073#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x00000014 11074#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L 11075#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x00000000 11076#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L 11077#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x00000019 11078#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000L 11079#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x0000001a 11080#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000ffffeL 11081#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x00000001 11082#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00f00000L 11083#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L 11084#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x00000018 11085#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x00000014 11086#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L 11087#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x00000000 11088#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L 11089#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x00000019 11090#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000L 11091#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x0000001a 11092#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000ffffeL 11093#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x00000001 11094#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00f00000L 11095#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L 11096#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x00000018 11097#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x00000014 11098#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L 11099#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x00000000 11100#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L 11101#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x00000019 11102#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x01ffffffL 11103#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000 11104#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x01ffffffL 11105#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000 11106#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x01ffffffL 11107#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000 11108#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x01ffffffL 11109#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000 11110#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x01ffffffL 11111#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x00000000 11112#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x01ffffffL 11113#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x00000000 11114#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x01ffffffL 11115#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x00000000 11116#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x01ffffffL 11117#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x00000000 11118#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x01ffffffL 11119#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x00000000 11120#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x01ffffffL 11121#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x00000000 11122#define MC_XPB_STICKY__BITS_MASK 0xffffffffL 11123#define MC_XPB_STICKY__BITS__SHIFT 0x00000000 11124#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffffL 11125#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x00000000 11126#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L 11127#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x00000013 11128#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L 11129#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0x0000000a 11130#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L 11131#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x00000010 11132#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L 11133#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0x0000000f 11134#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L 11135#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0x0000000d 11136#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L 11137#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0x0000000c 11138#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L 11139#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0x0000000b 11140#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L 11141#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x00000011 11142#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L 11143#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x00000012 11144#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L 11145#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0x0000000e 11146#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L 11147#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x00000001 11148#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L 11149#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x00000008 11150#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L 11151#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x00000004 11152#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L 11153#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x00000006 11154#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L 11155#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x00000003 11156#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L 11157#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x00000002 11158#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L 11159#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x00000007 11160#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L 11161#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x00000005 11162#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L 11163#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x00000009 11164#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L 11165#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x00000000 11166#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x0000003fL 11167#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x00000000 11168#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0x00000fc0L 11169#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x00000006 11170#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x0003f000L 11171#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0x0000000c 11172#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x0000003fL 11173#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x00000000 11174#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0x00000fc0L 11175#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x00000006 11176#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x0003f000L 11177#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0x0000000c 11178#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x00030000L 11179#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x00000010 11180#define MC_XPB_WCB_CFG__SID_MAX_MASK 0x000c0000L 11181#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x00000012 11182#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0x0000ffffL 11183#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x00000000 11184#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0x0000ffffL 11185#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x00000000 11186#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007f0000L 11187#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000010 11188#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000L 11189#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000017 11190#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x07fffffcL 11191#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x00000002 11192#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x00000002L 11193#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x00000001 11194#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L 11195#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x00000000 11196#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x07fffffcL 11197#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x00000002 11198#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x00000002L 11199#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x00000001 11200#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L 11201#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x00000000 11202#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x07fffffcL 11203#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x00000002 11204#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x00000002L 11205#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x00000001 11206#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L 11207#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x00000000 11208#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x07fffffcL 11209#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x00000002 11210#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x00000002L 11211#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x00000001 11212#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L 11213#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x00000000 11214#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L 11215#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a 11216#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL 11217#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001 11218#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L 11219#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 11220#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018 11221#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014 11222#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L 11223#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x00000000 11224#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L 11225#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019 11226#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L 11227#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a 11228#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL 11229#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001 11230#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L 11231#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 11232#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018 11233#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014 11234#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L 11235#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x00000000 11236#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L 11237#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019 11238#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L 11239#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a 11240#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL 11241#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001 11242#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L 11243#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 11244#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018 11245#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014 11246#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L 11247#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x00000000 11248#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L 11249#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019 11250#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L 11251#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a 11252#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL 11253#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001 11254#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L 11255#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 11256#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018 11257#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014 11258#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L 11259#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x00000000 11260#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L 11261#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019 11262#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x01ffffffL 11263#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000 11264#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x01ffffffL 11265#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000 11266#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x01ffffffL 11267#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000 11268#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x01ffffffL 11269#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000 11270#define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8L 11271#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x00000003 11272#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x00000007L 11273#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x00000000 11274#define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x00040000L 11275#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x00000012 11276#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L 11277#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 11278#define MPLL_AD_STATUS__OINT_RESET_MASK 0x00020000L 11279#define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x00000011 11280#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L 11281#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 11282#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L 11283#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 11284#define MPLL_AD_STATUS__VCTRLADC_MASK 0x00000007L 11285#define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x00000000 11286#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x00600000L 11287#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x00000015 11288#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x00100000L 11289#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x00000014 11290#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x00020000L 11291#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x00000011 11292#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000L 11293#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x0000001f 11294#define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0x000000ffL 11295#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x00000000 11296#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x00010000L 11297#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x00000010 11298#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x00004000L 11299#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0x0000000e 11300#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x00000800L 11301#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0x0000000b 11302#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x00000100L 11303#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x00000008 11304#define MPLL_CNTL_MODE__QDR_MASK 0x00002000L 11305#define MPLL_CNTL_MODE__QDR__SHIFT 0x0000000d 11306#define MPLL_CNTL_MODE__SPARE_1_MASK 0x00001000L 11307#define MPLL_CNTL_MODE__SPARE_1__SHIFT 0x0000000c 11308#define MPLL_CNTL_MODE__SPARE_2_MASK 0x00800000L 11309#define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x00000017 11310#define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000L 11311#define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x0000001c 11312#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x04000000L 11313#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x0000001a 11314#define MPLL_CNTL_MODE__SS_SSEN_MASK 0x03000000L 11315#define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x00000018 11316#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x08000000L 11317#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x0000001b 11318#define MPLL_CONTROL__AD_BG_PWRON_MASK 0x00001000L 11319#define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0x0000000c 11320#define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x00002000L 11321#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0x0000000d 11322#define MPLL_CONTROL__AD_PLL_RESET_MASK 0x00004000L 11323#define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0x0000000e 11324#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x00010000L 11325#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x00000010 11326#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x00020000L 11327#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x00000011 11328#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x00040000L 11329#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x00000012 11330#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x00100000L 11331#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x00000014 11332#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x00200000L 11333#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x00000015 11334#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x00400000L 11335#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x00000016 11336#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x01000000L 11337#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x00000018 11338#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x02000000L 11339#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x00000019 11340#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x04000000L 11341#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x0000001a 11342#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000L 11343#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x0000001c 11344#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000L 11345#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x0000001d 11346#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000L 11347#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x0000001e 11348#define MPLL_CONTROL__GDDR_PWRON_MASK 0x00000001L 11349#define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x00000000 11350#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x00000004L 11351#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x00000002 11352#define MPLL_CONTROL__REFCLK_PWRON_MASK 0x00000002L 11353#define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x00000001 11354#define MPLL_CONTROL__SPARE_AD_0_MASK 0x00008000L 11355#define MPLL_CONTROL__SPARE_AD_0__SHIFT 0x0000000f 11356#define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x00080000L 11357#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x00000013 11358#define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x00800000L 11359#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x00000017 11360#define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x08000000L 11361#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x0000001b 11362#define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000L 11363#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x0000001f 11364#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x00040000L 11365#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x00000012 11366#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L 11367#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 11368#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x00020000L 11369#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x00000011 11370#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L 11371#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 11372#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L 11373#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 11374#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x00000007L 11375#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x00000000 11376#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x00040000L 11377#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x00000012 11378#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L 11379#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 11380#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x00020000L 11381#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x00000011 11382#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L 11383#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 11384#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L 11385#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 11386#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x00000007L 11387#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x00000000 11388#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x00040000L 11389#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x00000012 11390#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L 11391#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 11392#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x00020000L 11393#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x00000011 11394#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L 11395#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 11396#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L 11397#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 11398#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x00000007L 11399#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x00000000 11400#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x00040000L 11401#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x00000012 11402#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L 11403#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 11404#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x00020000L 11405#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x00000011 11406#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L 11407#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 11408#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L 11409#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 11410#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x00000007L 11411#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x00000000 11412#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x00000008L 11413#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x00000003 11414#define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0L 11415#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x00000005 11416#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x00000007L 11417#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x00000000 11418#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x00000010L 11419#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x00000004 11420#define MPLL_FUNC_CNTL_1__CLKF_MASK 0x0fff0000L 11421#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0x0000fff0L 11422#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x00000004 11423#define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x00000010 11424#define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0x0000000cL 11425#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x00000002 11426#define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000L 11427#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x0000001c 11428#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x00000003L 11429#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x00000000 11430#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0x000e0000L 11431#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x00000011 11432#define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000L 11433#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x0000001b 11434#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x07f00000L 11435#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x00000014 11436#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x00000080L 11437#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x00000007 11438#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x00003000L 11439#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0x0000000c 11440#define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x00000004L 11441#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x00000002 11442#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0x00000c00L 11443#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0x0000000a 11444#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x00000008L 11445#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x00000003 11446#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x00000010L 11447#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x00000004 11448#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x00000040L 11449#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x00000006 11450#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x00000020L 11451#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x00000005 11452#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x00000200L 11453#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x00000009 11454#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x00000100L 11455#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x00000008 11456#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x00000002L 11457#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x00000001 11458#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x00000001L 11459#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x00000000 11460#define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0x00000f00L 11461#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x00000008 11462#define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0x000f0000L 11463#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x00000010 11464#define MPLL_FUNC_CNTL__BWCTRL_MASK 0x0ff00000L 11465#define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x00000014 11466#define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000L 11467#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x0000001e 11468#define MPLL_FUNC_CNTL__SPARE_0_MASK 0x00000020L 11469#define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x00000005 11470#define MPLL_SEQ_UCODE_1__INSTR0_MASK 0x0000000fL 11471#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x00000000 11472#define MPLL_SEQ_UCODE_1__INSTR1_MASK 0x000000f0L 11473#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x00000004 11474#define MPLL_SEQ_UCODE_1__INSTR2_MASK 0x00000f00L 11475#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x00000008 11476#define MPLL_SEQ_UCODE_1__INSTR3_MASK 0x0000f000L 11477#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0x0000000c 11478#define MPLL_SEQ_UCODE_1__INSTR4_MASK 0x000f0000L 11479#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x00000010 11480#define MPLL_SEQ_UCODE_1__INSTR5_MASK 0x00f00000L 11481#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x00000014 11482#define MPLL_SEQ_UCODE_1__INSTR6_MASK 0x0f000000L 11483#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x00000018 11484#define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000L 11485#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x0000001c 11486#define MPLL_SEQ_UCODE_2__INSTR10_MASK 0x00000f00L 11487#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x00000008 11488#define MPLL_SEQ_UCODE_2__INSTR11_MASK 0x0000f000L 11489#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0x0000000c 11490#define MPLL_SEQ_UCODE_2__INSTR12_MASK 0x000f0000L 11491#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x00000010 11492#define MPLL_SEQ_UCODE_2__INSTR13_MASK 0x00f00000L 11493#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x00000014 11494#define MPLL_SEQ_UCODE_2__INSTR14_MASK 0x0f000000L 11495#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x00000018 11496#define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000L 11497#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x0000001c 11498#define MPLL_SEQ_UCODE_2__INSTR8_MASK 0x0000000fL 11499#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x00000000 11500#define MPLL_SEQ_UCODE_2__INSTR9_MASK 0x000000f0L 11501#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x00000004 11502#define MPLL_SS1__CLKV_MASK 0x03ffffffL 11503#define MPLL_SS1__CLKV__SHIFT 0x00000000 11504#define MPLL_SS1__SPARE_MASK 0xfc000000L 11505#define MPLL_SS1__SPARE__SHIFT 0x0000001a 11506#define MPLL_SS2__CLKS_MASK 0x00000fffL 11507#define MPLL_SS2__CLKS__SHIFT 0x00000000 11508#define MPLL_SS2__SPARE_MASK 0xfffff000L 11509#define MPLL_SS2__SPARE__SHIFT 0x0000000c 11510#define MPLL_TIME__MPLL_LOCK_TIME_MASK 0x0000ffffL 11511#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x00000000 11512#define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000L 11513#define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x00000010 11514#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L 11515#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000003 11516#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 11517#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000000 11518#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L 11519#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x00000001 11520#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L 11521#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x00000002 11522#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L 11523#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x00000004 11524#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 11525#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000007 11526#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L 11527#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000006 11528#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 11529#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 11530#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0f000000L 11531#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000018 11532#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 11533#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 11534#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 11535#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a 11536#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 11537#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 11538#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L 11539#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000b 11540#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 11541#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 11542#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 11543#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 11544#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L 11545#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000017 11546#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 11547#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000004 11548#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L 11549#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000003 11550#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 11551#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 11552#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 11553#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f 11554#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L 11555#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000011 11556#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 11557#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000d 11558#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 11559#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000c 11560#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L 11561#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000e 11562#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 11563#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000013 11564#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 11565#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000012 11566#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L 11567#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000014 11568#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11569#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11570#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11571#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11572#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11573#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11574#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0x0fffffffL 11575#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x00000000 11576#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0x0fffffffL 11577#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x00000000 11578#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x000ff000L 11579#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0x0000000c 11580#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L 11581#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x00000018 11582#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000ffL 11583#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x00000000 11584#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000L 11585#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x00000019 11586#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11587#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11588#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11589#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11590#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11591#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11592#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11593#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11594#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11595#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11596#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11597#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11598#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L 11599#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000003 11600#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 11601#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000000 11602#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L 11603#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x00000001 11604#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L 11605#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x00000002 11606#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L 11607#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x00000004 11608#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 11609#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000007 11610#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L 11611#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000006 11612#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 11613#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 11614#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0f000000L 11615#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000018 11616#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 11617#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 11618#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 11619#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a 11620#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 11621#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 11622#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L 11623#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000b 11624#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 11625#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 11626#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 11627#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 11628#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L 11629#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000017 11630#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 11631#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000004 11632#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L 11633#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000003 11634#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 11635#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 11636#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 11637#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f 11638#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L 11639#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000011 11640#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 11641#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000d 11642#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 11643#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000c 11644#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L 11645#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000e 11646#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 11647#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000013 11648#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 11649#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000012 11650#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L 11651#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000014 11652#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11653#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11654#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11655#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11656#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11657#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11658#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0x0fffffffL 11659#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x00000000 11660#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0x0fffffffL 11661#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x00000000 11662#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x000ff000L 11663#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0x0000000c 11664#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L 11665#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x00000018 11666#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000ffL 11667#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x00000000 11668#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000L 11669#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x00000019 11670#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11671#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11672#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11673#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11674#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11675#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11676#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11677#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11678#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11679#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11680#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11681#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11682#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11683#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11684#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL 11685#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 11686#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 11687#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x00000000 11688#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 11689#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0x0000000a 11690#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 11691#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0x0000000b 11692#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 11693#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0x0000000c 11694#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 11695#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0x0000000d 11696#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 11697#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0x0000000e 11698#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 11699#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0x0000000f 11700#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 11701#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x00000001 11702#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 11703#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x00000002 11704#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 11705#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x00000003 11706#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 11707#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x00000004 11708#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 11709#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x00000005 11710#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 11711#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x00000006 11712#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 11713#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x00000007 11714#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 11715#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x00000008 11716#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 11717#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x00000009 11718#define VM_DEBUG__FLAGS_MASK 0xffffffffL 11719#define VM_DEBUG__FLAGS__SHIFT 0x00000000 11720#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0x0fffffffL 11721#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x00000000 11722#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 11723#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x00000001 11724#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0x0000000cL 11725#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x00000002 11726#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 11727#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x00000000 11728#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x000001ffL 11729#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x0003fe00L 11730#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x00000009 11731#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x00000000 11732#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x00000001L 11733#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x00000000 11734#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x00000400L 11735#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0x0000000a 11736#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x00000800L 11737#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0x0000000b 11738#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x00001000L 11739#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0x0000000c 11740#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x00002000L 11741#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0x0000000d 11742#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x00004000L 11743#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0x0000000e 11744#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x00008000L 11745#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0x0000000f 11746#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x00000002L 11747#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x00000001 11748#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x00000004L 11749#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x00000002 11750#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x00000008L 11751#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x00000003 11752#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x00000010L 11753#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x00000004 11754#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x00000020L 11755#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x00000005 11756#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x00000040L 11757#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x00000006 11758#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x00000080L 11759#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x00000007 11760#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x00000100L 11761#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x00000008 11762#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x00000200L 11763#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x00000009 11764#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x00000001L 11765#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x00000000 11766#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x00000400L 11767#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0x0000000a 11768#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x00000800L 11769#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0x0000000b 11770#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x00001000L 11771#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0x0000000c 11772#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x00002000L 11773#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0x0000000d 11774#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x00004000L 11775#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0x0000000e 11776#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x00008000L 11777#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0x0000000f 11778#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x00000002L 11779#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x00000001 11780#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x00000004L 11781#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x00000002 11782#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x00000008L 11783#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x00000003 11784#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x00000010L 11785#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x00000004 11786#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x00000020L 11787#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x00000005 11788#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x00000040L 11789#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x00000006 11790#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x00000080L 11791#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x00000007 11792#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x00000100L 11793#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x00000008 11794#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x00000200L 11795#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x00000009 11796#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0x0fffffffL 11797#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x00000000 11798#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x000000ffL 11799#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x00000000 11800#define VM_L2_CG__ENABLE_MASK 0x00040000L 11801#define VM_L2_CG__ENABLE__SHIFT 0x00000012 11802#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x00080000L 11803#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x00000013 11804#define VM_L2_CG__OFFDLY_MASK 0x00000fc0L 11805#define VM_L2_CG__OFFDLY__SHIFT 0x00000006 11806#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 11807#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x00000016 11808#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 11809#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x00000015 11810#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 11811#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x00000000 11812#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0c000000L 11813#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x0000001a 11814#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 11815#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x00000001 11816#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L 11817#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x00000017 11818#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003fL 11819#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x00000000 11820#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00e00000L 11821#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x00000015 11822#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 11823#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x0000001c 11824#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 11825#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x00000014 11826#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0f000000L 11827#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x00000018 11828#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 11829#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x0000001d 11830#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000f8000L 11831#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x0000000f 11832#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000c0L 11833#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x00000006 11834#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001f00L 11835#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x00000008 11836#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 11837#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x00000013 11838#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 11839#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0x0000000f 11840#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 11841#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x00000000 11842#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 11843#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x00000001 11844#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 11845#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x0000000a 11846#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 11847#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x00000009 11848#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03e00000L 11849#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x00000015 11850#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0c000000L 11851#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x0000001a 11852#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L 11853#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x0000001c 11854#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 11855#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x00000004 11856#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000cL 11857#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x00000002 11858#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 11859#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0x0000000c 11860#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 11861#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x00000008 11862#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 11863#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x00000012 11864#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11865#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11866#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11867#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11868#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0x0fffffffL 11869#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x00000000 11870#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001fffeL 11871#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x00000001 11872#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L 11873#define VM_L2_STATUS__L2_BUSY__SHIFT 0x00000000 11874#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11875#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11876#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11877#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11878#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11879#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11880#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11881#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11882#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11883#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11884#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11885#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11886#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11887#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11888#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL 11889#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 11890#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x00000008L 11891#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x00000003 11892#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x00000004L 11893#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x00000002 11894#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x00000001L 11895#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x00000000 11896#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x00000002L 11897#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x00000001 11898 11899#endif
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