FILE
gfx_7_2_sh_mask.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h
1/* 2 * GFX_7_2 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef GFX_7_2_SH_MASK_H 25#define GFX_7_2_SH_MASK_H 26 27#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff 28#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 29#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff 30#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 31#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff 32#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 33#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff 34#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 35#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8 36#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 37#define CB_COLOR_CONTROL__MODE_MASK 0x70 38#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 39#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000 40#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 41#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f 42#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 43#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0 44#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 45#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 46#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 47#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 48#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 49#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 50#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 51#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 52#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 53#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 54#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 55#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000 56#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e 57#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000 58#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f 59#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f 60#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 61#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0 62#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 63#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 64#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 65#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 66#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 67#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 68#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 69#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 70#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 71#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 72#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 73#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000 74#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e 75#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000 76#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f 77#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f 78#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 79#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0 80#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 81#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 82#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 83#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 84#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 85#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 86#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 87#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 88#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 89#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 90#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 91#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000 92#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e 93#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000 94#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f 95#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f 96#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 97#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0 98#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 99#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 100#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 101#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 102#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 103#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 104#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 105#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 106#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 107#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 108#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 109#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000 110#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e 111#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000 112#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f 113#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f 114#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 115#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0 116#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 117#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 118#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 119#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 120#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 121#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 122#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 123#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 124#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 125#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 126#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 127#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000 128#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e 129#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000 130#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f 131#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f 132#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 133#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0 134#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 135#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 136#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 137#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 138#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 139#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 140#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 141#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 142#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 143#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 144#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 145#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000 146#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e 147#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000 148#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f 149#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f 150#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 151#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0 152#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 153#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 154#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 155#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 156#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 157#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 158#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 159#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 160#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 161#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 162#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 163#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000 164#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e 165#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000 166#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f 167#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f 168#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 169#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0 170#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 171#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 172#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 173#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 174#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 175#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 176#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 177#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 178#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 179#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 180#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 181#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000 182#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e 183#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000 184#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f 185#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff 186#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 187#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff 188#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 189#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff 190#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 191#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff 192#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 193#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff 194#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 195#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff 196#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 197#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff 198#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 199#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff 200#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 201#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff 202#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0 203#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 204#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14 205#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff 206#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0 207#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 208#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14 209#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff 210#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0 211#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 212#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14 213#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff 214#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0 215#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 216#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14 217#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff 218#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0 219#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 220#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14 221#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff 222#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0 223#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 224#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14 225#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff 226#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0 227#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 228#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14 229#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff 230#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0 231#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 232#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14 233#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff 234#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0 235#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff 236#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0 237#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff 238#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0 239#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff 240#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0 241#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff 242#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0 243#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff 244#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0 245#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff 246#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0 247#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff 248#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0 249#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff 250#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 251#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000 252#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd 253#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff 254#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 255#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000 256#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd 257#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff 258#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 259#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000 260#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd 261#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff 262#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 263#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000 264#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd 265#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff 266#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 267#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000 268#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd 269#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff 270#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 271#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000 272#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd 273#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff 274#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 275#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000 276#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd 277#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff 278#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 279#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000 280#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd 281#define CB_COLOR0_INFO__ENDIAN_MASK 0x3 282#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 283#define CB_COLOR0_INFO__FORMAT_MASK 0x7c 284#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 285#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80 286#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 287#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700 288#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 289#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800 290#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb 291#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000 292#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd 293#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000 294#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe 295#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000 296#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf 297#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000 298#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 299#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000 300#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 301#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000 302#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 303#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000 304#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13 305#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 306#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 307#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 308#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 309#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 310#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 311#define CB_COLOR1_INFO__ENDIAN_MASK 0x3 312#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 313#define CB_COLOR1_INFO__FORMAT_MASK 0x7c 314#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 315#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80 316#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 317#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700 318#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 319#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800 320#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb 321#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000 322#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd 323#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000 324#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe 325#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000 326#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf 327#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000 328#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 329#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000 330#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 331#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000 332#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 333#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000 334#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13 335#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 336#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 337#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 338#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 339#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 340#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 341#define CB_COLOR2_INFO__ENDIAN_MASK 0x3 342#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 343#define CB_COLOR2_INFO__FORMAT_MASK 0x7c 344#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 345#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80 346#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 347#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700 348#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 349#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800 350#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb 351#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000 352#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd 353#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000 354#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe 355#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000 356#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf 357#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000 358#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 359#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000 360#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 361#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000 362#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 363#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000 364#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13 365#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 366#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 367#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 368#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 369#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 370#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 371#define CB_COLOR3_INFO__ENDIAN_MASK 0x3 372#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 373#define CB_COLOR3_INFO__FORMAT_MASK 0x7c 374#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 375#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80 376#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 377#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700 378#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 379#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800 380#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb 381#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000 382#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd 383#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000 384#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe 385#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000 386#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf 387#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000 388#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 389#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000 390#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 391#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000 392#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 393#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000 394#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13 395#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 396#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 397#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 398#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 399#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 400#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 401#define CB_COLOR4_INFO__ENDIAN_MASK 0x3 402#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 403#define CB_COLOR4_INFO__FORMAT_MASK 0x7c 404#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 405#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80 406#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 407#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700 408#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 409#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800 410#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb 411#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000 412#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd 413#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000 414#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe 415#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000 416#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf 417#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000 418#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 419#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000 420#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 421#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000 422#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 423#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000 424#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13 425#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 426#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 427#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 428#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 429#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 430#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 431#define CB_COLOR5_INFO__ENDIAN_MASK 0x3 432#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 433#define CB_COLOR5_INFO__FORMAT_MASK 0x7c 434#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 435#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80 436#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 437#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700 438#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 439#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800 440#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb 441#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000 442#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd 443#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000 444#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe 445#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000 446#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf 447#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000 448#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 449#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000 450#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 451#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000 452#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 453#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000 454#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13 455#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 456#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 457#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 458#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 459#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 460#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 461#define CB_COLOR6_INFO__ENDIAN_MASK 0x3 462#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 463#define CB_COLOR6_INFO__FORMAT_MASK 0x7c 464#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 465#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80 466#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 467#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700 468#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 469#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800 470#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb 471#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000 472#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd 473#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000 474#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe 475#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000 476#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf 477#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000 478#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 479#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000 480#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 481#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000 482#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 483#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000 484#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13 485#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 486#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 487#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 488#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 489#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 490#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 491#define CB_COLOR7_INFO__ENDIAN_MASK 0x3 492#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 493#define CB_COLOR7_INFO__FORMAT_MASK 0x7c 494#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 495#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80 496#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 497#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700 498#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 499#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800 500#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb 501#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000 502#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd 503#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000 504#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe 505#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000 506#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf 507#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000 508#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 509#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000 510#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 511#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000 512#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 513#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000 514#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13 515#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 516#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 517#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 518#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 519#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 520#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 521#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 522#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 523#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 524#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 525#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 526#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 527#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000 528#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc 529#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 530#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 531#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 532#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 533#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 534#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 535#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 536#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 537#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 538#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 539#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000 540#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc 541#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 542#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 543#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 544#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 545#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 546#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 547#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 548#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 549#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 550#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 551#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000 552#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc 553#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 554#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 555#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 556#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 557#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 558#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 559#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 560#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 561#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 562#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 563#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000 564#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc 565#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 566#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 567#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 568#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 569#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 570#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 571#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 572#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 573#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 574#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 575#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000 576#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc 577#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 578#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 579#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 580#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 581#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 582#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 583#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 584#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 585#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 586#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 587#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000 588#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc 589#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 590#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 591#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 592#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 593#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 594#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 595#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 596#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 597#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 598#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 599#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000 600#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc 601#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 602#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 603#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 604#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 605#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 606#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 607#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 608#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 609#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 610#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 611#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000 612#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc 613#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 614#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 615#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 616#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 617#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff 618#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 619#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff 620#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 621#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff 622#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 623#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff 624#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 625#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff 626#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 627#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff 628#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 629#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff 630#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 631#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff 632#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 633#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff 634#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0 635#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff 636#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0 637#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff 638#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0 639#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff 640#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0 641#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff 642#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0 643#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff 644#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0 645#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff 646#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0 647#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff 648#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0 649#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff 650#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 651#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff 652#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 653#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff 654#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 655#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff 656#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 657#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff 658#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 659#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff 660#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 661#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff 662#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 663#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff 664#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 665#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 666#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0 667#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 668#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0 669#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 670#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0 671#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 672#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0 673#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 674#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0 675#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 676#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0 677#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 678#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0 679#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 680#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0 681#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 682#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 683#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 684#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 685#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 686#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 687#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 688#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 689#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 690#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 691#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 692#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 693#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 694#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 695#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 696#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 697#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 698#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 699#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 700#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 701#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 702#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 703#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 704#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 705#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 706#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 707#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 708#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 709#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 710#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 711#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 712#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 713#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf 714#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 715#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0 716#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 717#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00 718#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 719#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000 720#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc 721#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000 722#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 723#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000 724#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 725#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000 726#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 727#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000 728#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c 729#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf 730#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 731#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0 732#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 733#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00 734#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 735#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000 736#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc 737#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000 738#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 739#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000 740#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 741#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000 742#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 743#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000 744#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c 745#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf 746#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 747#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0 748#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 749#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000 750#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc 751#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000 752#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 753#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000 754#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 755#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000 756#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 757#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000 758#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 759#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000 760#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 761#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000 762#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 763#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000 764#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 765#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000 766#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 767#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000 768#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 769#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000 770#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a 771#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000 772#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b 773#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000 774#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c 775#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000 776#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d 777#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000 778#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e 779#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000 780#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f 781#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f 782#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 783#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0 784#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 785#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800 786#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb 787#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000 788#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 789#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000 790#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a 791#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff 792#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 793#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00 794#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 795#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000 796#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf 797#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff000000 798#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x18 799#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1 800#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 801#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1 802#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 803#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe 804#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 805#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10 806#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 807#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0 808#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 809#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400 810#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa 811#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800 812#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb 813#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000 814#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc 815#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000 816#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd 817#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000 818#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 819#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000 820#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 821#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000 822#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 823#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000 824#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 825#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff 826#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 827#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00 828#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 829#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 830#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 831#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 832#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 833#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 834#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 835#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff 836#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 837#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00 838#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 839#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 840#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 841#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 842#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 843#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff 844#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 845#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 846#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 847#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff 848#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 849#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 850#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 851#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff 852#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 853#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 854#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 855#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 856#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 857#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 858#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 859#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 860#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 861#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 862#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 863#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 864#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 865#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 866#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 867#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 868#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 869#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 870#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 871#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf 872#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 873#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 874#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 875#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 876#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 877#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 878#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 879#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 880#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 881#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 882#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 883#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 884#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 885#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 886#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 887#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 888#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 889#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 890#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 891#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x1 892#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x0 893#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x2 894#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x1 895#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x4 896#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x2 897#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x8 898#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x3 899#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x10 900#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x4 901#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x20 902#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x5 903#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x40 904#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x6 905#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x80 906#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x7 907#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x100 908#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x8 909#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x200 910#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x9 911#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x400 912#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0xa 913#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x7f800 914#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0xb 915#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x1 916#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x0 917#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x2 918#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x1 919#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x4 920#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x2 921#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x8 922#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x3 923#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x10 924#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x4 925#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x20 926#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x5 927#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x40 928#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x6 929#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x80 930#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x7 931#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x100 932#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x8 933#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x3 934#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x0 935#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x4 936#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x2 937#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x8 938#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x3 939#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x10 940#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x4 941#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x20 942#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x5 943#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x40 944#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x6 945#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x80 946#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x7 947#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x100 948#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x8 949#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x3f 950#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x0 951#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x3c0 952#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x6 953#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0xfc00 954#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0xa 955#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0xf0000 956#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x10 957#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x100000 958#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14 959#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x200000 960#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15 961#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x400000 962#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16 963#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x1 964#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x0 965#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x2 966#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x1 967#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x4 968#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x2 969#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x8 970#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x3 971#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x10 972#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x4 973#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x20 974#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x5 975#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x40 976#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x6 977#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x80 978#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x7 979#define CB_DEBUG_BUS_18__NOT_USED_MASK 0xffffff 980#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x0 981#define CP_DFY_CNTL__POLICY_MASK 0x300 982#define CP_DFY_CNTL__POLICY__SHIFT 0x8 983#define CP_DFY_CNTL__VOL_MASK 0x400 984#define CP_DFY_CNTL__VOL__SHIFT 0xa 985#define CP_DFY_CNTL__ATC_MASK 0x800 986#define CP_DFY_CNTL__ATC__SHIFT 0xb 987#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff 988#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 989#define CP_DFY_STAT__TAGS_PENDING_MASK 0xff0000 990#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 991#define CP_DFY_STAT__BUSY_MASK 0x80000000 992#define CP_DFY_STAT__BUSY__SHIFT 0x1f 993#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff 994#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 995#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0 996#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 997#define CP_DFY_DATA_0__DATA_MASK 0xffffffff 998#define CP_DFY_DATA_0__DATA__SHIFT 0x0 999#define CP_DFY_DATA_1__DATA_MASK 0xffffffff 1000#define CP_DFY_DATA_1__DATA__SHIFT 0x0 1001#define CP_DFY_DATA_2__DATA_MASK 0xffffffff 1002#define CP_DFY_DATA_2__DATA__SHIFT 0x0 1003#define CP_DFY_DATA_3__DATA_MASK 0xffffffff 1004#define CP_DFY_DATA_3__DATA__SHIFT 0x0 1005#define CP_DFY_DATA_4__DATA_MASK 0xffffffff 1006#define CP_DFY_DATA_4__DATA__SHIFT 0x0 1007#define CP_DFY_DATA_5__DATA_MASK 0xffffffff 1008#define CP_DFY_DATA_5__DATA__SHIFT 0x0 1009#define CP_DFY_DATA_6__DATA_MASK 0xffffffff 1010#define CP_DFY_DATA_6__DATA__SHIFT 0x0 1011#define CP_DFY_DATA_7__DATA_MASK 0xffffffff 1012#define CP_DFY_DATA_7__DATA__SHIFT 0x0 1013#define CP_DFY_DATA_8__DATA_MASK 0xffffffff 1014#define CP_DFY_DATA_8__DATA__SHIFT 0x0 1015#define CP_DFY_DATA_9__DATA_MASK 0xffffffff 1016#define CP_DFY_DATA_9__DATA__SHIFT 0x0 1017#define CP_DFY_DATA_10__DATA_MASK 0xffffffff 1018#define CP_DFY_DATA_10__DATA__SHIFT 0x0 1019#define CP_DFY_DATA_11__DATA_MASK 0xffffffff 1020#define CP_DFY_DATA_11__DATA__SHIFT 0x0 1021#define CP_DFY_DATA_12__DATA_MASK 0xffffffff 1022#define CP_DFY_DATA_12__DATA__SHIFT 0x0 1023#define CP_DFY_DATA_13__DATA_MASK 0xffffffff 1024#define CP_DFY_DATA_13__DATA__SHIFT 0x0 1025#define CP_DFY_DATA_14__DATA_MASK 0xffffffff 1026#define CP_DFY_DATA_14__DATA__SHIFT 0x0 1027#define CP_DFY_DATA_15__DATA_MASK 0xffffffff 1028#define CP_DFY_DATA_15__DATA__SHIFT 0x0 1029#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff 1030#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 1031#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff 1032#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 1033#define CP_RB_BASE__RB_BASE_MASK 0xffffffff 1034#define CP_RB_BASE__RB_BASE__SHIFT 0x0 1035#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff 1036#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 1037#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff 1038#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 1039#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff 1040#define CP_RB2_BASE__RB_BASE__SHIFT 0x0 1041#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f 1042#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 1043#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00 1044#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 1045#define CP_RB0_CNTL__BUF_SWAP_MASK 0x30000 1046#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x10 1047#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000 1048#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 1049#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 1050#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 1051#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x3000000 1052#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 1053#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x4000000 1054#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a 1055#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000 1056#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b 1057#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 1058#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 1059#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f 1060#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 1061#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00 1062#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 1063#define CP_RB_CNTL__BUF_SWAP_MASK 0x30000 1064#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x10 1065#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000 1066#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 1067#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 1068#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 1069#define CP_RB_CNTL__CACHE_POLICY_MASK 0x3000000 1070#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 1071#define CP_RB_CNTL__RB_VOLATILE_MASK 0x4000000 1072#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a 1073#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000 1074#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b 1075#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 1076#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 1077#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f 1078#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 1079#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00 1080#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 1081#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000 1082#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 1083#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 1084#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 1085#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x3000000 1086#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 1087#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x4000000 1088#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a 1089#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000 1090#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b 1091#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 1092#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 1093#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f 1094#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 1095#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00 1096#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 1097#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000 1098#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 1099#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 1100#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 1101#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x3000000 1102#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 1103#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x4000000 1104#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x1a 1105#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000 1106#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b 1107#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 1108#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 1109#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff 1110#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 1111#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 1112#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 1113#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc 1114#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 1115#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 1116#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 1117#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc 1118#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 1119#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 1120#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 1121#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc 1122#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 1123#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 1124#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 1125#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc 1126#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 1127#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff 1128#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 1129#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff 1130#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 1131#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff 1132#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 1133#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff 1134#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 1135#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff 1136#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 1137#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff 1138#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 1139#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff 1140#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 1141#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff 1142#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 1143#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffc 1144#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x2 1145#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0xff 1146#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x0 1147#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1148#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1149#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1150#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1151#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000 1152#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 1153#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 1154#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 1155#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000 1156#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 1157#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1158#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1159#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1160#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1161#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1162#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1163#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1164#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1165#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1166#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1167#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1168#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1169#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1170#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1171#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1172#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1173#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1174#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1175#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000 1176#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 1177#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 1178#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 1179#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 1180#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 1181#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 1182#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 1183#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1184#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1185#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1186#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1187#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1188#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1189#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000 1190#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d 1191#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000 1192#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e 1193#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000 1194#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f 1195#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1196#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1197#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1198#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1199#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000 1200#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 1201#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 1202#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 1203#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000 1204#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 1205#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000 1206#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 1207#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1208#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1209#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1210#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1211#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1212#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1213#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000 1214#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d 1215#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000 1216#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e 1217#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000 1218#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f 1219#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1220#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1221#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1222#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1223#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000 1224#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 1225#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 1226#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 1227#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000 1228#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 1229#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000 1230#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 1231#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1232#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1233#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1234#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1235#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1236#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1237#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000 1238#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d 1239#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000 1240#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e 1241#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000 1242#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f 1243#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000 1244#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 1245#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 1246#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 1247#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000 1248#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 1249#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000 1250#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 1251#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000 1252#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 1253#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000 1254#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 1255#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000 1256#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 1257#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000 1258#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a 1259#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 1260#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 1261#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000 1262#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d 1263#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000 1264#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e 1265#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000 1266#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f 1267#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000 1268#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 1269#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 1270#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 1271#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x80000 1272#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x13 1273#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000 1274#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 1275#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000 1276#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 1277#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000 1278#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 1279#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000 1280#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 1281#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000 1282#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a 1283#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 1284#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 1285#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000 1286#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d 1287#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000 1288#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e 1289#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000 1290#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f 1291#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000 1292#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 1293#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 1294#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 1295#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000 1296#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 1297#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000 1298#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 1299#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000 1300#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 1301#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000 1302#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 1303#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000 1304#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 1305#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000 1306#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a 1307#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 1308#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 1309#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000 1310#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d 1311#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000 1312#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e 1313#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000 1314#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f 1315#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000 1316#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 1317#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 1318#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 1319#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000 1320#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 1321#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000 1322#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 1323#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000 1324#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 1325#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000 1326#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 1327#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000 1328#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 1329#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000 1330#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a 1331#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 1332#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 1333#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000 1334#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d 1335#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000 1336#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e 1337#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000 1338#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f 1339#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff 1340#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 1341#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff 1342#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 1343#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 1344#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 1345#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 1346#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 1347#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 1348#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 1349#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff 1350#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 1351#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 1352#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 1353#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 1354#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 1355#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 1356#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 1357#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3 1358#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 1359#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3 1360#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 1361#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3 1362#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 1363#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3 1364#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 1365#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3 1366#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 1367#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3 1368#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 1369#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3 1370#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0 1371#define CP_RB_VMID__RB0_VMID_MASK 0xf 1372#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 1373#define CP_RB_VMID__RB1_VMID_MASK 0xf00 1374#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 1375#define CP_RB_VMID__RB2_VMID_MASK 0xf0000 1376#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 1377#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf 1378#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 1379#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf 1380#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 1381#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0xfff 1382#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 1383#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 1384#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 1385#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0xfff 1386#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 1387#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0xfff 1388#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 1389#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff 1390#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 1391#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf 1392#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 1393#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 1394#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1395#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 1396#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 1397#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 1398#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 1399#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf 1400#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 1401#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 1402#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1403#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 1404#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 1405#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 1406#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 1407#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf 1408#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 1409#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 1410#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1411#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 1412#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 1413#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 1414#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 1415#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff 1416#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 1417#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 1418#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 1419#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff 1420#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 1421#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 1422#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 1423#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff 1424#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 1425#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 1426#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 1427#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 1428#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 1429#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 1430#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 1431#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 1432#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 1433#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x1 1434#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x0 1435#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 1436#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 1437#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2 1438#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 1439#define CP_MEM_SLP_CNTL__RESERVED_MASK 0xfc 1440#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 1441#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00 1442#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 1443#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000 1444#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 1445#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 1446#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 1447#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3 1448#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 1449#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0xf0 1450#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x4 1451#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x3c00 1452#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0xa 1453#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000 1454#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 1455#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x3 1456#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x0 1457#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0xf0 1458#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x4 1459#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x3c00 1460#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0xa 1461#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0xf0000 1462#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x10 1463#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x3 1464#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x0 1465#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0xf0 1466#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x4 1467#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x3c00 1468#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0xa 1469#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0xf0000 1470#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x10 1471#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x3 1472#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x0 1473#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0xf0 1474#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x4 1475#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x3c00 1476#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0xa 1477#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0xf0000 1478#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x10 1479#define CP_FETCHER_SOURCE__ME_SRC_MASK 0x1 1480#define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0 1481#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff 1482#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 1483#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000 1484#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e 1485#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000 1486#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f 1487#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff 1488#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 1489#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1490#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1491#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1492#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1493#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1494#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1495#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1496#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1497#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1498#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1499#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1500#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1501#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1502#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1503#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1504#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1505#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1506#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1507#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1508#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1509#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1510#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1511#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1512#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1513#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1514#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1515#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1516#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1517#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1518#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1519#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1520#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1521#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1522#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1523#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1524#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1525#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1526#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1527#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1528#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1529#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1530#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1531#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1532#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1533#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1534#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1535#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1536#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1537#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1538#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1539#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1540#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1541#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1542#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1543#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1544#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1545#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1546#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1547#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1548#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1549#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1550#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1551#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1552#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1553#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1554#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1555#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1556#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1557#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1558#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1559#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1560#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1561#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1562#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1563#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1564#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1565#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1566#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1567#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1568#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1569#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1570#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1571#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1572#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1573#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1574#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1575#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1576#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1577#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1578#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1579#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1580#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1581#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1582#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1583#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1584#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1585#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1586#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1587#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1588#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1589#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1590#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1591#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1592#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1593#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1594#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1595#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1596#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1597#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1598#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1599#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1600#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1601#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1602#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1603#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1604#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1605#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1606#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1607#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1608#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1609#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1610#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1611#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1612#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1613#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1614#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1615#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1616#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1617#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1618#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1619#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1620#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1621#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1622#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1623#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1624#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1625#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1626#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1627#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1628#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1629#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1630#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1631#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1632#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1633#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1634#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1635#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1636#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1637#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1638#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1639#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1640#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1641#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1642#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1643#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1644#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1645#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1646#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1647#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1648#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1649#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1650#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1651#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1652#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1653#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1654#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1655#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1656#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1657#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1658#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1659#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1660#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1661#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1662#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1663#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1664#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1665#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1666#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1667#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1668#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1669#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 1670#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 1671#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 1672#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 1673#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 1674#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 1675#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 1676#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 1677#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 1678#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 1679#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 1680#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 1681#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 1682#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 1683#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 1684#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1685#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 1686#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 1687#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 1688#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 1689#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 1690#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 1691#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 1692#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 1693#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 1694#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 1695#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 1696#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 1697#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 1698#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 1699#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 1700#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 1701#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 1702#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 1703#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 1704#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1705#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 1706#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 1707#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 1708#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 1709#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 1710#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 1711#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 1712#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 1713#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 1714#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 1715#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 1716#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 1717#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 1718#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 1719#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 1720#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 1721#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 1722#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 1723#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 1724#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1725#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 1726#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 1727#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 1728#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 1729#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 1730#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 1731#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 1732#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 1733#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 1734#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 1735#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 1736#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 1737#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 1738#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 1739#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 1740#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 1741#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 1742#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 1743#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 1744#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1745#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 1746#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 1747#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 1748#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 1749#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 1750#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 1751#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 1752#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 1753#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 1754#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 1755#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 1756#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 1757#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 1758#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 1759#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 1760#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 1761#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 1762#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 1763#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 1764#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1765#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 1766#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 1767#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 1768#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 1769#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 1770#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 1771#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 1772#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 1773#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 1774#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 1775#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 1776#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 1777#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 1778#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 1779#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 1780#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 1781#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 1782#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 1783#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 1784#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1785#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 1786#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 1787#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 1788#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 1789#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 1790#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 1791#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 1792#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 1793#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 1794#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 1795#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 1796#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 1797#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 1798#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 1799#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 1800#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 1801#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 1802#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 1803#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 1804#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1805#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 1806#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 1807#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 1808#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 1809#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 1810#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 1811#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 1812#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 1813#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 1814#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 1815#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 1816#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 1817#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 1818#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 1819#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 1820#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 1821#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 1822#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 1823#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 1824#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1825#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 1826#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 1827#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 1828#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 1829#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 1830#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 1831#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 1832#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 1833#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 1834#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 1835#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 1836#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 1837#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 1838#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 1839#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 1840#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 1841#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 1842#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 1843#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 1844#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1845#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 1846#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 1847#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 1848#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 1849#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 1850#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd 1851#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 1852#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe 1853#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 1854#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 1855#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 1856#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 1857#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 1858#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 1859#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 1860#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a 1861#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 1862#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b 1863#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 1864#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 1865#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 1866#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e 1867#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 1868#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f 1869#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 1870#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd 1871#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 1872#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe 1873#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 1874#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 1875#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 1876#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 1877#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 1878#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 1879#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 1880#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a 1881#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 1882#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b 1883#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 1884#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 1885#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 1886#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e 1887#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 1888#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f 1889#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff 1890#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 1891#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 1892#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 1893#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 1894#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 1895#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 1896#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 1897#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3 1898#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 1899#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3 1900#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 1901#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3 1902#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 1903#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3 1904#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 1905#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff 1906#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 1907#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 1908#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 1909#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 1910#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 1911#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 1912#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 1913#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3 1914#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 1915#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3 1916#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 1917#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3 1918#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 1919#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3 1920#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 1921#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff 1922#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 1923#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x7ff 1924#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 1925#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x7ff 1926#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 1927#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xfff 1928#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 1929#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xfff 1930#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 1931#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff 1932#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 1933#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x7ff 1934#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 1935#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x7ff 1936#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 1937#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xfff 1938#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 1939#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xfff 1940#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 1941#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7 1942#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 1943#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70 1944#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 1945#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000 1946#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 1947#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000 1948#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 1949#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7 1950#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 1951#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff 1952#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 1953#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00 1954#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 1955#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000 1956#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 1957#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000 1958#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 1959#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff 1960#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 1961#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00 1962#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 1963#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000 1964#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 1965#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000 1966#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 1967#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff 1968#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 1969#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000 1970#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10 1971#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff 1972#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 1973#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000 1974#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x10 1975#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xffff 1976#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 1977#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1 1978#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 1979#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2 1980#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 1981#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1 1982#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 1983#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2 1984#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 1985#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4 1986#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 1987#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8 1988#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 1989#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10 1990#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 1991#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20 1992#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 1993#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40 1994#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 1995#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80 1996#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 1997#define CP_CPC_STATUS__MIU_RDREQ_BUSY_MASK 0x100 1998#define CP_CPC_STATUS__MIU_RDREQ_BUSY__SHIFT 0x8 1999#define CP_CPC_STATUS__MIU_WRREQ_BUSY_MASK 0x200 2000#define CP_CPC_STATUS__MIU_WRREQ_BUSY__SHIFT 0x9 2001#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400 2002#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa 2003#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800 2004#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb 2005#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000 2006#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc 2007#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000 2008#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d 2009#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000 2010#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e 2011#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000 2012#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f 2013#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1 2014#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 2015#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2 2016#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 2017#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4 2018#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 2019#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8 2020#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 2021#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10 2022#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 2023#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20 2024#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 2025#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40 2026#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 2027#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80 2028#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 2029#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100 2030#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 2031#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200 2032#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 2033#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400 2034#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa 2035#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800 2036#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb 2037#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000 2038#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc 2039#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000 2040#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd 2041#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000 2042#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 2043#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000 2044#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 2045#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000 2046#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 2047#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000 2048#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 2049#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000 2050#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 2051#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000 2052#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 2053#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000 2054#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 2055#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000 2056#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 2057#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000 2058#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 2059#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000 2060#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 2061#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000 2062#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a 2063#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000 2064#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b 2065#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000 2066#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c 2067#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000 2068#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d 2069#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL_MASK 0x1 2070#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL__SHIFT 0x0 2071#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL_MASK 0x2 2072#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL__SHIFT 0x1 2073#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8 2074#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 2075#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10 2076#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 2077#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40 2078#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 2079#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100 2080#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 2081#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200 2082#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 2083#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400 2084#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa 2085#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ_MASK 0x800 2086#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ__SHIFT 0xb 2087#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK_MASK 0x1000 2088#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK__SHIFT 0xc 2089#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000 2090#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd 2091#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000 2092#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 2093#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000 2094#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 2095#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000 2096#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 2097#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ_MASK 0x80000 2098#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ__SHIFT 0x13 2099#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK_MASK 0x100000 2100#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK__SHIFT 0x14 2101#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000 2102#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 2103#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1 2104#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 2105#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2 2106#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 2107#define CP_CPF_STATUS__MIU_RDREQ_BUSY_MASK 0x4 2108#define CP_CPF_STATUS__MIU_RDREQ_BUSY__SHIFT 0x2 2109#define CP_CPF_STATUS__MIU_WRREQ_BUSY_MASK 0x8 2110#define CP_CPF_STATUS__MIU_WRREQ_BUSY__SHIFT 0x3 2111#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10 2112#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 2113#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20 2114#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 2115#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40 2116#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 2117#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80 2118#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 2119#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100 2120#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 2121#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200 2122#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 2123#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400 2124#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa 2125#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800 2126#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb 2127#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000 2128#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc 2129#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000 2130#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd 2131#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000 2132#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe 2133#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000 2134#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf 2135#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000 2136#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e 2137#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000 2138#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f 2139#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 2140#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 2141#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2 2142#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 2143#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4 2144#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 2145#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8 2146#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 2147#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10 2148#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 2149#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20 2150#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 2151#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40 2152#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 2153#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80 2154#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 2155#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100 2156#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 2157#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200 2158#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 2159#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800 2160#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb 2161#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000 2162#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc 2163#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000 2164#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd 2165#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000 2166#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe 2167#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000 2168#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf 2169#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000 2170#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 2171#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000 2172#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 2173#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000 2174#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 2175#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000 2176#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 2177#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000 2178#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 2179#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000 2180#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 2181#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000 2182#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 2183#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000 2184#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 2185#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000 2186#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 2187#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000 2188#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 2189#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000 2190#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a 2191#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000 2192#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b 2193#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000 2194#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c 2195#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000 2196#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d 2197#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000 2198#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e 2199#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000 2200#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f 2201#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1 2202#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 2203#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2 2204#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 2205#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4 2206#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 2207#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8 2208#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 2209#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10 2210#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x4 2211#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20 2212#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 2213#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40 2214#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 2215#define CP_CPC_MC_CNTL__PACK_DELAY_CNT_MASK 0x1f 2216#define CP_CPC_MC_CNTL__PACK_DELAY_CNT__SHIFT 0x0 2217#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f 2218#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 2219#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10 2220#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 2221#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 2222#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c 2223#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000 2224#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d 2225#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 2226#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e 2227#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000 2228#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f 2229#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff 2230#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 2231#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff 2232#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 2233#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff 2234#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 2235#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff 2236#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 2237#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 2238#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 2239#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 2240#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 2241#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 2242#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 2243#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f 2244#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 2245#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 2246#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 2247#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 2248#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 2249#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 2250#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 2251#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 2252#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 2253#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 2254#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 2255#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 2256#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 2257#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 2258#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 2259#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 2260#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 2261#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 2262#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 2263#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f 2264#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 2265#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 2266#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 2267#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 2268#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 2269#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 2270#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 2271#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 2272#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 2273#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 2274#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 2275#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 2276#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 2277#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 2278#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 2279#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 2280#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 2281#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 2282#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 2283#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f 2284#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 2285#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 2286#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 2287#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 2288#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 2289#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 2290#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 2291#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 2292#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 2293#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 2294#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 2295#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 2296#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 2297#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf 2298#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 2299#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff 2300#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 2301#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff 2302#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 2303#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff 2304#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 2305#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff 2306#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 2307#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff 2308#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 2309#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000 2310#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 2311#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1 2312#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 2313#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2 2314#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 2315#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4 2316#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 2317#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100 2318#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 2319#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff 2320#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 2321#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff 2322#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 2323#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3 2324#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 2325#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc 2326#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2 2327#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00 2328#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa 2329#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000 2330#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12 2331#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000 2332#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13 2333#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP_MASK 0x300000 2334#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP__SHIFT 0x14 2335#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000 2336#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17 2337#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff 2338#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 2339#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff 2340#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 2341#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff 2342#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 2343#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff 2344#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 2345#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff 2346#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 2347#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f 2348#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 2349#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000 2350#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc 2351#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x6000000 2352#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19 2353#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x8000000 2354#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b 2355#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff 2356#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0 2357#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000 2358#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 2359#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000 2360#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 2361#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000 2362#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d 2363#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x3 2364#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x0 2365#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc 2366#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 2367#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff 2368#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 2369#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff 2370#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 2371#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff 2372#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 2373#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff 2374#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 2375#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff 2376#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 2377#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x3 2378#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x0 2379#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc 2380#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 2381#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff 2382#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 2383#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff 2384#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 2385#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff 2386#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 2387#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff 2388#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 2389#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff 2390#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 2391#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff 2392#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 2393#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff 2394#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 2395#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff 2396#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 2397#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff 2398#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 2399#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff 2400#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 2401#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff 2402#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 2403#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff 2404#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 2405#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff 2406#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 2407#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff 2408#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 2409#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff 2410#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 2411#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff 2412#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 2413#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff 2414#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 2415#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x3 2416#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x0 2417#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc 2418#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 2419#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff 2420#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 2421#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff 2422#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 2423#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff 2424#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 2425#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff 2426#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 2427#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff 2428#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 2429#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff 2430#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 2431#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff 2432#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 2433#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff 2434#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 2435#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff 2436#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 2437#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff 2438#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 2439#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff 2440#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 2441#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff 2442#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 2443#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff 2444#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 2445#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff 2446#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 2447#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff 2448#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 2449#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff 2450#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 2451#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff 2452#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 2453#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff 2454#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 2455#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff 2456#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 2457#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff 2458#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 2459#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff 2460#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 2461#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff 2462#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 2463#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff 2464#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 2465#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff 2466#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 2467#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff 2468#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 2469#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1 2470#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 2471#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff 2472#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 2473#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff 2474#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 2475#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff 2476#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 2477#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff 2478#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 2479#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff 2480#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 2481#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff 2482#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 2483#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff 2484#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 2485#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff 2486#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 2487#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff 2488#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 2489#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000 2490#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 2491#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff 2492#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 2493#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff 2494#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 2495#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff 2496#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 2497#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff 2498#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 2499#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff 2500#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 2501#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff 2502#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 2503#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff 2504#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 2505#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc 2506#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 2507#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff 2508#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 2509#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000 2510#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 2511#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000 2512#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d 2513#define CP_APPEND_DATA__DATA_MASK 0xffffffff 2514#define CP_APPEND_DATA__DATA__SHIFT 0x0 2515#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff 2516#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 2517#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff 2518#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 2519#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff 2520#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 2521#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff 2522#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 2523#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff 2524#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 2525#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff 2526#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 2527#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff 2528#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 2529#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff 2530#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 2531#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff 2532#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 2533#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff 2534#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 2535#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff 2536#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 2537#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff 2538#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 2539#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff 2540#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 2541#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff 2542#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 2543#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3 2544#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0 2545#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc 2546#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 2547#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff 2548#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 2549#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff 2550#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 2551#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff 2552#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 2553#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3 2554#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0 2555#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc 2556#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 2557#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff 2558#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 2559#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff 2560#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 2561#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 2562#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 2563#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 2564#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 2565#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff 2566#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 2567#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 2568#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 2569#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 2570#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 2571#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 2572#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 2573#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 2574#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 2575#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 2576#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 2577#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 2578#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 2579#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff 2580#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 2581#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 2582#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 2583#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 2584#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 2585#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 2586#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 2587#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 2588#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 2589#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff 2590#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 2591#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f 2592#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 2593#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1 2594#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 2595#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2 2596#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 2597#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40 2598#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 2599#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80 2600#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 2601#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100 2602#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 2603#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200 2604#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 2605#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400 2606#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa 2607#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800 2608#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb 2609#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000 2610#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc 2611#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000 2612#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd 2613#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000 2614#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe 2615#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000 2616#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf 2617#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x10000 2618#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x10 2619#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000 2620#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 2621#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000 2622#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 2623#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000 2624#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 2625#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000 2626#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 2627#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000 2628#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 2629#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000 2630#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 2631#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000 2632#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a 2633#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000 2634#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b 2635#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000 2636#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c 2637#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000 2638#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d 2639#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff 2640#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 2641#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff 2642#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 2643#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff 2644#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 2645#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff 2646#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 2647#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff 2648#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 2649#define CP_COHER_STATUS__MEID_MASK 0x3000000 2650#define CP_COHER_STATUS__MEID__SHIFT 0x18 2651#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000 2652#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e 2653#define CP_COHER_STATUS__STATUS_MASK 0x80000000 2654#define CP_COHER_STATUS__STATUS__SHIFT 0x1f 2655#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff 2656#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 2657#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff 2658#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 2659#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff 2660#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 2661#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff 2662#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 2663#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff 2664#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 2665#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff 2666#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 2667#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff 2668#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 2669#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff 2670#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 2671#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff 2672#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 2673#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff 2674#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 2675#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff 2676#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 2677#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff 2678#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 2679#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000 2680#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc 2681#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x6000 2682#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd 2683#define CP_DMA_ME_CONTROL__SRC_VOLATILE_MASK 0x8000 2684#define CP_DMA_ME_CONTROL__SRC_VOLATILE__SHIFT 0xf 2685#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000 2686#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 2687#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000 2688#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18 2689#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x6000000 2690#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 2691#define CP_DMA_ME_CONTROL__DST_VOLATILE_MASK 0x8000000 2692#define CP_DMA_ME_CONTROL__DST_VOLATILE__SHIFT 0x1b 2693#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000 2694#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d 2695#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff 2696#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 2697#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000 2698#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15 2699#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000 2700#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16 2701#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000 2702#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18 2703#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000 2704#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a 2705#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000 2706#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b 2707#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000 2708#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c 2709#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000 2710#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d 2711#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000 2712#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e 2713#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff 2714#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 2715#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff 2716#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 2717#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff 2718#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 2719#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff 2720#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 2721#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000 2722#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc 2723#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x6000 2724#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd 2725#define CP_DMA_PFP_CONTROL__SRC_VOLATILE_MASK 0x8000 2726#define CP_DMA_PFP_CONTROL__SRC_VOLATILE__SHIFT 0xf 2727#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000 2728#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 2729#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000 2730#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18 2731#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x6000000 2732#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 2733#define CP_DMA_PFP_CONTROL__DST_VOLATILE_MASK 0x8000000 2734#define CP_DMA_PFP_CONTROL__DST_VOLATILE__SHIFT 0x1b 2735#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000 2736#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d 2737#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff 2738#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 2739#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000 2740#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15 2741#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000 2742#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16 2743#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000 2744#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18 2745#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000 2746#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a 2747#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000 2748#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b 2749#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000 2750#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c 2751#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000 2752#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d 2753#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000 2754#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e 2755#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30 2756#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 2757#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000 2758#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 2759#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000 2760#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c 2761#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000 2762#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d 2763#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000 2764#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e 2765#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff 2766#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 2767#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000 2768#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c 2769#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff 2770#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 2771#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1 2772#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 2773#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2 2774#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 2775#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x8000 2776#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf 2777#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000 2778#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 2779#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000 2780#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 2781#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff 2782#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 2783#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff 2784#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 2785#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff 2786#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 2787#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff 2788#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 2789#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff 2790#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 2791#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff 2792#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 2793#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff 2794#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 2795#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff 2796#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 2797#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff 2798#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 2799#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff 2800#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 2801#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff 2802#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 2803#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff 2804#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 2805#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1 2806#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 2807#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4 2808#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 2809#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10 2810#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 2811#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400 2812#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa 2813#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800 2814#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb 2815#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000 2816#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc 2817#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000 2818#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd 2819#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x4000 2820#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0xe 2821#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000 2822#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf 2823#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10000 2824#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x10 2825#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x20000 2826#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x11 2827#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000 2828#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 2829#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000 2830#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 2831#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000 2832#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 2833#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000 2834#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a 2835#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000 2836#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b 2837#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000 2838#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c 2839#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000 2840#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d 2841#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 2842#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 2843#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2 2844#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 2845#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4 2846#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 2847#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10 2848#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 2849#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20 2850#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 2851#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x40 2852#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x6 2853#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x80 2854#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x7 2855#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100 2856#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 2857#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200 2858#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 2859#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400 2860#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa 2861#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800 2862#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb 2863#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000 2864#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc 2865#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000 2866#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd 2867#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000 2868#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe 2869#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000 2870#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf 2871#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000 2872#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 2873#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000 2874#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 2875#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000 2876#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 2877#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000 2878#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 2879#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000 2880#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 2881#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000 2882#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 2883#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000 2884#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 2885#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000 2886#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 2887#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000 2888#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 2889#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000 2890#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 2891#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000 2892#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a 2893#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000 2894#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b 2895#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000 2896#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c 2897#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000 2898#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d 2899#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000 2900#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e 2901#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000 2902#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f 2903#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 2904#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 2905#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2 2906#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 2907#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4 2908#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 2909#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8 2910#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 2911#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10 2912#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 2913#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20 2914#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 2915#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40 2916#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 2917#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80 2918#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 2919#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x100 2920#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x8 2921#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400 2922#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa 2923#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800 2924#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb 2925#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000 2926#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc 2927#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000 2928#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd 2929#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000 2930#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe 2931#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000 2932#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf 2933#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 2934#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 2935#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40 2936#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 2937#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80 2938#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 2939#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100 2940#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 2941#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200 2942#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 2943#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400 2944#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa 2945#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000 2946#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc 2947#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000 2948#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd 2949#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000 2950#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe 2951#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000 2952#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf 2953#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000 2954#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 2955#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000 2956#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 2957#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000 2958#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 2959#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000 2960#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 2961#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000 2962#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 2963#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000 2964#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 2965#define CP_STAT__MIU_RDREQ_BUSY_MASK 0x80 2966#define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x7 2967#define CP_STAT__MIU_WRREQ_BUSY_MASK 0x100 2968#define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x8 2969#define CP_STAT__ROQ_RING_BUSY_MASK 0x200 2970#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 2971#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400 2972#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa 2973#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800 2974#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb 2975#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000 2976#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc 2977#define CP_STAT__DC_BUSY_MASK 0x2000 2978#define CP_STAT__DC_BUSY__SHIFT 0xd 2979#define CP_STAT__PFP_BUSY_MASK 0x8000 2980#define CP_STAT__PFP_BUSY__SHIFT 0xf 2981#define CP_STAT__MEQ_BUSY_MASK 0x10000 2982#define CP_STAT__MEQ_BUSY__SHIFT 0x10 2983#define CP_STAT__ME_BUSY_MASK 0x20000 2984#define CP_STAT__ME_BUSY__SHIFT 0x11 2985#define CP_STAT__QUERY_BUSY_MASK 0x40000 2986#define CP_STAT__QUERY_BUSY__SHIFT 0x12 2987#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000 2988#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 2989#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000 2990#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 2991#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000 2992#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 2993#define CP_STAT__DMA_BUSY_MASK 0x400000 2994#define CP_STAT__DMA_BUSY__SHIFT 0x16 2995#define CP_STAT__RCIU_BUSY_MASK 0x800000 2996#define CP_STAT__RCIU_BUSY__SHIFT 0x17 2997#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000 2998#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 2999#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000 3000#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19 3001#define CP_STAT__CE_BUSY_MASK 0x4000000 3002#define CP_STAT__CE_BUSY__SHIFT 0x1a 3003#define CP_STAT__TCIU_BUSY_MASK 0x8000000 3004#define CP_STAT__TCIU_BUSY__SHIFT 0x1b 3005#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000 3006#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c 3007#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000 3008#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d 3009#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000 3010#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e 3011#define CP_STAT__CP_BUSY_MASK 0x80000000 3012#define CP_STAT__CP_BUSY__SHIFT 0x1f 3013#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff 3014#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 3015#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff 3016#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 3017#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f 3018#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 3019#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00 3020#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 3021#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000 3022#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 3023#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff 3024#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 3025#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x1f 3026#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x0 3027#define CP_MC_TAG_CNTL__TAG_RAM_INDEX_MASK 0x3f 3028#define CP_MC_TAG_CNTL__TAG_RAM_INDEX__SHIFT 0x0 3029#define CP_MC_TAG_CNTL__TAG_RAM_SEL_MASK 0x30000 3030#define CP_MC_TAG_CNTL__TAG_RAM_SEL__SHIFT 0x10 3031#define CP_MC_TAG_DATA__TAG_RAM_DATA_MASK 0xffffffff 3032#define CP_MC_TAG_DATA__TAG_RAM_DATA__SHIFT 0x0 3033#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf 3034#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0 3035#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x3f00 3036#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 3037#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf 3038#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0 3039#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10 3040#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 3041#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40 3042#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 3043#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100 3044#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 3045#define CP_ME_CNTL__CE_HALT_MASK 0x1000000 3046#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 3047#define CP_ME_CNTL__CE_STEP_MASK 0x2000000 3048#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 3049#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000 3050#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a 3051#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000 3052#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b 3053#define CP_ME_CNTL__ME_HALT_MASK 0x10000000 3054#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c 3055#define CP_ME_CNTL__ME_STEP_MASK 0x20000000 3056#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d 3057#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff 3058#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 3059#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700 3060#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 3061#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000 3062#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 3063#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000 3064#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c 3065#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x1 3066#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x0 3067#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff 3068#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 3069#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff 3070#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 3071#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff 3072#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 3073#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff 3074#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 3075#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff 3076#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 3077#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000 3078#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c 3079#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff 3080#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 3081#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 3082#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 3083#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0 3084#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 3085#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff 3086#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 3087#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff 3088#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 3089#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc 3090#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 3091#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff 3092#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 3093#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff 3094#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 3095#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc 3096#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 3097#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff 3098#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 3099#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff 3100#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 3101#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc 3102#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 3103#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff 3104#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 3105#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff 3106#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 3107#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc 3108#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 3109#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff 3110#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 3111#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff 3112#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 3113#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc 3114#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 3115#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff 3116#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 3117#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff 3118#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 3119#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff 3120#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 3121#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00 3122#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 3123#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff 3124#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 3125#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff 3126#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 3127#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00 3128#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 3129#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000 3130#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 3131#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000 3132#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 3133#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff 3134#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 3135#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00 3136#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 3137#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000 3138#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 3139#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000 3140#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 3141#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff 3142#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 3143#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00 3144#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 3145#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000 3146#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 3147#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f 3148#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 3149#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00 3150#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 3151#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff 3152#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 3153#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00 3154#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 3155#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff 3156#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 3157#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000 3158#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 3159#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff 3160#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 3161#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff 3162#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 3163#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff 3164#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 3165#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff 3166#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 3167#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000 3168#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc 3169#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x30000 3170#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 3171#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff 3172#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 3173#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff 3174#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 3175#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000 3176#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 3177#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff 3178#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 3179#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000 3180#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 3181#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff 3182#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 3183#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000 3184#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 3185#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff 3186#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 3187#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff 3188#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 3189#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff 3190#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 3191#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000 3192#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 3193#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff 3194#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 3195#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000 3196#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 3197#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff 3198#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 3199#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff 3200#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 3201#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 3202#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 3203#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff 3204#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 3205#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000 3206#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 3207#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff 3208#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 3209#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000 3210#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 3211#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 3212#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe 3213#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 3214#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 3215#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000 3216#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 3217#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000 3218#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 3219#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000 3220#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 3221#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 3222#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 3223#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 3224#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 3225#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 3226#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a 3227#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 3228#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b 3229#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 3230#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 3231#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 3232#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e 3233#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 3234#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f 3235#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf 3236#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 3237#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0 3238#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 3239#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 3240#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 3241#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 3242#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa 3243#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000 3244#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f 3245#define CP_RINGID__RINGID_MASK 0x3 3246#define CP_RINGID__RINGID__SHIFT 0x0 3247#define CP_PIPEID__PIPE_ID_MASK 0x3 3248#define CP_PIPEID__PIPE_ID__SHIFT 0x0 3249#define CP_VMID__VMID_MASK 0xf 3250#define CP_VMID__VMID__SHIFT 0x0 3251#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7 3252#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 3253#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00 3254#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 3255#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000 3256#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 3257#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff 3258#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 3259#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff 3260#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 3261#define CP_HPD_EOP_VMID__VMID_MASK 0xf 3262#define CP_HPD_EOP_VMID__VMID__SHIFT 0x0 3263#define CP_HPD_EOP_CONTROL__EOP_SIZE_MASK 0x3f 3264#define CP_HPD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 3265#define CP_HPD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100 3266#define CP_HPD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 3267#define CP_HPD_EOP_CONTROL__PROCESSING_QID_MASK 0xe00 3268#define CP_HPD_EOP_CONTROL__PROCESSING_QID__SHIFT 0x9 3269#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000 3270#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc 3271#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000 3272#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd 3273#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000 3274#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe 3275#define CP_HPD_EOP_CONTROL__EOP_ATC_MASK 0x800000 3276#define CP_HPD_EOP_CONTROL__EOP_ATC__SHIFT 0x17 3277#define CP_HPD_EOP_CONTROL__CACHE_POLICY_MASK 0x3000000 3278#define CP_HPD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 3279#define CP_HPD_EOP_CONTROL__EOP_VOLATILE_MASK 0x4000000 3280#define CP_HPD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a 3281#define CP_HPD_EOP_CONTROL__PEND_Q_SEM_MASK 0x70000000 3282#define CP_HPD_EOP_CONTROL__PEND_Q_SEM__SHIFT 0x1c 3283#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000 3284#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f 3285#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc 3286#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 3287#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff 3288#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 3289#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1 3290#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 3291#define CP_HQD_VMID__VMID_MASK 0xf 3292#define CP_HQD_VMID__VMID__SHIFT 0x0 3293#define CP_HQD_VMID__IB_VMID_MASK 0xf00 3294#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 3295#define CP_HQD_VMID__VQID_MASK 0x3ff0000 3296#define CP_HQD_VMID__VQID__SHIFT 0x10 3297#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1 3298#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 3299#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00 3300#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 3301#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000 3302#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f 3303#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3 3304#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 3305#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf 3306#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 3307#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1 3308#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 3309#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10 3310#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 3311#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00 3312#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 3313#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff 3314#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 3315#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff 3316#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 3317#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff 3318#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 3319#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc 3320#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 3321#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff 3322#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 3323#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc 3324#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2 3325#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff 3326#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 3327#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc 3328#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 3329#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000 3330#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c 3331#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000 3332#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d 3333#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000 3334#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e 3335#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000 3336#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f 3337#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff 3338#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0 3339#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f 3340#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 3341#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00 3342#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 3343#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x30000 3344#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x10 3345#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000 3346#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 3347#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000 3348#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17 3349#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x3000000 3350#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 3351#define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x4000000 3352#define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a 3353#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000 3354#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b 3355#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 3356#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c 3357#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000 3358#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d 3359#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000 3360#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e 3361#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000 3362#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f 3363#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc 3364#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 3365#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff 3366#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 3367#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff 3368#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 3369#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff 3370#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 3371#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000 3372#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 3373#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000 3374#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17 3375#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x3000000 3376#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 3377#define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x4000000 3378#define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a 3379#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000 3380#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f 3381#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff 3382#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 3383#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700 3384#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 3385#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000 3386#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc 3387#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000 3388#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 3389#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000 3390#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17 3391#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x3000000 3392#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 3393#define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x4000000 3394#define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a 3395#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000 3396#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d 3397#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000 3398#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e 3399#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000 3400#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f 3401#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f 3402#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 3403#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x3 3404#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 3405#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10 3406#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 3407#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100 3408#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 3409#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1 3410#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 3411#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1 3412#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 3413#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6 3414#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 3415#define CP_HQD_MSG_TYPE__ACTION_MASK 0x3 3416#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 3417#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff 3418#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 3419#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff 3420#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 3421#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff 3422#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 3423#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff 3424#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 3425#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS_MASK 0x3 3426#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS__SHIFT 0x0 3427#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT_MASK 0xc 3428#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT__SHIFT 0x2 3429#define CP_HQD_HQ_SCHEDULER0__RSV_5_4_MASK 0x30 3430#define CP_HQD_HQ_SCHEDULER0__RSV_5_4__SHIFT 0x4 3431#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK 0x40 3432#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT 0x6 3433#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK 0x80 3434#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT 0x7 3435#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK 0x100 3436#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT 0x8 3437#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED_MASK 0x200 3438#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED__SHIFT 0x9 3439#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED_MASK 0x400 3440#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED__SHIFT 0xa 3441#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11_MASK 0xfffff800 3442#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11__SHIFT 0xb 3443#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff 3444#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 3445#define CP_MQD_CONTROL__VMID_MASK 0xf 3446#define CP_MQD_CONTROL__VMID__SHIFT 0x0 3447#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000 3448#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17 3449#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x3000000 3450#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 3451#define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x4000000 3452#define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a 3453#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff 3454#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 3455#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff 3456#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 3457#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff 3458#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 3459#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff 3460#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 3461#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf 3462#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0 3463#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0 3464#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4 3465#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00 3466#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8 3467#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000 3468#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd 3469#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000 3470#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf 3471#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000 3472#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11 3473#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000 3474#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13 3475#define DB_Z_INFO__FORMAT_MASK 0x3 3476#define DB_Z_INFO__FORMAT__SHIFT 0x0 3477#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc 3478#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 3479#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000 3480#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd 3481#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000 3482#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14 3483#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 3484#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b 3485#define DB_Z_INFO__READ_SIZE_MASK 0x10000000 3486#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c 3487#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000 3488#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d 3489#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000 3490#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f 3491#define DB_STENCIL_INFO__FORMAT_MASK 0x1 3492#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 3493#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000 3494#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd 3495#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000 3496#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14 3497#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 3498#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b 3499#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000 3500#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d 3501#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff 3502#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0 3503#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800 3504#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb 3505#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff 3506#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0 3507#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff 3508#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 3509#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000 3510#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd 3511#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000 3512#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 3513#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000 3514#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 3515#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1 3516#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 3517#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2 3518#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 3519#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4 3520#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 3521#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8 3522#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 3523#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10 3524#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 3525#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20 3526#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 3527#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40 3528#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 3529#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80 3530#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 3531#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00 3532#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 3533#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1 3534#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 3535#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2 3536#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 3537#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70 3538#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 3539#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00 3540#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 3541#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000 3542#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc 3543#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000 3544#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 3545#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000 3546#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 3547#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000 3548#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 3549#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000 3550#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c 3551#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3 3552#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 3553#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc 3554#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 3555#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30 3556#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 3557#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40 3558#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 3559#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80 3560#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 3561#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100 3562#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 3563#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200 3564#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 3565#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400 3566#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa 3567#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800 3568#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb 3569#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000 3570#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc 3571#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000 3572#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd 3573#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000 3574#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf 3575#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000 3576#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 3577#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000 3578#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 3579#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000 3580#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 3581#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000 3582#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 3583#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000 3584#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 3585#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000 3586#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a 3587#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000 3588#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b 3589#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000 3590#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c 3591#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000 3592#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d 3593#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000 3594#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e 3595#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000 3596#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f 3597#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3 3598#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 3599#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c 3600#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 3601#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20 3602#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 3603#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40 3604#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 3605#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80 3606#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 3607#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100 3608#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 3609#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200 3610#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 3611#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400 3612#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa 3613#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800 3614#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb 3615#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000 3616#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc 3617#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000 3618#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf 3619#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000 3620#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 3621#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000 3622#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 3623#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000 3624#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 3625#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000 3626#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 3627#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7 3628#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 3629#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70 3630#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 3631#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700 3632#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 3633#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000 3634#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc 3635#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000 3636#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 3637#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000 3638#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 3639#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000 3640#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 3641#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000 3642#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 3643#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000 3644#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 3645#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000 3646#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 3647#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000 3648#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 3649#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000 3650#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b 3651#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1 3652#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 3653#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2 3654#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 3655#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4 3656#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 3657#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30 3658#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 3659#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40 3660#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 3661#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80 3662#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 3663#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100 3664#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 3665#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200 3666#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 3667#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400 3668#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa 3669#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800 3670#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb 3671#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000 3672#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc 3673#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000 3674#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd 3675#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff 3676#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 3677#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff 3678#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 3679#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff 3680#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 3681#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff 3682#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 3683#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff 3684#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 3685#define DB_HTILE_SURFACE__LINEAR_MASK 0x1 3686#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0 3687#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2 3688#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 3689#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4 3690#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 3691#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8 3692#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 3693#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0 3694#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 3695#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00 3696#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa 3697#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000 3698#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 3699#define DB_PRELOAD_CONTROL__START_X_MASK 0xff 3700#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 3701#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00 3702#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 3703#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000 3704#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 3705#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000 3706#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 3707#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff 3708#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 3709#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00 3710#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 3711#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000 3712#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 3713#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000 3714#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 3715#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff 3716#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 3717#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00 3718#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 3719#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000 3720#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 3721#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000 3722#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 3723#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7 3724#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 3725#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0 3726#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 3727#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000 3728#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc 3729#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000 3730#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 3731#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7 3732#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 3733#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0 3734#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 3735#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000 3736#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc 3737#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000 3738#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 3739#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1 3740#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 3741#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2 3742#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 3743#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4 3744#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 3745#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8 3746#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 3747#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70 3748#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 3749#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80 3750#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 3751#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700 3752#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 3753#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000 3754#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 3755#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000 3756#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e 3757#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000 3758#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f 3759#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf 3760#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 3761#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0 3762#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 3763#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00 3764#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 3765#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000 3766#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc 3767#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000 3768#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 3769#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000 3770#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 3771#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1 3772#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 3773#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300 3774#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 3775#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00 3776#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa 3777#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000 3778#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc 3779#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000 3780#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe 3781#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000 3782#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 3783#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 3784#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 3785#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 3786#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 3787#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 3788#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 3789#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 3790#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 3791#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 3792#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 3793#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 3794#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 3795#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 3796#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 3797#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 3798#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 3799#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 3800#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 3801#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 3802#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 3803#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 3804#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 3805#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 3806#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa 3807#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 3808#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 3809#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000 3810#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 3811#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 3812#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 3813#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 3814#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 3815#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 3816#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa 3817#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 3818#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 3819#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000 3820#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 3821#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 3822#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 3823#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 3824#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 3825#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 3826#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 3827#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 3828#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 3829#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 3830#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 3831#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 3832#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 3833#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 3834#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 3835#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 3836#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 3837#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 3838#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c 3839#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 3840#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 3841#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 3842#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 3843#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 3844#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 3845#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 3846#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 3847#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 3848#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 3849#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 3850#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 3851#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 3852#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 3853#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 3854#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 3855#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1 3856#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 3857#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2 3858#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 3859#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4 3860#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 3861#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8 3862#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 3863#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30 3864#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 3865#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40 3866#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 3867#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80 3868#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 3869#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300 3870#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 3871#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00 3872#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa 3873#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000 3874#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc 3875#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000 3876#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe 3877#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000 3878#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf 3879#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000 3880#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 3881#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000 3882#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 3883#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000 3884#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 3885#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000 3886#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 3887#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000 3888#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 3889#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000 3890#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 3891#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000 3892#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 3893#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000 3894#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 3895#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000 3896#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c 3897#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000 3898#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d 3899#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000 3900#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e 3901#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000 3902#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f 3903#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1 3904#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 3905#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2 3906#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 3907#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4 3908#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 3909#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8 3910#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 3911#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10 3912#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 3913#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20 3914#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5 3915#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40 3916#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6 3917#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80 3918#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7 3919#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100 3920#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8 3921#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00 3922#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 3923#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000 3924#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe 3925#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000 3926#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf 3927#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000 3928#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10 3929#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000 3930#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 3931#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000 3932#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 3933#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000 3934#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 3935#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000 3936#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c 3937#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000 3938#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d 3939#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000 3940#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e 3941#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000 3942#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f 3943#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4 3944#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 3945#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8 3946#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 3947#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10 3948#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 3949#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20 3950#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 3951#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40 3952#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 3953#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80 3954#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 3955#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100 3956#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 3957#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200 3958#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 3959#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400 3960#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa 3961#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800 3962#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb 3963#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000 3964#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc 3965#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000 3966#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd 3967#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000 3968#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe 3969#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000 3970#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf 3971#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000 3972#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 3973#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000 3974#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 3975#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000 3976#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 3977#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000 3978#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 3979#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000 3980#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 3981#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000 3982#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 3983#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000 3984#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 3985#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000 3986#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 3987#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000 3988#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 3989#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000 3990#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 3991#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000 3992#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a 3993#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000 3994#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b 3995#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000 3996#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c 3997#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000 3998#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d 3999#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xc0000000 4000#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x1e 4001#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1 4002#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 4003#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2 4004#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 4005#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4 4006#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 4007#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8 4008#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 4009#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0 4010#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4 4011#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f 4012#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 4013#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0 4014#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 4015#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00 4016#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa 4017#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000 4018#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 4019#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f 4020#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 4021#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0 4022#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 4023#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800 4024#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb 4025#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000 4026#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf 4027#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000 4028#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 4029#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000 4030#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b 4031#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000 4032#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c 4033#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000 4034#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d 4035#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000 4036#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e 4037#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000 4038#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f 4039#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3 4040#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 4041#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc 4042#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 4043#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30 4044#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 4045#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0 4046#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 4047#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300 4048#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 4049#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00 4050#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa 4051#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000 4052#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc 4053#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000 4054#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe 4055#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000 4056#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 4057#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000 4058#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 4059#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f 4060#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 4061#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80 4062#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 4063#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000 4064#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe 4065#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000 4066#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15 4067#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000 4068#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19 4069#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f 4070#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 4071#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0 4072#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5 4073#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00 4074#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa 4075#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000 4076#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 4077#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000 4078#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 4079#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff 4080#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 4081#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00 4082#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 4083#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000 4084#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf 4085#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000 4086#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 4087#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf 4088#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 4089#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0 4090#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 4091#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000 4092#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc 4093#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000 4094#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 4095#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000 4096#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 4097#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000 4098#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a 4099#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000 4100#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b 4101#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000 4102#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c 4103#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000 4104#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d 4105#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000 4106#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e 4107#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000 4108#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f 4109#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff 4110#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 4111#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff 4112#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 4113#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3 4114#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 4115#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff 4116#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0 4117#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff 4118#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0 4119#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff 4120#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0 4121#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff 4122#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0 4123#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff 4124#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0 4125#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff 4126#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0 4127#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff 4128#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0 4129#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff 4130#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0 4131#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff 4132#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0 4133#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff 4134#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0 4135#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff 4136#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0 4137#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff 4138#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0 4139#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff 4140#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0 4141#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff 4142#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0 4143#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff 4144#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0 4145#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff 4146#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0 4147#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff 4148#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 4149#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff 4150#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 4151#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff 4152#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 4153#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff 4154#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 4155#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff 4156#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 4157#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff 4158#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 4159#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff 4160#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 4161#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff 4162#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 4163#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 4164#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 4165#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 4166#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc 4167#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 4168#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 4169#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 4170#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 4171#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 4172#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 4173#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 4174#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 4175#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 4176#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc 4177#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 4178#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 4179#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 4180#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 4181#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 4182#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 4183#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 4184#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 4185#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 4186#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 4187#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 4188#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 4189#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 4190#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 4191#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 4192#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 4193#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 4194#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 4195#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 4196#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 4197#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 4198#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 4199#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 4200#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 4201#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff 4202#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 4203#define GB_GPU_ID__GPU_ID_MASK 0xf 4204#define GB_GPU_ID__GPU_ID__SHIFT 0x0 4205#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf 4206#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 4207#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0 4208#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 4209#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00 4210#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 4211#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000 4212#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc 4213#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000 4214#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 4215#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000 4216#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 4217#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000 4218#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 4219#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000 4220#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c 4221#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c 4222#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 4223#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0 4224#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 4225#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800 4226#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb 4227#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4228#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 4229#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000 4230#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 4231#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c 4232#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 4233#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0 4234#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 4235#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800 4236#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb 4237#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4238#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 4239#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000 4240#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 4241#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c 4242#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 4243#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0 4244#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 4245#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800 4246#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb 4247#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4248#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 4249#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000 4250#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 4251#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c 4252#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 4253#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0 4254#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 4255#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800 4256#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb 4257#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4258#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 4259#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000 4260#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 4261#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c 4262#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 4263#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0 4264#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 4265#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800 4266#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb 4267#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4268#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 4269#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000 4270#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 4271#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c 4272#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 4273#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0 4274#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 4275#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800 4276#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb 4277#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4278#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 4279#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000 4280#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 4281#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c 4282#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 4283#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0 4284#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 4285#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800 4286#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb 4287#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4288#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 4289#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000 4290#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 4291#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c 4292#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 4293#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0 4294#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 4295#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800 4296#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb 4297#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4298#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 4299#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000 4300#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 4301#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c 4302#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 4303#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0 4304#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 4305#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800 4306#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb 4307#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4308#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 4309#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000 4310#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 4311#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c 4312#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 4313#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0 4314#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 4315#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800 4316#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb 4317#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4318#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 4319#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000 4320#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 4321#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c 4322#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 4323#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0 4324#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 4325#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800 4326#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb 4327#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4328#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 4329#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000 4330#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 4331#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c 4332#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 4333#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0 4334#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 4335#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800 4336#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb 4337#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4338#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 4339#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000 4340#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 4341#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c 4342#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 4343#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0 4344#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 4345#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800 4346#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb 4347#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4348#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 4349#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000 4350#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 4351#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c 4352#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 4353#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0 4354#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 4355#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800 4356#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb 4357#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4358#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 4359#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000 4360#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 4361#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c 4362#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 4363#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0 4364#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 4365#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800 4366#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb 4367#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4368#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 4369#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000 4370#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 4371#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c 4372#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 4373#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0 4374#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 4375#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800 4376#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb 4377#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4378#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 4379#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000 4380#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 4381#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c 4382#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 4383#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0 4384#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 4385#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800 4386#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb 4387#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4388#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 4389#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000 4390#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 4391#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c 4392#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 4393#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0 4394#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 4395#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800 4396#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb 4397#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4398#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 4399#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000 4400#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 4401#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c 4402#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 4403#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0 4404#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 4405#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800 4406#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb 4407#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4408#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 4409#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000 4410#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 4411#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c 4412#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 4413#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0 4414#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 4415#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800 4416#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb 4417#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4418#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 4419#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000 4420#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 4421#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c 4422#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 4423#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0 4424#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 4425#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800 4426#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb 4427#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4428#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 4429#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000 4430#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 4431#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c 4432#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 4433#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0 4434#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 4435#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800 4436#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb 4437#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4438#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 4439#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000 4440#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 4441#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c 4442#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 4443#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0 4444#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 4445#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800 4446#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb 4447#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4448#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 4449#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000 4450#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 4451#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c 4452#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 4453#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0 4454#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 4455#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800 4456#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb 4457#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4458#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 4459#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000 4460#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 4461#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c 4462#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 4463#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0 4464#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 4465#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800 4466#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb 4467#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4468#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 4469#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000 4470#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 4471#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c 4472#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 4473#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0 4474#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 4475#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800 4476#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb 4477#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4478#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 4479#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000 4480#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 4481#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c 4482#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 4483#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0 4484#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 4485#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800 4486#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb 4487#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4488#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 4489#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000 4490#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 4491#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c 4492#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 4493#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0 4494#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 4495#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800 4496#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb 4497#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4498#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 4499#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000 4500#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 4501#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c 4502#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 4503#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0 4504#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 4505#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800 4506#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb 4507#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4508#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 4509#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000 4510#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 4511#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c 4512#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 4513#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0 4514#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 4515#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800 4516#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb 4517#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4518#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 4519#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000 4520#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 4521#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c 4522#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 4523#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0 4524#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 4525#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800 4526#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb 4527#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4528#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 4529#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000 4530#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 4531#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c 4532#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 4533#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0 4534#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 4535#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800 4536#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb 4537#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4538#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 4539#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000 4540#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 4541#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3 4542#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 4543#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc 4544#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 4545#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30 4546#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 4547#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0 4548#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 4549#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3 4550#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 4551#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc 4552#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 4553#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30 4554#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 4555#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0 4556#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 4557#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3 4558#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 4559#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc 4560#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 4561#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30 4562#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 4563#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0 4564#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 4565#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3 4566#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 4567#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc 4568#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 4569#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30 4570#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 4571#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0 4572#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 4573#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3 4574#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 4575#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc 4576#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 4577#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30 4578#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 4579#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0 4580#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 4581#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3 4582#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 4583#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc 4584#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 4585#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30 4586#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 4587#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0 4588#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 4589#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3 4590#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 4591#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc 4592#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 4593#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30 4594#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 4595#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0 4596#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 4597#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3 4598#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 4599#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc 4600#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 4601#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30 4602#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 4603#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0 4604#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 4605#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3 4606#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 4607#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc 4608#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 4609#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30 4610#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 4611#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0 4612#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 4613#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3 4614#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 4615#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc 4616#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 4617#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30 4618#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 4619#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0 4620#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 4621#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3 4622#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 4623#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc 4624#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 4625#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30 4626#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 4627#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0 4628#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 4629#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3 4630#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 4631#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc 4632#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 4633#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30 4634#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 4635#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0 4636#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 4637#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3 4638#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 4639#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc 4640#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 4641#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30 4642#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 4643#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0 4644#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 4645#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3 4646#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 4647#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc 4648#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 4649#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30 4650#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 4651#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0 4652#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 4653#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3 4654#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 4655#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc 4656#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 4657#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30 4658#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 4659#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0 4660#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 4661#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3 4662#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 4663#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc 4664#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 4665#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30 4666#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 4667#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0 4668#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 4669#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000 4670#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10 4671#define GB_EDC_MODE__DED_MODE_MASK 0x300000 4672#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 4673#define GB_EDC_MODE__PROP_FED_MASK 0x20000000 4674#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d 4675#define GB_EDC_MODE__BYPASS_MASK 0x80000000 4676#define GB_EDC_MODE__BYPASS__SHIFT 0x1f 4677#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2 4678#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 4679#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1 4680#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 4681#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff 4682#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 4683#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4684#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 4685#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff 4686#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 4687#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff 4688#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 4689#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff 4690#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 4691#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4692#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 4693#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4694#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 4695#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4696#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 4697#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4698#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0 4699#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4700#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 4701#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff 4702#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 4703#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff 4704#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 4705#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff 4706#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 4707#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff 4708#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 4709#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff 4710#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 4711#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff 4712#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 4713#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff 4714#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 4715#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4716#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 4717#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff 4718#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 4719#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4720#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 4721#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff 4722#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 4723#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4724#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 4725#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4726#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 4727#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4728#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 4729#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff 4730#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 4731#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff 4732#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 4733#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7 4734#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 4735#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff 4736#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 4737#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 4738#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 4739#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff 4740#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 4741#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f 4742#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 4743#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0 4744#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 4745#define GRBM_PWR_CNTL__REQ_TYPE_MASK 0xf 4746#define GRBM_PWR_CNTL__REQ_TYPE__SHIFT 0x0 4747#define GRBM_PWR_CNTL__RSP_TYPE_MASK 0xf0 4748#define GRBM_PWR_CNTL__RSP_TYPE__SHIFT 0x4 4749#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf 4750#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 4751#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20 4752#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5 4753#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80 4754#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 4755#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100 4756#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 4757#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200 4758#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 4759#define GRBM_STATUS__DB_CLEAN_MASK 0x1000 4760#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc 4761#define GRBM_STATUS__CB_CLEAN_MASK 0x2000 4762#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd 4763#define GRBM_STATUS__TA_BUSY_MASK 0x4000 4764#define GRBM_STATUS__TA_BUSY__SHIFT 0xe 4765#define GRBM_STATUS__GDS_BUSY_MASK 0x8000 4766#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf 4767#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000 4768#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 4769#define GRBM_STATUS__VGT_BUSY_MASK 0x20000 4770#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 4771#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000 4772#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 4773#define GRBM_STATUS__IA_BUSY_MASK 0x80000 4774#define GRBM_STATUS__IA_BUSY__SHIFT 0x13 4775#define GRBM_STATUS__SX_BUSY_MASK 0x100000 4776#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 4777#define GRBM_STATUS__WD_BUSY_MASK 0x200000 4778#define GRBM_STATUS__WD_BUSY__SHIFT 0x15 4779#define GRBM_STATUS__SPI_BUSY_MASK 0x400000 4780#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 4781#define GRBM_STATUS__BCI_BUSY_MASK 0x800000 4782#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 4783#define GRBM_STATUS__SC_BUSY_MASK 0x1000000 4784#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 4785#define GRBM_STATUS__PA_BUSY_MASK 0x2000000 4786#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 4787#define GRBM_STATUS__DB_BUSY_MASK 0x4000000 4788#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a 4789#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000 4790#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c 4791#define GRBM_STATUS__CP_BUSY_MASK 0x20000000 4792#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d 4793#define GRBM_STATUS__CB_BUSY_MASK 0x40000000 4794#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e 4795#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000 4796#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f 4797#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf 4798#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 4799#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10 4800#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 4801#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20 4802#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 4803#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40 4804#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 4805#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80 4806#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 4807#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100 4808#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 4809#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200 4810#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 4811#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400 4812#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa 4813#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800 4814#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb 4815#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000 4816#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc 4817#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000 4818#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd 4819#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000 4820#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe 4821#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000 4822#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 4823#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000 4824#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 4825#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000 4826#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c 4827#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000 4828#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d 4829#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000 4830#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e 4831#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2 4832#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 4833#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4 4834#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 4835#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000 4836#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 4837#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000 4838#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 4839#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000 4840#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 4841#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000 4842#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 4843#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000 4844#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a 4845#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000 4846#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b 4847#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000 4848#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d 4849#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000 4850#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e 4851#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000 4852#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f 4853#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2 4854#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 4855#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4 4856#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 4857#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000 4858#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 4859#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000 4860#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 4861#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000 4862#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 4863#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000 4864#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 4865#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000 4866#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a 4867#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000 4868#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b 4869#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000 4870#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d 4871#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000 4872#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e 4873#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000 4874#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f 4875#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2 4876#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 4877#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4 4878#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 4879#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000 4880#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 4881#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000 4882#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 4883#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000 4884#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 4885#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000 4886#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 4887#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000 4888#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a 4889#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000 4890#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b 4891#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000 4892#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d 4893#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000 4894#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e 4895#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000 4896#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f 4897#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2 4898#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 4899#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4 4900#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 4901#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000 4902#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 4903#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000 4904#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 4905#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000 4906#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 4907#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000 4908#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 4909#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000 4910#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a 4911#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000 4912#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b 4913#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000 4914#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d 4915#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000 4916#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e 4917#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000 4918#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f 4919#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1 4920#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 4921#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4 4922#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 4923#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000 4924#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 4925#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000 4926#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 4927#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000 4928#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 4929#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000 4930#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 4931#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f 4932#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0 4933#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff 4934#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0 4935#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff 4936#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 4937#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00 4938#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 4939#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000 4940#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 4941#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000 4942#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d 4943#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 4944#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e 4945#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000 4946#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f 4947#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 4948#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 4949#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 4950#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 4951#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff 4952#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 4953#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2 4954#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1 4955#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20 4956#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5 4957#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40 4958#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6 4959#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80 4960#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7 4961#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00 4962#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8 4963#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000 4964#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc 4965#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1 4966#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0 4967#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2 4968#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1 4969#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4 4970#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2 4971#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8 4972#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3 4973#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10 4974#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4 4975#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20 4976#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5 4977#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40 4978#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6 4979#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80 4980#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7 4981#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100 4982#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8 4983#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200 4984#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9 4985#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400 4986#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa 4987#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800 4988#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb 4989#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000 4990#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc 4991#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000 4992#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd 4993#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000 4994#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe 4995#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000 4996#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf 4997#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000 4998#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10 4999#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000 5000#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11 5001#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000 5002#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12 5003#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000 5004#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13 5005#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000 5006#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14 5007#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000 5008#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15 5009#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc 5010#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 5011#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000 5012#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 5013#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000 5014#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 5015#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 5016#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f 5017#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000 5018#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11 5019#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000 5020#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 5021#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000 5022#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 5023#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000 5024#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 5025#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000 5026#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 5027#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000 5028#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 5029#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000 5030#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 5031#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000 5032#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 5033#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000 5034#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 5035#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000 5036#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a 5037#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000 5038#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b 5039#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000 5040#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c 5041#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000 5042#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d 5043#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000 5044#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e 5045#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000 5046#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f 5047#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1 5048#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 5049#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000 5050#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 5051#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 5052#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 5053#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5054#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5055#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5056#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5057#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 5058#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5059#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 5060#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5061#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 5062#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe 5063#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 5064#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5065#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 5066#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 5067#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 5068#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 5069#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 5070#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 5071#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 5072#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 5073#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 5074#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 5075#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 5076#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 5077#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 5078#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 5079#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 5080#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 5081#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 5082#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 5083#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 5084#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a 5085#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 5086#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b 5087#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 5088#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c 5089#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 5090#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 5091#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5092#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5093#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5094#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5095#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 5096#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5097#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 5098#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5099#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 5100#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe 5101#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 5102#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5103#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 5104#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 5105#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 5106#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 5107#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 5108#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 5109#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 5110#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 5111#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 5112#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 5113#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 5114#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 5115#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 5116#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 5117#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 5118#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 5119#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 5120#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 5121#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 5122#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a 5123#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 5124#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b 5125#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 5126#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c 5127#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f 5128#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 5129#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5130#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5131#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5132#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5133#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 5134#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5135#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 5136#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5137#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 5138#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 5139#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 5140#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5141#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 5142#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 5143#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 5144#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 5145#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 5146#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 5147#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 5148#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 5149#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 5150#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 5151#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f 5152#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 5153#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5154#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5155#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5156#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5157#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 5158#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5159#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 5160#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5161#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 5162#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 5163#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 5164#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5165#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 5166#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 5167#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 5168#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 5169#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 5170#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 5171#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 5172#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 5173#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 5174#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 5175#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f 5176#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 5177#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5178#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5179#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5180#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5181#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 5182#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5183#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 5184#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5185#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 5186#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 5187#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 5188#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5189#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 5190#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 5191#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 5192#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 5193#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 5194#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 5195#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 5196#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 5197#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 5198#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 5199#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f 5200#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 5201#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5202#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5203#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5204#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5205#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 5206#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5207#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 5208#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5209#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 5210#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 5211#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 5212#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5213#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 5214#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 5215#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 5216#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 5217#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 5218#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 5219#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 5220#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 5221#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 5222#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 5223#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 5224#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 5225#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 5226#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 5227#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 5228#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 5229#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 5230#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 5231#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff 5232#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 5233#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff 5234#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 5235#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff 5236#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 5237#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff 5238#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 5239#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff 5240#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 5241#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff 5242#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 5243#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff 5244#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 5245#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff 5246#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 5247#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff 5248#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 5249#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff 5250#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 5251#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff 5252#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 5253#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff 5254#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 5255#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff 5256#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 5257#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff 5258#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 5259#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff 5260#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 5261#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff 5262#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 5263#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff 5264#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0 5265#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff 5266#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 5267#define GRBM_NOWHERE__DATA_MASK 0xffffffff 5268#define GRBM_NOWHERE__DATA__SHIFT 0x0 5269#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff 5270#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 5271#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff 5272#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 5273#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff 5274#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 5275#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff 5276#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 5277#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff 5278#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 5279#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff 5280#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 5281#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff 5282#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 5283#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff 5284#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 5285#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff 5286#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 5287#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff 5288#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 5289#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff 5290#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 5291#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff 5292#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 5293#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff 5294#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 5295#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff 5296#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 5297#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff 5298#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 5299#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff 5300#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 5301#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff 5302#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 5303#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff 5304#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 5305#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff 5306#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 5307#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff 5308#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 5309#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff 5310#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 5311#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff 5312#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 5313#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff 5314#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 5315#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff 5316#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 5317#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff 5318#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 5319#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff 5320#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 5321#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff 5322#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 5323#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff 5324#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 5325#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff 5326#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 5327#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff 5328#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 5329#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff 5330#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 5331#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff 5332#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 5333#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff 5334#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 5335#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff 5336#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 5337#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff 5338#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 5339#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff 5340#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 5341#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff 5342#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 5343#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff 5344#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 5345#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff 5346#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 5347#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff 5348#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 5349#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff 5350#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 5351#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff 5352#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 5353#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff 5354#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 5355#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff 5356#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 5357#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff 5358#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 5359#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff 5360#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 5361#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff 5362#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 5363#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff 5364#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 5365#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff 5366#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 5367#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff 5368#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 5369#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff 5370#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 5371#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff 5372#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 5373#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff 5374#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 5375#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff 5376#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 5377#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff 5378#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 5379#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff 5380#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 5381#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff 5382#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 5383#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff 5384#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 5385#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff 5386#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 5387#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff 5388#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 5389#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff 5390#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 5391#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff 5392#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 5393#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff 5394#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 5395#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff 5396#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 5397#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff 5398#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 5399#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff 5400#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 5401#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff 5402#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 5403#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff 5404#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 5405#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff 5406#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 5407#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff 5408#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 5409#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff 5410#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 5411#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff 5412#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 5413#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff 5414#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 5415#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff 5416#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 5417#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff 5418#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 5419#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff 5420#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 5421#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff 5422#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 5423#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff 5424#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 5425#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff 5426#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 5427#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff 5428#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 5429#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff 5430#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 5431#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff 5432#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 5433#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff 5434#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 5435#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff 5436#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 5437#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff 5438#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 5439#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff 5440#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 5441#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff 5442#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 5443#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff 5444#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 5445#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff 5446#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 5447#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff 5448#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 5449#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff 5450#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 5451#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff 5452#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 5453#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff 5454#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 5455#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff 5456#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 5457#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff 5458#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 5459#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff 5460#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 5461#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1 5462#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 5463#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2 5464#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 5465#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4 5466#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 5467#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8 5468#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 5469#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10 5470#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 5471#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20 5472#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 5473#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100 5474#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 5475#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200 5476#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 5477#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400 5478#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa 5479#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800 5480#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb 5481#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1 5482#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 5483#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2 5484#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 5485#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4 5486#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 5487#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8 5488#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 5489#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10 5490#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 5491#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20 5492#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 5493#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40 5494#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 5495#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80 5496#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 5497#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100 5498#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 5499#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200 5500#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 5501#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400 5502#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa 5503#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800 5504#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb 5505#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000 5506#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc 5507#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000 5508#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd 5509#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000 5510#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe 5511#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000 5512#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf 5513#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000 5514#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 5515#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000 5516#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 5517#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000 5518#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 5519#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000 5520#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 5521#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000 5522#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 5523#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000 5524#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 5525#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000 5526#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 5527#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000 5528#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 5529#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000 5530#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 5531#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000 5532#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 5533#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1 5534#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 5535#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2 5536#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 5537#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4 5538#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 5539#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8 5540#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 5541#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10 5542#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 5543#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20 5544#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 5545#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40 5546#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 5547#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80 5548#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 5549#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100 5550#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 5551#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200 5552#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 5553#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400 5554#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa 5555#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800 5556#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb 5557#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000 5558#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc 5559#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000 5560#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd 5561#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000 5562#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe 5563#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000 5564#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 5565#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 5566#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 5567#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2 5568#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 5569#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4 5570#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 5571#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8 5572#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 5573#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10 5574#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 5575#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 5576#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 5577#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000 5578#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd 5579#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000 5580#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe 5581#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000 5582#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 5583#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000 5584#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 5585#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000 5586#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 5587#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000 5588#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 5589#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000 5590#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 5591#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000 5592#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 5593#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000 5594#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 5595#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000 5596#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 5597#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000 5598#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 5599#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000 5600#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a 5601#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000 5602#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b 5603#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff 5604#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 5605#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff 5606#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 5607#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff 5608#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 5609#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff 5610#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 5611#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff 5612#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 5613#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff 5614#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 5615#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff 5616#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 5617#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff 5618#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 5619#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff 5620#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 5621#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff 5622#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 5623#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff 5624#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 5625#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff 5626#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 5627#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff 5628#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 5629#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff 5630#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 5631#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff 5632#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 5633#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff 5634#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 5635#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff 5636#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 5637#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff 5638#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 5639#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff 5640#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 5641#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff 5642#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 5643#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff 5644#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 5645#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff 5646#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 5647#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff 5648#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 5649#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff 5650#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 5651#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff 5652#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 5653#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff 5654#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 5655#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff 5656#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 5657#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff 5658#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 5659#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff 5660#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 5661#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff 5662#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 5663#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff 5664#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 5665#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff 5666#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 5667#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1 5668#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 5669#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6 5670#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 5671#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8 5672#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 5673#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10 5674#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 5675#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20 5676#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 5677#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000 5678#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c 5679#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000 5680#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d 5681#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000 5682#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e 5683#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000 5684#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f 5685#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1 5686#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 5687#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1 5688#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 5689#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6 5690#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 5691#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38 5692#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 5693#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff 5694#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 5695#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000 5696#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 5697#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff 5698#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 5699#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000 5700#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 5701#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff 5702#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 5703#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3 5704#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 5705#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4 5706#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 5707#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8 5708#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 5709#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10 5710#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 5711#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff 5712#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 5713#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1 5714#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 5715#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2 5716#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 5717#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4 5718#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 5719#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8 5720#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 5721#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10 5722#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 5723#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20 5724#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 5725#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40 5726#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 5727#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80 5728#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 5729#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00 5730#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 5731#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000 5732#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e 5733#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000 5734#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f 5735#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1 5736#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 5737#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2 5738#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 5739#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4 5740#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 5741#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18 5742#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 5743#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0 5744#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 5745#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700 5746#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 5747#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800 5748#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb 5749#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000 5750#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc 5751#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000 5752#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd 5753#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000 5754#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 5755#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000 5756#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 5757#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000 5758#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 5759#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000 5760#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 5761#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff 5762#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 5763#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100 5764#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 5765#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff 5766#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 5767#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff 5768#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 5769#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff 5770#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 5771#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff 5772#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 5773#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff 5774#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 5775#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff 5776#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 5777#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000 5778#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 5779#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff 5780#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 5781#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 5782#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 5783#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 5784#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 5785#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 5786#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 5787#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 5788#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 5789#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 5790#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 5791#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 5792#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 5793#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 5794#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 5795#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 5796#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 5797#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 5798#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 5799#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 5800#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 5801#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 5802#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 5803#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 5804#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 5805#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 5806#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 5807#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 5808#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 5809#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 5810#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 5811#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff 5812#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 5813#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 5814#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 5815#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff 5816#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 5817#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 5818#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 5819#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff 5820#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 5821#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 5822#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 5823#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff 5824#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 5825#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7 5826#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 5827#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10 5828#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 5829#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000 5830#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd 5831#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000 5832#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 5833#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000 5834#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 5835#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff 5836#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 5837#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000 5838#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 5839#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff 5840#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 5841#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000 5842#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 5843#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf 5844#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 5845#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0 5846#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 5847#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00 5848#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 5849#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000 5850#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc 5851#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000 5852#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 5853#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000 5854#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 5855#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000 5856#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 5857#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000 5858#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c 5859#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf 5860#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 5861#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0 5862#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 5863#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00 5864#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 5865#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000 5866#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc 5867#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000 5868#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 5869#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000 5870#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 5871#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000 5872#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 5873#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000 5874#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c 5875#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf 5876#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 5877#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0 5878#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 5879#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00 5880#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 5881#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000 5882#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc 5883#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000 5884#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 5885#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000 5886#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 5887#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000 5888#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 5889#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000 5890#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c 5891#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf 5892#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 5893#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0 5894#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 5895#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00 5896#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 5897#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000 5898#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc 5899#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000 5900#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 5901#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000 5902#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 5903#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000 5904#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 5905#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000 5906#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c 5907#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf 5908#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 5909#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0 5910#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 5911#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00 5912#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 5913#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000 5914#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc 5915#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000 5916#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 5917#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000 5918#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 5919#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000 5920#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 5921#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000 5922#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c 5923#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf 5924#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 5925#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0 5926#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 5927#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00 5928#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 5929#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000 5930#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc 5931#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000 5932#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 5933#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000 5934#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 5935#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000 5936#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 5937#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000 5938#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c 5939#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf 5940#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 5941#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0 5942#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 5943#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00 5944#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 5945#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000 5946#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc 5947#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000 5948#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 5949#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000 5950#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 5951#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000 5952#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 5953#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000 5954#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c 5955#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf 5956#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 5957#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0 5958#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 5959#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00 5960#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 5961#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000 5962#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc 5963#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000 5964#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 5965#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000 5966#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 5967#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000 5968#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 5969#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000 5970#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c 5971#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf 5972#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 5973#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0 5974#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 5975#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00 5976#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 5977#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000 5978#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc 5979#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000 5980#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 5981#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000 5982#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 5983#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000 5984#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 5985#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000 5986#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c 5987#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf 5988#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 5989#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0 5990#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 5991#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00 5992#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 5993#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000 5994#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc 5995#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000 5996#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 5997#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000 5998#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 5999#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000 6000#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 6001#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000 6002#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c 6003#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf 6004#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 6005#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0 6006#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 6007#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00 6008#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 6009#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000 6010#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc 6011#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000 6012#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 6013#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000 6014#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 6015#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000 6016#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 6017#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000 6018#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c 6019#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf 6020#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 6021#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0 6022#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 6023#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00 6024#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 6025#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000 6026#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc 6027#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000 6028#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 6029#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000 6030#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 6031#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000 6032#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 6033#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000 6034#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c 6035#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf 6036#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 6037#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0 6038#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 6039#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00 6040#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 6041#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000 6042#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc 6043#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000 6044#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 6045#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000 6046#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 6047#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000 6048#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 6049#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000 6050#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c 6051#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf 6052#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 6053#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0 6054#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 6055#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00 6056#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 6057#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000 6058#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc 6059#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000 6060#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 6061#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000 6062#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 6063#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000 6064#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 6065#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000 6066#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c 6067#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf 6068#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 6069#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0 6070#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 6071#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00 6072#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 6073#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000 6074#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc 6075#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000 6076#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 6077#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000 6078#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 6079#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000 6080#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 6081#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000 6082#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c 6083#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf 6084#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 6085#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0 6086#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 6087#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00 6088#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 6089#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000 6090#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc 6091#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000 6092#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 6093#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000 6094#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 6095#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000 6096#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 6097#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000 6098#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c 6099#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf 6100#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 6101#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0 6102#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 6103#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00 6104#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 6105#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000 6106#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc 6107#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000 6108#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 6109#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000 6110#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 6111#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000 6112#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 6113#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000 6114#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c 6115#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf 6116#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 6117#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0 6118#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 6119#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00 6120#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 6121#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000 6122#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc 6123#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000 6124#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 6125#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000 6126#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 6127#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000 6128#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 6129#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000 6130#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c 6131#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff 6132#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 6133#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000 6134#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 6135#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff 6136#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 6137#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000 6138#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 6139#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff 6140#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 6141#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000 6142#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 6143#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff 6144#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 6145#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000 6146#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 6147#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff 6148#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 6149#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000 6150#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 6151#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff 6152#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 6153#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000 6154#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 6155#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff 6156#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 6157#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000 6158#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 6159#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff 6160#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 6161#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000 6162#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 6163#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff 6164#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 6165#define PA_SC_EDGERULE__ER_TRI_MASK 0xf 6166#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 6167#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0 6168#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 6169#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00 6170#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 6171#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000 6172#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc 6173#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000 6174#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 6175#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000 6176#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 6177#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000 6178#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c 6179#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200 6180#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 6181#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400 6182#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa 6183#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800 6184#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb 6185#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000 6186#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc 6187#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff 6188#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 6189#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000 6190#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 6191#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000 6192#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c 6193#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000 6194#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d 6195#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1 6196#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 6197#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2 6198#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 6199#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4 6200#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 6201#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8 6202#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 6203#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1 6204#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 6205#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2 6206#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 6207#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4 6208#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 6209#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8 6210#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 6211#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70 6212#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 6213#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80 6214#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 6215#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100 6216#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 6217#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200 6218#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 6219#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400 6220#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa 6221#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800 6222#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb 6223#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000 6224#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc 6225#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000 6226#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd 6227#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000 6228#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe 6229#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000 6230#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf 6231#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000 6232#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 6233#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000 6234#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 6235#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000 6236#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 6237#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000 6238#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 6239#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000 6240#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 6241#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000 6242#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 6243#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000 6244#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 6245#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000 6246#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a 6247#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000 6248#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b 6249#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000 6250#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c 6251#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3 6252#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 6253#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc 6254#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 6255#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30 6256#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 6257#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40 6258#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 6259#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80 6260#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 6261#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300 6262#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 6263#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00 6264#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa 6265#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000 6266#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc 6267#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000 6268#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe 6269#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000 6270#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 6271#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000 6272#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 6273#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000 6274#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 6275#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000 6276#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 6277#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000 6278#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a 6279#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000 6280#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c 6281#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3 6282#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 6283#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc 6284#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 6285#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30 6286#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 6287#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3 6288#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 6289#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc 6290#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 6291#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff 6292#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 6293#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000 6294#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 6295#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6296#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6297#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff 6298#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 6299#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000 6300#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 6301#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff 6302#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 6303#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000 6304#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 6305#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff 6306#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 6307#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000 6308#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 6309#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff 6310#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 6311#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000 6312#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 6313#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff 6314#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 6315#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000 6316#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 6317#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6318#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6319#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff 6320#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 6321#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000 6322#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 6323#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff 6324#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 6325#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000 6326#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 6327#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6328#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6329#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff 6330#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 6331#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000 6332#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 6333#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6334#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6335#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff 6336#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 6337#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000 6338#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 6339#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6340#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6341#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff 6342#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 6343#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000 6344#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 6345#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6346#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6347#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff 6348#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 6349#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000 6350#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 6351#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6352#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6353#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff 6354#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 6355#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000 6356#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 6357#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6358#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6359#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff 6360#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 6361#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000 6362#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 6363#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6364#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6365#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff 6366#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 6367#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000 6368#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 6369#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6370#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6371#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff 6372#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 6373#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000 6374#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 6375#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6376#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6377#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff 6378#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 6379#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000 6380#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 6381#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6382#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6383#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff 6384#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 6385#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000 6386#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 6387#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6388#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6389#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff 6390#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 6391#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000 6392#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 6393#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6394#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6395#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff 6396#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 6397#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000 6398#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 6399#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6400#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6401#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff 6402#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 6403#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000 6404#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 6405#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6406#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6407#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff 6408#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 6409#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000 6410#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 6411#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6412#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6413#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff 6414#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 6415#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000 6416#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 6417#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 6418#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 6419#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff 6420#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 6421#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000 6422#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 6423#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff 6424#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 6425#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000 6426#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 6427#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff 6428#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 6429#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000 6430#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 6431#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff 6432#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 6433#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000 6434#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 6435#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff 6436#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 6437#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000 6438#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 6439#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff 6440#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 6441#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000 6442#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 6443#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff 6444#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 6445#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000 6446#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 6447#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff 6448#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 6449#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000 6450#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 6451#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff 6452#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 6453#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000 6454#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 6455#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff 6456#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 6457#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000 6458#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 6459#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff 6460#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 6461#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000 6462#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 6463#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff 6464#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 6465#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000 6466#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 6467#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff 6468#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 6469#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000 6470#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 6471#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff 6472#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 6473#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000 6474#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 6475#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff 6476#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 6477#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000 6478#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 6479#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff 6480#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 6481#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000 6482#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 6483#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff 6484#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 6485#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff 6486#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 6487#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff 6488#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 6489#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff 6490#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 6491#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff 6492#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 6493#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff 6494#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 6495#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff 6496#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 6497#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff 6498#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 6499#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff 6500#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 6501#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff 6502#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 6503#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff 6504#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 6505#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff 6506#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 6507#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff 6508#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 6509#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff 6510#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 6511#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff 6512#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 6513#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff 6514#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 6515#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff 6516#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 6517#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff 6518#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 6519#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff 6520#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 6521#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff 6522#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 6523#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff 6524#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 6525#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff 6526#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 6527#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff 6528#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 6529#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff 6530#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 6531#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff 6532#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 6533#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff 6534#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 6535#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff 6536#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 6537#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff 6538#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 6539#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff 6540#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 6541#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff 6542#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 6543#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff 6544#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 6545#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff 6546#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 6547#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1 6548#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 6549#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2 6550#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 6551#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4 6552#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 6553#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8 6554#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 6555#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10 6556#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 6557#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20 6558#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 6559#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0 6560#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6 6561#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100 6562#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8 6563#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200 6564#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9 6565#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400 6566#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa 6567#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800 6568#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb 6569#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000 6570#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc 6571#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000 6572#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd 6573#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000 6574#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe 6575#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000 6576#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf 6577#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000 6578#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10 6579#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000 6580#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11 6581#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000 6582#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12 6583#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000 6584#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13 6585#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000 6586#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14 6587#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000 6588#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15 6589#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000 6590#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16 6591#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000 6592#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17 6593#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000 6594#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18 6595#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000 6596#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19 6597#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000 6598#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a 6599#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000 6600#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b 6601#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000 6602#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c 6603#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000 6604#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d 6605#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000 6606#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e 6607#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000 6608#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f 6609#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f 6610#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 6611#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0 6612#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 6613#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000 6614#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf 6615#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000 6616#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17 6617#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f 6618#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 6619#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0 6620#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 6621#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000 6622#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc 6623#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000 6624#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 6625#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff 6626#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 6627#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000 6628#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 6629#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf 6630#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 6631#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00 6632#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 6633#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff 6634#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 6635#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000 6636#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 6637#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff 6638#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 6639#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000 6640#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 6641#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff 6642#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 6643#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000 6644#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 6645#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff 6646#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 6647#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000 6648#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 6649#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 6650#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 6651#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 6652#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 6653#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 6654#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 6655#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 6656#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 6657#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 6658#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 6659#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 6660#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 6661#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 6662#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 6663#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 6664#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 6665#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff 6666#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 6667#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff 6668#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 6669#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff 6670#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 6671#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff 6672#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 6673#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 6674#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 6675#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 6676#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 6677#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 6678#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 6679#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 6680#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 6681#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 6682#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 6683#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 6684#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 6685#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 6686#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 6687#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 6688#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 6689#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff 6690#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 6691#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff 6692#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 6693#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff 6694#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 6695#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff 6696#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 6697#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff 6698#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 6699#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff 6700#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 6701#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff 6702#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 6703#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff 6704#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 6705#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 6706#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 6707#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 6708#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 6709#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff 6710#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 6711#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff 6712#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 6713#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff 6714#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 6715#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff 6716#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 6717#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 6718#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 6719#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 6720#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 6721#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff 6722#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 6723#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff 6724#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 6725#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff 6726#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 6727#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff 6728#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 6729#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 6730#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 6731#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 6732#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 6733#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff 6734#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 6735#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff 6736#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 6737#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff 6738#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 6739#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff 6740#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 6741#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 6742#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 6743#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 6744#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 6745#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 6746#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 6747#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000 6748#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f 6749#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000 6750#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f 6751#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff 6752#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 6753#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf 6754#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 6755#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 6756#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6757#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 6758#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 6759#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 6760#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 6761#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 6762#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 6763#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 6764#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 6765#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 6766#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 6767#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000 6768#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d 6769#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000 6770#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e 6771#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000 6772#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f 6773#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf 6774#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0 6775#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 6776#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6777#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 6778#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 6779#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 6780#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 6781#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 6782#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 6783#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 6784#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 6785#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 6786#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 6787#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 6788#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 6789#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 6790#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 6791#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 6792#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 6793#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f 6794#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0 6795#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff 6796#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0 6797#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f 6798#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0 6799#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff 6800#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0 6801#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff 6802#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0 6803#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100 6804#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8 6805#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600 6806#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9 6807#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800 6808#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb 6809#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000 6810#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc 6811#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000 6812#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd 6813#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000 6814#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe 6815#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000 6816#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf 6817#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000 6818#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10 6819#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000 6820#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11 6821#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000 6822#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12 6823#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000 6824#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13 6825#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000 6826#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14 6827#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000 6828#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15 6829#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000 6830#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16 6831#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000 6832#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17 6833#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000 6834#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18 6835#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000 6836#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19 6837#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000 6838#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a 6839#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000 6840#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b 6841#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000 6842#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c 6843#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000 6844#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d 6845#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000 6846#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e 6847#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000 6848#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f 6849#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff 6850#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0 6851#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700 6852#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8 6853#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800 6854#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb 6855#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000 6856#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe 6857#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000 6858#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11 6859#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000 6860#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14 6861#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000 6862#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15 6863#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000 6864#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16 6865#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000 6866#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17 6867#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000 6868#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18 6869#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000 6870#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19 6871#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000 6872#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a 6873#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000 6874#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c 6875#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000 6876#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d 6877#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000 6878#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e 6879#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000 6880#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f 6881#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7 6882#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0 6883#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38 6884#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3 6885#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0 6886#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6 6887#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00 6888#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8 6889#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000 6890#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc 6891#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000 6892#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10 6893#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000 6894#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14 6895#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000 6896#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15 6897#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000 6898#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16 6899#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000 6900#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17 6901#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000 6902#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18 6903#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000 6904#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19 6905#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000 6906#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a 6907#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000 6908#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b 6909#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000 6910#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c 6911#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000 6912#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d 6913#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000 6914#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e 6915#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000 6916#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f 6917#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff 6918#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0 6919#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000 6920#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe 6921#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000 6922#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14 6923#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000 6924#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17 6925#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000 6926#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18 6927#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 6928#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b 6929#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000 6930#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c 6931#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000 6932#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d 6933#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 6934#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e 6935#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 6936#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f 6937#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe 6938#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 6939#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 6940#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb 6941#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 6942#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 6943#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 6944#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 6945#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000 6946#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d 6947#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 6948#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e 6949#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 6950#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f 6951#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff 6952#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0 6953#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000 6954#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe 6955#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000 6956#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14 6957#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000 6958#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17 6959#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000 6960#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18 6961#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 6962#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b 6963#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000 6964#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c 6965#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000 6966#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d 6967#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 6968#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e 6969#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 6970#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f 6971#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe 6972#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 6973#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 6974#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb 6975#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 6976#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 6977#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 6978#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 6979#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000 6980#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d 6981#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 6982#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e 6983#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 6984#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f 6985#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff 6986#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0 6987#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000 6988#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe 6989#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000 6990#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14 6991#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000 6992#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17 6993#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000 6994#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18 6995#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 6996#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b 6997#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000 6998#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c 6999#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000 7000#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d 7001#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 7002#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e 7003#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 7004#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f 7005#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe 7006#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 7007#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 7008#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb 7009#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 7010#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 7011#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 7012#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 7013#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000 7014#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d 7015#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 7016#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e 7017#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 7018#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f 7019#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff 7020#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0 7021#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000 7022#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe 7023#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000 7024#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14 7025#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000 7026#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17 7027#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000 7028#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18 7029#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 7030#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b 7031#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000 7032#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c 7033#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000 7034#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d 7035#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 7036#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e 7037#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 7038#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f 7039#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe 7040#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 7041#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 7042#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb 7043#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 7044#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 7045#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 7046#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 7047#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000 7048#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d 7049#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 7050#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e 7051#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 7052#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f 7053#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1 7054#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0 7055#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2 7056#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1 7057#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4 7058#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2 7059#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8 7060#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3 7061#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10 7062#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4 7063#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20 7064#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5 7065#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40 7066#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6 7067#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80 7068#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7 7069#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00 7070#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8 7071#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000 7072#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc 7073#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000 7074#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10 7075#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000 7076#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14 7077#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000 7078#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18 7079#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000 7080#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19 7081#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000 7082#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a 7083#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000 7084#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b 7085#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000 7086#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c 7087#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000 7088#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d 7089#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000 7090#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e 7091#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000 7092#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f 7093#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff 7094#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0 7095#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00 7096#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8 7097#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000 7098#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd 7099#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000 7100#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12 7101#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000 7102#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14 7103#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000 7104#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16 7105#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000 7106#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18 7107#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000 7108#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19 7109#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000 7110#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a 7111#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000 7112#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b 7113#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000 7114#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c 7115#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000 7116#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d 7117#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000 7118#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e 7119#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 7120#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f 7121#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7 7122#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0 7123#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8 7124#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3 7125#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10 7126#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4 7127#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20 7128#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5 7129#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40 7130#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6 7131#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80 7132#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7 7133#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00 7134#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8 7135#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000 7136#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc 7137#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000 7138#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe 7139#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000 7140#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf 7141#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000 7142#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10 7143#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000 7144#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11 7145#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000 7146#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15 7147#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000 7148#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17 7149#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000 7150#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18 7151#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000 7152#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d 7153#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000 7154#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e 7155#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000 7156#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f 7157#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f 7158#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0 7159#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0 7160#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6 7161#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000 7162#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc 7163#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000 7164#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12 7165#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000 7166#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13 7167#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000 7168#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14 7169#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000 7170#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15 7171#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000 7172#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18 7173#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000 7174#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e 7175#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000 7176#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f 7177#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff 7178#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0 7179#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000 7180#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10 7181#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000 7182#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15 7183#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000 7184#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a 7185#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000 7186#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f 7187#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f 7188#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0 7189#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80 7190#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7 7191#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00 7192#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8 7193#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000 7194#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd 7195#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000 7196#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12 7197#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000 7198#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13 7199#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000 7200#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14 7201#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 7202#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b 7203#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000 7204#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c 7205#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000 7206#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d 7207#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000 7208#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e 7209#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000 7210#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f 7211#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f 7212#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0 7213#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80 7214#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7 7215#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00 7216#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8 7217#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000 7218#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd 7219#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000 7220#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12 7221#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000 7222#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13 7223#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000 7224#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14 7225#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 7226#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b 7227#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000 7228#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c 7229#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000 7230#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d 7231#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000 7232#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e 7233#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000 7234#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f 7235#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f 7236#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0 7237#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80 7238#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7 7239#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00 7240#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8 7241#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000 7242#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd 7243#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000 7244#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12 7245#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000 7246#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13 7247#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000 7248#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14 7249#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 7250#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b 7251#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000 7252#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c 7253#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000 7254#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d 7255#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000 7256#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e 7257#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000 7258#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f 7259#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f 7260#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0 7261#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80 7262#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7 7263#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00 7264#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8 7265#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000 7266#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd 7267#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000 7268#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12 7269#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000 7270#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13 7271#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000 7272#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14 7273#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 7274#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b 7275#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000 7276#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c 7277#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000 7278#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d 7279#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000 7280#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e 7281#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000 7282#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f 7283#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f 7284#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0 7285#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0 7286#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6 7287#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00 7288#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9 7289#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000 7290#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc 7291#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000 7292#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10 7293#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000 7294#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a 7295#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000 7296#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c 7297#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000 7298#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e 7299#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000 7300#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f 7301#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f 7302#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0 7303#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380 7304#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7 7305#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00 7306#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa 7307#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000 7308#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf 7309#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000 7310#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10 7311#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000 7312#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14 7313#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000 7314#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16 7315#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000 7316#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17 7317#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000 7318#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18 7319#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000 7320#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c 7321#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f 7322#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0 7323#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180 7324#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7 7325#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00 7326#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9 7327#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000 7328#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf 7329#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000 7330#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10 7331#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000 7332#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17 7333#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000 7334#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a 7335#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff 7336#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0 7337#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00 7338#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8 7339#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000 7340#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc 7341#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000 7342#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd 7343#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000 7344#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe 7345#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000 7346#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15 7347#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000 7348#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17 7349#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000 7350#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18 7351#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000 7352#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19 7353#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000 7354#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a 7355#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000 7356#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b 7357#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000 7358#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c 7359#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000 7360#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d 7361#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000 7362#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e 7363#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000 7364#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f 7365#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3 7366#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0 7367#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c 7368#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2 7369#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00 7370#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8 7371#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000 7372#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe 7373#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000 7374#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf 7375#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000 7376#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10 7377#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000 7378#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12 7379#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000 7380#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13 7381#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000 7382#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14 7383#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000 7384#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15 7385#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000 7386#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16 7387#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000 7388#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c 7389#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000 7390#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d 7391#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000 7392#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e 7393#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000 7394#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f 7395#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff 7396#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0 7397#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000 7398#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10 7399#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff 7400#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0 7401#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000 7402#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10 7403#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff 7404#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0 7405#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000 7406#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10 7407#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff 7408#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0 7409#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000 7410#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe 7411#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000 7412#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf 7413#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000 7414#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10 7415#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000 7416#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13 7417#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000 7418#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14 7419#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000 7420#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17 7421#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000 7422#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18 7423#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000 7424#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a 7425#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000 7426#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d 7427#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000 7428#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f 7429#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff 7430#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0 7431#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000 7432#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe 7433#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000 7434#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c 7435#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000 7436#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e 7437#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000 7438#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f 7439#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3 7440#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0 7441#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc 7442#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2 7443#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3 7444#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0 7445#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc 7446#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2 7447#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1 7448#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 7449#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2 7450#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 7451#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4 7452#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 7453#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8 7454#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 7455#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10 7456#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 7457#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20 7458#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 7459#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40 7460#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 7461#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380 7462#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7 7463#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400 7464#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa 7465#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800 7466#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb 7467#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000 7468#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc 7469#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000 7470#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe 7471#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff 7472#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 7473#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff 7474#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 7475#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff 7476#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 7477#define COMPUTE_START_X__START_MASK 0xffffffff 7478#define COMPUTE_START_X__START__SHIFT 0x0 7479#define COMPUTE_START_Y__START_MASK 0xffffffff 7480#define COMPUTE_START_Y__START__SHIFT 0x0 7481#define COMPUTE_START_Z__START_MASK 0xffffffff 7482#define COMPUTE_START_Z__START__SHIFT 0x0 7483#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff 7484#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 7485#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000 7486#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 7487#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff 7488#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 7489#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000 7490#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 7491#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff 7492#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 7493#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000 7494#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 7495#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1 7496#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 7497#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1 7498#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 7499#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff 7500#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 7501#define COMPUTE_PGM_HI__DATA_MASK 0xff 7502#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 7503#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100 7504#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8 7505#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff 7506#define COMPUTE_TBA_LO__DATA__SHIFT 0x0 7507#define COMPUTE_TBA_HI__DATA_MASK 0xff 7508#define COMPUTE_TBA_HI__DATA__SHIFT 0x0 7509#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff 7510#define COMPUTE_TMA_LO__DATA__SHIFT 0x0 7511#define COMPUTE_TMA_HI__DATA_MASK 0xff 7512#define COMPUTE_TMA_HI__DATA__SHIFT 0x0 7513#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f 7514#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 7515#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0 7516#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 7517#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00 7518#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa 7519#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000 7520#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc 7521#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000 7522#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 7523#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000 7524#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 7525#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000 7526#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 7527#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000 7528#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 7529#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000 7530#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 7531#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000 7532#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 7533#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1 7534#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 7535#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e 7536#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 7537#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40 7538#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 7539#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80 7540#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 7541#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100 7542#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 7543#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200 7544#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 7545#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400 7546#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa 7547#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800 7548#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb 7549#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000 7550#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd 7551#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000 7552#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf 7553#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000 7554#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 7555#define COMPUTE_VMID__DATA_MASK 0xf 7556#define COMPUTE_VMID__DATA__SHIFT 0x0 7557#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff 7558#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 7559#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000 7560#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc 7561#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000 7562#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 7563#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000 7564#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 7565#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000 7566#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 7567#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000 7568#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 7569#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff 7570#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 7571#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000 7572#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 7573#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff 7574#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 7575#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000 7576#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 7577#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff 7578#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 7579#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 7580#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc 7581#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff 7582#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 7583#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000 7584#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 7585#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff 7586#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 7587#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000 7588#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 7589#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff 7590#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 7591#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff 7592#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 7593#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff 7594#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 7595#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1 7596#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 7597#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3 7598#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 7599#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4 7600#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 7601#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8 7602#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 7603#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10 7604#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 7605#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff 7606#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 7607#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff 7608#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 7609#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff 7610#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 7611#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff 7612#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 7613#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff 7614#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 7615#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff 7616#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 7617#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff 7618#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 7619#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff 7620#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 7621#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff 7622#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 7623#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff 7624#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 7625#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff 7626#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 7627#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff 7628#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 7629#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff 7630#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 7631#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff 7632#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 7633#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff 7634#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 7635#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff 7636#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 7637#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff 7638#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0 7639#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000 7640#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15 7641#define CSPRIV_CONNECT__VMID_MASK 0x3c000000 7642#define CSPRIV_CONNECT__VMID__SHIFT 0x1a 7643#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000 7644#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f 7645#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff 7646#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0 7647#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff 7648#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0 7649#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff 7650#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0 7651#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff 7652#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0 7653#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000 7654#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc 7655#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000 7656#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18 7657#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000 7658#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19 7659#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000 7660#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a 7661#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000 7662#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b 7663#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000 7664#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c 7665#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f 7666#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0 7667#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 7668#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 7669#define RLC_CNTL__FORCE_RETRY_MASK 0x2 7670#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 7671#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4 7672#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 7673#define RLC_CNTL__RLC_STEP_F32_MASK 0x8 7674#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 7675#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10 7676#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4 7677#define RLC_CNTL__RESERVED_MASK 0xffffff00 7678#define RLC_CNTL__RESERVED__SHIFT 0x8 7679#define RLC_DEBUG_SELECT__SELECT_MASK 0xff 7680#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0 7681#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00 7682#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8 7683#define RLC_DEBUG__DATA_MASK 0xffffffff 7684#define RLC_DEBUG__DATA__SHIFT 0x0 7685#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3 7686#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0 7687#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4 7688#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2 7689#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8 7690#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3 7691#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10 7692#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4 7693#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0 7694#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5 7695#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00 7696#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9 7697#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000 7698#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd 7699#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000 7700#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14 7701#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000 7702#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18 7703#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000 7704#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a 7705#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000 7706#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b 7707#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000 7708#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c 7709#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000 7710#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d 7711#define RLC_STAT__RLC_BUSY_MASK 0x1 7712#define RLC_STAT__RLC_BUSY__SHIFT 0x0 7713#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2 7714#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1 7715#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4 7716#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2 7717#define RLC_STAT__RESERVED_MASK 0xfffffff8 7718#define RLC_STAT__RESERVED__SHIFT 0x3 7719#define RLC_SAFE_MODE__REQ_MASK 0x1 7720#define RLC_SAFE_MODE__REQ__SHIFT 0x0 7721#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e 7722#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 7723#define RLC_SAFE_MODE__RESERVED_MASK 0xffffffe0 7724#define RLC_SAFE_MODE__RESERVED__SHIFT 0x5 7725#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1 7726#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0 7727#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe 7728#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1 7729#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 7730#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 7731#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2 7732#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 7733#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0xfc 7734#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 7735#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00 7736#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 7737#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000 7738#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 7739#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 7740#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 7741#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7 7742#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 7743#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 7744#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa 7745#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff 7746#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 7747#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff 7748#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 7749#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 7750#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 7751#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 7752#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 7753#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 7754#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 7755#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 7756#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 7757#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf 7758#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 7759#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 7760#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7761#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 7762#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 7763#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 7764#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 7765#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1 7766#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 7767#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2 7768#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 7769#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4 7770#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 7771#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8 7772#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 7773#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0 7774#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 7775#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000 7776#define RLC_LB_CNTL__RESERVED__SHIFT 0xc 7777#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff 7778#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 7779#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff 7780#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 7781#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff 7782#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 7783#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff 7784#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0 7785#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff 7786#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 7787#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1 7788#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0 7789#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe 7790#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1 7791#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10 7792#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4 7793#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0 7794#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5 7795#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff 7796#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 7797#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00 7798#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 7799#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000 7800#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 7801#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff 7802#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0 7803#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xffffff00 7804#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0x8 7805#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff 7806#define RLC_GPM_DEBUG__DATA__SHIFT 0x0 7807#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff 7808#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 7809#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000 7810#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc 7811#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 7812#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 7813#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff 7814#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 7815#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff 7816#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 7817#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1 7818#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 7819#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe 7820#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 7821#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff 7822#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 7823#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1 7824#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 7825#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2 7826#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 7827#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4 7828#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 7829#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8 7830#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 7831#define RLC_GPM_STAT__RESERVED_MASK 0xfffffff0 7832#define RLC_GPM_STAT__RESERVED__SHIFT 0x4 7833#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f 7834#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 7835#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0 7836#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 7837#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff 7838#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 7839#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1 7840#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 7841#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2 7842#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 7843#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4 7844#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 7845#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8 7846#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 7847#define RLC_PG_CNTL__RESERVED_MASK 0xfff0 7848#define RLC_PG_CNTL__RESERVED__SHIFT 0x4 7849#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000 7850#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 7851#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000 7852#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 7853#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000 7854#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 7855#define RLC_PG_CNTL__RESERVED1_MASK 0xf80000 7856#define RLC_PG_CNTL__RESERVED1__SHIFT 0x13 7857#define RLC_PG_CNTL__PG_ERROR_STATUS_MASK 0xff000000 7858#define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT 0x18 7859#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff 7860#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 7861#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00 7862#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 7863#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000 7864#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 7865#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000 7866#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 7867#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1 7868#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 7869#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2 7870#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 7871#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4 7872#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 7873#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8 7874#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 7875#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0 7876#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 7877#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf 7878#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0 7879#define RLC_GPM_VMID_THREAD0__RESERVED_MASK 0xfffffff0 7880#define RLC_GPM_VMID_THREAD0__RESERVED__SHIFT 0x4 7881#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf 7882#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0 7883#define RLC_GPM_VMID_THREAD1__RESERVED_MASK 0xfffffff0 7884#define RLC_GPM_VMID_THREAD1__RESERVED__SHIFT 0x4 7885#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff 7886#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0 7887#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 7888#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 7889#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 7890#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 7891#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc 7892#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 7893#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00 7894#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 7895#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000 7896#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b 7897#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000 7898#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c 7899#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000 7900#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d 7901#define RLC_CGCG_CGLS_CTRL__SPARE_MASK 0x80000000 7902#define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT 0x1f 7903#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf 7904#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 7905#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0 7906#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 7907#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00 7908#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 7909#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000 7910#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc 7911#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000 7912#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 7913#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000 7914#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c 7915#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff 7916#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 7917#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff 7918#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 7919#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff 7920#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 7921#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00 7922#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 7923#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000 7924#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 7925#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000 7926#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 7927#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff 7928#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 7929#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff 7930#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 7931#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff 7932#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 7933#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1 7934#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 7935#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe 7936#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 7937#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00 7938#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 7939#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000 7940#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 7941#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff 7942#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 7943#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00 7944#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 7945#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000 7946#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 7947#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000 7948#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 7949#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff 7950#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 7951#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff 7952#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 7953#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00 7954#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 7955#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1 7956#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 7957#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2 7958#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 7959#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4 7960#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 7961#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8 7962#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 7963#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000 7964#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 7965#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1 7966#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 7967#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe 7968#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 7969#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1 7970#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0 7971#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe 7972#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1 7973#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1 7974#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0 7975#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe 7976#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1 7977#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf 7978#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 7979#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30 7980#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 7981#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0 7982#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 7983#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200 7984#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 7985#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400 7986#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa 7987#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x3800 7988#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb 7989#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0xc000 7990#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xe 7991#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xffff0000 7992#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x10 7993#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff 7994#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 7995#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff 7996#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 7997#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff 7998#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 7999#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff 8000#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 8001#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff 8002#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 8003#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000 8004#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 8005#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x20000 8006#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x11 8007#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x40000 8008#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x12 8009#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x80000 8010#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x13 8011#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x100000 8012#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x14 8013#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x200000 8014#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x15 8015#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x400000 8016#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x16 8017#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff800000 8018#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x17 8019#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff 8020#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 8021#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100 8022#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 8023#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200 8024#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 8025#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400 8026#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa 8027#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800 8028#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb 8029#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000 8030#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc 8031#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000 8032#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd 8033#define RLC_SERDES_WR_CTRL__RESERVED_1_MASK 0xc000 8034#define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT 0xe 8035#define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK 0x10000 8036#define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT 0x10 8037#define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK 0x20000 8038#define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT 0x11 8039#define RLC_SERDES_WR_CTRL__CGLS_ON_MASK 0x40000 8040#define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT 0x12 8041#define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK 0x80000 8042#define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT 0x13 8043#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK 0x100000 8044#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT 0x14 8045#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK 0x200000 8046#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT 0x15 8047#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK 0x400000 8048#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT 0x16 8049#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK 0x800000 8050#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT 0x17 8051#define RLC_SERDES_WR_CTRL__RESERVED_2_MASK 0xf000000 8052#define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT 0x18 8053#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000 8054#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c 8055#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff 8056#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 8057#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff 8058#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 8059#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff 8060#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 8061#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000 8062#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 8063#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x20000 8064#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x11 8065#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x40000 8066#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x12 8067#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x80000 8068#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x13 8069#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x100000 8070#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x14 8071#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x200000 8072#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x15 8073#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x400000 8074#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x16 8075#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff800000 8076#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x17 8077#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff 8078#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 8079#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff 8080#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 8081#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff 8082#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 8083#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff 8084#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 8085#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff 8086#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 8087#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff 8088#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 8089#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff 8090#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 8091#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff 8092#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 8093#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff 8094#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0 8095#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff 8096#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 8097#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00 8098#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 8099#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff 8100#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 8101#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff 8102#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 8103#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf 8104#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 8105#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0 8106#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 8107#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00 8108#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 8109#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000 8110#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc 8111#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000 8112#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 8113#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000 8114#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 8115#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000 8116#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 8117#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000 8118#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 8119#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf 8120#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 8121#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0 8122#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 8123#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00 8124#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 8125#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000 8126#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc 8127#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000 8128#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 8129#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000 8130#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 8131#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000 8132#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 8133#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000 8134#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 8135#define RLC_GPR_REG1__DATA_MASK 0xffffffff 8136#define RLC_GPR_REG1__DATA__SHIFT 0x0 8137#define RLC_GPR_REG2__DATA_MASK 0xffffffff 8138#define RLC_GPR_REG2__DATA__SHIFT 0x0 8139#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf 8140#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0 8141#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0 8142#define RLC_SPM_VMID__RESERVED__SHIFT 0x4 8143#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1 8144#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 8145#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe 8146#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 8147#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1 8148#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 8149#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe 8150#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 8151#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff 8152#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0 8153#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00 8154#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8 8155#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000 8156#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf 8157#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000 8158#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10 8159#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff 8160#define RLC_SPM_DEBUG__DATA__SHIFT 0x0 8161#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff 8162#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0 8163#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff 8164#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 8165#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff 8166#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 8167#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff 8168#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 8169#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000 8170#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc 8171#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000 8172#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe 8173#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000 8174#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 8175#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff 8176#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 8177#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff 8178#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 8179#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000 8180#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 8181#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff 8182#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 8183#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff 8184#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 8185#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700 8186#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 8187#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800 8188#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb 8189#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000 8190#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 8191#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000 8192#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 8193#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000 8194#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a 8195#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000 8196#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f 8197#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff 8198#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 8199#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff 8200#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 8201#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8202#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8203#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8204#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8205#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8206#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8207#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8208#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8209#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8210#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8211#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8212#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8213#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8214#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8215#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8216#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8217#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8218#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8219#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8220#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8221#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8222#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8223#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8224#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8225#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8226#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8227#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8228#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8229#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8230#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8231#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8232#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8233#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8234#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8235#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8236#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8237#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8238#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8239#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8240#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8241#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8242#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8243#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8244#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8245#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8246#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8247#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8248#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8249#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8250#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8251#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8252#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8253#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8254#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8255#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8256#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8257#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8258#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8259#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8260#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8261#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8262#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8263#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8264#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8265#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8266#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8267#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8268#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8269#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8270#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8271#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8272#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8273#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8274#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8275#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8276#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8277#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff 8278#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 8279#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff 8280#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 8281#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff 8282#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 8283#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff 8284#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 8285#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8286#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8287#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8288#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8289#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8290#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8291#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8292#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8293#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8294#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8295#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8296#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8297#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 8298#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 8299#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 8300#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 8301#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f 8302#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 8303#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300 8304#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 8305#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400 8306#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa 8307#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000 8308#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd 8309#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000 8310#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 8311#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000 8312#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 8313#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f 8314#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 8315#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300 8316#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 8317#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400 8318#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa 8319#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 8320#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd 8321#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000 8322#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 8323#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000 8324#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 8325#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f 8326#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 8327#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300 8328#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 8329#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400 8330#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa 8331#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000 8332#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd 8333#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000 8334#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 8335#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000 8336#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 8337#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f 8338#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 8339#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300 8340#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 8341#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400 8342#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa 8343#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000 8344#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd 8345#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000 8346#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 8347#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000 8348#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 8349#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f 8350#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 8351#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300 8352#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 8353#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400 8354#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa 8355#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000 8356#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd 8357#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000 8358#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 8359#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000 8360#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 8361#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f 8362#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 8363#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300 8364#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 8365#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400 8366#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa 8367#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000 8368#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd 8369#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000 8370#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 8371#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000 8372#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 8373#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f 8374#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 8375#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300 8376#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 8377#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400 8378#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa 8379#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000 8380#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd 8381#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000 8382#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 8383#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000 8384#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 8385#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f 8386#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 8387#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300 8388#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 8389#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400 8390#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa 8391#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000 8392#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd 8393#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000 8394#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 8395#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000 8396#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 8397#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f 8398#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 8399#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300 8400#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 8401#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400 8402#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa 8403#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000 8404#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd 8405#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000 8406#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 8407#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000 8408#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 8409#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f 8410#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 8411#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300 8412#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 8413#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400 8414#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa 8415#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000 8416#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd 8417#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000 8418#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 8419#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000 8420#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 8421#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f 8422#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 8423#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300 8424#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 8425#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400 8426#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa 8427#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000 8428#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd 8429#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000 8430#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 8431#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000 8432#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 8433#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f 8434#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 8435#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300 8436#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 8437#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400 8438#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa 8439#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000 8440#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd 8441#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000 8442#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 8443#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000 8444#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 8445#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f 8446#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 8447#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300 8448#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 8449#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400 8450#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa 8451#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000 8452#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd 8453#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000 8454#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 8455#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000 8456#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 8457#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f 8458#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 8459#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300 8460#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 8461#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400 8462#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa 8463#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000 8464#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd 8465#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000 8466#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 8467#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000 8468#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 8469#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f 8470#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 8471#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300 8472#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 8473#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400 8474#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa 8475#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000 8476#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd 8477#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000 8478#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 8479#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000 8480#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 8481#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f 8482#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 8483#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300 8484#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 8485#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400 8486#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa 8487#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000 8488#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd 8489#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000 8490#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 8491#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000 8492#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 8493#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f 8494#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 8495#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300 8496#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 8497#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400 8498#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa 8499#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000 8500#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd 8501#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000 8502#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 8503#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000 8504#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 8505#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f 8506#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 8507#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300 8508#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 8509#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400 8510#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa 8511#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000 8512#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd 8513#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000 8514#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 8515#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000 8516#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 8517#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f 8518#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 8519#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300 8520#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 8521#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400 8522#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa 8523#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000 8524#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd 8525#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000 8526#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 8527#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000 8528#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 8529#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f 8530#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 8531#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300 8532#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 8533#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400 8534#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa 8535#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000 8536#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd 8537#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000 8538#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 8539#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000 8540#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 8541#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f 8542#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 8543#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300 8544#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 8545#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400 8546#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa 8547#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000 8548#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 8549#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f 8550#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 8551#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300 8552#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 8553#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400 8554#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa 8555#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000 8556#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 8557#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f 8558#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 8559#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300 8560#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 8561#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400 8562#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa 8563#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000 8564#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 8565#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f 8566#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 8567#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300 8568#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 8569#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400 8570#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa 8571#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000 8572#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 8573#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f 8574#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 8575#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300 8576#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 8577#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400 8578#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa 8579#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000 8580#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 8581#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f 8582#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 8583#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300 8584#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 8585#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400 8586#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa 8587#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000 8588#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 8589#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f 8590#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 8591#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300 8592#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 8593#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400 8594#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa 8595#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000 8596#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 8597#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f 8598#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 8599#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300 8600#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 8601#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400 8602#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa 8603#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000 8604#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 8605#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f 8606#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 8607#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300 8608#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 8609#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400 8610#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa 8611#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000 8612#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 8613#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f 8614#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 8615#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300 8616#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 8617#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400 8618#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa 8619#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000 8620#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 8621#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f 8622#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 8623#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300 8624#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 8625#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400 8626#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa 8627#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000 8628#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 8629#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f 8630#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 8631#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300 8632#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 8633#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400 8634#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa 8635#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000 8636#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 8637#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e 8638#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 8639#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40 8640#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 8641#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1 8642#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 8643#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2 8644#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 8645#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4 8646#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 8647#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8 8648#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 8649#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10 8650#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 8651#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20 8652#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 8653#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40 8654#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 8655#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80 8656#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 8657#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100 8658#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 8659#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200 8660#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 8661#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400 8662#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa 8663#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800 8664#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb 8665#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000 8666#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc 8667#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000 8668#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd 8669#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000 8670#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe 8671#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000 8672#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf 8673#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1 8674#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 8675#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2 8676#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 8677#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4 8678#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 8679#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8 8680#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 8681#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10 8682#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 8683#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20 8684#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 8685#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40 8686#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 8687#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80 8688#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 8689#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100 8690#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 8691#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200 8692#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 8693#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400 8694#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa 8695#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800 8696#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb 8697#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000 8698#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc 8699#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000 8700#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd 8701#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000 8702#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe 8703#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000 8704#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf 8705#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1 8706#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 8707#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2 8708#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 8709#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c 8710#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 8711#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0 8712#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 8713#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700 8714#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 8715#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800 8716#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb 8717#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000 8718#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe 8719#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f 8720#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 8721#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40 8722#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 8723#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000 8724#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe 8725#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1 8726#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 8727#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10 8728#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 8729#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100 8730#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 8731#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000 8732#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc 8733#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000 8734#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 8735#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000 8736#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 8737#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000 8738#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 8739#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff 8740#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 8741#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 8742#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc 8743#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf 8744#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 8745#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0 8746#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 8747#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00 8748#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 8749#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000 8750#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc 8751#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf 8752#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 8753#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf 8754#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 8755#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0 8756#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 8757#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00 8758#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 8759#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000 8760#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc 8761#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000 8762#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 8763#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000 8764#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 8765#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000 8766#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 8767#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000 8768#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c 8769#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7 8770#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 8771#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38 8772#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 8773#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0 8774#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 8775#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00 8776#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 8777#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000 8778#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc 8779#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000 8780#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe 8781#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000 8782#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 8783#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000 8784#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 8785#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff 8786#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 8787#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000 8788#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 8789#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff 8790#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 8791#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000 8792#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 8793#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1 8794#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 8795#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2 8796#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1 8797#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4 8798#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 8799#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8 8800#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3 8801#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10 8802#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 8803#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20 8804#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5 8805#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40 8806#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 8807#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1 8808#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 8809#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2 8810#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1 8811#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4 8812#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 8813#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8 8814#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3 8815#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10 8816#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 8817#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20 8818#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5 8819#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff 8820#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 8821#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00 8822#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 8823#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000 8824#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 8825#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000 8826#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 8827#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff 8828#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0 8829#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00 8830#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8 8831#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000 8832#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10 8833#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000 8834#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18 8835#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x1f 8836#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 8837#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x1f 8838#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 8839#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x1f 8840#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 8841#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x1f 8842#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 8843#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x1f 8844#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 8845#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x1f 8846#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 8847#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x1f 8848#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 8849#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x1f 8850#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 8851#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x1f 8852#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 8853#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x1f 8854#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 8855#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 8856#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 8857#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3 8858#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 8859#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc 8860#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 8861#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70 8862#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 8863#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80 8864#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 8865#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100 8866#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 8867#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200 8868#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 8869#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000 8870#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf 8871#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000 8872#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 8873#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff 8874#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 8875#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200 8876#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 8877#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff 8878#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0 8879#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff 8880#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0 8881#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff 8882#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0 8883#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff 8884#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0 8885#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff 8886#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 8887#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff 8888#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 8889#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1 8890#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0 8891#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2 8892#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1 8893#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4 8894#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2 8895#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8 8896#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3 8897#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10 8898#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4 8899#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1 8900#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 8901#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf 8902#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 8903#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0 8904#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 8905#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00 8906#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 8907#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000 8908#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc 8909#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000 8910#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf 8911#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf 8912#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 8913#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0 8914#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 8915#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00 8916#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 8917#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000 8918#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc 8919#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000 8920#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf 8921#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf 8922#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 8923#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0 8924#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 8925#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00 8926#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 8927#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000 8928#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc 8929#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000 8930#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf 8931#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf 8932#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 8933#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0 8934#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 8935#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00 8936#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 8937#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000 8938#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc 8939#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000 8940#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf 8941#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf 8942#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 8943#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0 8944#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 8945#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00 8946#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 8947#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000 8948#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc 8949#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000 8950#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf 8951#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf 8952#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 8953#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0 8954#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 8955#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00 8956#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 8957#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000 8958#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc 8959#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000 8960#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf 8961#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf 8962#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 8963#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0 8964#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 8965#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00 8966#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 8967#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000 8968#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc 8969#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000 8970#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf 8971#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf 8972#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 8973#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0 8974#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 8975#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00 8976#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 8977#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000 8978#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc 8979#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000 8980#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf 8981#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf 8982#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 8983#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0 8984#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 8985#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00 8986#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 8987#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000 8988#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc 8989#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000 8990#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf 8991#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf 8992#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 8993#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0 8994#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 8995#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00 8996#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 8997#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000 8998#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc 8999#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000 9000#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf 9001#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf 9002#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 9003#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0 9004#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 9005#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00 9006#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 9007#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000 9008#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc 9009#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000 9010#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf 9011#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf 9012#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 9013#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0 9014#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 9015#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00 9016#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 9017#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000 9018#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc 9019#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000 9020#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf 9021#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1 9022#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 9023#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe 9024#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 9025#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000 9026#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 9027#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000 9028#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 9029#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1 9030#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 9031#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe 9032#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 9033#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000 9034#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 9035#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000 9036#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 9037#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1 9038#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 9039#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe 9040#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 9041#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000 9042#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 9043#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000 9044#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 9045#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1 9046#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 9047#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe 9048#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 9049#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000 9050#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 9051#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000 9052#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 9053#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1 9054#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 9055#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe 9056#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 9057#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000 9058#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 9059#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000 9060#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 9061#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1 9062#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 9063#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe 9064#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 9065#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000 9066#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 9067#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000 9068#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 9069#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1 9070#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 9071#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe 9072#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 9073#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000 9074#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 9075#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000 9076#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 9077#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1 9078#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 9079#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe 9080#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 9081#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000 9082#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 9083#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000 9084#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 9085#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1 9086#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 9087#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe 9088#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 9089#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000 9090#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 9091#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000 9092#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 9093#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1 9094#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 9095#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe 9096#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 9097#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000 9098#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 9099#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000 9100#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 9101#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1 9102#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 9103#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe 9104#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 9105#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000 9106#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 9107#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000 9108#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 9109#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1 9110#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 9111#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe 9112#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 9113#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000 9114#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 9115#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000 9116#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 9117#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff 9118#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 9119#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff 9120#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 9121#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000 9122#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 9123#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000 9124#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 9125#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000 9126#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 9127#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000 9128#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a 9129#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000 9130#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b 9131#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1 9132#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0 9133#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe 9134#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1 9135#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0 9136#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4 9137#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00 9138#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa 9139#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000 9140#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10 9141#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000 9142#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11 9143#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000 9144#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12 9145#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000 9146#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13 9147#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000 9148#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14 9149#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000 9150#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15 9151#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000 9152#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16 9153#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000 9154#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17 9155#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000 9156#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18 9157#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000 9158#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19 9159#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000 9160#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f 9161#define SPI_DEBUG_READ__DATA_MASK 0xffffff 9162#define SPI_DEBUG_READ__DATA__SHIFT 0x0 9163#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 9164#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 9165#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 9166#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 9167#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 9168#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 9169#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 9170#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 9171#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 9172#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 9173#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 9174#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 9175#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 9176#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 9177#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 9178#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa 9179#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 9180#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 9181#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 9182#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 9183#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 9184#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa 9185#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 9186#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 9187#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 9188#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 9189#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 9190#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 9191#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 9192#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 9193#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 9194#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 9195#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff 9196#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 9197#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00 9198#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa 9199#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff 9200#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 9201#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00 9202#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa 9203#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff 9204#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 9205#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff 9206#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 9207#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf 9208#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 9209#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0 9210#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 9211#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00 9212#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 9213#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000 9214#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc 9215#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000 9216#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 9217#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000 9218#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 9219#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000 9220#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 9221#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000 9222#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c 9223#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 9224#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 9225#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 9226#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 9227#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 9228#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 9229#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 9230#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 9231#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 9232#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 9233#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 9234#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 9235#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 9236#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 9237#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 9238#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 9239#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff 9240#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 9241#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff 9242#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 9243#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff 9244#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 9245#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff 9246#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 9247#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf 9248#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 9249#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10 9250#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 9251#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40 9252#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 9253#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80 9254#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 9255#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100 9256#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 9257#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200 9258#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 9259#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00 9260#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa 9261#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000 9262#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 9263#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1 9264#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0 9265#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2 9266#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1 9267#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4 9268#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2 9269#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8 9270#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3 9271#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10 9272#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4 9273#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20 9274#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5 9275#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40 9276#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6 9277#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80 9278#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7 9279#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100 9280#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8 9281#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200 9282#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9 9283#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400 9284#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa 9285#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800 9286#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb 9287#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000 9288#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc 9289#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000 9290#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd 9291#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000 9292#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe 9293#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000 9294#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf 9295#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000 9296#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10 9297#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000 9298#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11 9299#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000 9300#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12 9301#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000 9302#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13 9303#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000 9304#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14 9305#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000 9306#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15 9307#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000 9308#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16 9309#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000 9310#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17 9311#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf 9312#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 9313#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0 9314#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 9315#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000 9316#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc 9317#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000 9318#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 9319#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000 9320#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 9321#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000 9322#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 9323#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000 9324#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 9325#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000 9326#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 9327#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000 9328#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 9329#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000 9330#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 9331#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f 9332#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 9333#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00 9334#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 9335#define CGTS_RD_REG__READ_DATA_MASK 0x3fff 9336#define CGTS_RD_REG__READ_DATA__SHIFT 0x0 9337#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 9338#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 9339#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 9340#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 9341#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f 9342#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 9343#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 9344#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 9345#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 9346#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 9347#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 9348#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 9349#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 9350#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 9351#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000 9352#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 9353#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 9354#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 9355#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 9356#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 9357#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 9358#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 9359#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 9360#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9361#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 9362#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 9363#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 9364#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 9365#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 9366#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 9367#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 9368#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 9369#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 9370#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 9371#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 9372#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 9373#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 9374#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 9375#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 9376#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 9377#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 9378#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 9379#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 9380#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9381#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f 9382#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 9383#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 9384#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 9385#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 9386#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 9387#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 9388#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 9389#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 9390#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 9391#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 9392#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 9393#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 9394#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 9395#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 9396#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 9397#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 9398#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 9399#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 9400#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9401#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f 9402#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 9403#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 9404#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 9405#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 9406#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 9407#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 9408#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 9409#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 9410#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 9411#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000 9412#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 9413#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 9414#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 9415#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 9416#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 9417#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 9418#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 9419#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 9420#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9421#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f 9422#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 9423#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 9424#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 9425#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 9426#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 9427#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 9428#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 9429#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 9430#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 9431#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 9432#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 9433#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 9434#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 9435#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 9436#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 9437#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 9438#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 9439#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 9440#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9441#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f 9442#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 9443#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 9444#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 9445#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 9446#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 9447#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 9448#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 9449#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 9450#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 9451#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000 9452#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 9453#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 9454#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 9455#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 9456#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 9457#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 9458#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 9459#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 9460#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9461#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 9462#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 9463#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 9464#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 9465#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 9466#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 9467#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 9468#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 9469#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 9470#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 9471#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 9472#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 9473#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 9474#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 9475#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 9476#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 9477#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 9478#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 9479#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 9480#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9481#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f 9482#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0 9483#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 9484#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 9485#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 9486#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 9487#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 9488#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 9489#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 9490#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 9491#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f 9492#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 9493#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 9494#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 9495#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 9496#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 9497#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 9498#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 9499#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 9500#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 9501#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000 9502#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 9503#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 9504#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 9505#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 9506#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 9507#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 9508#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 9509#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 9510#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9511#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f 9512#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 9513#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 9514#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 9515#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 9516#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 9517#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 9518#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 9519#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 9520#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 9521#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 9522#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 9523#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 9524#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 9525#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 9526#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 9527#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 9528#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 9529#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 9530#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9531#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f 9532#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 9533#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 9534#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 9535#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 9536#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 9537#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 9538#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 9539#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 9540#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 9541#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000 9542#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 9543#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 9544#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 9545#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 9546#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 9547#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 9548#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 9549#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 9550#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9551#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 9552#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 9553#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 9554#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 9555#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 9556#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 9557#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 9558#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 9559#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 9560#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 9561#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 9562#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 9563#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 9564#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 9565#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 9566#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 9567#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 9568#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 9569#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 9570#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9571#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f 9572#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0 9573#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 9574#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 9575#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 9576#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 9577#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 9578#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 9579#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 9580#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 9581#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f 9582#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 9583#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 9584#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 9585#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 9586#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 9587#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 9588#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 9589#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 9590#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 9591#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000 9592#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 9593#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 9594#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 9595#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 9596#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 9597#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 9598#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 9599#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 9600#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9601#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f 9602#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 9603#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 9604#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 9605#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 9606#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 9607#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 9608#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 9609#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 9610#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 9611#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 9612#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 9613#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 9614#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 9615#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 9616#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 9617#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 9618#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 9619#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 9620#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9621#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f 9622#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 9623#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 9624#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 9625#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 9626#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 9627#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 9628#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 9629#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 9630#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 9631#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000 9632#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 9633#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 9634#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 9635#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 9636#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 9637#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 9638#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 9639#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 9640#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9641#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 9642#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 9643#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 9644#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 9645#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 9646#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 9647#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 9648#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 9649#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 9650#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 9651#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 9652#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 9653#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 9654#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 9655#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 9656#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 9657#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 9658#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 9659#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 9660#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9661#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f 9662#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0 9663#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 9664#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 9665#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 9666#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 9667#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 9668#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 9669#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 9670#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 9671#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f 9672#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 9673#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 9674#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 9675#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 9676#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 9677#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 9678#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 9679#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 9680#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 9681#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000 9682#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 9683#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 9684#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 9685#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 9686#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 9687#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 9688#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 9689#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 9690#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9691#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f 9692#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 9693#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 9694#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 9695#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 9696#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 9697#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 9698#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 9699#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 9700#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 9701#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 9702#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 9703#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 9704#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 9705#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 9706#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 9707#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 9708#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 9709#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 9710#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9711#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f 9712#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 9713#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 9714#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 9715#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 9716#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 9717#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 9718#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 9719#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 9720#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 9721#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000 9722#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 9723#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 9724#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 9725#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 9726#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 9727#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 9728#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 9729#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 9730#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9731#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 9732#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 9733#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 9734#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 9735#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 9736#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 9737#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 9738#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 9739#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 9740#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 9741#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 9742#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 9743#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 9744#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 9745#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 9746#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 9747#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 9748#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 9749#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 9750#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9751#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f 9752#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 9753#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 9754#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 9755#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 9756#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 9757#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 9758#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 9759#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 9760#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 9761#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 9762#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 9763#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 9764#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 9765#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 9766#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 9767#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 9768#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 9769#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 9770#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9771#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f 9772#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 9773#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 9774#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 9775#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 9776#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 9777#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 9778#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 9779#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 9780#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 9781#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000 9782#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 9783#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 9784#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 9785#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 9786#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 9787#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 9788#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 9789#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 9790#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9791#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f 9792#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 9793#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 9794#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 9795#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 9796#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 9797#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 9798#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 9799#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 9800#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 9801#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 9802#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 9803#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 9804#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 9805#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 9806#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 9807#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 9808#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 9809#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 9810#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9811#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f 9812#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 9813#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 9814#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 9815#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 9816#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 9817#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 9818#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 9819#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 9820#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 9821#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 9822#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 9823#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 9824#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 9825#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 9826#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 9827#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 9828#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 9829#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 9830#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9831#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 9832#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 9833#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 9834#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 9835#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 9836#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 9837#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 9838#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 9839#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 9840#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 9841#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 9842#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 9843#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 9844#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 9845#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 9846#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 9847#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 9848#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 9849#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 9850#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9851#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f 9852#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0 9853#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 9854#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 9855#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 9856#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 9857#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 9858#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 9859#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 9860#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 9861#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f 9862#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 9863#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 9864#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 9865#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 9866#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 9867#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 9868#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 9869#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 9870#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 9871#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000 9872#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 9873#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 9874#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 9875#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 9876#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 9877#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 9878#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 9879#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 9880#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9881#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f 9882#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 9883#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 9884#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 9885#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 9886#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 9887#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 9888#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 9889#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 9890#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 9891#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 9892#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 9893#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 9894#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 9895#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 9896#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 9897#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 9898#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 9899#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 9900#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9901#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f 9902#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 9903#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 9904#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 9905#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 9906#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 9907#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 9908#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 9909#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 9910#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 9911#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000 9912#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 9913#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 9914#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 9915#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 9916#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 9917#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 9918#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 9919#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 9920#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9921#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 9922#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 9923#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 9924#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 9925#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 9926#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 9927#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 9928#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 9929#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 9930#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 9931#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 9932#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 9933#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 9934#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 9935#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 9936#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 9937#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 9938#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 9939#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 9940#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9941#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f 9942#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0 9943#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 9944#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 9945#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 9946#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 9947#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 9948#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 9949#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 9950#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 9951#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f 9952#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 9953#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 9954#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 9955#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 9956#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 9957#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 9958#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 9959#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 9960#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 9961#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000 9962#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 9963#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 9964#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 9965#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 9966#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 9967#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 9968#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 9969#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 9970#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9971#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f 9972#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 9973#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 9974#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 9975#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 9976#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 9977#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 9978#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 9979#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 9980#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 9981#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 9982#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 9983#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 9984#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 9985#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 9986#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 9987#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 9988#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 9989#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 9990#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 9991#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f 9992#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 9993#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 9994#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 9995#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 9996#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 9997#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 9998#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 9999#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 10000#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 10001#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000 10002#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 10003#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 10004#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 10005#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 10006#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 10007#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 10008#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 10009#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 10010#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10011#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 10012#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 10013#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 10014#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 10015#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 10016#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 10017#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 10018#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 10019#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 10020#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 10021#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 10022#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 10023#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 10024#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 10025#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 10026#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 10027#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 10028#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 10029#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 10030#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10031#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f 10032#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0 10033#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 10034#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 10035#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 10036#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 10037#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 10038#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 10039#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 10040#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 10041#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f 10042#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 10043#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 10044#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 10045#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 10046#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 10047#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 10048#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 10049#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 10050#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 10051#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000 10052#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 10053#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 10054#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 10055#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 10056#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 10057#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 10058#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 10059#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 10060#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10061#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f 10062#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 10063#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 10064#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 10065#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 10066#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 10067#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 10068#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 10069#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 10070#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 10071#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 10072#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 10073#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 10074#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 10075#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 10076#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 10077#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 10078#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 10079#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 10080#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10081#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f 10082#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 10083#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 10084#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 10085#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 10086#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 10087#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 10088#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 10089#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 10090#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 10091#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000 10092#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 10093#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 10094#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 10095#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 10096#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 10097#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 10098#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 10099#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 10100#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10101#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 10102#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 10103#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 10104#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 10105#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 10106#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 10107#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 10108#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 10109#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 10110#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 10111#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 10112#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 10113#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 10114#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 10115#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 10116#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 10117#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 10118#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 10119#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 10120#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10121#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f 10122#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 10123#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 10124#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 10125#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 10126#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 10127#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 10128#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 10129#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 10130#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 10131#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 10132#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 10133#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 10134#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 10135#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 10136#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 10137#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 10138#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 10139#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 10140#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10141#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f 10142#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 10143#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 10144#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 10145#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 10146#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 10147#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 10148#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 10149#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 10150#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 10151#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000 10152#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 10153#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 10154#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 10155#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 10156#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 10157#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 10158#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 10159#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 10160#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10161#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f 10162#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 10163#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 10164#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 10165#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 10166#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 10167#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 10168#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 10169#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 10170#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 10171#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 10172#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 10173#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 10174#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 10175#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 10176#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 10177#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 10178#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 10179#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 10180#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10181#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f 10182#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 10183#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 10184#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 10185#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 10186#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 10187#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 10188#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 10189#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 10190#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 10191#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000 10192#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 10193#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 10194#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 10195#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 10196#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 10197#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 10198#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 10199#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 10200#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10201#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 10202#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 10203#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 10204#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 10205#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 10206#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 10207#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 10208#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 10209#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 10210#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 10211#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 10212#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 10213#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 10214#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 10215#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 10216#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 10217#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 10218#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 10219#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 10220#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10221#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f 10222#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0 10223#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 10224#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 10225#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 10226#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 10227#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 10228#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 10229#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 10230#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 10231#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f 10232#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 10233#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 10234#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 10235#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 10236#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 10237#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 10238#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 10239#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 10240#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 10241#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000 10242#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 10243#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 10244#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 10245#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 10246#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 10247#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 10248#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 10249#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 10250#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10251#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f 10252#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 10253#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 10254#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 10255#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 10256#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 10257#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 10258#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 10259#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 10260#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 10261#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 10262#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 10263#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 10264#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 10265#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 10266#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 10267#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 10268#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 10269#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 10270#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10271#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f 10272#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 10273#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 10274#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 10275#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 10276#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 10277#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 10278#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 10279#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 10280#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 10281#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000 10282#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 10283#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 10284#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 10285#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 10286#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 10287#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 10288#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 10289#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 10290#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10291#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 10292#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 10293#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 10294#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 10295#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 10296#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 10297#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 10298#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 10299#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 10300#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 10301#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 10302#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 10303#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 10304#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 10305#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 10306#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 10307#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 10308#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 10309#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 10310#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10311#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f 10312#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0 10313#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 10314#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 10315#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 10316#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 10317#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 10318#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 10319#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 10320#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 10321#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f 10322#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 10323#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 10324#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 10325#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 10326#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 10327#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 10328#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 10329#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 10330#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 10331#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000 10332#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 10333#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 10334#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 10335#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 10336#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 10337#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 10338#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 10339#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 10340#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10341#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f 10342#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 10343#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 10344#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 10345#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 10346#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 10347#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 10348#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 10349#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 10350#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 10351#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 10352#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 10353#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 10354#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 10355#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 10356#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 10357#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 10358#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 10359#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 10360#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10361#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f 10362#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 10363#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 10364#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 10365#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 10366#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 10367#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 10368#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 10369#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 10370#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 10371#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000 10372#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 10373#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 10374#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 10375#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 10376#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 10377#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 10378#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 10379#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 10380#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10381#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 10382#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 10383#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 10384#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 10385#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 10386#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 10387#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 10388#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 10389#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 10390#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 10391#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 10392#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 10393#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 10394#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 10395#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 10396#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 10397#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 10398#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 10399#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 10400#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10401#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f 10402#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0 10403#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 10404#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 10405#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 10406#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 10407#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 10408#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 10409#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 10410#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 10411#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f 10412#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 10413#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 10414#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 10415#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 10416#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 10417#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 10418#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 10419#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 10420#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 10421#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000 10422#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 10423#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 10424#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 10425#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 10426#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 10427#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 10428#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 10429#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 10430#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10431#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f 10432#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 10433#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 10434#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 10435#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 10436#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 10437#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 10438#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 10439#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 10440#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 10441#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 10442#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 10443#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 10444#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 10445#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 10446#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 10447#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 10448#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 10449#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 10450#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10451#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f 10452#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 10453#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 10454#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 10455#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 10456#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 10457#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 10458#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 10459#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 10460#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 10461#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000 10462#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 10463#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 10464#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 10465#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 10466#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 10467#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 10468#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 10469#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 10470#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10471#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 10472#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 10473#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 10474#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 10475#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 10476#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 10477#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 10478#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 10479#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 10480#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 10481#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 10482#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 10483#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 10484#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 10485#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 10486#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 10487#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 10488#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 10489#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 10490#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10491#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f 10492#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 10493#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 10494#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 10495#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 10496#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 10497#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 10498#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 10499#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 10500#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 10501#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 10502#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 10503#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 10504#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 10505#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 10506#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 10507#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 10508#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 10509#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 10510#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10511#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f 10512#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 10513#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 10514#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 10515#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 10516#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 10517#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 10518#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 10519#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 10520#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 10521#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000 10522#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 10523#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 10524#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 10525#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 10526#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 10527#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 10528#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 10529#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 10530#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10531#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f 10532#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 10533#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 10534#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 10535#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 10536#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 10537#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 10538#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 10539#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 10540#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 10541#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 10542#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 10543#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 10544#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 10545#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 10546#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 10547#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 10548#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 10549#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 10550#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10551#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f 10552#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 10553#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 10554#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 10555#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 10556#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 10557#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 10558#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 10559#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 10560#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 10561#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000 10562#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 10563#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 10564#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 10565#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 10566#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 10567#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 10568#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 10569#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 10570#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10571#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 10572#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 10573#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 10574#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 10575#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 10576#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 10577#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 10578#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 10579#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 10580#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 10581#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 10582#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 10583#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 10584#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 10585#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 10586#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 10587#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 10588#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 10589#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 10590#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10591#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f 10592#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0 10593#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 10594#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 10595#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 10596#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 10597#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 10598#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 10599#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 10600#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 10601#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f 10602#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 10603#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 10604#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 10605#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 10606#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 10607#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 10608#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 10609#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 10610#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 10611#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000 10612#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 10613#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 10614#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 10615#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 10616#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 10617#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 10618#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 10619#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 10620#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10621#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f 10622#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 10623#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 10624#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 10625#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 10626#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 10627#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 10628#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 10629#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 10630#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 10631#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 10632#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 10633#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 10634#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 10635#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 10636#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 10637#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 10638#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 10639#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 10640#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10641#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f 10642#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 10643#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 10644#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 10645#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 10646#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 10647#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 10648#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 10649#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 10650#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 10651#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000 10652#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 10653#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 10654#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 10655#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 10656#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 10657#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 10658#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 10659#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 10660#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10661#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 10662#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 10663#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 10664#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 10665#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 10666#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 10667#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 10668#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 10669#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 10670#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 10671#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 10672#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 10673#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 10674#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 10675#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 10676#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 10677#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 10678#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 10679#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 10680#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10681#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f 10682#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0 10683#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 10684#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 10685#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 10686#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 10687#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 10688#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 10689#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 10690#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 10691#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f 10692#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 10693#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 10694#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 10695#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 10696#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 10697#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 10698#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 10699#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 10700#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 10701#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000 10702#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 10703#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 10704#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 10705#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 10706#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 10707#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 10708#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 10709#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 10710#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10711#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f 10712#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 10713#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 10714#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 10715#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 10716#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 10717#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 10718#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 10719#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 10720#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 10721#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 10722#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 10723#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 10724#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 10725#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 10726#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 10727#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 10728#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 10729#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 10730#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10731#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f 10732#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 10733#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 10734#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 10735#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 10736#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 10737#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 10738#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 10739#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 10740#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 10741#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000 10742#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 10743#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 10744#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 10745#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 10746#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 10747#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 10748#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 10749#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 10750#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10751#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 10752#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 10753#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 10754#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 10755#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 10756#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 10757#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 10758#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 10759#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 10760#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 10761#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 10762#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 10763#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 10764#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 10765#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 10766#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 10767#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 10768#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 10769#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 10770#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10771#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f 10772#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0 10773#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 10774#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 10775#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 10776#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 10777#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 10778#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 10779#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 10780#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 10781#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f 10782#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 10783#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 10784#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 10785#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 10786#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 10787#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 10788#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 10789#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 10790#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 10791#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000 10792#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 10793#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 10794#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 10795#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 10796#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 10797#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 10798#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 10799#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 10800#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10801#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f 10802#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 10803#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 10804#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 10805#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 10806#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 10807#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 10808#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 10809#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 10810#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 10811#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 10812#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 10813#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 10814#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 10815#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 10816#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 10817#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 10818#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 10819#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 10820#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 10821#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf 10822#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 10823#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 10824#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 10825#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 10826#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 10827#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 10828#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 10829#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000 10830#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a 10831#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000 10832#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b 10833#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000 10834#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c 10835#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000 10836#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d 10837#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000 10838#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e 10839#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 10840#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 10841#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf 10842#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 10843#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 10844#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 10845#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 10846#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 10847#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 10848#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 10849#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000 10850#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19 10851#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000 10852#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a 10853#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 10854#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b 10855#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 10856#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c 10857#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 10858#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 10859#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 10860#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e 10861#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 10862#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 10863#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf 10864#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 10865#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 10866#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 10867#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000 10868#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc 10869#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000 10870#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 10871#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000 10872#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 10873#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000 10874#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a 10875#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 10876#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b 10877#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 10878#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c 10879#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 10880#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 10881#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 10882#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e 10883#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 10884#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 10885#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf 10886#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 10887#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10 10888#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 10889#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff 10890#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 10891#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000 10892#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f 10893#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff 10894#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 10895#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000 10896#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f 10897#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff 10898#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 10899#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000 10900#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f 10901#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff 10902#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 10903#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000 10904#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f 10905#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff 10906#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 10907#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000 10908#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f 10909#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff 10910#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 10911#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000 10912#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f 10913#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff 10914#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 10915#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000 10916#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f 10917#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff 10918#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 10919#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000 10920#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f 10921#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff 10922#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 10923#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000 10924#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f 10925#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff 10926#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 10927#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000 10928#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f 10929#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff 10930#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 10931#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000 10932#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f 10933#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff 10934#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 10935#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000 10936#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f 10937#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff 10938#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 10939#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000 10940#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f 10941#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff 10942#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 10943#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000 10944#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f 10945#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff 10946#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 10947#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000 10948#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f 10949#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff 10950#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 10951#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000 10952#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f 10953#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff 10954#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 10955#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000 10956#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f 10957#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff 10958#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 10959#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000 10960#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f 10961#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff 10962#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 10963#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000 10964#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f 10965#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff 10966#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 10967#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000 10968#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f 10969#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff 10970#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 10971#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000 10972#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f 10973#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff 10974#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 10975#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000 10976#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f 10977#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff 10978#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 10979#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000 10980#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f 10981#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff 10982#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 10983#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000 10984#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f 10985#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff 10986#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 10987#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000 10988#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f 10989#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff 10990#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 10991#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000 10992#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f 10993#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff 10994#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 10995#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000 10996#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f 10997#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff 10998#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 10999#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000 11000#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f 11001#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff 11002#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 11003#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000 11004#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f 11005#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff 11006#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 11007#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000 11008#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f 11009#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff 11010#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 11011#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000 11012#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f 11013#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff 11014#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0 11015#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000 11016#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f 11017#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1 11018#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0 11019#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2 11020#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1 11021#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4 11022#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2 11023#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8 11024#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3 11025#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10 11026#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4 11027#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20 11028#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5 11029#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40 11030#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6 11031#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80 11032#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7 11033#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100 11034#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8 11035#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200 11036#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9 11037#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400 11038#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa 11039#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800 11040#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb 11041#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000 11042#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc 11043#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000 11044#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd 11045#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000 11046#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe 11047#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000 11048#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf 11049#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000 11050#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10 11051#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000 11052#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11 11053#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000 11054#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12 11055#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000 11056#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13 11057#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000 11058#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14 11059#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000 11060#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15 11061#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1 11062#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 11063#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff 11064#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 11065#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff 11066#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 11067#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff 11068#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 11069#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff 11070#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 11071#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00 11072#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 11073#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000 11074#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 11075#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff 11076#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 11077#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000 11078#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 11079#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff 11080#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 11081#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000 11082#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 11083#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff 11084#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 11085#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff 11086#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 11087#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff 11088#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 11089#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff 11090#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 11091#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff 11092#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 11093#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff 11094#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 11095#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff 11096#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 11097#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff 11098#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 11099#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff 11100#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 11101#define BCI_DEBUG_READ__DATA_MASK 0xffffff 11102#define BCI_DEBUG_READ__DATA__SHIFT 0x0 11103#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff 11104#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 11105#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff 11106#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 11107#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff 11108#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 11109#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff 11110#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 11111#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f 11112#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 11113#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 11114#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 11115#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff 11116#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 11117#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff 11118#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 11119#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff 11120#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 11121#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff 11122#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 11123#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f 11124#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 11125#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 11126#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 11127#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff 11128#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0 11129#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff 11130#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0 11131#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff 11132#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0 11133#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff 11134#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0 11135#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff 11136#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 11137#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff 11138#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 11139#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f 11140#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 11141#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0 11142#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 11143#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00 11144#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa 11145#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000 11146#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc 11147#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000 11148#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 11149#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000 11150#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 11151#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000 11152#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 11153#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000 11154#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 11155#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000 11156#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 11157#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000 11158#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19 11159#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000 11160#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c 11161#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1 11162#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 11163#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e 11164#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 11165#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40 11166#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 11167#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80 11168#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 11169#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00 11170#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 11171#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000 11172#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 11173#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff 11174#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 11175#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000 11176#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 11177#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 11178#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 11179#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff 11180#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 11181#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff 11182#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 11183#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff 11184#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 11185#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff 11186#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 11187#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff 11188#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 11189#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff 11190#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 11191#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff 11192#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 11193#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff 11194#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 11195#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff 11196#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 11197#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff 11198#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 11199#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff 11200#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 11201#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff 11202#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 11203#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff 11204#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 11205#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff 11206#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 11207#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff 11208#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 11209#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff 11210#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 11211#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff 11212#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0 11213#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff 11214#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0 11215#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff 11216#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0 11217#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff 11218#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0 11219#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff 11220#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 11221#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff 11222#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 11223#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f 11224#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 11225#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0 11226#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 11227#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00 11228#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa 11229#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000 11230#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc 11231#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000 11232#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 11233#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000 11234#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 11235#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000 11236#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16 11237#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000 11238#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 11239#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000 11240#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 11241#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000 11242#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a 11243#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000 11244#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b 11245#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000 11246#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e 11247#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1 11248#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 11249#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e 11250#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 11251#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40 11252#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 11253#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80 11254#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 11255#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100 11256#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 11257#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200 11258#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 11259#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400 11260#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa 11261#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800 11262#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb 11263#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000 11264#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc 11265#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000 11266#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd 11267#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff 11268#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 11269#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000 11270#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 11271#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 11272#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 11273#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f 11274#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 11275#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff 11276#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 11277#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff 11278#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 11279#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff 11280#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 11281#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff 11282#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 11283#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff 11284#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 11285#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff 11286#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 11287#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff 11288#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 11289#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff 11290#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 11291#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff 11292#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 11293#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff 11294#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 11295#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff 11296#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 11297#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff 11298#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 11299#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff 11300#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 11301#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff 11302#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 11303#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff 11304#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 11305#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff 11306#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 11307#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1 11308#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0 11309#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e 11310#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1 11311#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40 11312#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6 11313#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80 11314#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7 11315#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00 11316#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8 11317#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000 11318#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14 11319#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1 11320#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0 11321#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e 11322#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1 11323#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40 11324#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6 11325#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80 11326#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7 11327#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000 11328#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10 11329#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff 11330#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0 11331#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff 11332#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0 11333#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff 11334#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0 11335#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff 11336#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0 11337#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff 11338#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 11339#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff 11340#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 11341#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f 11342#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 11343#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0 11344#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 11345#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00 11346#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa 11347#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000 11348#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc 11349#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000 11350#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 11351#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000 11352#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 11353#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000 11354#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 11355#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000 11356#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 11357#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000 11358#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 11359#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000 11360#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19 11361#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000 11362#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c 11363#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1 11364#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 11365#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e 11366#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 11367#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40 11368#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 11369#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80 11370#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 11371#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff 11372#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 11373#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000 11374#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 11375#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 11376#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 11377#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff 11378#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 11379#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff 11380#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 11381#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff 11382#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 11383#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff 11384#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 11385#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff 11386#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 11387#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff 11388#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 11389#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff 11390#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 11391#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff 11392#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 11393#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff 11394#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 11395#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff 11396#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 11397#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff 11398#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 11399#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff 11400#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 11401#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff 11402#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 11403#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff 11404#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 11405#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff 11406#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 11407#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff 11408#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 11409#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1 11410#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0 11411#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e 11412#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1 11413#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40 11414#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6 11415#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80 11416#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7 11417#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00 11418#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8 11419#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000 11420#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14 11421#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff 11422#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0 11423#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff 11424#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0 11425#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff 11426#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0 11427#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff 11428#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0 11429#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff 11430#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 11431#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff 11432#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 11433#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f 11434#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0 11435#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0 11436#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6 11437#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00 11438#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa 11439#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000 11440#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc 11441#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000 11442#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14 11443#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000 11444#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15 11445#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000 11446#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16 11447#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000 11448#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17 11449#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000 11450#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18 11451#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000 11452#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a 11453#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000 11454#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b 11455#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000 11456#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e 11457#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1 11458#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0 11459#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e 11460#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1 11461#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40 11462#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6 11463#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80 11464#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7 11465#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00 11466#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8 11467#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000 11468#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14 11469#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff 11470#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0 11471#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000 11472#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10 11473#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000 11474#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16 11475#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff 11476#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 11477#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff 11478#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 11479#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff 11480#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 11481#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff 11482#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 11483#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff 11484#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 11485#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff 11486#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 11487#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff 11488#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 11489#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff 11490#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 11491#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff 11492#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 11493#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff 11494#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 11495#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff 11496#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 11497#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff 11498#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 11499#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff 11500#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 11501#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff 11502#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 11503#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff 11504#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 11505#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff 11506#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 11507#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1 11508#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0 11509#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e 11510#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1 11511#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40 11512#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6 11513#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80 11514#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7 11515#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000 11516#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10 11517#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff 11518#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0 11519#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff 11520#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0 11521#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff 11522#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0 11523#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff 11524#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0 11525#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff 11526#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 11527#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff 11528#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 11529#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f 11530#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 11531#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0 11532#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 11533#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00 11534#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa 11535#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000 11536#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc 11537#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000 11538#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 11539#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000 11540#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 11541#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000 11542#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 11543#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000 11544#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 11545#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000 11546#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18 11547#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000 11548#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b 11549#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1 11550#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 11551#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e 11552#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 11553#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40 11554#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 11555#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80 11556#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 11557#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100 11558#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 11559#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00 11560#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 11561#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f 11562#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 11563#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0 11564#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 11565#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff 11566#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 11567#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff 11568#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 11569#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff 11570#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 11571#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff 11572#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 11573#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff 11574#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 11575#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff 11576#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 11577#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff 11578#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 11579#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff 11580#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 11581#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff 11582#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 11583#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff 11584#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 11585#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff 11586#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 11587#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff 11588#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 11589#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff 11590#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 11591#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff 11592#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 11593#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff 11594#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 11595#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff 11596#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 11597#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1 11598#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0 11599#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e 11600#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1 11601#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40 11602#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6 11603#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80 11604#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7 11605#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000 11606#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10 11607#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff 11608#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0 11609#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff 11610#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0 11611#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff 11612#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0 11613#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff 11614#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0 11615#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff 11616#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 11617#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff 11618#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 11619#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f 11620#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0 11621#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0 11622#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6 11623#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00 11624#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa 11625#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000 11626#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc 11627#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000 11628#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14 11629#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000 11630#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15 11631#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000 11632#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16 11633#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000 11634#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17 11635#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000 11636#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18 11637#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000 11638#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a 11639#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000 11640#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d 11641#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1 11642#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0 11643#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e 11644#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1 11645#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40 11646#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6 11647#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80 11648#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7 11649#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000 11650#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10 11651#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff 11652#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0 11653#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000 11654#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10 11655#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 11656#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16 11657#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff 11658#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 11659#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff 11660#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 11661#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff 11662#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 11663#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff 11664#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 11665#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff 11666#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 11667#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff 11668#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 11669#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff 11670#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 11671#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff 11672#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 11673#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff 11674#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 11675#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff 11676#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 11677#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff 11678#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 11679#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff 11680#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 11681#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff 11682#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 11683#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff 11684#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 11685#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff 11686#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 11687#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff 11688#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 11689#define SQ_CONFIG__UNUSED_MASK 0xff 11690#define SQ_CONFIG__UNUSED__SHIFT 0x0 11691#define SQ_CONFIG__DEBUG_EN_MASK 0x100 11692#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8 11693#define SQ_CONFIG__DISABLE_SCA_BYPASS_MASK 0x200 11694#define SQ_CONFIG__DISABLE_SCA_BYPASS__SHIFT 0x9 11695#define SQ_CONFIG__DISABLE_IB_DEP_CHECK_MASK 0x400 11696#define SQ_CONFIG__DISABLE_IB_DEP_CHECK__SHIFT 0xa 11697#define SQ_CONFIG__ENABLE_SOFT_CLAUSE_MASK 0x800 11698#define SQ_CONFIG__ENABLE_SOFT_CLAUSE__SHIFT 0xb 11699#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000 11700#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc 11701#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000 11702#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd 11703#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000 11704#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe 11705#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000 11706#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf 11707#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3 11708#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 11709#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc 11710#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 11711#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30 11712#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 11713#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40 11714#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 11715#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80 11716#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 11717#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100 11718#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 11719#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200 11720#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 11721#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400 11722#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa 11723#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800 11724#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb 11725#define SQC_CACHES__INST_INVALIDATE_MASK 0x1 11726#define SQC_CACHES__INST_INVALIDATE__SHIFT 0x0 11727#define SQC_CACHES__DATA_INVALIDATE_MASK 0x2 11728#define SQC_CACHES__DATA_INVALIDATE__SHIFT 0x1 11729#define SQC_CACHES__INVALIDATE_VOLATILE_MASK 0x4 11730#define SQC_CACHES__INVALIDATE_VOLATILE__SHIFT 0x2 11731#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f 11732#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 11733#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380 11734#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 11735#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00 11736#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa 11737#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f 11738#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 11739#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00 11740#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 11741#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000 11742#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c 11743#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000 11744#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d 11745#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000 11746#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e 11747#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000 11748#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f 11749#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf 11750#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 11751#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00 11752#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 11753#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000 11754#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 11755#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000 11756#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 11757#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff 11758#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 11759#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1 11760#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 11761#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1 11762#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 11763#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2 11764#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 11765#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4 11766#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 11767#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8 11768#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 11769#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10 11770#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 11771#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20 11772#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 11773#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40 11774#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 11775#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00 11776#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 11777#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000 11778#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd 11779#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff 11780#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 11781#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000 11782#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 11783#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1 11784#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 11785#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 11786#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 11787#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 11788#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 11789#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 11790#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 11791#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 11792#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c 11793#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 11794#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 11795#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 11796#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 11797#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 11798#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 11799#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 11800#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c 11801#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 11802#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 11803#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 11804#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 11805#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 11806#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 11807#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 11808#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 11809#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff 11810#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 11811#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff 11812#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 11813#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff 11814#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 11815#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff 11816#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 11817#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff 11818#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 11819#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff 11820#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 11821#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff 11822#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 11823#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff 11824#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 11825#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff 11826#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 11827#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff 11828#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 11829#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff 11830#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 11831#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff 11832#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 11833#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 11834#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 11835#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 11836#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 11837#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 11838#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 11839#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 11840#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 11841#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff 11842#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 11843#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff 11844#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 11845#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff 11846#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 11847#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff 11848#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 11849#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff 11850#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 11851#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff 11852#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 11853#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff 11854#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 11855#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff 11856#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 11857#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff 11858#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 11859#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff 11860#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 11861#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff 11862#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 11863#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff 11864#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 11865#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff 11866#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 11867#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000 11868#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc 11869#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 11870#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 11871#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000 11872#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 11873#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000 11874#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 11875#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 11876#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 11877#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff 11878#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 11879#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000 11880#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc 11881#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 11882#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 11883#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000 11884#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 11885#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000 11886#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 11887#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 11888#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 11889#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff 11890#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 11891#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000 11892#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc 11893#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 11894#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 11895#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000 11896#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 11897#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000 11898#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 11899#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 11900#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 11901#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff 11902#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 11903#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000 11904#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc 11905#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 11906#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 11907#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000 11908#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 11909#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000 11910#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 11911#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 11912#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 11913#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff 11914#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 11915#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000 11916#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc 11917#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 11918#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 11919#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000 11920#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 11921#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000 11922#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 11923#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000 11924#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c 11925#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff 11926#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 11927#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000 11928#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc 11929#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 11930#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 11931#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000 11932#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 11933#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000 11934#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 11935#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000 11936#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c 11937#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0xff 11938#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 11939#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000 11940#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc 11941#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 11942#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 11943#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000 11944#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 11945#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000 11946#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 11947#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000 11948#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c 11949#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0xff 11950#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 11951#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000 11952#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc 11953#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 11954#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 11955#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000 11956#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 11957#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000 11958#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 11959#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000 11960#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c 11961#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0xff 11962#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 11963#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000 11964#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc 11965#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 11966#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 11967#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000 11968#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 11969#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000 11970#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 11971#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000 11972#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c 11973#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0xff 11974#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 11975#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000 11976#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc 11977#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 11978#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 11979#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000 11980#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 11981#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000 11982#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 11983#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000 11984#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c 11985#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0xff 11986#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 11987#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000 11988#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc 11989#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 11990#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 11991#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000 11992#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 11993#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000 11994#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 11995#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000 11996#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c 11997#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0xff 11998#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 11999#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000 12000#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc 12001#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 12002#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 12003#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000 12004#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 12005#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000 12006#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 12007#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000 12008#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c 12009#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0xff 12010#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 12011#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000 12012#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc 12013#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 12014#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 12015#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000 12016#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 12017#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000 12018#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 12019#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000 12020#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c 12021#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0xff 12022#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 12023#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000 12024#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc 12025#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 12026#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 12027#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000 12028#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 12029#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000 12030#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 12031#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000 12032#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c 12033#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0xff 12034#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 12035#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000 12036#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc 12037#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 12038#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 12039#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000 12040#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 12041#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000 12042#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 12043#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000 12044#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c 12045#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0xff 12046#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 12047#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000 12048#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc 12049#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 12050#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 12051#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000 12052#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 12053#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000 12054#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 12055#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000 12056#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c 12057#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf 12058#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 12059#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 12060#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 12061#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 12062#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 12063#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 12064#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 12065#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf 12066#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 12067#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 12068#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 12069#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 12070#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 12071#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 12072#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 12073#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff 12074#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 12075#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 12076#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 12077#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff 12078#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 12079#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 12080#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 12081#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff 12082#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 12083#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 12084#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 12085#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff 12086#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 12087#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000 12088#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 12089#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000 12090#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e 12091#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff 12092#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 12093#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 12094#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 12095#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 12096#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 12097#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000 12098#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f 12099#define SQ_TIME_HI__TIME_MASK 0xffffffff 12100#define SQ_TIME_HI__TIME__SHIFT 0x0 12101#define SQ_TIME_LO__TIME_MASK 0xffffffff 12102#define SQ_TIME_LO__TIME__SHIFT 0x0 12103#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff 12104#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 12105#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf 12106#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 12107#define SQ_THREAD_TRACE_BASE2__ATC_MASK 0x10 12108#define SQ_THREAD_TRACE_BASE2__ATC__SHIFT 0x4 12109#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff 12110#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 12111#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f 12112#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 12113#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20 12114#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 12115#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80 12116#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 12117#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00 12118#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 12119#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000 12120#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc 12121#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000 12122#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe 12123#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000 12124#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf 12125#define SQ_THREAD_TRACE_MASK__RANDOM_SEED_MASK 0xffff0000 12126#define SQ_THREAD_TRACE_MASK__RANDOM_SEED__SHIFT 0x10 12127#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff 12128#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 12129#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff 12130#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 12131#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff 12132#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 12133#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff 12134#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 12135#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7 12136#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 12137#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38 12138#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 12139#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0 12140#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 12141#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00 12142#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 12143#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000 12144#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc 12145#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000 12146#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf 12147#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000 12148#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 12149#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000 12150#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 12151#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000 12152#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 12153#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000 12154#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 12155#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000 12156#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a 12157#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000 12158#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b 12159#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000 12160#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d 12161#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000 12162#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e 12163#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000 12164#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f 12165#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000 12166#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f 12167#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff 12168#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 12169#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000 12170#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 12171#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000 12172#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 12173#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffff 12174#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 12175#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff 12176#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 12177#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000 12178#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 12179#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff 12180#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 12181#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000 12182#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e 12183#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff 12184#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 12185#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000 12186#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 12187#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000 12188#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d 12189#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000 12190#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e 12191#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000 12192#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f 12193#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff 12194#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 12195#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7 12196#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 12197#define SQ_LB_CTR_CTRL__START_MASK 0x1 12198#define SQ_LB_CTR_CTRL__START__SHIFT 0x0 12199#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2 12200#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 12201#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4 12202#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 12203#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff 12204#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0 12205#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff 12206#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0 12207#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff 12208#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0 12209#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff 12210#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0 12211#define SQC_SECDED_CNT__INST_SEC_MASK 0xff 12212#define SQC_SECDED_CNT__INST_SEC__SHIFT 0x0 12213#define SQC_SECDED_CNT__INST_DED_MASK 0xff00 12214#define SQC_SECDED_CNT__INST_DED__SHIFT 0x8 12215#define SQC_SECDED_CNT__DATA_SEC_MASK 0xff0000 12216#define SQC_SECDED_CNT__DATA_SEC__SHIFT 0x10 12217#define SQC_SECDED_CNT__DATA_DED_MASK 0xff000000 12218#define SQC_SECDED_CNT__DATA_DED__SHIFT 0x18 12219#define SQ_SEC_CNT__LDS_SEC_MASK 0x3f 12220#define SQ_SEC_CNT__LDS_SEC__SHIFT 0x0 12221#define SQ_SEC_CNT__SGPR_SEC_MASK 0x1f00 12222#define SQ_SEC_CNT__SGPR_SEC__SHIFT 0x8 12223#define SQ_SEC_CNT__VGPR_SEC_MASK 0x1ff0000 12224#define SQ_SEC_CNT__VGPR_SEC__SHIFT 0x10 12225#define SQ_DED_CNT__LDS_DED_MASK 0x3f 12226#define SQ_DED_CNT__LDS_DED__SHIFT 0x0 12227#define SQ_DED_CNT__SGPR_DED_MASK 0x1f00 12228#define SQ_DED_CNT__SGPR_DED__SHIFT 0x8 12229#define SQ_DED_CNT__VGPR_DED_MASK 0x1ff0000 12230#define SQ_DED_CNT__VGPR_DED__SHIFT 0x10 12231#define SQ_DED_INFO__WAVE_ID_MASK 0xf 12232#define SQ_DED_INFO__WAVE_ID__SHIFT 0x0 12233#define SQ_DED_INFO__SIMD_ID_MASK 0x30 12234#define SQ_DED_INFO__SIMD_ID__SHIFT 0x4 12235#define SQ_DED_INFO__SOURCE_MASK 0x1c0 12236#define SQ_DED_INFO__SOURCE__SHIFT 0x6 12237#define SQ_DED_INFO__VM_ID_MASK 0x1e00 12238#define SQ_DED_INFO__VM_ID__SHIFT 0x9 12239#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff 12240#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 12241#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff 12242#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 12243#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000 12244#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 12245#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000 12246#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e 12247#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000 12248#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f 12249#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff 12250#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 12251#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7 12252#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 12253#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38 12254#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 12255#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 12256#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 12257#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00 12258#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 12259#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000 12260#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc 12261#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000 12262#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf 12263#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000 12264#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13 12265#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000 12266#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 12267#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000 12268#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 12269#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000 12270#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18 12271#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000 12272#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19 12273#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000 12274#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a 12275#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000 12276#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b 12277#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000 12278#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e 12279#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff 12280#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 12281#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff 12282#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 12283#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00 12284#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 12285#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000 12286#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 12287#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000 12288#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a 12289#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000 12290#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e 12291#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff 12292#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 12293#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000 12294#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe 12295#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000 12296#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c 12297#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000 12298#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f 12299#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7 12300#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 12301#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38 12302#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 12303#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 12304#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 12305#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00 12306#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 12307#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000 12308#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc 12309#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000 12310#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 12311#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000 12312#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14 12313#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000 12314#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19 12315#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000 12316#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a 12317#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000 12318#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b 12319#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000 12320#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c 12321#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff 12322#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 12323#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000 12324#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd 12325#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff 12326#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 12327#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000 12328#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd 12329#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff 12330#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 12331#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000 12332#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc 12333#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000 12334#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 12335#define SQ_IMG_RSRC_WORD6__UNUNSED_MASK 0xffe00000 12336#define SQ_IMG_RSRC_WORD6__UNUNSED__SHIFT 0x15 12337#define SQ_IMG_RSRC_WORD7__UNUNSED_MASK 0xffffffff 12338#define SQ_IMG_RSRC_WORD7__UNUNSED__SHIFT 0x0 12339#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7 12340#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 12341#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38 12342#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 12343#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0 12344#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 12345#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00 12346#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 12347#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000 12348#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc 12349#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000 12350#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf 12351#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000 12352#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 12353#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000 12354#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 12355#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000 12356#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 12357#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000 12358#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 12359#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000 12360#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b 12361#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000 12362#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c 12363#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000 12364#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d 12365#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff 12366#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 12367#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000 12368#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc 12369#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000 12370#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 12371#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000 12372#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c 12373#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff 12374#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 12375#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000 12376#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe 12377#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000 12378#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 12379#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000 12380#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 12381#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000 12382#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 12383#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000 12384#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a 12385#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000 12386#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c 12387#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000 12388#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d 12389#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000 12390#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e 12391#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff 12392#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 12393#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000 12394#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e 12395#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff 12396#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 12397#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff 12398#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 12399#define SQ_IND_INDEX__WAVE_ID_MASK 0xf 12400#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 12401#define SQ_IND_INDEX__SIMD_ID_MASK 0x30 12402#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 12403#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0 12404#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 12405#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000 12406#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc 12407#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000 12408#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd 12409#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000 12410#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe 12411#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000 12412#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf 12413#define SQ_IND_INDEX__INDEX_MASK 0xffff0000 12414#define SQ_IND_INDEX__INDEX__SHIFT 0x10 12415#define SQ_CMD__CMD_MASK 0x7 12416#define SQ_CMD__CMD__SHIFT 0x0 12417#define SQ_CMD__MODE_MASK 0x70 12418#define SQ_CMD__MODE__SHIFT 0x4 12419#define SQ_CMD__CHECK_VMID_MASK 0x80 12420#define SQ_CMD__CHECK_VMID__SHIFT 0x7 12421#define SQ_CMD__TRAP_ID_MASK 0x700 12422#define SQ_CMD__TRAP_ID__SHIFT 0x8 12423#define SQ_CMD__WAVE_ID_MASK 0xf0000 12424#define SQ_CMD__WAVE_ID__SHIFT 0x10 12425#define SQ_CMD__SIMD_ID_MASK 0x300000 12426#define SQ_CMD__SIMD_ID__SHIFT 0x14 12427#define SQ_CMD__QUEUE_ID_MASK 0x7000000 12428#define SQ_CMD__QUEUE_ID__SHIFT 0x18 12429#define SQ_CMD__VM_ID_MASK 0xf0000000 12430#define SQ_CMD__VM_ID__SHIFT 0x1c 12431#define SQ_IND_DATA__DATA_MASK 0xffffffff 12432#define SQ_IND_DATA__DATA__SHIFT 0x0 12433#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff 12434#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 12435#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff 12436#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 12437#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf 12438#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0 12439#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0 12440#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4 12441#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff 12442#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 12443#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff 12444#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 12445#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff 12446#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 12447#define SQ_WAVE_PC_HI__PC_HI_MASK 0xff 12448#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 12449#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7 12450#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 12451#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8 12452#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 12453#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10 12454#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 12455#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0 12456#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 12457#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300 12458#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 12459#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00 12460#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa 12461#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x70000 12462#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 12463#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0x380000 12464#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x13 12465#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0xc00000 12466#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x16 12467#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x1000000 12468#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x18 12469#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x6000000 12470#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x19 12471#define SQ_WAVE_IB_DBG0__KILL_MASK 0x8000000 12472#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1b 12473#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x10000000 12474#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1c 12475#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff 12476#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 12477#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff 12478#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 12479#define SQ_WAVE_STATUS__SCC_MASK 0x1 12480#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 12481#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6 12482#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 12483#define SQ_WAVE_STATUS__WAVE_PRIO_MASK 0x18 12484#define SQ_WAVE_STATUS__WAVE_PRIO__SHIFT 0x3 12485#define SQ_WAVE_STATUS__PRIV_MASK 0x20 12486#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 12487#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40 12488#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 12489#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80 12490#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 12491#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100 12492#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 12493#define SQ_WAVE_STATUS__EXECZ_MASK 0x200 12494#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 12495#define SQ_WAVE_STATUS__VCCZ_MASK 0x400 12496#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa 12497#define SQ_WAVE_STATUS__IN_TG_MASK 0x800 12498#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb 12499#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000 12500#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc 12501#define SQ_WAVE_STATUS__HALT_MASK 0x2000 12502#define SQ_WAVE_STATUS__HALT__SHIFT 0xd 12503#define SQ_WAVE_STATUS__TRAP_MASK 0x4000 12504#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe 12505#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000 12506#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf 12507#define SQ_WAVE_STATUS__VALID_MASK 0x10000 12508#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 12509#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000 12510#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 12511#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000 12512#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 12513#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000 12514#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 12515#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000 12516#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14 12517#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000 12518#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15 12519#define SQ_WAVE_STATUS__DATA_ATC_MASK 0x400000 12520#define SQ_WAVE_STATUS__DATA_ATC__SHIFT 0x16 12521#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000 12522#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17 12523#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL_MASK 0x7000000 12524#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL__SHIFT 0x18 12525#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000 12526#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b 12527#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf 12528#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 12529#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0 12530#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 12531#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100 12532#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 12533#define SQ_WAVE_MODE__IEEE_MASK 0x200 12534#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 12535#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400 12536#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa 12537#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800 12538#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb 12539#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000 12540#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc 12541#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000 12542#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c 12543#define SQ_WAVE_MODE__CSP_MASK 0xe0000000 12544#define SQ_WAVE_MODE__CSP__SHIFT 0x1d 12545#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff 12546#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 12547#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000 12548#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 12549#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000 12550#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d 12551#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf 12552#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 12553#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30 12554#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 12555#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0 12556#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 12557#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00 12558#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 12559#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000 12560#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc 12561#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000 12562#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd 12563#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000 12564#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 12565#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000 12566#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 12567#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000 12568#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 12569#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000 12570#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b 12571#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000 12572#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e 12573#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f 12574#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 12575#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00 12576#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 12577#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000 12578#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 12579#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000 12580#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 12581#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff 12582#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 12583#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000 12584#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc 12585#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf 12586#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 12587#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70 12588#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 12589#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00 12590#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 12591#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000 12592#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc 12593#define SQ_WAVE_M0__M0_MASK 0xffffffff 12594#define SQ_WAVE_M0__M0__SHIFT 0x0 12595#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff 12596#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0 12597#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff 12598#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0 12599#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff 12600#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0 12601#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff 12602#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0 12603#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff 12604#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 12605#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff 12606#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 12607#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff 12608#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 12609#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff 12610#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 12611#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff 12612#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 12613#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff 12614#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 12615#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff 12616#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 12617#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff 12618#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 12619#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff 12620#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 12621#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff 12622#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 12623#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff 12624#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 12625#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff 12626#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 12627#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1 12628#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 12629#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2 12630#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1 12631#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0 12632#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4 12633#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000 12634#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10 12635#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff 12636#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0 12637#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00 12638#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8 12639#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000 12640#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10 12641#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000 12642#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18 12643#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf 12644#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0 12645#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0xf0 12646#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4 12647#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1 12648#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 12649#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0 12650#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 12651#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff 12652#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 12653#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff 12654#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 12655#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000 12656#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 12657#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff 12658#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0 12659#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff 12660#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0 12661#define SH_MEM_CONFIG__PTR32_MASK 0x1 12662#define SH_MEM_CONFIG__PTR32__SHIFT 0x0 12663#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x2 12664#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x1 12665#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0xc 12666#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2 12667#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0x70 12668#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x4 12669#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x380 12670#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x7 12671#define SQC_POLICY__DATA_L1_POLICY_0_MASK 0x1 12672#define SQC_POLICY__DATA_L1_POLICY_0__SHIFT 0x0 12673#define SQC_POLICY__DATA_L1_POLICY_1_MASK 0x2 12674#define SQC_POLICY__DATA_L1_POLICY_1__SHIFT 0x1 12675#define SQC_POLICY__DATA_L1_POLICY_2_MASK 0x4 12676#define SQC_POLICY__DATA_L1_POLICY_2__SHIFT 0x2 12677#define SQC_POLICY__DATA_L1_POLICY_3_MASK 0x8 12678#define SQC_POLICY__DATA_L1_POLICY_3__SHIFT 0x3 12679#define SQC_POLICY__DATA_L1_POLICY_4_MASK 0x10 12680#define SQC_POLICY__DATA_L1_POLICY_4__SHIFT 0x4 12681#define SQC_POLICY__DATA_L1_POLICY_5_MASK 0x20 12682#define SQC_POLICY__DATA_L1_POLICY_5__SHIFT 0x5 12683#define SQC_POLICY__DATA_L1_POLICY_6_MASK 0x40 12684#define SQC_POLICY__DATA_L1_POLICY_6__SHIFT 0x6 12685#define SQC_POLICY__DATA_L1_POLICY_7_MASK 0x80 12686#define SQC_POLICY__DATA_L1_POLICY_7__SHIFT 0x7 12687#define SQC_POLICY__DATA_L2_POLICY_0_MASK 0x300 12688#define SQC_POLICY__DATA_L2_POLICY_0__SHIFT 0x8 12689#define SQC_POLICY__DATA_L2_POLICY_1_MASK 0xc00 12690#define SQC_POLICY__DATA_L2_POLICY_1__SHIFT 0xa 12691#define SQC_POLICY__DATA_L2_POLICY_2_MASK 0x3000 12692#define SQC_POLICY__DATA_L2_POLICY_2__SHIFT 0xc 12693#define SQC_POLICY__DATA_L2_POLICY_3_MASK 0xc000 12694#define SQC_POLICY__DATA_L2_POLICY_3__SHIFT 0xe 12695#define SQC_POLICY__DATA_L2_POLICY_4_MASK 0x30000 12696#define SQC_POLICY__DATA_L2_POLICY_4__SHIFT 0x10 12697#define SQC_POLICY__DATA_L2_POLICY_5_MASK 0xc0000 12698#define SQC_POLICY__DATA_L2_POLICY_5__SHIFT 0x12 12699#define SQC_POLICY__DATA_L2_POLICY_6_MASK 0x300000 12700#define SQC_POLICY__DATA_L2_POLICY_6__SHIFT 0x14 12701#define SQC_POLICY__DATA_L2_POLICY_7_MASK 0xc00000 12702#define SQC_POLICY__DATA_L2_POLICY_7__SHIFT 0x16 12703#define SQC_POLICY__INST_L2_POLICY_MASK 0x3000000 12704#define SQC_POLICY__INST_L2_POLICY__SHIFT 0x18 12705#define SQC_VOLATILE__DATA_L1_MASK 0xf 12706#define SQC_VOLATILE__DATA_L1__SHIFT 0x0 12707#define SQC_VOLATILE__DATA_L2_MASK 0xf0 12708#define SQC_VOLATILE__DATA_L2__SHIFT 0x4 12709#define SQC_VOLATILE__INST_L2_MASK 0x100 12710#define SQC_VOLATILE__INST_L2__SHIFT 0x8 12711#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf 12712#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 12713#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10 12714#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 12715#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf 12716#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 12717#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10 12718#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 12719#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0 12720#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 12721#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600 12722#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 12723#define SQ_THREAD_TRACE_WORD_INST__SIZE_MASK 0x800 12724#define SQ_THREAD_TRACE_WORD_INST__SIZE__SHIFT 0xb 12725#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf000 12726#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xc 12727#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf 12728#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 12729#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10 12730#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 12731#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0 12732#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 12733#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600 12734#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 12735#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000 12736#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 12737#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff 12738#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 12739#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf 12740#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 12741#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10 12742#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 12743#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20 12744#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 12745#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0 12746#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 12747#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00 12748#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa 12749#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000 12750#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe 12751#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000 12752#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 12753#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff 12754#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 12755#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf 12756#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 12757#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000 12758#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 12759#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff 12760#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 12761#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf 12762#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 12763#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10 12764#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 12765#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20 12766#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 12767#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0 12768#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 12769#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00 12770#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa 12771#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000 12772#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe 12773#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf 12774#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 12775#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0 12776#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 12777#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000 12778#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc 12779#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000 12780#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd 12781#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf 12782#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 12783#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10 12784#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 12785#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20 12786#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 12787#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0 12788#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 12789#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00 12790#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa 12791#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000 12792#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe 12793#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000 12794#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 12795#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000 12796#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 12797#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000 12798#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 12799#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000 12800#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d 12801#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf 12802#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 12803#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10 12804#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 12805#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60 12806#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 12807#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180 12808#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 12809#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200 12810#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 12811#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00 12812#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa 12813#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000 12814#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe 12815#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000 12816#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf 12817#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000 12818#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 12819#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff 12820#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 12821#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf 12822#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 12823#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10 12824#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 12825#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60 12826#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 12827#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180 12828#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 12829#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00 12830#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 12831#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000 12832#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 12833#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff 12834#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 12835#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf 12836#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 12837#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10 12838#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 12839#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20 12840#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 12841#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0 12842#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 12843#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00 12844#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa 12845#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf 12846#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 12847#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10 12848#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 12849#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60 12850#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 12851#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300 12852#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 12853#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00 12854#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa 12855#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000 12856#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc 12857#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000 12858#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe 12859#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000 12860#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 12861#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000 12862#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 12863#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000 12864#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 12865#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000 12866#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 12867#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000 12868#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 12869#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000 12870#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a 12871#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf 12872#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 12873#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10 12874#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 12875#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20 12876#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 12877#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0 12878#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 12879#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00 12880#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa 12881#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000 12882#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc 12883#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000 12884#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 12885#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f 12886#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 12887#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0 12888#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 12889#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000 12890#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 12891#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000 12892#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18 12893#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000 12894#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a 12895#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1 12896#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0 12897#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2 12898#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1 12899#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4 12900#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 12901#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8 12902#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3 12903#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10 12904#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4 12905#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20 12906#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5 12907#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40 12908#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6 12909#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80 12910#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7 12911#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000 12912#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18 12913#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000 12914#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a 12915#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff 12916#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0 12917#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100 12918#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8 12919#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200 12920#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9 12921#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00 12922#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa 12923#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000 12924#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe 12925#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000 12926#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12 12927#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000 12928#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14 12929#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000 12930#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18 12931#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000 12932#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a 12933#define SQ_SOP2__SSRC0_MASK 0xff 12934#define SQ_SOP2__SSRC0__SHIFT 0x0 12935#define SQ_SOP2__SSRC1_MASK 0xff00 12936#define SQ_SOP2__SSRC1__SHIFT 0x8 12937#define SQ_SOP2__SDST_MASK 0x7f0000 12938#define SQ_SOP2__SDST__SHIFT 0x10 12939#define SQ_SOP2__OP_MASK 0x3f800000 12940#define SQ_SOP2__OP__SHIFT 0x17 12941#define SQ_SOP2__ENCODING_MASK 0xc0000000 12942#define SQ_SOP2__ENCODING__SHIFT 0x1e 12943#define SQ_VOP1__SRC0_MASK 0x1ff 12944#define SQ_VOP1__SRC0__SHIFT 0x0 12945#define SQ_VOP1__OP_MASK 0x1fe00 12946#define SQ_VOP1__OP__SHIFT 0x9 12947#define SQ_VOP1__VDST_MASK 0x1fe0000 12948#define SQ_VOP1__VDST__SHIFT 0x11 12949#define SQ_VOP1__ENCODING_MASK 0xfe000000 12950#define SQ_VOP1__ENCODING__SHIFT 0x19 12951#define SQ_MTBUF_1__VADDR_MASK 0xff 12952#define SQ_MTBUF_1__VADDR__SHIFT 0x0 12953#define SQ_MTBUF_1__VDATA_MASK 0xff00 12954#define SQ_MTBUF_1__VDATA__SHIFT 0x8 12955#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000 12956#define SQ_MTBUF_1__SRSRC__SHIFT 0x10 12957#define SQ_MTBUF_1__SLC_MASK 0x400000 12958#define SQ_MTBUF_1__SLC__SHIFT 0x16 12959#define SQ_MTBUF_1__TFE_MASK 0x800000 12960#define SQ_MTBUF_1__TFE__SHIFT 0x17 12961#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000 12962#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 12963#define SQ_EXP_1__VSRC0_MASK 0xff 12964#define SQ_EXP_1__VSRC0__SHIFT 0x0 12965#define SQ_EXP_1__VSRC1_MASK 0xff00 12966#define SQ_EXP_1__VSRC1__SHIFT 0x8 12967#define SQ_EXP_1__VSRC2_MASK 0xff0000 12968#define SQ_EXP_1__VSRC2__SHIFT 0x10 12969#define SQ_EXP_1__VSRC3_MASK 0xff000000 12970#define SQ_EXP_1__VSRC3__SHIFT 0x18 12971#define SQ_MUBUF_1__VADDR_MASK 0xff 12972#define SQ_MUBUF_1__VADDR__SHIFT 0x0 12973#define SQ_MUBUF_1__VDATA_MASK 0xff00 12974#define SQ_MUBUF_1__VDATA__SHIFT 0x8 12975#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000 12976#define SQ_MUBUF_1__SRSRC__SHIFT 0x10 12977#define SQ_MUBUF_1__SLC_MASK 0x400000 12978#define SQ_MUBUF_1__SLC__SHIFT 0x16 12979#define SQ_MUBUF_1__TFE_MASK 0x800000 12980#define SQ_MUBUF_1__TFE__SHIFT 0x17 12981#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000 12982#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 12983#define SQ_INST__ENCODING_MASK 0xffffffff 12984#define SQ_INST__ENCODING__SHIFT 0x0 12985#define SQ_EXP_0__EN_MASK 0xf 12986#define SQ_EXP_0__EN__SHIFT 0x0 12987#define SQ_EXP_0__TGT_MASK 0x3f0 12988#define SQ_EXP_0__TGT__SHIFT 0x4 12989#define SQ_EXP_0__COMPR_MASK 0x400 12990#define SQ_EXP_0__COMPR__SHIFT 0xa 12991#define SQ_EXP_0__DONE_MASK 0x800 12992#define SQ_EXP_0__DONE__SHIFT 0xb 12993#define SQ_EXP_0__VM_MASK 0x1000 12994#define SQ_EXP_0__VM__SHIFT 0xc 12995#define SQ_EXP_0__ENCODING_MASK 0xfc000000 12996#define SQ_EXP_0__ENCODING__SHIFT 0x1a 12997#define SQ_MUBUF_0__OFFSET_MASK 0xfff 12998#define SQ_MUBUF_0__OFFSET__SHIFT 0x0 12999#define SQ_MUBUF_0__OFFEN_MASK 0x1000 13000#define SQ_MUBUF_0__OFFEN__SHIFT 0xc 13001#define SQ_MUBUF_0__IDXEN_MASK 0x2000 13002#define SQ_MUBUF_0__IDXEN__SHIFT 0xd 13003#define SQ_MUBUF_0__GLC_MASK 0x4000 13004#define SQ_MUBUF_0__GLC__SHIFT 0xe 13005#define SQ_MUBUF_0__ADDR64_MASK 0x8000 13006#define SQ_MUBUF_0__ADDR64__SHIFT 0xf 13007#define SQ_MUBUF_0__LDS_MASK 0x10000 13008#define SQ_MUBUF_0__LDS__SHIFT 0x10 13009#define SQ_MUBUF_0__OP_MASK 0x1fc0000 13010#define SQ_MUBUF_0__OP__SHIFT 0x12 13011#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000 13012#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a 13013#define SQ_VOP3_0__VDST_MASK 0xff 13014#define SQ_VOP3_0__VDST__SHIFT 0x0 13015#define SQ_VOP3_0__ABS_MASK 0x700 13016#define SQ_VOP3_0__ABS__SHIFT 0x8 13017#define SQ_VOP3_0__CLAMP_MASK 0x800 13018#define SQ_VOP3_0__CLAMP__SHIFT 0xb 13019#define SQ_VOP3_0__OP_MASK 0x3fe0000 13020#define SQ_VOP3_0__OP__SHIFT 0x11 13021#define SQ_VOP3_0__ENCODING_MASK 0xfc000000 13022#define SQ_VOP3_0__ENCODING__SHIFT 0x1a 13023#define SQ_VOP2__SRC0_MASK 0x1ff 13024#define SQ_VOP2__SRC0__SHIFT 0x0 13025#define SQ_VOP2__VSRC1_MASK 0x1fe00 13026#define SQ_VOP2__VSRC1__SHIFT 0x9 13027#define SQ_VOP2__VDST_MASK 0x1fe0000 13028#define SQ_VOP2__VDST__SHIFT 0x11 13029#define SQ_VOP2__OP_MASK 0x7e000000 13030#define SQ_VOP2__OP__SHIFT 0x19 13031#define SQ_VOP2__ENCODING_MASK 0x80000000 13032#define SQ_VOP2__ENCODING__SHIFT 0x1f 13033#define SQ_MTBUF_0__OFFSET_MASK 0xfff 13034#define SQ_MTBUF_0__OFFSET__SHIFT 0x0 13035#define SQ_MTBUF_0__OFFEN_MASK 0x1000 13036#define SQ_MTBUF_0__OFFEN__SHIFT 0xc 13037#define SQ_MTBUF_0__IDXEN_MASK 0x2000 13038#define SQ_MTBUF_0__IDXEN__SHIFT 0xd 13039#define SQ_MTBUF_0__GLC_MASK 0x4000 13040#define SQ_MTBUF_0__GLC__SHIFT 0xe 13041#define SQ_MTBUF_0__ADDR64_MASK 0x8000 13042#define SQ_MTBUF_0__ADDR64__SHIFT 0xf 13043#define SQ_MTBUF_0__OP_MASK 0x70000 13044#define SQ_MTBUF_0__OP__SHIFT 0x10 13045#define SQ_MTBUF_0__DFMT_MASK 0x780000 13046#define SQ_MTBUF_0__DFMT__SHIFT 0x13 13047#define SQ_MTBUF_0__NFMT_MASK 0x3800000 13048#define SQ_MTBUF_0__NFMT__SHIFT 0x17 13049#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000 13050#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a 13051#define SQ_SOPP__SIMM16_MASK 0xffff 13052#define SQ_SOPP__SIMM16__SHIFT 0x0 13053#define SQ_SOPP__OP_MASK 0x7f0000 13054#define SQ_SOPP__OP__SHIFT 0x10 13055#define SQ_SOPP__ENCODING_MASK 0xff800000 13056#define SQ_SOPP__ENCODING__SHIFT 0x17 13057#define SQ_FLAT_0__GLC_MASK 0x10000 13058#define SQ_FLAT_0__GLC__SHIFT 0x10 13059#define SQ_FLAT_0__SLC_MASK 0x20000 13060#define SQ_FLAT_0__SLC__SHIFT 0x11 13061#define SQ_FLAT_0__OP_MASK 0x1fc0000 13062#define SQ_FLAT_0__OP__SHIFT 0x12 13063#define SQ_FLAT_0__ENCODING_MASK 0xfc000000 13064#define SQ_FLAT_0__ENCODING__SHIFT 0x1a 13065#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff 13066#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 13067#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00 13068#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 13069#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3fe0000 13070#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x11 13071#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000 13072#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a 13073#define SQ_MIMG_1__VADDR_MASK 0xff 13074#define SQ_MIMG_1__VADDR__SHIFT 0x0 13075#define SQ_MIMG_1__VDATA_MASK 0xff00 13076#define SQ_MIMG_1__VDATA__SHIFT 0x8 13077#define SQ_MIMG_1__SRSRC_MASK 0x1f0000 13078#define SQ_MIMG_1__SRSRC__SHIFT 0x10 13079#define SQ_MIMG_1__SSAMP_MASK 0x3e00000 13080#define SQ_MIMG_1__SSAMP__SHIFT 0x15 13081#define SQ_SMRD__OFFSET_MASK 0xff 13082#define SQ_SMRD__OFFSET__SHIFT 0x0 13083#define SQ_SMRD__IMM_MASK 0x100 13084#define SQ_SMRD__IMM__SHIFT 0x8 13085#define SQ_SMRD__SBASE_MASK 0x7e00 13086#define SQ_SMRD__SBASE__SHIFT 0x9 13087#define SQ_SMRD__SDST_MASK 0x3f8000 13088#define SQ_SMRD__SDST__SHIFT 0xf 13089#define SQ_SMRD__OP_MASK 0x7c00000 13090#define SQ_SMRD__OP__SHIFT 0x16 13091#define SQ_SMRD__ENCODING_MASK 0xf8000000 13092#define SQ_SMRD__ENCODING__SHIFT 0x1b 13093#define SQ_SOP1__SSRC0_MASK 0xff 13094#define SQ_SOP1__SSRC0__SHIFT 0x0 13095#define SQ_SOP1__OP_MASK 0xff00 13096#define SQ_SOP1__OP__SHIFT 0x8 13097#define SQ_SOP1__SDST_MASK 0x7f0000 13098#define SQ_SOP1__SDST__SHIFT 0x10 13099#define SQ_SOP1__ENCODING_MASK 0xff800000 13100#define SQ_SOP1__ENCODING__SHIFT 0x17 13101#define SQ_SOPC__SSRC0_MASK 0xff 13102#define SQ_SOPC__SSRC0__SHIFT 0x0 13103#define SQ_SOPC__SSRC1_MASK 0xff00 13104#define SQ_SOPC__SSRC1__SHIFT 0x8 13105#define SQ_SOPC__OP_MASK 0x7f0000 13106#define SQ_SOPC__OP__SHIFT 0x10 13107#define SQ_SOPC__ENCODING_MASK 0xff800000 13108#define SQ_SOPC__ENCODING__SHIFT 0x17 13109#define SQ_FLAT_1__ADDR_MASK 0xff 13110#define SQ_FLAT_1__ADDR__SHIFT 0x0 13111#define SQ_FLAT_1__DATA_MASK 0xff00 13112#define SQ_FLAT_1__DATA__SHIFT 0x8 13113#define SQ_FLAT_1__TFE_MASK 0x800000 13114#define SQ_FLAT_1__TFE__SHIFT 0x17 13115#define SQ_FLAT_1__VDST_MASK 0xff000000 13116#define SQ_FLAT_1__VDST__SHIFT 0x18 13117#define SQ_DS_1__ADDR_MASK 0xff 13118#define SQ_DS_1__ADDR__SHIFT 0x0 13119#define SQ_DS_1__DATA0_MASK 0xff00 13120#define SQ_DS_1__DATA0__SHIFT 0x8 13121#define SQ_DS_1__DATA1_MASK 0xff0000 13122#define SQ_DS_1__DATA1__SHIFT 0x10 13123#define SQ_DS_1__VDST_MASK 0xff000000 13124#define SQ_DS_1__VDST__SHIFT 0x18 13125#define SQ_VOP3_1__SRC0_MASK 0x1ff 13126#define SQ_VOP3_1__SRC0__SHIFT 0x0 13127#define SQ_VOP3_1__SRC1_MASK 0x3fe00 13128#define SQ_VOP3_1__SRC1__SHIFT 0x9 13129#define SQ_VOP3_1__SRC2_MASK 0x7fc0000 13130#define SQ_VOP3_1__SRC2__SHIFT 0x12 13131#define SQ_VOP3_1__OMOD_MASK 0x18000000 13132#define SQ_VOP3_1__OMOD__SHIFT 0x1b 13133#define SQ_VOP3_1__NEG_MASK 0xe0000000 13134#define SQ_VOP3_1__NEG__SHIFT 0x1d 13135#define SQ_MIMG_0__DMASK_MASK 0xf00 13136#define SQ_MIMG_0__DMASK__SHIFT 0x8 13137#define SQ_MIMG_0__UNORM_MASK 0x1000 13138#define SQ_MIMG_0__UNORM__SHIFT 0xc 13139#define SQ_MIMG_0__GLC_MASK 0x2000 13140#define SQ_MIMG_0__GLC__SHIFT 0xd 13141#define SQ_MIMG_0__DA_MASK 0x4000 13142#define SQ_MIMG_0__DA__SHIFT 0xe 13143#define SQ_MIMG_0__R128_MASK 0x8000 13144#define SQ_MIMG_0__R128__SHIFT 0xf 13145#define SQ_MIMG_0__TFE_MASK 0x10000 13146#define SQ_MIMG_0__TFE__SHIFT 0x10 13147#define SQ_MIMG_0__LWE_MASK 0x20000 13148#define SQ_MIMG_0__LWE__SHIFT 0x11 13149#define SQ_MIMG_0__OP_MASK 0x1fc0000 13150#define SQ_MIMG_0__OP__SHIFT 0x12 13151#define SQ_MIMG_0__SLC_MASK 0x2000000 13152#define SQ_MIMG_0__SLC__SHIFT 0x19 13153#define SQ_MIMG_0__ENCODING_MASK 0xfc000000 13154#define SQ_MIMG_0__ENCODING__SHIFT 0x1a 13155#define SQ_SOPK__SIMM16_MASK 0xffff 13156#define SQ_SOPK__SIMM16__SHIFT 0x0 13157#define SQ_SOPK__SDST_MASK 0x7f0000 13158#define SQ_SOPK__SDST__SHIFT 0x10 13159#define SQ_SOPK__OP_MASK 0xf800000 13160#define SQ_SOPK__OP__SHIFT 0x17 13161#define SQ_SOPK__ENCODING_MASK 0xf0000000 13162#define SQ_SOPK__ENCODING__SHIFT 0x1c 13163#define SQ_DS_0__OFFSET0_MASK 0xff 13164#define SQ_DS_0__OFFSET0__SHIFT 0x0 13165#define SQ_DS_0__OFFSET1_MASK 0xff00 13166#define SQ_DS_0__OFFSET1__SHIFT 0x8 13167#define SQ_DS_0__GDS_MASK 0x20000 13168#define SQ_DS_0__GDS__SHIFT 0x11 13169#define SQ_DS_0__OP_MASK 0x3fc0000 13170#define SQ_DS_0__OP__SHIFT 0x12 13171#define SQ_DS_0__ENCODING_MASK 0xfc000000 13172#define SQ_DS_0__ENCODING__SHIFT 0x1a 13173#define SQ_VOPC__SRC0_MASK 0x1ff 13174#define SQ_VOPC__SRC0__SHIFT 0x0 13175#define SQ_VOPC__VSRC1_MASK 0x1fe00 13176#define SQ_VOPC__VSRC1__SHIFT 0x9 13177#define SQ_VOPC__OP_MASK 0x1fe0000 13178#define SQ_VOPC__OP__SHIFT 0x11 13179#define SQ_VOPC__ENCODING_MASK 0xfe000000 13180#define SQ_VOPC__ENCODING__SHIFT 0x19 13181#define SQ_VINTRP__VSRC_MASK 0xff 13182#define SQ_VINTRP__VSRC__SHIFT 0x0 13183#define SQ_VINTRP__ATTRCHAN_MASK 0x300 13184#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 13185#define SQ_VINTRP__ATTR_MASK 0xfc00 13186#define SQ_VINTRP__ATTR__SHIFT 0xa 13187#define SQ_VINTRP__OP_MASK 0x30000 13188#define SQ_VINTRP__OP__SHIFT 0x10 13189#define SQ_VINTRP__VDST_MASK 0x3fc0000 13190#define SQ_VINTRP__VDST__SHIFT 0x12 13191#define SQ_VINTRP__ENCODING_MASK 0xfc000000 13192#define SQ_VINTRP__ENCODING__SHIFT 0x1a 13193#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf 13194#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 13195#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 13196#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 13197#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000 13198#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc 13199#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000 13200#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 13201#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000 13202#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 13203#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000 13204#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a 13205#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000 13206#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b 13207#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000 13208#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c 13209#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000 13210#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d 13211#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 13212#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 13213#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 13214#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 13215#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf 13216#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 13217#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0 13218#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 13219#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000 13220#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc 13221#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000 13222#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18 13223#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000 13224#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 13225#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000 13226#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a 13227#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000 13228#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b 13229#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000 13230#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c 13231#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000 13232#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d 13233#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000 13234#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e 13235#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000 13236#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f 13237#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf 13238#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 13239#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0 13240#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 13241#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000 13242#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc 13243#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000 13244#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18 13245#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000 13246#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 13247#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000 13248#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a 13249#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000 13250#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b 13251#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000 13252#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c 13253#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000 13254#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d 13255#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000 13256#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e 13257#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000 13258#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f 13259#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf 13260#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 13261#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0 13262#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 13263#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000 13264#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc 13265#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000 13266#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 13267#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000 13268#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 13269#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000 13270#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a 13271#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000 13272#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b 13273#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000 13274#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c 13275#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000 13276#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d 13277#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000 13278#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e 13279#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000 13280#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f 13281#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf 13282#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 13283#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0 13284#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 13285#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000 13286#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc 13287#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000 13288#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18 13289#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000 13290#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 13291#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000 13292#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a 13293#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000 13294#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b 13295#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000 13296#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c 13297#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000 13298#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d 13299#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000 13300#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e 13301#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000 13302#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f 13303#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1 13304#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0 13305#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2 13306#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1 13307#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4 13308#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2 13309#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8 13310#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3 13311#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10 13312#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4 13313#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20 13314#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5 13315#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40 13316#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6 13317#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80 13318#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7 13319#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100 13320#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8 13321#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200 13322#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9 13323#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400 13324#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa 13325#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800 13326#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb 13327#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000 13328#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc 13329#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000 13330#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd 13331#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000 13332#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe 13333#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000 13334#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf 13335#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000 13336#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10 13337#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000 13338#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11 13339#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000 13340#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12 13341#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000 13342#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13 13343#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000 13344#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14 13345#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000 13346#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15 13347#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000 13348#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16 13349#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000 13350#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17 13351#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000 13352#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18 13353#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000 13354#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19 13355#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000 13356#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a 13357#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000 13358#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b 13359#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000 13360#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c 13361#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000 13362#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d 13363#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000 13364#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e 13365#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000 13366#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f 13367#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1 13368#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0 13369#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2 13370#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1 13371#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4 13372#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2 13373#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8 13374#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3 13375#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10 13376#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4 13377#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20 13378#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5 13379#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40 13380#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6 13381#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80 13382#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7 13383#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100 13384#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8 13385#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200 13386#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9 13387#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400 13388#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa 13389#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800 13390#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb 13391#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000 13392#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc 13393#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000 13394#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd 13395#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000 13396#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe 13397#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000 13398#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf 13399#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000 13400#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10 13401#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000 13402#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11 13403#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000 13404#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12 13405#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000 13406#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13 13407#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000 13408#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14 13409#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000 13410#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15 13411#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000 13412#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16 13413#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000 13414#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17 13415#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000 13416#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18 13417#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000 13418#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19 13419#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000 13420#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a 13421#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000 13422#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b 13423#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000 13424#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c 13425#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000 13426#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d 13427#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000 13428#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e 13429#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000 13430#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f 13431#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1 13432#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0 13433#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2 13434#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1 13435#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4 13436#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2 13437#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8 13438#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3 13439#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10 13440#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4 13441#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20 13442#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5 13443#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40 13444#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6 13445#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80 13446#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7 13447#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100 13448#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8 13449#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200 13450#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9 13451#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400 13452#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa 13453#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800 13454#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb 13455#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000 13456#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc 13457#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000 13458#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd 13459#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000 13460#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe 13461#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000 13462#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf 13463#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000 13464#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10 13465#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000 13466#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11 13467#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000 13468#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12 13469#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000 13470#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13 13471#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000 13472#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14 13473#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000 13474#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15 13475#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000 13476#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16 13477#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000 13478#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17 13479#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000 13480#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18 13481#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000 13482#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19 13483#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000 13484#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a 13485#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000 13486#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b 13487#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000 13488#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c 13489#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000 13490#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d 13491#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000 13492#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e 13493#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000 13494#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f 13495#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1 13496#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0 13497#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2 13498#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1 13499#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4 13500#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2 13501#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8 13502#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3 13503#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10 13504#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4 13505#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20 13506#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5 13507#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40 13508#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6 13509#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80 13510#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7 13511#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100 13512#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8 13513#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200 13514#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9 13515#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400 13516#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa 13517#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800 13518#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb 13519#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000 13520#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc 13521#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000 13522#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd 13523#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000 13524#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe 13525#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000 13526#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf 13527#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000 13528#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10 13529#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000 13530#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11 13531#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000 13532#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12 13533#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000 13534#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13 13535#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000 13536#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14 13537#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000 13538#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15 13539#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000 13540#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16 13541#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000 13542#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17 13543#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000 13544#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18 13545#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000 13546#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19 13547#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f 13548#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 13549#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80 13550#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7 13551#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 13552#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 13553#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 13554#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 13555#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 13556#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 13557#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 13558#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 13559#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 13560#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 13561#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 13562#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 13563#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 13564#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 13565#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 13566#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 13567#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 13568#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 13569#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 13570#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 13571#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 13572#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 13573#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 13574#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 13575#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff 13576#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 13577#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 13578#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa 13579#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff 13580#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 13581#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 13582#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa 13583#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 13584#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 13585#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 13586#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 13587#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 13588#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 13589#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 13590#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 13591#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 13592#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 13593#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 13594#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 13595#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 13596#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 13597#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 13598#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 13599#define TCC_CTRL__CACHE_SIZE_MASK 0x3 13600#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 13601#define TCC_CTRL__RATE_MASK 0xc 13602#define TCC_CTRL__RATE__SHIFT 0x2 13603#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0 13604#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 13605#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000 13606#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc 13607#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000 13608#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 13609#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000 13610#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14 13611#define TCC_EDC_COUNTER__SEC_COUNT_MASK 0xf 13612#define TCC_EDC_COUNTER__SEC_COUNT__SHIFT 0x0 13613#define TCC_EDC_COUNTER__DED_COUNT_MASK 0xf0000 13614#define TCC_EDC_COUNTER__DED_COUNT__SHIFT 0x10 13615#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1 13616#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 13617#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2 13618#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 13619#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf 13620#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 13621#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 13622#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 13623#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 13624#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 13625#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 13626#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 13627#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 13628#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 13629#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 13630#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 13631#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 13632#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 13633#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 13634#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 13635#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 13636#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 13637#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 13638#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 13639#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf 13640#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 13641#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 13642#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 13643#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 13644#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 13645#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 13646#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 13647#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 13648#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 13649#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 13650#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 13651#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 13652#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 13653#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 13654#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 13655#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 13656#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 13657#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 13658#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 13659#define TCS_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf 13660#define TCS_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 13661#define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 13662#define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 13663#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 13664#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 13665#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 13666#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 13667#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 13668#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 13669#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 13670#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 13671#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 13672#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 13673#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 13674#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 13675#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 13676#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 13677#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 13678#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 13679#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 13680#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 13681#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 13682#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 13683#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 13684#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 13685#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 13686#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 13687#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 13688#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 13689#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 13690#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 13691#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 13692#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 13693#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 13694#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 13695#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 13696#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 13697#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 13698#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 13699#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 13700#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 13701#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 13702#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 13703#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 13704#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 13705#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 13706#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c 13707#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 13708#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 13709#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 13710#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 13711#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 13712#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 13713#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 13714#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c 13715#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 13716#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 13717#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 13718#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 13719#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 13720#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 13721#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 13722#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 13723#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 13724#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 13725#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 13726#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 13727#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 13728#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 13729#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 13730#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 13731#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 13732#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 13733#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 13734#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 13735#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 13736#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 13737#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 13738#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 13739#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 13740#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 13741#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 13742#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 13743#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf 13744#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 13745#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 13746#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 13747#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 13748#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 13749#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 13750#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 13751#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 13752#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 13753#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 13754#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 13755#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 13756#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 13757#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 13758#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 13759#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 13760#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 13761#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 13762#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 13763#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 13764#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 13765#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 13766#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 13767#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 13768#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 13769#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 13770#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 13771#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 13772#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c 13773#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 13774#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 13775#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 13776#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 13777#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 13778#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 13779#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 13780#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c 13781#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 13782#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 13783#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 13784#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 13785#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 13786#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 13787#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 13788#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 13789#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 13790#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 13791#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 13792#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 13793#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 13794#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 13795#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 13796#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 13797#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 13798#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 13799#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 13800#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 13801#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 13802#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 13803#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 13804#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 13805#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 13806#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 13807#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 13808#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 13809#define TCS_CTRL__RATE_MASK 0x3 13810#define TCS_CTRL__RATE__SHIFT 0x0 13811#define TCS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 13812#define TCS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 13813#define TCS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 13814#define TCS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 13815#define TCS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 13816#define TCS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 13817#define TCS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 13818#define TCS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 13819#define TCS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 13820#define TCS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 13821#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 13822#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 13823#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 13824#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 13825#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 13826#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 13827#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 13828#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c 13829#define TCS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 13830#define TCS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 13831#define TCS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 13832#define TCS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 13833#define TCS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 13834#define TCS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 13835#define TCS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 13836#define TCS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 13837#define TCS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 13838#define TCS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 13839#define TCS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 13840#define TCS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 13841#define TCS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 13842#define TCS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 13843#define TCS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 13844#define TCS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 13845#define TCS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 13846#define TCS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 13847#define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 13848#define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 13849#define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 13850#define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 13851#define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 13852#define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 13853#define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 13854#define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 13855#define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 13856#define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 13857#define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 13858#define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 13859#define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 13860#define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 13861#define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 13862#define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 13863#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff 13864#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 13865#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff 13866#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 13867#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3 13868#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 13869#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30 13870#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 13871#define TD_CNTL__PAD_STALL_EN_MASK 0x100 13872#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 13873#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600 13874#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 13875#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800 13876#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb 13877#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000 13878#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf 13879#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000 13880#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 13881#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000 13882#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 13883#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000 13884#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 13885#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000 13886#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 13887#define TD_STATUS__BUSY_MASK 0x80000000 13888#define TD_STATUS__BUSY__SHIFT 0x1f 13889#define TD_DEBUG_INDEX__INDEX_MASK 0x1f 13890#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0 13891#define TD_DEBUG_DATA__DATA_MASK 0xffffffff 13892#define TD_DEBUG_DATA__DATA__SHIFT 0x0 13893#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff 13894#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 13895#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 13896#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 13897#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 13898#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 13899#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 13900#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 13901#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 13902#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 13903#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff 13904#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 13905#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 13906#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 13907#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 13908#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 13909#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 13910#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 13911#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 13912#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 13913#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff 13914#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 13915#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 13916#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 13917#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 13918#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 13919#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 13920#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 13921#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 13922#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 13923#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 13924#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 13925#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 13926#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 13927#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 13928#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 13929#define TD_SCRATCH__SCRATCH_MASK 0xffffffff 13930#define TD_SCRATCH__SCRATCH__SHIFT 0x0 13931#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000 13932#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd 13933#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000 13934#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 13935#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000 13936#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 13937#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1 13938#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 13939#define TA_CNTL_AUX__RESERVED_MASK 0xe 13940#define TA_CNTL_AUX__RESERVED__SHIFT 0x1 13941#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000 13942#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 13943#define TA_RESERVED_010C__Unused_MASK 0xffffffff 13944#define TA_RESERVED_010C__Unused__SHIFT 0x0 13945#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff 13946#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 13947#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff 13948#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 13949#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000 13950#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc 13951#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000 13952#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd 13953#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000 13954#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe 13955#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000 13956#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 13957#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000 13958#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 13959#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000 13960#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 13961#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000 13962#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 13963#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000 13964#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 13965#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000 13966#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 13967#define TA_STATUS__IN_BUSY_MASK 0x1000000 13968#define TA_STATUS__IN_BUSY__SHIFT 0x18 13969#define TA_STATUS__FG_BUSY_MASK 0x2000000 13970#define TA_STATUS__FG_BUSY__SHIFT 0x19 13971#define TA_STATUS__LA_BUSY_MASK 0x4000000 13972#define TA_STATUS__LA_BUSY__SHIFT 0x1a 13973#define TA_STATUS__FL_BUSY_MASK 0x8000000 13974#define TA_STATUS__FL_BUSY__SHIFT 0x1b 13975#define TA_STATUS__TA_BUSY_MASK 0x10000000 13976#define TA_STATUS__TA_BUSY__SHIFT 0x1c 13977#define TA_STATUS__FA_BUSY_MASK 0x20000000 13978#define TA_STATUS__FA_BUSY__SHIFT 0x1d 13979#define TA_STATUS__AL_BUSY_MASK 0x40000000 13980#define TA_STATUS__AL_BUSY__SHIFT 0x1e 13981#define TA_STATUS__BUSY_MASK 0x80000000 13982#define TA_STATUS__BUSY__SHIFT 0x1f 13983#define TA_DEBUG_INDEX__INDEX_MASK 0x1f 13984#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0 13985#define TA_DEBUG_DATA__DATA_MASK 0xffffffff 13986#define TA_DEBUG_DATA__DATA__SHIFT 0x0 13987#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff 13988#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 13989#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 13990#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 13991#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 13992#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 13993#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 13994#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 13995#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 13996#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 13997#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff 13998#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 13999#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 14000#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 14001#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 14002#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 14003#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 14004#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 14005#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 14006#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 14007#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff 14008#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 14009#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 14010#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 14011#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 14012#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 14013#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 14014#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 14015#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 14016#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 14017#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 14018#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 14019#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 14020#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 14021#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 14022#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 14023#define TA_SCRATCH__SCRATCH_MASK 0xffffffff 14024#define TA_SCRATCH__SCRATCH__SHIFT 0x0 14025#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff 14026#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0 14027#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1 14028#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0 14029#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6 14030#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1 14031#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18 14032#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3 14033#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0 14034#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5 14035#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00 14036#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8 14037#define TCP_INVALIDATE__START_MASK 0x1 14038#define TCP_INVALIDATE__START__SHIFT 0x0 14039#define TCP_STATUS__TCP_BUSY_MASK 0x1 14040#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 14041#define TCP_CNTL__FORCE_HIT_MASK 0x1 14042#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 14043#define TCP_CNTL__FORCE_MISS_MASK 0x2 14044#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 14045#define TCP_CNTL__L1_SIZE_MASK 0xc 14046#define TCP_CNTL__L1_SIZE__SHIFT 0x2 14047#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10 14048#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 14049#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20 14050#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 14051#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000 14052#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf 14053#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000 14054#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 14055#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000 14056#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c 14057#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000 14058#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d 14059#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf 14060#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 14061#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0 14062#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 14063#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00 14064#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 14065#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000 14066#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc 14067#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000 14068#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 14069#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000 14070#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 14071#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000 14072#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 14073#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000 14074#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c 14075#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf 14076#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 14077#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0 14078#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 14079#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00 14080#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 14081#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000 14082#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc 14083#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000 14084#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 14085#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000 14086#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 14087#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000 14088#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 14089#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000 14090#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c 14091#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf 14092#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 14093#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30 14094#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 14095#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0 14096#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 14097#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200 14098#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 14099#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff 14100#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 14101#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000 14102#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 14103#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000 14104#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d 14105#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 14106#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 14107#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 14108#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 14109#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 14110#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 14111#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 14112#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 14113#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 14114#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 14115#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 14116#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 14117#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 14118#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 14119#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 14120#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 14121#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 14122#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 14123#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 14124#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 14125#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 14126#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 14127#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 14128#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 14129#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 14130#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 14131#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 14132#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 14133#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 14134#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 14135#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 14136#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 14137#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 14138#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 14139#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 14140#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c 14141#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 14142#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 14143#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 14144#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 14145#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 14146#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 14147#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 14148#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 14149#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 14150#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 14151#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 14152#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 14153#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 14154#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 14155#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 14156#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 14157#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 14158#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 14159#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 14160#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 14161#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 14162#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 14163#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 14164#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 14165#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 14166#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 14167#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 14168#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 14169#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7 14170#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 14171#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700 14172#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 14173#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000 14174#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 14175#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000 14176#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 14177#define TCP_EDC_COUNTER__SEC_COUNT_MASK 0xf 14178#define TCP_EDC_COUNTER__SEC_COUNT__SHIFT 0x0 14179#define TCP_EDC_COUNTER__DED_COUNT_MASK 0xf0000 14180#define TCP_EDC_COUNTER__DED_COUNT__SHIFT 0x10 14181#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3 14182#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 14183#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc 14184#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 14185#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30 14186#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 14187#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0 14188#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 14189#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300 14190#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 14191#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00 14192#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa 14193#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000 14194#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc 14195#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000 14196#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe 14197#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000 14198#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 14199#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000 14200#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 14201#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000 14202#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 14203#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000 14204#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 14205#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000 14206#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 14207#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000 14208#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a 14209#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000 14210#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c 14211#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 14212#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e 14213#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3 14214#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 14215#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc 14216#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 14217#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30 14218#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 14219#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0 14220#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 14221#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300 14222#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 14223#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00 14224#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa 14225#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000 14226#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc 14227#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000 14228#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe 14229#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000 14230#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 14231#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000 14232#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 14233#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000 14234#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 14235#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000 14236#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 14237#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000 14238#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 14239#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000 14240#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a 14241#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000 14242#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c 14243#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 14244#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e 14245#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1 14246#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 14247#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2 14248#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 14249#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4 14250#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 14251#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8 14252#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 14253#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10 14254#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 14255#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20 14256#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 14257#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40 14258#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 14259#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80 14260#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 14261#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100 14262#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 14263#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200 14264#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 14265#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400 14266#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa 14267#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800 14268#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb 14269#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000 14270#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc 14271#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000 14272#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd 14273#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000 14274#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe 14275#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000 14276#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf 14277#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000 14278#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 14279#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000 14280#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 14281#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000 14282#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 14283#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000 14284#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 14285#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000 14286#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 14287#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000 14288#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 14289#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000 14290#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 14291#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000 14292#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 14293#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000 14294#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 14295#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000 14296#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 14297#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000 14298#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a 14299#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000 14300#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b 14301#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000 14302#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c 14303#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000 14304#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d 14305#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000 14306#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e 14307#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000 14308#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f 14309#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3 14310#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 14311#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc 14312#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 14313#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30 14314#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 14315#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0 14316#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 14317#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300 14318#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 14319#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00 14320#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa 14321#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000 14322#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc 14323#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000 14324#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe 14325#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000 14326#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 14327#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000 14328#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 14329#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000 14330#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 14331#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000 14332#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 14333#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000 14334#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 14335#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000 14336#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a 14337#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000 14338#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c 14339#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 14340#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e 14341#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3 14342#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 14343#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc 14344#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 14345#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30 14346#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 14347#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0 14348#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 14349#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300 14350#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 14351#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00 14352#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa 14353#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000 14354#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc 14355#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000 14356#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe 14357#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000 14358#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 14359#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000 14360#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 14361#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000 14362#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 14363#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000 14364#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 14365#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000 14366#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 14367#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000 14368#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a 14369#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000 14370#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c 14371#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 14372#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e 14373#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3 14374#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 14375#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc 14376#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 14377#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30 14378#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 14379#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0 14380#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 14381#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300 14382#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 14383#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00 14384#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa 14385#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000 14386#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc 14387#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000 14388#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe 14389#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000 14390#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 14391#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000 14392#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 14393#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000 14394#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 14395#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000 14396#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 14397#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000 14398#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 14399#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000 14400#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a 14401#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000 14402#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c 14403#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000 14404#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e 14405#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3 14406#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 14407#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc 14408#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 14409#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30 14410#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 14411#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0 14412#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 14413#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300 14414#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 14415#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00 14416#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa 14417#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000 14418#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc 14419#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000 14420#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe 14421#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000 14422#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 14423#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000 14424#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 14425#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000 14426#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 14427#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000 14428#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 14429#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000 14430#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 14431#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000 14432#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a 14433#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000 14434#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c 14435#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000 14436#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e 14437#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3 14438#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 14439#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc 14440#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 14441#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30 14442#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 14443#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0 14444#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 14445#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300 14446#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 14447#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00 14448#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa 14449#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000 14450#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc 14451#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000 14452#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe 14453#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000 14454#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 14455#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000 14456#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 14457#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000 14458#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 14459#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000 14460#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 14461#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000 14462#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 14463#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000 14464#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a 14465#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000 14466#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c 14467#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000 14468#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e 14469#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf 14470#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 14471#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf 14472#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 14473#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff 14474#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 14475#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff 14476#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 14477#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff 14478#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 14479#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff 14480#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 14481#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0 14482#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 14483#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0 14484#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 14485#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0 14486#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 14487#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0 14488#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 14489#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff 14490#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 14491#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000 14492#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 14493#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000 14494#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d 14495#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000 14496#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f 14497#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff 14498#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 14499#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000 14500#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 14501#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000 14502#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d 14503#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000 14504#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f 14505#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff 14506#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 14507#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000 14508#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 14509#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000 14510#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d 14511#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000 14512#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f 14513#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff 14514#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 14515#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000 14516#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 14517#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000 14518#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d 14519#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000 14520#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f 14521#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf 14522#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 14523#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 14524#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 14525#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 14526#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 14527#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 14528#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 14529#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 14530#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 14531#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 14532#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 14533#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 14534#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 14535#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 14536#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 14537#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 14538#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 14539#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 14540#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 14541#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf 14542#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 14543#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 14544#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 14545#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 14546#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 14547#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 14548#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 14549#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 14550#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 14551#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 14552#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 14553#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 14554#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 14555#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 14556#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 14557#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 14558#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 14559#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 14560#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 14561#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf 14562#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0 14563#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 14564#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 14565#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 14566#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 14567#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 14568#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 14569#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 14570#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 14571#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 14572#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 14573#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 14574#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 14575#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 14576#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 14577#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 14578#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 14579#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 14580#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 14581#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf 14582#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 14583#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 14584#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 14585#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 14586#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 14587#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 14588#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 14589#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 14590#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 14591#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 14592#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 14593#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 14594#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 14595#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 14596#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 14597#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 14598#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 14599#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 14600#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 14601#define TCI_STATUS__TCI_BUSY_MASK 0x1 14602#define TCI_STATUS__TCI_BUSY__SHIFT 0x0 14603#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff 14604#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 14605#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000 14606#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 14607#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000 14608#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 14609#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1 14610#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 14611#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe 14612#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 14613#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6 14614#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 14615#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18 14616#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 14617#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60 14618#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 14619#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180 14620#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 14621#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1 14622#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 14623#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2 14624#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 14625#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4 14626#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 14627#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8 14628#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 14629#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10 14630#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 14631#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20 14632#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 14633#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40 14634#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 14635#define GDS_ENHANCE2__MISC_MASK 0xffff 14636#define GDS_ENHANCE2__MISC__SHIFT 0x0 14637#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000 14638#define GDS_ENHANCE2__UNUSED__SHIFT 0x10 14639#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 14640#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 14641#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 14642#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 14643#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4 14644#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 14645#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38 14646#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 14647#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0 14648#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 14649#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00 14650#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa 14651#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000 14652#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc 14653#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 14654#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 14655#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 14656#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 14657#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 14658#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 14659#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4 14660#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 14661#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8 14662#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 14663#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10 14664#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 14665#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00 14666#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 14667#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 14668#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 14669#define GDS_SECDED_CNT__DED_MASK 0xffff 14670#define GDS_SECDED_CNT__DED__SHIFT 0x0 14671#define GDS_SECDED_CNT__SEC_MASK 0xffff0000 14672#define GDS_SECDED_CNT__SEC__SHIFT 0x10 14673#define GDS_GRBM_SECDED_CNT__DED_MASK 0xffff 14674#define GDS_GRBM_SECDED_CNT__DED__SHIFT 0x0 14675#define GDS_GRBM_SECDED_CNT__SEC_MASK 0xffff0000 14676#define GDS_GRBM_SECDED_CNT__SEC__SHIFT 0x10 14677#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1 14678#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 14679#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2 14680#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 14681#define GDS_OA_DED__ME0_CS_DED_MASK 0x4 14682#define GDS_OA_DED__ME0_CS_DED__SHIFT 0x2 14683#define GDS_OA_DED__UNUSED0_MASK 0x8 14684#define GDS_OA_DED__UNUSED0__SHIFT 0x3 14685#define GDS_OA_DED__ME1_PIPE0_DED_MASK 0x10 14686#define GDS_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 14687#define GDS_OA_DED__ME1_PIPE1_DED_MASK 0x20 14688#define GDS_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 14689#define GDS_OA_DED__ME1_PIPE2_DED_MASK 0x40 14690#define GDS_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 14691#define GDS_OA_DED__ME1_PIPE3_DED_MASK 0x80 14692#define GDS_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 14693#define GDS_OA_DED__ME2_PIPE0_DED_MASK 0x100 14694#define GDS_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 14695#define GDS_OA_DED__ME2_PIPE1_DED_MASK 0x200 14696#define GDS_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 14697#define GDS_OA_DED__ME2_PIPE2_DED_MASK 0x400 14698#define GDS_OA_DED__ME2_PIPE2_DED__SHIFT 0xa 14699#define GDS_OA_DED__ME2_PIPE3_DED_MASK 0x800 14700#define GDS_OA_DED__ME2_PIPE3_DED__SHIFT 0xb 14701#define GDS_OA_DED__UNUSED1_MASK 0xfffff000 14702#define GDS_OA_DED__UNUSED1__SHIFT 0xc 14703#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f 14704#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0 14705#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0 14706#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5 14707#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff 14708#define GDS_DEBUG_DATA__DATA__SHIFT 0x0 14709#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf 14710#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 14711#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 14712#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 14713#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 14714#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 14715#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 14716#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 14717#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 14718#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 14719#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 14720#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 14721#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 14722#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 14723#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 14724#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 14725#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 14726#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 14727#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 14728#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 14729#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff 14730#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 14731#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff 14732#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 14733#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff 14734#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 14735#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff 14736#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 14737#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff 14738#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 14739#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff 14740#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 14741#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff 14742#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 14743#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff 14744#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 14745#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff 14746#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 14747#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff 14748#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 14749#define GDS_ATOM_CNTL__AINC_MASK 0x3f 14750#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 14751#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0 14752#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 14753#define GDS_ATOM_CNTL__DMODE_MASK 0x100 14754#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 14755#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffe00 14756#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0x9 14757#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1 14758#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 14759#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe 14760#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 14761#define GDS_ATOM_BASE__BASE_MASK 0xffff 14762#define GDS_ATOM_BASE__BASE__SHIFT 0x0 14763#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000 14764#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 14765#define GDS_ATOM_SIZE__SIZE_MASK 0xffff 14766#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 14767#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000 14768#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 14769#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff 14770#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 14771#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00 14772#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 14773#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff 14774#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 14775#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00 14776#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 14777#define GDS_ATOM_DST__DST_MASK 0xffffffff 14778#define GDS_ATOM_DST__DST__SHIFT 0x0 14779#define GDS_ATOM_OP__OP_MASK 0xff 14780#define GDS_ATOM_OP__OP__SHIFT 0x0 14781#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00 14782#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 14783#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff 14784#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 14785#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff 14786#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 14787#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff 14788#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 14789#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff 14790#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 14791#define GDS_ATOM_READ0__DATA_MASK 0xffffffff 14792#define GDS_ATOM_READ0__DATA__SHIFT 0x0 14793#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff 14794#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 14795#define GDS_ATOM_READ1__DATA_MASK 0xffffffff 14796#define GDS_ATOM_READ1__DATA__SHIFT 0x0 14797#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff 14798#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 14799#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f 14800#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 14801#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0 14802#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 14803#define GDS_GWS_RESOURCE__FLAG_MASK 0x1 14804#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 14805#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe 14806#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 14807#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000 14808#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd 14809#define GDS_GWS_RESOURCE__DED_MASK 0x4000 14810#define GDS_GWS_RESOURCE__DED__SHIFT 0xe 14811#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000 14812#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf 14813#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000 14814#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 14815#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000 14816#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b 14817#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000 14818#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c 14819#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000 14820#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d 14821#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff 14822#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 14823#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000 14824#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 14825#define GDS_OA_CNTL__INDEX_MASK 0xf 14826#define GDS_OA_CNTL__INDEX__SHIFT 0x0 14827#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0 14828#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 14829#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff 14830#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 14831#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff 14832#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 14833#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0xf0000 14834#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x10 14835#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf00000 14836#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x14 14837#define GDS_OA_ADDRESS__UNUSED_MASK 0x3f000000 14838#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x18 14839#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000 14840#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e 14841#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000 14842#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f 14843#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff 14844#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 14845#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000 14846#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f 14847#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff 14848#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 14849#define GDS_DEBUG_REG0__spare1_MASK 0x3f 14850#define GDS_DEBUG_REG0__spare1__SHIFT 0x0 14851#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40 14852#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6 14853#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80 14854#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7 14855#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000 14856#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc 14857#define GDS_DEBUG_REG0__cstate_MASK 0x1e000 14858#define GDS_DEBUG_REG0__cstate__SHIFT 0xd 14859#define GDS_DEBUG_REG0__buff_write_MASK 0x20000 14860#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11 14861#define GDS_DEBUG_REG0__flush_request_MASK 0x40000 14862#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12 14863#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000 14864#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13 14865#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000 14866#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14 14867#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000 14868#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15 14869#define GDS_DEBUG_REG0__spare_MASK 0xffc00000 14870#define GDS_DEBUG_REG0__spare__SHIFT 0x16 14871#define GDS_DEBUG_REG1__tag_hit_MASK 0x1 14872#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0 14873#define GDS_DEBUG_REG1__tag_miss_MASK 0x2 14874#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1 14875#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc 14876#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2 14877#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000 14878#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11 14879#define GDS_DEBUG_REG1__data_ready_MASK 0x40000 14880#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12 14881#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000 14882#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13 14883#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000 14884#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14 14885#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000 14886#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15 14887#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000 14888#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16 14889#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000 14890#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17 14891#define GDS_DEBUG_REG1__spare_MASK 0xff000000 14892#define GDS_DEBUG_REG1__spare__SHIFT 0x18 14893#define GDS_DEBUG_REG2__ds_full_MASK 0x1 14894#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0 14895#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2 14896#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1 14897#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4 14898#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2 14899#define GDS_DEBUG_REG2__cmd_write_MASK 0x8 14900#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3 14901#define GDS_DEBUG_REG2__app_sel_MASK 0xf0 14902#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4 14903#define GDS_DEBUG_REG2__req_MASK 0x7fff00 14904#define GDS_DEBUG_REG2__req__SHIFT 0x8 14905#define GDS_DEBUG_REG2__spare_MASK 0xff800000 14906#define GDS_DEBUG_REG2__spare__SHIFT 0x17 14907#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff 14908#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0 14909#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800 14910#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb 14911#define GDS_DEBUG_REG3__spare_MASK 0xffff8000 14912#define GDS_DEBUG_REG3__spare__SHIFT 0xf 14913#define GDS_DEBUG_REG4__gws_busy_MASK 0x1 14914#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0 14915#define GDS_DEBUG_REG4__gws_req_MASK 0x2 14916#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1 14917#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4 14918#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2 14919#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8 14920#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3 14921#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200 14922#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9 14923#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400 14924#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa 14925#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800 14926#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb 14927#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000 14928#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc 14929#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000 14930#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd 14931#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000 14932#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe 14933#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000 14934#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf 14935#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000 14936#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10 14937#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000 14938#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11 14939#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000 14940#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12 14941#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000 14942#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13 14943#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000 14944#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14 14945#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000 14946#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15 14947#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000 14948#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16 14949#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000 14950#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17 14951#define GDS_DEBUG_REG4__spare_MASK 0xff000000 14952#define GDS_DEBUG_REG4__spare__SHIFT 0x18 14953#define GDS_DEBUG_REG5__write_dis_MASK 0x1 14954#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0 14955#define GDS_DEBUG_REG5__dec_error_MASK 0x2 14956#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1 14957#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4 14958#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2 14959#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8 14960#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3 14961#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10 14962#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4 14963#define GDS_DEBUG_REG5__spare_MASK 0xe0 14964#define GDS_DEBUG_REG5__spare__SHIFT 0x5 14965#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00 14966#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8 14967#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000 14968#define GDS_DEBUG_REG5__spare1__SHIFT 0x16 14969#define GDS_DEBUG_REG6__oa_busy_MASK 0x1 14970#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0 14971#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e 14972#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1 14973#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0 14974#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5 14975#define GDS_DEBUG_REG6__spare_MASK 0xffe00000 14976#define GDS_DEBUG_REG6__spare__SHIFT 0x15 14977#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 14978#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 14979#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 14980#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 14981#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 14982#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 14983#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 14984#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 14985#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 14986#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 14987#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 14988#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 14989#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 14990#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 14991#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 14992#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 14993#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 14994#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 14995#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 14996#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 14997#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 14998#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 14999#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 15000#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 15001#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 15002#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 15003#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 15004#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 15005#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 15006#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 15007#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 15008#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 15009#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 15010#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 15011#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 15012#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 15013#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 15014#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 15015#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 15016#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 15017#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff 15018#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 15019#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 15020#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa 15021#define GDS_VMID0_BASE__BASE_MASK 0xffff 15022#define GDS_VMID0_BASE__BASE__SHIFT 0x0 15023#define GDS_VMID1_BASE__BASE_MASK 0xffff 15024#define GDS_VMID1_BASE__BASE__SHIFT 0x0 15025#define GDS_VMID2_BASE__BASE_MASK 0xffff 15026#define GDS_VMID2_BASE__BASE__SHIFT 0x0 15027#define GDS_VMID3_BASE__BASE_MASK 0xffff 15028#define GDS_VMID3_BASE__BASE__SHIFT 0x0 15029#define GDS_VMID4_BASE__BASE_MASK 0xffff 15030#define GDS_VMID4_BASE__BASE__SHIFT 0x0 15031#define GDS_VMID5_BASE__BASE_MASK 0xffff 15032#define GDS_VMID5_BASE__BASE__SHIFT 0x0 15033#define GDS_VMID6_BASE__BASE_MASK 0xffff 15034#define GDS_VMID6_BASE__BASE__SHIFT 0x0 15035#define GDS_VMID7_BASE__BASE_MASK 0xffff 15036#define GDS_VMID7_BASE__BASE__SHIFT 0x0 15037#define GDS_VMID8_BASE__BASE_MASK 0xffff 15038#define GDS_VMID8_BASE__BASE__SHIFT 0x0 15039#define GDS_VMID9_BASE__BASE_MASK 0xffff 15040#define GDS_VMID9_BASE__BASE__SHIFT 0x0 15041#define GDS_VMID10_BASE__BASE_MASK 0xffff 15042#define GDS_VMID10_BASE__BASE__SHIFT 0x0 15043#define GDS_VMID11_BASE__BASE_MASK 0xffff 15044#define GDS_VMID11_BASE__BASE__SHIFT 0x0 15045#define GDS_VMID12_BASE__BASE_MASK 0xffff 15046#define GDS_VMID12_BASE__BASE__SHIFT 0x0 15047#define GDS_VMID13_BASE__BASE_MASK 0xffff 15048#define GDS_VMID13_BASE__BASE__SHIFT 0x0 15049#define GDS_VMID14_BASE__BASE_MASK 0xffff 15050#define GDS_VMID14_BASE__BASE__SHIFT 0x0 15051#define GDS_VMID15_BASE__BASE_MASK 0xffff 15052#define GDS_VMID15_BASE__BASE__SHIFT 0x0 15053#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff 15054#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 15055#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff 15056#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 15057#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff 15058#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 15059#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff 15060#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 15061#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff 15062#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 15063#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff 15064#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 15065#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff 15066#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 15067#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff 15068#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 15069#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff 15070#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 15071#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff 15072#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 15073#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff 15074#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 15075#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff 15076#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 15077#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff 15078#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 15079#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff 15080#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 15081#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff 15082#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 15083#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff 15084#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 15085#define GDS_GWS_VMID0__BASE_MASK 0x3f 15086#define GDS_GWS_VMID0__BASE__SHIFT 0x0 15087#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000 15088#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 15089#define GDS_GWS_VMID1__BASE_MASK 0x3f 15090#define GDS_GWS_VMID1__BASE__SHIFT 0x0 15091#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000 15092#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 15093#define GDS_GWS_VMID2__BASE_MASK 0x3f 15094#define GDS_GWS_VMID2__BASE__SHIFT 0x0 15095#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000 15096#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 15097#define GDS_GWS_VMID3__BASE_MASK 0x3f 15098#define GDS_GWS_VMID3__BASE__SHIFT 0x0 15099#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000 15100#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 15101#define GDS_GWS_VMID4__BASE_MASK 0x3f 15102#define GDS_GWS_VMID4__BASE__SHIFT 0x0 15103#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000 15104#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 15105#define GDS_GWS_VMID5__BASE_MASK 0x3f 15106#define GDS_GWS_VMID5__BASE__SHIFT 0x0 15107#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000 15108#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 15109#define GDS_GWS_VMID6__BASE_MASK 0x3f 15110#define GDS_GWS_VMID6__BASE__SHIFT 0x0 15111#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000 15112#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 15113#define GDS_GWS_VMID7__BASE_MASK 0x3f 15114#define GDS_GWS_VMID7__BASE__SHIFT 0x0 15115#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000 15116#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 15117#define GDS_GWS_VMID8__BASE_MASK 0x3f 15118#define GDS_GWS_VMID8__BASE__SHIFT 0x0 15119#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000 15120#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 15121#define GDS_GWS_VMID9__BASE_MASK 0x3f 15122#define GDS_GWS_VMID9__BASE__SHIFT 0x0 15123#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000 15124#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 15125#define GDS_GWS_VMID10__BASE_MASK 0x3f 15126#define GDS_GWS_VMID10__BASE__SHIFT 0x0 15127#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000 15128#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 15129#define GDS_GWS_VMID11__BASE_MASK 0x3f 15130#define GDS_GWS_VMID11__BASE__SHIFT 0x0 15131#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000 15132#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 15133#define GDS_GWS_VMID12__BASE_MASK 0x3f 15134#define GDS_GWS_VMID12__BASE__SHIFT 0x0 15135#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000 15136#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 15137#define GDS_GWS_VMID13__BASE_MASK 0x3f 15138#define GDS_GWS_VMID13__BASE__SHIFT 0x0 15139#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000 15140#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 15141#define GDS_GWS_VMID14__BASE_MASK 0x3f 15142#define GDS_GWS_VMID14__BASE__SHIFT 0x0 15143#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000 15144#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 15145#define GDS_GWS_VMID15__BASE_MASK 0x3f 15146#define GDS_GWS_VMID15__BASE__SHIFT 0x0 15147#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000 15148#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 15149#define GDS_OA_VMID0__MASK_MASK 0xffff 15150#define GDS_OA_VMID0__MASK__SHIFT 0x0 15151#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000 15152#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 15153#define GDS_OA_VMID1__MASK_MASK 0xffff 15154#define GDS_OA_VMID1__MASK__SHIFT 0x0 15155#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000 15156#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 15157#define GDS_OA_VMID2__MASK_MASK 0xffff 15158#define GDS_OA_VMID2__MASK__SHIFT 0x0 15159#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000 15160#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 15161#define GDS_OA_VMID3__MASK_MASK 0xffff 15162#define GDS_OA_VMID3__MASK__SHIFT 0x0 15163#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000 15164#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 15165#define GDS_OA_VMID4__MASK_MASK 0xffff 15166#define GDS_OA_VMID4__MASK__SHIFT 0x0 15167#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000 15168#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 15169#define GDS_OA_VMID5__MASK_MASK 0xffff 15170#define GDS_OA_VMID5__MASK__SHIFT 0x0 15171#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000 15172#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 15173#define GDS_OA_VMID6__MASK_MASK 0xffff 15174#define GDS_OA_VMID6__MASK__SHIFT 0x0 15175#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000 15176#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 15177#define GDS_OA_VMID7__MASK_MASK 0xffff 15178#define GDS_OA_VMID7__MASK__SHIFT 0x0 15179#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000 15180#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 15181#define GDS_OA_VMID8__MASK_MASK 0xffff 15182#define GDS_OA_VMID8__MASK__SHIFT 0x0 15183#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000 15184#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 15185#define GDS_OA_VMID9__MASK_MASK 0xffff 15186#define GDS_OA_VMID9__MASK__SHIFT 0x0 15187#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000 15188#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 15189#define GDS_OA_VMID10__MASK_MASK 0xffff 15190#define GDS_OA_VMID10__MASK__SHIFT 0x0 15191#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000 15192#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 15193#define GDS_OA_VMID11__MASK_MASK 0xffff 15194#define GDS_OA_VMID11__MASK__SHIFT 0x0 15195#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000 15196#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 15197#define GDS_OA_VMID12__MASK_MASK 0xffff 15198#define GDS_OA_VMID12__MASK__SHIFT 0x0 15199#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000 15200#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 15201#define GDS_OA_VMID13__MASK_MASK 0xffff 15202#define GDS_OA_VMID13__MASK__SHIFT 0x0 15203#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000 15204#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 15205#define GDS_OA_VMID14__MASK_MASK 0xffff 15206#define GDS_OA_VMID14__MASK__SHIFT 0x0 15207#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000 15208#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 15209#define GDS_OA_VMID15__MASK_MASK 0xffff 15210#define GDS_OA_VMID15__MASK__SHIFT 0x0 15211#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000 15212#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 15213#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1 15214#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 15215#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2 15216#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 15217#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4 15218#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 15219#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8 15220#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 15221#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10 15222#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 15223#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20 15224#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 15225#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40 15226#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 15227#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80 15228#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 15229#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100 15230#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 15231#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200 15232#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 15233#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400 15234#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa 15235#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800 15236#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb 15237#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000 15238#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc 15239#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000 15240#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd 15241#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000 15242#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe 15243#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000 15244#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf 15245#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000 15246#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 15247#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000 15248#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 15249#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000 15250#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 15251#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000 15252#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 15253#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000 15254#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 15255#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000 15256#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 15257#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000 15258#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 15259#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000 15260#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 15261#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000 15262#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 15263#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000 15264#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 15265#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000 15266#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a 15267#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000 15268#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b 15269#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000 15270#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c 15271#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000 15272#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d 15273#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000 15274#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e 15275#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000 15276#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f 15277#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1 15278#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 15279#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2 15280#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 15281#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4 15282#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 15283#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8 15284#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 15285#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10 15286#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 15287#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20 15288#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 15289#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40 15290#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 15291#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80 15292#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 15293#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100 15294#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 15295#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200 15296#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 15297#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400 15298#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa 15299#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800 15300#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb 15301#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000 15302#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc 15303#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000 15304#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd 15305#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000 15306#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe 15307#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000 15308#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf 15309#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000 15310#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 15311#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000 15312#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 15313#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000 15314#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 15315#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000 15316#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 15317#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000 15318#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 15319#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000 15320#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 15321#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000 15322#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 15323#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000 15324#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 15325#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000 15326#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 15327#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000 15328#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 15329#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000 15330#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a 15331#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000 15332#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b 15333#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000 15334#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c 15335#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000 15336#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d 15337#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000 15338#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e 15339#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000 15340#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f 15341#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1 15342#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 15343#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00 15344#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 15345#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff 15346#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 15347#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1 15348#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 15349#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2 15350#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 15351#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4 15352#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 15353#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8 15354#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3 15355#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10 15356#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 15357#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20 15358#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 15359#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40 15360#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 15361#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80 15362#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 15363#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100 15364#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 15365#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200 15366#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 15367#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400 15368#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa 15369#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800 15370#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb 15371#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000 15372#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc 15373#define GDS_OA_RESET__RESET_MASK 0x1 15374#define GDS_OA_RESET__RESET__SHIFT 0x0 15375#define GDS_OA_RESET__PIPE_ID_MASK 0xff00 15376#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 15377#define GDS_ENHANCE__MISC_MASK 0xffff 15378#define GDS_ENHANCE__MISC__SHIFT 0x0 15379#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000 15380#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 15381#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000 15382#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 15383#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000 15384#define GDS_ENHANCE__UNUSED__SHIFT 0x12 15385#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff 15386#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 15387#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00 15388#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 15389#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000 15390#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc 15391#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xffff0000 15392#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x10 15393#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7 15394#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 15395#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7 15396#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 15397#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3 15398#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 15399#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc 15400#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 15401#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10 15402#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 15403#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20 15404#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 15405#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40 15406#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 15407#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f 15408#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 15409#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000 15410#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12 15411#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000 15412#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b 15413#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff 15414#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 15415#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff 15416#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 15417#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff 15418#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 15419#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3 15420#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 15421#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc 15422#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 15423#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30 15424#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 15425#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0xc0 15426#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 15427#define VGT_DMA_INDEX_TYPE__ATC_MASK 0x100 15428#define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x8 15429#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200 15430#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 15431#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400 15432#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa 15433#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff 15434#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 15435#define IA_ENHANCE__MISC_MASK 0xffffffff 15436#define IA_ENHANCE__MISC__SHIFT 0x0 15437#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff 15438#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 15439#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff 15440#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 15441#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f 15442#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 15443#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff 15444#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 15445#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000 15446#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 15447#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000 15448#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 15449#define VGT_IMMED_DATA__DATA_MASK 0xffffffff 15450#define VGT_IMMED_DATA__DATA__SHIFT 0x0 15451#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3 15452#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 15453#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff 15454#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 15455#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff 15456#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 15457#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f 15458#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 15459#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1 15460#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 15461#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2 15462#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 15463#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff 15464#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 15465#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1 15466#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 15467#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1 15468#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 15469#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff 15470#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 15471#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff 15472#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 15473#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff 15474#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 15475#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff 15476#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 15477#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff 15478#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 15479#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff 15480#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 15481#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f 15482#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 15483#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff 15484#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 15485#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1 15486#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 15487#define VGT_ENHANCE__MISC_MASK 0xffffffff 15488#define VGT_ENHANCE__MISC__SHIFT 0x0 15489#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7 15490#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 15491#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3 15492#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 15493#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff 15494#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 15495#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff 15496#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 15497#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff 15498#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 15499#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f 15500#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 15501#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000 15502#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe 15503#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000 15504#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf 15505#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000 15506#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 15507#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf 15508#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 15509#define VGT_GROUP_DECR__DECR_MASK 0xf 15510#define VGT_GROUP_DECR__DECR__SHIFT 0x0 15511#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1 15512#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 15513#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2 15514#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 15515#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4 15516#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 15517#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8 15518#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 15519#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00 15520#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 15521#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000 15522#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 15523#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1 15524#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 15525#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2 15526#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 15527#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4 15528#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 15529#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8 15530#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 15531#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00 15532#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 15533#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000 15534#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 15535#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf 15536#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 15537#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0 15538#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 15539#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00 15540#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 15541#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000 15542#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc 15543#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000 15544#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 15545#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000 15546#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 15547#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000 15548#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 15549#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000 15550#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c 15551#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf 15552#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 15553#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0 15554#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 15555#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00 15556#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 15557#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000 15558#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc 15559#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000 15560#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 15561#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000 15562#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 15563#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000 15564#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 15565#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000 15566#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c 15567#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff 15568#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 15569#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff 15570#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 15571#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f 15572#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 15573#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f 15574#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 15575#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7 15576#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 15577#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000 15578#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 15579#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x6 15580#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x1 15581#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 15582#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 15583#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x10 15584#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x4 15585#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 15586#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 15587#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x6 15588#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x1 15589#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 15590#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 15591#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x10 15592#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x4 15593#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 15594#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 15595#define VGT_GS_MODE__MODE_MASK 0x7 15596#define VGT_GS_MODE__MODE__SHIFT 0x0 15597#define VGT_GS_MODE__RESERVED_0_MASK 0x8 15598#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 15599#define VGT_GS_MODE__CUT_MODE_MASK 0x30 15600#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 15601#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0 15602#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 15603#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800 15604#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb 15605#define VGT_GS_MODE__RESERVED_2_MASK 0x1000 15606#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc 15607#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000 15608#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd 15609#define VGT_GS_MODE__COMPUTE_MODE_MASK 0x4000 15610#define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0xe 15611#define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x8000 15612#define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0xf 15613#define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x10000 15614#define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x10 15615#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000 15616#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 15617#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000 15618#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 15619#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000 15620#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 15621#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000 15622#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 15623#define VGT_GS_MODE__ONCHIP_MASK 0x600000 15624#define VGT_GS_MODE__ONCHIP__SHIFT 0x15 15625#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff 15626#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 15627#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800 15628#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb 15629#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f 15630#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 15631#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00 15632#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 15633#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000 15634#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 15635#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000 15636#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 15637#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000 15638#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f 15639#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3 15640#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 15641#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20 15642#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 15643#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0 15644#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 15645#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200 15646#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 15647#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800 15648#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb 15649#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000 15650#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc 15651#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000 15652#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd 15653#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000 15654#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 15655#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1 15656#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 15657#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2 15658#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 15659#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4 15660#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 15661#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff 15662#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 15663#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700 15664#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 15665#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800 15666#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb 15667#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000 15668#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe 15669#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000 15670#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 15671#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f 15672#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 15673#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80 15674#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 15675#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00 15676#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 15677#define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0x400000 15678#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x16 15679#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff 15680#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 15681#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff 15682#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 15683#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf 15684#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 15685#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f 15686#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 15687#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3 15688#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 15689#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1 15690#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 15691#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2 15692#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 15693#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4 15694#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 15695#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8 15696#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 15697#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10 15698#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 15699#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1 15700#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 15701#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2 15702#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 15703#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4 15704#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 15705#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8 15706#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 15707#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70 15708#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 15709#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00 15710#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 15711#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000 15712#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f 15713#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff 15714#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 15715#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff 15716#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 15717#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff 15718#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 15719#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff 15720#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 15721#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff 15722#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 15723#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff 15724#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 15725#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff 15726#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 15727#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff 15728#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 15729#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff 15730#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 15731#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff 15732#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 15733#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff 15734#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 15735#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff 15736#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 15737#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf 15738#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 15739#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0 15740#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 15741#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00 15742#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 15743#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000 15744#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc 15745#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff 15746#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 15747#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff 15748#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 15749#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff 15750#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 15751#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff 15752#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 15753#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff 15754#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 15755#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff 15756#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 15757#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff 15758#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 15759#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff 15760#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 15761#define IA_VMID_OVERRIDE__ENABLE_MASK 0x1 15762#define IA_VMID_OVERRIDE__ENABLE__SHIFT 0x0 15763#define IA_VMID_OVERRIDE__VMID_MASK 0x1e 15764#define IA_VMID_OVERRIDE__VMID__SHIFT 0x1 15765#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3 15766#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 15767#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4 15768#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 15769#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18 15770#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 15771#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20 15772#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 15773#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0 15774#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 15775#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100 15776#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8 15777#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff 15778#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 15779#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff 15780#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 15781#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 15782#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 15783#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000 15784#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe 15785#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 15786#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 15787#define VGT_TF_PARAM__TYPE_MASK 0x3 15788#define VGT_TF_PARAM__TYPE__SHIFT 0x0 15789#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c 15790#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 15791#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0 15792#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 15793#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100 15794#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 15795#define VGT_TF_PARAM__DEPRECATED_MASK 0x200 15796#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 15797#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00 15798#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa 15799#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000 15800#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe 15801#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x18000 15802#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf 15803#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff 15804#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 15805#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1 15806#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 15807#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e 15808#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 15809#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80 15810#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 15811#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff 15812#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 15813#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600 15814#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 15815#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff 15816#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 15817#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1 15818#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 15819#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc 15820#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 15821#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff 15822#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 15823#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000 15824#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 15825#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000 15826#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 15827#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000 15828#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 15829#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000 15830#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 15831#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000 15832#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 15833#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff 15834#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 15835#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff 15836#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0 15837#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff 15838#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 15839#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff 15840#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 15841#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff 15842#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 15843#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff 15844#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 15845#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff 15846#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 15847#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff 15848#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 15849#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff 15850#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 15851#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff 15852#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 15853#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff 15854#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 15855#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff 15856#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 15857#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1 15858#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 15859#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2 15860#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 15861#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4 15862#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 15863#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8 15864#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 15865#define WD_ENHANCE__MISC_MASK 0xffffffff 15866#define WD_ENHANCE__MISC__SHIFT 0x0 15867#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff 15868#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 15869#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000 15870#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd 15871#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000 15872#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 15873#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1 15874#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0 15875#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf 15876#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 15877#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 15878#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 15879#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 15880#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 15881#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 15882#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 15883#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 15884#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a 15885#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 15886#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 15887#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 15888#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 15889#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000 15890#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d 15891#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 15892#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 15893#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 15894#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 15895#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf 15896#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 15897#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 15898#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 15899#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 15900#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 15901#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 15902#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 15903#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 15904#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a 15905#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 15906#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 15907#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 15908#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 15909#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 15910#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 15911#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 15912#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 15913#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 15914#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 15915#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf 15916#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 15917#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 15918#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 15919#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 15920#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 15921#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 15922#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 15923#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 15924#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a 15925#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 15926#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 15927#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000 15928#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c 15929#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000 15930#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d 15931#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000 15932#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e 15933#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 15934#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 15935#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f 15936#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0 15937#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40 15938#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6 15939#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff 15940#define VGT_DEBUG_DATA__DATA__SHIFT 0x0 15941#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f 15942#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0 15943#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40 15944#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6 15945#define IA_DEBUG_DATA__DATA_MASK 0xffffffff 15946#define IA_DEBUG_DATA__DATA__SHIFT 0x0 15947#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1 15948#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 15949#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2 15950#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 15951#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4 15952#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 15953#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8 15954#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 15955#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10 15956#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 15957#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20 15958#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 15959#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40 15960#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 15961#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80 15962#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 15963#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100 15964#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 15965#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200 15966#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 15967#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f 15968#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0 15969#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40 15970#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6 15971#define WD_DEBUG_DATA__DATA_MASK 0xffffffff 15972#define WD_DEBUG_DATA__DATA__SHIFT 0x0 15973#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 15974#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 15975#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 15976#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 15977#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 15978#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 15979#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 15980#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 15981#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1 15982#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0 15983#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2 15984#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1 15985#define WD_DEBUG_REG0__wd_busy_MASK 0x4 15986#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2 15987#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8 15988#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3 15989#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10 15990#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4 15991#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20 15992#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5 15993#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40 15994#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6 15995#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80 15996#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7 15997#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100 15998#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8 15999#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200 16000#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9 16001#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400 16002#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa 16003#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800 16004#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb 16005#define WD_DEBUG_REG0__SPARE2_MASK 0x1000 16006#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc 16007#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000 16008#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd 16009#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000 16010#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe 16011#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000 16012#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf 16013#define WD_DEBUG_REG0__SPARE3_MASK 0x10000 16014#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10 16015#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000 16016#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11 16017#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000 16018#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12 16019#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000 16020#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13 16021#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000 16022#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14 16023#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000 16024#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15 16025#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000 16026#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16 16027#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000 16028#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17 16029#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 16030#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 16031#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000 16032#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19 16033#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000 16034#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a 16035#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000 16036#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b 16037#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 16038#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c 16039#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000 16040#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d 16041#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000 16042#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e 16043#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000 16044#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f 16045#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1 16046#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0 16047#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2 16048#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1 16049#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4 16050#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2 16051#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8 16052#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3 16053#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10 16054#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4 16055#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20 16056#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5 16057#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40 16058#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6 16059#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80 16060#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7 16061#define WD_DEBUG_REG1__SPARE0_MASK 0x100 16062#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8 16063#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200 16064#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9 16065#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400 16066#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa 16067#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800 16068#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb 16069#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000 16070#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc 16071#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000 16072#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11 16073#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000 16074#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14 16075#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000 16076#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a 16077#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000 16078#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b 16079#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000 16080#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c 16081#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000 16082#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d 16083#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000 16084#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e 16085#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000 16086#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f 16087#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1 16088#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0 16089#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2 16090#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1 16091#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4 16092#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2 16093#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8 16094#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3 16095#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10 16096#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4 16097#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20 16098#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5 16099#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40 16100#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6 16101#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80 16102#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7 16103#define WD_DEBUG_REG2__SPARE0_MASK 0x100 16104#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8 16105#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200 16106#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9 16107#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400 16108#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa 16109#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800 16110#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb 16111#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000 16112#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc 16113#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000 16114#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11 16115#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000 16116#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14 16117#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000 16118#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a 16119#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000 16120#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b 16121#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000 16122#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c 16123#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000 16124#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d 16125#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000 16126#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e 16127#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000 16128#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f 16129#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1 16130#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0 16131#define WD_DEBUG_REG3__SPARE0_MASK 0x2 16132#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1 16133#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4 16134#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2 16135#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8 16136#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3 16137#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10 16138#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4 16139#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20 16140#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5 16141#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40 16142#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6 16143#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80 16144#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7 16145#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300 16146#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8 16147#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400 16148#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa 16149#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800 16150#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb 16151#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000 16152#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc 16153#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000 16154#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd 16155#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000 16156#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe 16157#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000 16158#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf 16159#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000 16160#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10 16161#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000 16162#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11 16163#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000 16164#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12 16165#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000 16166#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13 16167#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000 16168#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14 16169#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000 16170#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15 16171#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000 16172#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16 16173#define WD_DEBUG_REG3__SPARE1_MASK 0x800000 16174#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17 16175#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000 16176#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18 16177#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000 16178#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19 16179#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000 16180#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a 16181#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000 16182#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b 16183#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000 16184#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c 16185#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000 16186#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d 16187#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000 16188#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e 16189#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000 16190#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f 16191#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1 16192#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0 16193#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2 16194#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1 16195#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4 16196#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2 16197#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8 16198#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3 16199#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10 16200#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4 16201#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20 16202#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5 16203#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40 16204#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6 16205#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80 16206#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7 16207#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100 16208#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8 16209#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200 16210#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9 16211#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400 16212#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa 16213#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800 16214#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb 16215#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000 16216#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc 16217#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000 16218#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd 16219#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000 16220#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe 16221#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000 16222#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10 16223#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000 16224#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13 16225#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000 16226#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14 16227#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000 16228#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15 16229#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000 16230#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16 16231#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000 16232#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17 16233#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000 16234#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18 16235#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000 16236#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19 16237#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000 16238#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a 16239#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000 16240#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b 16241#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000 16242#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c 16243#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000 16244#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d 16245#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000 16246#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e 16247#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000 16248#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f 16249#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1 16250#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0 16251#define WD_DEBUG_REG5__SPARE0_MASK 0x2 16252#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1 16253#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4 16254#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2 16255#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8 16256#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3 16257#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10 16258#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4 16259#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20 16260#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5 16261#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40 16262#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6 16263#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80 16264#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7 16265#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300 16266#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8 16267#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400 16268#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa 16269#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800 16270#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb 16271#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000 16272#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc 16273#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000 16274#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd 16275#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000 16276#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe 16277#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000 16278#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf 16279#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000 16280#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10 16281#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000 16282#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11 16283#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000 16284#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12 16285#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000 16286#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13 16287#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000 16288#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14 16289#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000 16290#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15 16291#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000 16292#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16 16293#define WD_DEBUG_REG5__SPARE1_MASK 0x800000 16294#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17 16295#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000 16296#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18 16297#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000 16298#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19 16299#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000 16300#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a 16301#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000 16302#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b 16303#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000 16304#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c 16305#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000 16306#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d 16307#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000 16308#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e 16309#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000 16310#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f 16311#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1 16312#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0 16313#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2 16314#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1 16315#define IA_DEBUG_REG0__ia_busy_MASK 0x4 16316#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2 16317#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8 16318#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3 16319#define IA_DEBUG_REG0__SPARE0_MASK 0x10 16320#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4 16321#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20 16322#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5 16323#define IA_DEBUG_REG0__dma_busy_MASK 0x40 16324#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6 16325#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80 16326#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7 16327#define IA_DEBUG_REG0__grp_busy_MASK 0x100 16328#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8 16329#define IA_DEBUG_REG0__SPARE1_MASK 0x200 16330#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9 16331#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400 16332#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa 16333#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800 16334#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb 16335#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000 16336#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc 16337#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000 16338#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd 16339#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000 16340#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe 16341#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 16342#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 16343#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000 16344#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19 16345#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000 16346#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a 16347#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000 16348#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b 16349#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 16350#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c 16351#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 16352#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d 16353#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000 16354#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e 16355#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000 16356#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f 16357#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1 16358#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0 16359#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2 16360#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1 16361#define IA_DEBUG_REG1__start_new_packet_MASK 0x4 16362#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2 16363#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8 16364#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3 16365#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10 16366#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4 16367#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60 16368#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5 16369#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80 16370#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7 16371#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100 16372#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8 16373#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200 16374#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9 16375#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400 16376#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa 16377#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800 16378#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb 16379#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000 16380#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc 16381#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000 16382#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd 16383#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000 16384#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe 16385#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000 16386#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf 16387#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000 16388#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10 16389#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000 16390#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11 16391#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000 16392#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12 16393#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000 16394#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13 16395#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000 16396#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14 16397#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000 16398#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15 16399#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000 16400#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16 16401#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000 16402#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17 16403#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000 16404#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18 16405#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000 16406#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19 16407#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000 16408#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a 16409#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000 16410#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b 16411#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000 16412#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c 16413#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000 16414#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d 16415#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000 16416#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e 16417#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000 16418#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f 16419#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1 16420#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0 16421#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2 16422#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1 16423#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4 16424#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2 16425#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8 16426#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3 16427#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10 16428#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4 16429#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60 16430#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5 16431#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80 16432#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7 16433#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100 16434#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8 16435#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200 16436#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9 16437#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400 16438#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa 16439#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800 16440#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb 16441#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000 16442#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc 16443#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000 16444#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd 16445#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000 16446#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe 16447#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000 16448#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf 16449#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000 16450#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10 16451#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000 16452#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11 16453#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000 16454#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12 16455#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000 16456#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13 16457#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000 16458#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14 16459#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000 16460#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15 16461#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000 16462#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16 16463#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000 16464#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17 16465#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000 16466#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18 16467#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000 16468#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19 16469#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000 16470#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a 16471#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000 16472#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b 16473#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000 16474#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c 16475#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000 16476#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d 16477#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000 16478#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e 16479#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000 16480#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f 16481#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1 16482#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0 16483#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2 16484#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1 16485#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4 16486#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2 16487#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8 16488#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3 16489#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10 16490#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4 16491#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20 16492#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5 16493#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40 16494#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6 16495#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80 16496#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7 16497#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100 16498#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8 16499#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200 16500#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9 16501#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400 16502#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa 16503#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800 16504#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb 16505#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000 16506#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc 16507#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000 16508#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd 16509#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000 16510#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe 16511#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000 16512#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf 16513#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000 16514#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10 16515#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000 16516#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11 16517#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000 16518#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12 16519#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000 16520#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13 16521#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000 16522#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14 16523#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000 16524#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15 16525#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000 16526#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16 16527#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000 16528#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17 16529#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000 16530#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18 16531#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000 16532#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a 16533#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000 16534#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b 16535#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000 16536#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c 16537#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000 16538#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d 16539#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000 16540#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e 16541#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000 16542#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f 16543#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1 16544#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0 16545#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2 16546#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1 16547#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4 16548#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2 16549#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8 16550#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3 16551#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10 16552#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4 16553#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20 16554#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5 16555#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40 16556#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6 16557#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80 16558#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7 16559#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100 16560#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8 16561#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200 16562#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9 16563#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400 16564#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa 16565#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800 16566#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb 16567#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000 16568#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc 16569#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000 16570#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd 16571#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000 16572#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe 16573#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000 16574#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf 16575#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000 16576#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10 16577#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000 16578#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11 16579#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000 16580#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14 16581#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000 16582#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15 16583#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000 16584#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18 16585#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000 16586#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19 16587#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000 16588#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a 16589#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000 16590#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c 16591#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000 16592#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d 16593#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000 16594#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e 16595#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000 16596#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f 16597#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff 16598#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0 16599#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000 16600#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10 16601#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000 16602#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e 16603#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000 16604#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f 16605#define IA_DEBUG_REG6__current_shift_q_MASK 0xf 16606#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0 16607#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0 16608#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4 16609#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00 16610#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8 16611#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000 16612#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd 16613#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000 16614#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe 16615#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000 16616#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf 16617#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000 16618#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10 16619#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000 16620#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15 16621#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000 16622#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16 16623#define IA_DEBUG_REG6__extract_group_MASK 0x800000 16624#define IA_DEBUG_REG6__extract_group__SHIFT 0x17 16625#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000 16626#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18 16627#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf 16628#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0 16629#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0 16630#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4 16631#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00 16632#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8 16633#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000 16634#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc 16635#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000 16636#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10 16637#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000 16638#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14 16639#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000 16640#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17 16641#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000 16642#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18 16643#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000 16644#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19 16645#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000 16646#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a 16647#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000 16648#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b 16649#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000 16650#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c 16651#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000 16652#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d 16653#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000 16654#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e 16655#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000 16656#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f 16657#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f 16658#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0 16659#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20 16660#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5 16661#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40 16662#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6 16663#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80 16664#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7 16665#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100 16666#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8 16667#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200 16668#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9 16669#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400 16670#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa 16671#define IA_DEBUG_REG8__grp_continued_MASK 0x800 16672#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb 16673#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000 16674#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc 16675#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000 16676#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf 16677#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000 16678#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15 16679#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000 16680#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18 16681#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000 16682#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19 16683#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000 16684#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a 16685#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000 16686#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b 16687#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000 16688#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c 16689#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1 16690#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0 16691#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2 16692#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1 16693#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4 16694#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2 16695#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8 16696#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3 16697#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10 16698#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4 16699#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20 16700#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5 16701#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40 16702#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6 16703#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80 16704#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7 16705#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100 16706#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8 16707#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200 16708#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9 16709#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400 16710#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa 16711#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800 16712#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb 16713#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000 16714#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc 16715#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000 16716#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd 16717#define IA_DEBUG_REG9__SPARE0_MASK 0x4000 16718#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe 16719#define IA_DEBUG_REG9__SPARE1_MASK 0x8000 16720#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf 16721#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000 16722#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10 16723#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000 16724#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11 16725#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000 16726#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12 16727#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000 16728#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13 16729#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000 16730#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14 16731#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1 16732#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0 16733#define VGT_DEBUG_REG0__SPARE9_MASK 0x2 16734#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1 16735#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4 16736#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2 16737#define VGT_DEBUG_REG0__SPARE8_MASK 0x8 16738#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3 16739#define VGT_DEBUG_REG0__SPARE7_MASK 0x10 16740#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4 16741#define VGT_DEBUG_REG0__SPARE6_MASK 0x20 16742#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5 16743#define VGT_DEBUG_REG0__SPARE5_MASK 0x40 16744#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6 16745#define VGT_DEBUG_REG0__SPARE4_MASK 0x80 16746#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7 16747#define VGT_DEBUG_REG0__pi_busy_MASK 0x100 16748#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8 16749#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200 16750#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9 16751#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400 16752#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa 16753#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800 16754#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb 16755#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000 16756#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc 16757#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000 16758#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd 16759#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000 16760#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe 16761#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000 16762#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf 16763#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000 16764#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10 16765#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000 16766#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11 16767#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000 16768#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12 16769#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000 16770#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13 16771#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000 16772#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14 16773#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000 16774#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15 16775#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000 16776#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16 16777#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000 16778#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17 16779#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 16780#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 16781#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000 16782#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19 16783#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000 16784#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a 16785#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000 16786#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b 16787#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000 16788#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c 16789#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 16790#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d 16791#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000 16792#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e 16793#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000 16794#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f 16795#define VGT_DEBUG_REG1__SPARE9_MASK 0x1 16796#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0 16797#define VGT_DEBUG_REG1__SPARE8_MASK 0x2 16798#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1 16799#define VGT_DEBUG_REG1__SPARE7_MASK 0x4 16800#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2 16801#define VGT_DEBUG_REG1__SPARE6_MASK 0x8 16802#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3 16803#define VGT_DEBUG_REG1__SPARE5_MASK 0x10 16804#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4 16805#define VGT_DEBUG_REG1__SPARE4_MASK 0x20 16806#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5 16807#define VGT_DEBUG_REG1__SPARE3_MASK 0x40 16808#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6 16809#define VGT_DEBUG_REG1__SPARE2_MASK 0x80 16810#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7 16811#define VGT_DEBUG_REG1__SPARE1_MASK 0x100 16812#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8 16813#define VGT_DEBUG_REG1__SPARE0_MASK 0x200 16814#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9 16815#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400 16816#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa 16817#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800 16818#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb 16819#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000 16820#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc 16821#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000 16822#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd 16823#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000 16824#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe 16825#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000 16826#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf 16827#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000 16828#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10 16829#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000 16830#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11 16831#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000 16832#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12 16833#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000 16834#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13 16835#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000 16836#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14 16837#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000 16838#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15 16839#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000 16840#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16 16841#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000 16842#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17 16843#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000 16844#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18 16845#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000 16846#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19 16847#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000 16848#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a 16849#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000 16850#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b 16851#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000 16852#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c 16853#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000 16854#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d 16855#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000 16856#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e 16857#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000 16858#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f 16859#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1 16860#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0 16861#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2 16862#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1 16863#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4 16864#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2 16865#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8 16866#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3 16867#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10 16868#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4 16869#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20 16870#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5 16871#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40 16872#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6 16873#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80 16874#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7 16875#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100 16876#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8 16877#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200 16878#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9 16879#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400 16880#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa 16881#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800 16882#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb 16883#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000 16884#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc 16885#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000 16886#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd 16887#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000 16888#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe 16889#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000 16890#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf 16891#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000 16892#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10 16893#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000 16894#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11 16895#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000 16896#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12 16897#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000 16898#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13 16899#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000 16900#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14 16901#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000 16902#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15 16903#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000 16904#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16 16905#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000 16906#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17 16907#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000 16908#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18 16909#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000 16910#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19 16911#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000 16912#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a 16913#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000 16914#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b 16915#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000 16916#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c 16917#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000 16918#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d 16919#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff 16920#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0 16921#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000 16922#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc 16923#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000 16924#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12 16925#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000 16926#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a 16927#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff 16928#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0 16929#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00 16930#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8 16931#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000 16932#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18 16933#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000 16934#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d 16935#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000 16936#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e 16937#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000 16938#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f 16939#define VGT_DEBUG_REG5__SPARE4_MASK 0x7 16940#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0 16941#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8 16942#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3 16943#define VGT_DEBUG_REG5__SPARE3_MASK 0x700 16944#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8 16945#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800 16946#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb 16947#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000 16948#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10 16949#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000 16950#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13 16951#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000 16952#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18 16953#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000 16954#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b 16955#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff 16956#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0 16957#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000 16958#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10 16959#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1 16960#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0 16961#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2 16962#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1 16963#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4 16964#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2 16965#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8 16966#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3 16967#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10 16968#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4 16969#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0 16970#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5 16971#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000 16972#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10 16973#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1 16974#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0 16975#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2 16976#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1 16977#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4 16978#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2 16979#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8 16980#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3 16981#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10 16982#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4 16983#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20 16984#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5 16985#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40 16986#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6 16987#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80 16988#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7 16989#define VGT_DEBUG_REG8__valid_r2_MASK 0x100 16990#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8 16991#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200 16992#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9 16993#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400 16994#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa 16995#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800 16996#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb 16997#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000 16998#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc 16999#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000 17000#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd 17001#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000 17002#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe 17003#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000 17004#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf 17005#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000 17006#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10 17007#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000 17008#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11 17009#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000 17010#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12 17011#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000 17012#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13 17013#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000 17014#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14 17015#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000 17016#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15 17017#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000 17018#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16 17019#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000 17020#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17 17021#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000 17022#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18 17023#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000 17024#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19 17025#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000 17026#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a 17027#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000 17028#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b 17029#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000 17030#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c 17031#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000 17032#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d 17033#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000 17034#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e 17035#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000 17036#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f 17037#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3 17038#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0 17039#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4 17040#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2 17041#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8 17042#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3 17043#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10 17044#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4 17045#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20 17046#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5 17047#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40 17048#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6 17049#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80 17050#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7 17051#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100 17052#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8 17053#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200 17054#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9 17055#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400 17056#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa 17057#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800 17058#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb 17059#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000 17060#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12 17061#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000 17062#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13 17063#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000 17064#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16 17065#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000 17066#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17 17067#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000 17068#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18 17069#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000 17070#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19 17071#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000 17072#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a 17073#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000 17074#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b 17075#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000 17076#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c 17077#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000 17078#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d 17079#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000 17080#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e 17081#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000 17082#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f 17083#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f 17084#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0 17085#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20 17086#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5 17087#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40 17088#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6 17089#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180 17090#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7 17091#define VGT_DEBUG_REG10__SPARE2_MASK 0x600 17092#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9 17093#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800 17094#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb 17095#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000 17096#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc 17097#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000 17098#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd 17099#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000 17100#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17 17101#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1 17102#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0 17103#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2 17104#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1 17105#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4 17106#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2 17107#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8 17108#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3 17109#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10 17110#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4 17111#define VGT_DEBUG_REG11__SPARE1_MASK 0x20 17112#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5 17113#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40 17114#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6 17115#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80 17116#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7 17117#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100 17118#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8 17119#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200 17120#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9 17121#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400 17122#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa 17123#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800 17124#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb 17125#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000 17126#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc 17127#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000 17128#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd 17129#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000 17130#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe 17131#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000 17132#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf 17133#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000 17134#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10 17135#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000 17136#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11 17137#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000 17138#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12 17139#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000 17140#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13 17141#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000 17142#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14 17143#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000 17144#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15 17145#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000 17146#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16 17147#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000 17148#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17 17149#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000 17150#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18 17151#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000 17152#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19 17153#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000 17154#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a 17155#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000 17156#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b 17157#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000 17158#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c 17159#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000 17160#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d 17161#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000 17162#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e 17163#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000 17164#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f 17165#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7 17166#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0 17167#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38 17168#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3 17169#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0 17170#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6 17171#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00 17172#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9 17173#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000 17174#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc 17175#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000 17176#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf 17177#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000 17178#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12 17179#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000 17180#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15 17181#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000 17182#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18 17183#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000 17184#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b 17185#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000 17186#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e 17187#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000 17188#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f 17189#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7 17190#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0 17191#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38 17192#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3 17193#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0 17194#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6 17195#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00 17196#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9 17197#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000 17198#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc 17199#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000 17200#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf 17201#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000 17202#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12 17203#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000 17204#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16 17205#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000 17206#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17 17207#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000 17208#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18 17209#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000 17210#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19 17211#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000 17212#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a 17213#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000 17214#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b 17215#define VGT_DEBUG_REG14__SPARE3_MASK 0xf 17216#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0 17217#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10 17218#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4 17219#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20 17220#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5 17221#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40 17222#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6 17223#define VGT_DEBUG_REG14__SPARE8_MASK 0x180 17224#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7 17225#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200 17226#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9 17227#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400 17228#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa 17229#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800 17230#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb 17231#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000 17232#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc 17233#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000 17234#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15 17235#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000 17236#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16 17237#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000 17238#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19 17239#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000 17240#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a 17241#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000 17242#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b 17243#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000 17244#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c 17245#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000 17246#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d 17247#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000 17248#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e 17249#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000 17250#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f 17251#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1 17252#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0 17253#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2 17254#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1 17255#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4 17256#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2 17257#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8 17258#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3 17259#define VGT_DEBUG_REG15__counters_full_MASK 0x10 17260#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4 17261#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0 17262#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5 17263#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00 17264#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa 17265#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000 17266#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf 17267#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000 17268#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14 17269#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000 17270#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a 17271#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000 17272#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c 17273#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000 17274#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d 17275#define VGT_DEBUG_REG16__gog_busy_MASK 0x1 17276#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0 17277#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe 17278#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1 17279#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10 17280#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4 17281#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20 17282#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5 17283#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40 17284#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6 17285#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80 17286#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7 17287#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100 17288#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8 17289#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200 17290#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9 17291#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400 17292#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa 17293#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800 17294#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb 17295#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000 17296#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc 17297#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000 17298#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd 17299#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000 17300#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe 17301#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000 17302#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf 17303#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000 17304#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10 17305#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000 17306#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11 17307#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000 17308#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12 17309#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000 17310#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13 17311#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000 17312#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14 17313#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000 17314#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15 17315#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000 17316#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16 17317#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000 17318#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17 17319#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000 17320#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18 17321#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000 17322#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19 17323#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000 17324#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c 17325#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000 17326#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d 17327#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000 17328#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e 17329#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000 17330#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f 17331#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f 17332#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0 17333#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0 17334#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6 17335#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000 17336#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc 17337#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000 17338#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12 17339#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1 17340#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0 17341#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2 17342#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1 17343#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4 17344#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2 17345#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8 17346#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3 17347#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10 17348#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4 17349#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20 17350#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5 17351#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40 17352#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6 17353#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80 17354#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7 17355#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700 17356#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8 17357#define VGT_DEBUG_REG18__valid_indices_MASK 0x800 17358#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb 17359#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000 17360#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc 17361#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000 17362#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd 17363#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000 17364#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe 17365#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000 17366#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf 17367#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000 17368#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10 17369#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000 17370#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11 17371#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000 17372#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12 17373#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000 17374#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13 17375#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000 17376#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14 17377#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000 17378#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15 17379#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000 17380#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16 17381#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000 17382#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17 17383#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000 17384#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18 17385#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000 17386#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b 17387#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000 17388#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c 17389#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000 17390#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d 17391#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1 17392#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0 17393#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2 17394#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1 17395#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4 17396#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2 17397#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8 17398#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3 17399#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10 17400#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4 17401#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20 17402#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5 17403#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40 17404#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6 17405#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80 17406#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7 17407#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100 17408#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8 17409#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200 17410#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9 17411#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400 17412#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa 17413#define VGT_DEBUG_REG19__hold_prim_MASK 0x800 17414#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb 17415#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000 17416#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc 17417#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000 17418#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd 17419#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000 17420#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe 17421#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000 17422#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf 17423#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000 17424#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10 17425#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000 17426#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11 17427#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000 17428#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12 17429#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000 17430#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13 17431#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000 17432#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14 17433#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000 17434#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a 17435#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000 17436#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b 17437#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000 17438#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c 17439#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000 17440#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e 17441#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000 17442#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f 17443#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff 17444#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0 17445#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000 17446#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10 17447#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000 17448#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11 17449#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000 17450#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12 17451#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000 17452#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16 17453#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000 17454#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d 17455#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000 17456#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e 17457#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000 17458#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f 17459#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1 17460#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0 17461#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2 17462#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1 17463#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4 17464#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2 17465#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8 17466#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3 17467#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10 17468#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4 17469#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20 17470#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5 17471#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40 17472#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6 17473#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80 17474#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7 17475#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100 17476#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8 17477#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200 17478#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9 17479#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400 17480#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa 17481#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800 17482#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb 17483#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000 17484#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc 17485#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000 17486#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd 17487#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000 17488#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe 17489#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000 17490#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf 17491#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000 17492#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10 17493#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000 17494#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11 17495#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000 17496#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14 17497#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000 17498#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15 17499#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000 17500#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16 17501#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000 17502#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17 17503#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000 17504#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18 17505#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000 17506#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19 17507#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000 17508#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a 17509#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000 17510#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b 17511#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000 17512#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c 17513#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000 17514#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d 17515#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000 17516#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e 17517#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000 17518#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f 17519#define VGT_DEBUG_REG22__cm_state16_MASK 0x3 17520#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0 17521#define VGT_DEBUG_REG22__cm_state17_MASK 0xc 17522#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2 17523#define VGT_DEBUG_REG22__cm_state18_MASK 0x30 17524#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4 17525#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0 17526#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6 17527#define VGT_DEBUG_REG22__cm_state20_MASK 0x300 17528#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8 17529#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00 17530#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa 17531#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000 17532#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc 17533#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000 17534#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe 17535#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000 17536#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10 17537#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000 17538#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12 17539#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000 17540#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14 17541#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000 17542#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16 17543#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000 17544#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18 17545#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000 17546#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a 17547#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000 17548#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c 17549#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000 17550#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e 17551#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1 17552#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0 17553#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2 17554#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1 17555#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4 17556#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2 17557#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8 17558#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3 17559#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10 17560#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4 17561#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20 17562#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5 17563#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40 17564#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6 17565#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80 17566#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7 17567#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100 17568#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8 17569#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200 17570#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9 17571#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400 17572#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa 17573#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800 17574#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb 17575#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000 17576#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc 17577#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000 17578#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd 17579#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000 17580#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe 17581#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000 17582#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf 17583#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000 17584#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11 17585#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000 17586#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15 17587#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000 17588#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18 17589#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff 17590#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0 17591#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000 17592#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18 17593#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000 17594#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a 17595#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff 17596#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0 17597#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000 17598#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a 17599#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000 17600#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e 17601#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000 17602#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f 17603#define VGT_DEBUG_REG26__cm_state0_MASK 0x3 17604#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0 17605#define VGT_DEBUG_REG26__cm_state1_MASK 0xc 17606#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2 17607#define VGT_DEBUG_REG26__cm_state2_MASK 0x30 17608#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4 17609#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0 17610#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6 17611#define VGT_DEBUG_REG26__cm_state4_MASK 0x300 17612#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8 17613#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00 17614#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa 17615#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000 17616#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc 17617#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000 17618#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe 17619#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000 17620#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10 17621#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000 17622#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12 17623#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000 17624#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14 17625#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000 17626#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16 17627#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000 17628#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18 17629#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000 17630#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a 17631#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000 17632#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c 17633#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000 17634#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e 17635#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1 17636#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0 17637#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2 17638#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1 17639#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4 17640#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2 17641#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8 17642#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3 17643#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10 17644#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4 17645#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20 17646#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5 17647#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40 17648#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6 17649#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80 17650#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7 17651#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300 17652#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8 17653#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400 17654#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa 17655#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800 17656#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb 17657#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000 17658#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc 17659#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000 17660#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe 17661#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000 17662#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf 17663#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000 17664#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10 17665#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000 17666#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11 17667#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000 17668#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12 17669#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000 17670#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13 17671#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000 17672#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14 17673#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000 17674#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f 17675#define VGT_DEBUG_REG28__con_state_q_MASK 0xf 17676#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0 17677#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10 17678#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4 17679#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20 17680#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5 17681#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40 17682#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 17683#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80 17684#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7 17685#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100 17686#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8 17687#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200 17688#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9 17689#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400 17690#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa 17691#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800 17692#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb 17693#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000 17694#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc 17695#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000 17696#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd 17697#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000 17698#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe 17699#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000 17700#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf 17701#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000 17702#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10 17703#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000 17704#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11 17705#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000 17706#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12 17707#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000 17708#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13 17709#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000 17710#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14 17711#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000 17712#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 17713#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000 17714#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16 17715#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000 17716#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17 17717#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000 17718#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18 17719#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000 17720#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19 17721#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000 17722#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a 17723#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000 17724#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b 17725#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000 17726#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c 17727#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000 17728#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d 17729#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000 17730#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e 17731#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000 17732#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f 17733#define VGT_DEBUG_REG29__con_state_q_MASK 0xf 17734#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0 17735#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10 17736#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4 17737#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20 17738#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5 17739#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40 17740#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 17741#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80 17742#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7 17743#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100 17744#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8 17745#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200 17746#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9 17747#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400 17748#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa 17749#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800 17750#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb 17751#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000 17752#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc 17753#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000 17754#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd 17755#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000 17756#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe 17757#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000 17758#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf 17759#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000 17760#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10 17761#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000 17762#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11 17763#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000 17764#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12 17765#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000 17766#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13 17767#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000 17768#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14 17769#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000 17770#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 17771#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000 17772#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16 17773#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000 17774#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17 17775#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000 17776#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18 17777#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000 17778#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19 17779#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000 17780#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a 17781#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000 17782#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b 17783#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000 17784#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c 17785#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000 17786#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d 17787#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000 17788#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e 17789#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000 17790#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f 17791#define VGT_DEBUG_REG30__pipe0_dr_MASK 0x1 17792#define VGT_DEBUG_REG30__pipe0_dr__SHIFT 0x0 17793#define VGT_DEBUG_REG30__pipe0_tf_dr_MASK 0x2 17794#define VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT 0x1 17795#define VGT_DEBUG_REG30__pipe2_dr_MASK 0x4 17796#define VGT_DEBUG_REG30__pipe2_dr__SHIFT 0x2 17797#define VGT_DEBUG_REG30__event_or_null_p0_q_MASK 0x8 17798#define VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT 0x3 17799#define VGT_DEBUG_REG30__pipe0_rtr_MASK 0x10 17800#define VGT_DEBUG_REG30__pipe0_rtr__SHIFT 0x4 17801#define VGT_DEBUG_REG30__pipe1_rtr_MASK 0x20 17802#define VGT_DEBUG_REG30__pipe1_rtr__SHIFT 0x5 17803#define VGT_DEBUG_REG30__pipe1_tf_rtr_MASK 0x40 17804#define VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT 0x6 17805#define VGT_DEBUG_REG30__pipe2_rtr_MASK 0x80 17806#define VGT_DEBUG_REG30__pipe2_rtr__SHIFT 0x7 17807#define VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK 0x100 17808#define VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT 0x8 17809#define VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK 0x200 17810#define VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT 0x9 17811#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK 0x400 17812#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT 0xa 17813#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK 0x800 17814#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT 0xb 17815#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK 0x1000 17816#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT 0xc 17817#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK 0x2000 17818#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT 0xd 17819#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK 0x4000 17820#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT 0xe 17821#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK 0x8000 17822#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT 0xf 17823#define VGT_DEBUG_REG30__tf_fetch_state_q_MASK 0x70000 17824#define VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT 0x10 17825#define VGT_DEBUG_REG30__last_tf_of_tg_MASK 0x80000 17826#define VGT_DEBUG_REG30__last_tf_of_tg__SHIFT 0x13 17827#define VGT_DEBUG_REG30__tf_pointer_p0_q_MASK 0xf00000 17828#define VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT 0x14 17829#define VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK 0x1000000 17830#define VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT 0x18 17831#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK 0x2000000 17832#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT 0x19 17833#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK 0x4000000 17834#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT 0x1a 17835#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK 0x8000000 17836#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT 0x1b 17837#define VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK 0x30000000 17838#define VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT 0x1c 17839#define VGT_DEBUG_REG30__pipe4_dr_MASK 0x40000000 17840#define VGT_DEBUG_REG30__pipe4_dr__SHIFT 0x1e 17841#define VGT_DEBUG_REG30__pipe4_rtr_MASK 0x80000000 17842#define VGT_DEBUG_REG30__pipe4_rtr__SHIFT 0x1f 17843#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1 17844#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0 17845#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2 17846#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1 17847#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4 17848#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2 17849#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8 17850#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3 17851#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10 17852#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4 17853#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20 17854#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5 17855#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40 17856#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6 17857#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80 17858#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7 17859#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100 17860#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8 17861#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200 17862#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9 17863#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400 17864#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa 17865#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800 17866#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb 17867#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000 17868#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc 17869#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000 17870#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd 17871#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000 17872#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe 17873#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000 17874#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf 17875#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000 17876#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10 17877#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000 17878#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11 17879#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000 17880#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12 17881#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000 17882#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13 17883#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000 17884#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14 17885#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000 17886#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15 17887#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000 17888#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16 17889#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000 17890#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17 17891#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000 17892#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18 17893#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000 17894#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19 17895#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000 17896#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a 17897#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000 17898#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b 17899#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000 17900#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c 17901#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000 17902#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d 17903#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000 17904#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e 17905#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000 17906#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f 17907#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1 17908#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0 17909#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2 17910#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1 17911#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4 17912#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2 17913#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8 17914#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3 17915#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10 17916#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4 17917#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20 17918#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5 17919#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40 17920#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6 17921#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80 17922#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7 17923#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100 17924#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8 17925#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200 17926#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9 17927#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400 17928#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa 17929#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800 17930#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb 17931#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000 17932#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc 17933#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000 17934#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe 17935#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000 17936#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf 17937#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000 17938#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10 17939#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000 17940#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11 17941#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000 17942#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12 17943#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000 17944#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13 17945#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000 17946#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14 17947#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000 17948#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15 17949#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000 17950#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16 17951#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000 17952#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17 17953#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000 17954#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18 17955#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000 17956#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19 17957#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000 17958#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a 17959#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000 17960#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b 17961#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000 17962#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c 17963#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1 17964#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0 17965#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2 17966#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1 17967#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4 17968#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2 17969#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8 17970#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3 17971#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10 17972#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4 17973#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20 17974#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5 17975#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40 17976#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6 17977#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80 17978#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7 17979#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100 17980#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8 17981#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200 17982#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9 17983#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400 17984#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa 17985#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800 17986#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb 17987#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000 17988#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc 17989#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000 17990#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd 17991#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000 17992#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe 17993#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000 17994#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf 17995#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000 17996#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10 17997#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000 17998#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11 17999#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000 18000#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12 18001#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000 18002#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13 18003#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000 18004#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14 18005#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000 18006#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15 18007#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000 18008#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16 18009#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000 18010#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17 18011#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000 18012#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18 18013#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000 18014#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a 18015#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000 18016#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c 18017#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000 18018#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d 18019#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000 18020#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e 18021#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000 18022#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f 18023#define VGT_DEBUG_REG34__con_state_q_MASK 0xf 18024#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0 18025#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10 18026#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4 18027#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20 18028#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5 18029#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40 18030#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 18031#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80 18032#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7 18033#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100 18034#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8 18035#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200 18036#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9 18037#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400 18038#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa 18039#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800 18040#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb 18041#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000 18042#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc 18043#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000 18044#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd 18045#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000 18046#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe 18047#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000 18048#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf 18049#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000 18050#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10 18051#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000 18052#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11 18053#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000 18054#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12 18055#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000 18056#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13 18057#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000 18058#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14 18059#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000 18060#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 18061#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000 18062#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16 18063#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000 18064#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17 18065#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000 18066#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18 18067#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000 18068#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19 18069#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000 18070#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a 18071#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000 18072#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b 18073#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000 18074#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c 18075#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000 18076#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d 18077#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000 18078#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e 18079#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000 18080#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f 18081#define VGT_DEBUG_REG35__pipe0_dr_MASK 0x1 18082#define VGT_DEBUG_REG35__pipe0_dr__SHIFT 0x0 18083#define VGT_DEBUG_REG35__pipe1_dr_MASK 0x2 18084#define VGT_DEBUG_REG35__pipe1_dr__SHIFT 0x1 18085#define VGT_DEBUG_REG35__pipe0_rtr_MASK 0x4 18086#define VGT_DEBUG_REG35__pipe0_rtr__SHIFT 0x2 18087#define VGT_DEBUG_REG35__pipe1_rtr_MASK 0x8 18088#define VGT_DEBUG_REG35__pipe1_rtr__SHIFT 0x3 18089#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK 0x10 18090#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT 0x4 18091#define VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK 0x20 18092#define VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT 0x5 18093#define VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK 0x40 18094#define VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT 0x6 18095#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK 0x80 18096#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT 0x7 18097#define VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK 0x100 18098#define VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT 0x8 18099#define VGT_DEBUG_REG35__tf_skid_fifo_full_MASK 0x200 18100#define VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT 0x9 18101#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK 0x400 18102#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT 0xa 18103#define VGT_DEBUG_REG35__last_req_of_tg_p2_MASK 0x800 18104#define VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT 0xb 18105#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK 0x3f000 18106#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT 0xc 18107#define VGT_DEBUG_REG35__event_flag_p1_q_MASK 0x40000 18108#define VGT_DEBUG_REG35__event_flag_p1_q__SHIFT 0x12 18109#define VGT_DEBUG_REG35__null_flag_p1_q_MASK 0x80000 18110#define VGT_DEBUG_REG35__null_flag_p1_q__SHIFT 0x13 18111#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK 0x7f00000 18112#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT 0x14 18113#define VGT_DEBUG_REG35__second_tf_ret_data_q_MASK 0x8000000 18114#define VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT 0x1b 18115#define VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK 0x10000000 18116#define VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT 0x1c 18117#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK 0x20000000 18118#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT 0x1d 18119#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK 0x40000000 18120#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT 0x1e 18121#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK 0x80000000 18122#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT 0x1f 18123#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff 18124#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 18125#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 18126#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 18127#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 18128#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 18129#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 18130#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 18131#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 18132#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 18133#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 18134#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 18135#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 18136#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 18137#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 18138#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 18139#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 18140#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 18141#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 18142#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 18143#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 18144#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 18145#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff 18146#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 18147#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 18148#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 18149#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff 18150#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 18151#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 18152#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 18153#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 18154#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 18155#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 18156#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 18157#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 18158#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 18159#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 18160#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 18161#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 18162#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 18163#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 18164#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 18165#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 18166#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 18167#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 18168#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c 18169#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 18170#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 18171#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 18172#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 18173#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 18174#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 18175#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 18176#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 18177#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 18178#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 18179#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 18180#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 18181#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 18182#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 18183#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 18184#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 18185#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 18186#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 18187#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 18188#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 18189#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 18190#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 18191#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 18192#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 18193#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 18194#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 18195#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff 18196#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 18197#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 18198#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 18199#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff 18200#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 18201#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 18202#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 18203#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff 18204#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 18205#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 18206#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 18207#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 18208#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 18209#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 18210#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 18211#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 18212#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 18213#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 18214#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 18215#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 18216#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 18217#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 18218#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 18219#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 18220#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 18221#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 18222#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 18223#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 18224#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 18225#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 18226#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 18227#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 18228#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 18229#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 18230#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 18231#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff 18232#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 18233#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 18234#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 18235#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff 18236#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 18237#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 18238#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 18239#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff 18240#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 18241#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 18242#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 18243#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff 18244#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 18245#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 18246#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 18247#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 18248#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 18249#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 18250#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 18251#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 18252#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 18253#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 18254#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 18255#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 18256#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 18257#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 18258#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 18259#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 18260#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 18261#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 18262#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 18263#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff 18264#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 18265#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff 18266#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 18267#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1 18268#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 18269#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2 18270#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1 18271#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc 18272#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2 18273#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10 18274#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 18275#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 18276#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 18277#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff 18278#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 18279#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000 18280#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 18281#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff 18282#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 18283#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 18284#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 18285#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 18286#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 18287#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff 18288#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 18289#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00 18290#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 18291#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000 18292#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 18293#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000 18294#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 18295#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff 18296#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 18297#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00 18298#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 18299#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000 18300#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 18301#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000 18302#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 18303#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff 18304#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 18305#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00 18306#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 18307#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000 18308#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 18309#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000 18310#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 18311#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1 18312#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 18313#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2 18314#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1 18315#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc 18316#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2 18317#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10 18318#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 18319#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 18320#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 18321#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff 18322#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 18323#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000 18324#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 18325#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff 18326#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 18327#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 18328#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 18329#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 18330#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 18331#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff 18332#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 18333#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00 18334#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 18335#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000 18336#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 18337#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000 18338#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 18339#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff 18340#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 18341#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00 18342#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 18343#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000 18344#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 18345#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000 18346#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 18347#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff 18348#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 18349#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00 18350#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 18351#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000 18352#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 18353#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000 18354#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 18355#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1 18356#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 18357#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2 18358#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1 18359#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc 18360#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2 18361#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10 18362#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 18363#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 18364#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 18365#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff 18366#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 18367#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000 18368#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 18369#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff 18370#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 18371#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 18372#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 18373#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 18374#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 18375#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff 18376#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 18377#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00 18378#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 18379#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000 18380#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 18381#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000 18382#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 18383#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff 18384#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 18385#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00 18386#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 18387#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000 18388#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 18389#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000 18390#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 18391#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff 18392#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 18393#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00 18394#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 18395#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000 18396#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 18397#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000 18398#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 18399#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1 18400#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 18401#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2 18402#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1 18403#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc 18404#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2 18405#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10 18406#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 18407#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 18408#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 18409#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff 18410#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 18411#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000 18412#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 18413#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff 18414#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 18415#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 18416#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 18417#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 18418#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 18419#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff 18420#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 18421#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00 18422#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 18423#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000 18424#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 18425#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000 18426#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 18427#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff 18428#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 18429#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00 18430#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 18431#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000 18432#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 18433#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000 18434#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 18435#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff 18436#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 18437#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00 18438#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 18439#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000 18440#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 18441#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000 18442#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 18443 18444#endif /* GFX_7_2_SH_MASK_H */
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