FILE
gfx_6_0_sh_mask.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h
1/* 2 * 3 * Copyright (C) 2016 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#ifndef GFX_6_0_SH_MASK_H 24#define GFX_6_0_SH_MASK_H 25 26#define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL 27#define BCI_DEBUG_READ__DATA__SHIFT 0x00000000 28#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L 29#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 30#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L 31#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 32#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L 33#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 34#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L 35#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 36#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L 37#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 38#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL 39#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 40#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L 41#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f 42#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L 43#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x0000001e 44#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 45#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d 46#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L 47#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 48#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L 49#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 50#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L 51#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 52#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L 53#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 54#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L 55#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 56#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL 57#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 58#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L 59#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f 60#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L 61#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x0000001e 62#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 63#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d 64#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L 65#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 66#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L 67#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 68#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L 69#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 70#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L 71#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 72#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L 73#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 74#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL 75#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 76#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L 77#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f 78#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L 79#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x0000001e 80#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 81#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d 82#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L 83#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 84#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L 85#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 86#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L 87#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 88#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L 89#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 90#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L 91#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 92#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL 93#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 94#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L 95#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f 96#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L 97#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x0000001e 98#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 99#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d 100#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L 101#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 102#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L 103#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 104#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L 105#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 106#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L 107#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 108#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L 109#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 110#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL 111#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 112#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L 113#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f 114#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L 115#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x0000001e 116#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 117#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d 118#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L 119#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 120#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L 121#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 122#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L 123#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 124#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L 125#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 126#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L 127#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 128#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL 129#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 130#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L 131#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f 132#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L 133#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x0000001e 134#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 135#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d 136#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L 137#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 138#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L 139#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 140#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L 141#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 142#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L 143#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 144#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L 145#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 146#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL 147#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 148#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L 149#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f 150#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L 151#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x0000001e 152#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 153#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d 154#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L 155#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 156#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L 157#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 158#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L 159#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 160#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L 161#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 162#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L 163#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 164#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL 165#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 166#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L 167#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f 168#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L 169#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x0000001e 170#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 171#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d 172#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffffL 173#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 174#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffffL 175#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 176#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffffL 177#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 178#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffffL 179#define CB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 180#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 181#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 182#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL 183#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 184#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 185#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f 186#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 187#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e 188#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 189#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d 190#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 191#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 192#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 193#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 194#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 195#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a 196#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 197#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 198#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 199#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 200#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L 201#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a 202#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L 203#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 204#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 205#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 206#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 207#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f 208#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 209#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c 210#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL 211#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 212#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffffL 213#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x00000000 214#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL 215#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 216#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL 217#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 218#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffffL 219#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x00000000 220#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL 221#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 222#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffffL 223#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x00000000 224#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL 225#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 226#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L 227#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x00000010 228#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L 229#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0x0000000f 230#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 231#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 232#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 233#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 234#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x00080000L 235#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 236#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L 237#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0x0000000e 238#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L 239#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0x0000000b 240#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L 241#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x00000000 242#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L 243#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0x0000000d 244#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 245#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a 246#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007cL 247#define CB_COLOR0_INFO__FORMAT__SHIFT 0x00000002 248#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L 249#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x00000007 250#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L 251#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x00000008 252#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L 253#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x00000012 254#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L 255#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 256#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L 257#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 258#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x000007ffL 259#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x00000000 260#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x003fffffL 261#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x00000000 262#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00ffe000L 263#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0x0000000d 264#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007ffL 265#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x00000000 266#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L 267#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a 268#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L 269#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 270#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 271#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 272#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 273#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f 274#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 275#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c 276#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL 277#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 278#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffffL 279#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x00000000 280#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL 281#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 282#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL 283#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 284#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffffL 285#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x00000000 286#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL 287#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 288#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffffL 289#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x00000000 290#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL 291#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 292#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L 293#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x00000010 294#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L 295#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0x0000000f 296#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 297#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 298#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 299#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 300#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x00080000L 301#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 302#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L 303#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0x0000000e 304#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L 305#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0x0000000b 306#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L 307#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x00000000 308#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L 309#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0x0000000d 310#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 311#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a 312#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007cL 313#define CB_COLOR1_INFO__FORMAT__SHIFT 0x00000002 314#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L 315#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x00000007 316#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L 317#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x00000008 318#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L 319#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x00000012 320#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L 321#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 322#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L 323#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 324#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x000007ffL 325#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x00000000 326#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x003fffffL 327#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x00000000 328#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00ffe000L 329#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0x0000000d 330#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007ffL 331#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x00000000 332#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L 333#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a 334#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L 335#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 336#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 337#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 338#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 339#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f 340#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 341#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c 342#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL 343#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 344#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffffL 345#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x00000000 346#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL 347#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 348#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL 349#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 350#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffffL 351#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x00000000 352#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL 353#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 354#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffffL 355#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x00000000 356#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL 357#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 358#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L 359#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x00000010 360#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L 361#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0x0000000f 362#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 363#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 364#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 365#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 366#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x00080000L 367#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 368#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L 369#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0x0000000e 370#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L 371#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0x0000000b 372#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L 373#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x00000000 374#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L 375#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0x0000000d 376#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 377#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a 378#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007cL 379#define CB_COLOR2_INFO__FORMAT__SHIFT 0x00000002 380#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L 381#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x00000007 382#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L 383#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x00000008 384#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L 385#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x00000012 386#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L 387#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 388#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L 389#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 390#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x000007ffL 391#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x00000000 392#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x003fffffL 393#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x00000000 394#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00ffe000L 395#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0x0000000d 396#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007ffL 397#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x00000000 398#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L 399#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a 400#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L 401#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 402#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 403#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 404#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 405#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f 406#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 407#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c 408#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL 409#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 410#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffffL 411#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x00000000 412#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL 413#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 414#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL 415#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 416#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffffL 417#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x00000000 418#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL 419#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 420#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffffL 421#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x00000000 422#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL 423#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 424#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L 425#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x00000010 426#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L 427#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0x0000000f 428#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 429#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 430#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 431#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 432#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x00080000L 433#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 434#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L 435#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0x0000000e 436#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L 437#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0x0000000b 438#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L 439#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x00000000 440#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L 441#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0x0000000d 442#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 443#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a 444#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007cL 445#define CB_COLOR3_INFO__FORMAT__SHIFT 0x00000002 446#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L 447#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x00000007 448#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L 449#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x00000008 450#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L 451#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x00000012 452#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L 453#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 454#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L 455#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 456#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x000007ffL 457#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x00000000 458#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x003fffffL 459#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x00000000 460#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00ffe000L 461#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0x0000000d 462#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007ffL 463#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x00000000 464#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L 465#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a 466#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L 467#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 468#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 469#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 470#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 471#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f 472#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 473#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c 474#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL 475#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 476#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffffL 477#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x00000000 478#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL 479#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 480#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL 481#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 482#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffffL 483#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x00000000 484#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL 485#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 486#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffffL 487#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x00000000 488#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL 489#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 490#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L 491#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x00000010 492#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L 493#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0x0000000f 494#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 495#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 496#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 497#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 498#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x00080000L 499#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 500#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L 501#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0x0000000e 502#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L 503#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0x0000000b 504#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L 505#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x00000000 506#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L 507#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0x0000000d 508#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 509#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a 510#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007cL 511#define CB_COLOR4_INFO__FORMAT__SHIFT 0x00000002 512#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L 513#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x00000007 514#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L 515#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x00000008 516#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L 517#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x00000012 518#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L 519#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 520#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L 521#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 522#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x000007ffL 523#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x00000000 524#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x003fffffL 525#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x00000000 526#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00ffe000L 527#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0x0000000d 528#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007ffL 529#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x00000000 530#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L 531#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a 532#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L 533#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 534#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 535#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 536#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 537#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f 538#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 539#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c 540#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL 541#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 542#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffffL 543#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x00000000 544#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL 545#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 546#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL 547#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 548#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffffL 549#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x00000000 550#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL 551#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 552#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffffL 553#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x00000000 554#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL 555#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 556#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L 557#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x00000010 558#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L 559#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0x0000000f 560#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 561#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 562#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 563#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 564#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x00080000L 565#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 566#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L 567#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0x0000000e 568#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L 569#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0x0000000b 570#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L 571#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x00000000 572#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L 573#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0x0000000d 574#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 575#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a 576#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007cL 577#define CB_COLOR5_INFO__FORMAT__SHIFT 0x00000002 578#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L 579#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x00000007 580#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L 581#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x00000008 582#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L 583#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x00000012 584#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L 585#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 586#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L 587#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 588#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x000007ffL 589#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x00000000 590#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x003fffffL 591#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x00000000 592#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00ffe000L 593#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0x0000000d 594#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007ffL 595#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x00000000 596#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L 597#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a 598#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L 599#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 600#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 601#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 602#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 603#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f 604#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 605#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c 606#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL 607#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 608#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffffL 609#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x00000000 610#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL 611#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 612#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL 613#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 614#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffffL 615#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x00000000 616#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL 617#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 618#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffffL 619#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x00000000 620#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL 621#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 622#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L 623#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x00000010 624#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L 625#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0x0000000f 626#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 627#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 628#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 629#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 630#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x00080000L 631#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 632#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L 633#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0x0000000e 634#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L 635#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0x0000000b 636#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L 637#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x00000000 638#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L 639#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0x0000000d 640#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 641#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a 642#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007cL 643#define CB_COLOR6_INFO__FORMAT__SHIFT 0x00000002 644#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L 645#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x00000007 646#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L 647#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x00000008 648#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L 649#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x00000012 650#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L 651#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 652#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L 653#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 654#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x000007ffL 655#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x00000000 656#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x003fffffL 657#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x00000000 658#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00ffe000L 659#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0x0000000d 660#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007ffL 661#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x00000000 662#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L 663#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a 664#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L 665#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 666#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 667#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 668#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 669#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f 670#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 671#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c 672#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL 673#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 674#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffffL 675#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x00000000 676#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL 677#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 678#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL 679#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 680#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffffL 681#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x00000000 682#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL 683#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 684#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffffL 685#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x00000000 686#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL 687#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 688#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L 689#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x00000010 690#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L 691#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0x0000000f 692#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 693#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 694#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 695#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 696#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x00080000L 697#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 698#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L 699#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0x0000000e 700#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L 701#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0x0000000b 702#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L 703#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x00000000 704#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L 705#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0x0000000d 706#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 707#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a 708#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007cL 709#define CB_COLOR7_INFO__FORMAT__SHIFT 0x00000002 710#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L 711#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x00000007 712#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L 713#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x00000008 714#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L 715#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x00000012 716#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L 717#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 718#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L 719#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 720#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x000007ffL 721#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x00000000 722#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x003fffffL 723#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x00000000 724#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00ffe000L 725#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0x0000000d 726#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007ffL 727#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x00000000 728#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L 729#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x00000003 730#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L 731#define CB_COLOR_CONTROL__MODE__SHIFT 0x00000004 732#define CB_COLOR_CONTROL__ROP3_MASK 0x00ff0000L 733#define CB_COLOR_CONTROL__ROP3__SHIFT 0x00000010 734#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x00000008L 735#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x00000003 736#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x00000020L 737#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x00000005 738#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x00000010L 739#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x00000004 740#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x00000200L 741#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x00000009 742#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x00000100L 743#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x00000008 744#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x00000080L 745#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x00000007 746#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x00000400L 747#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0x0000000a 748#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x00000040L 749#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x00000006 750#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x00000002L 751#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x00000001 752#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x0007f800L 753#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0x0000000b 754#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x00000001L 755#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x00000000 756#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x00000004L 757#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x00000002 758#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x00000010L 759#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x00000004 760#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x00000008L 761#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x00000003 762#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x00000100L 763#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x00000008 764#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x00000002L 765#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x00000001 766#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x00000004L 767#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x00000002 768#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x00000020L 769#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x00000005 770#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x00000040L 771#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x00000006 772#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x00000080L 773#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x00000007 774#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x00000001L 775#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x00000000 776#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x00000010L 777#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x00000004 778#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x00000040L 779#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x00000006 780#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x00000100L 781#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x00000008 782#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x00000020L 783#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x00000005 784#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x00000008L 785#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x00000003 786#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x00000004L 787#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x00000002 788#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x00000003L 789#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x00000000 790#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x00000080L 791#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x00000007 792#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x00100000L 793#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x00000014 794#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x00400000L 795#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x00000016 796#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x00200000L 797#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x00000015 798#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x000003c0L 799#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x00000006 800#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0x000f0000L 801#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x00000010 802#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x0000003fL 803#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x00000000 804#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0x0000fc00L 805#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0x0000000a 806#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x00000008L 807#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x00000003 808#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x00000004L 809#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x00000002 810#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x00000001L 811#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x00000000 812#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x00000020L 813#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x00000005 814#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x00000002L 815#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x00000001 816#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x00000010L 817#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x00000004 818#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x00000080L 819#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x00000007 820#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x00000040L 821#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x00000006 822#define CB_DEBUG_BUS_18__NOT_USED_MASK 0x00ffffffL 823#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x00000000 824#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001f800L 825#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0000000b 826#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000L 827#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x0000001a 828#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001fL 829#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x00000000 830#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03fe0000L 831#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x00000011 832#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007e0L 833#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x00000005 834#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000ffL 835#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x00000000 836#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff800000L 837#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x00000017 838#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007f8000L 839#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0x0000000f 840#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007f00L 841#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x00000008 842#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L 843#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x00000000 844#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L 845#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x00000010 846#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000f000L 847#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0x0000000c 848#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000fL 849#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x00000000 850#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L 851#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x00000019 852#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L 853#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x0000001a 854#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L 855#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x00000018 856#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L 857#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x00000015 858#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L 859#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x0000001b 860#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L 861#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x0000001e 862#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L 863#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x00000016 864#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L 865#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x00000012 866#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L 867#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x0000001f 868#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L 869#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x00000017 870#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003c0L 871#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x00000006 872#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L 873#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x00000014 874#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L 875#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x00000013 876#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L 877#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x0000001d 878#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L 879#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x0000001c 880#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 881#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 882#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 883#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 884#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L 885#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c 886#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L 887#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 888#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001ffL 889#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 890#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007fc00L 891#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 892#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 893#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 894#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 895#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 896#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 897#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 898#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 899#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 900#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 901#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 902#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 903#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 904#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000fL 905#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x00000000 906#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000f0L 907#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x00000004 908#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000f00L 909#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x00000008 910#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000f000L 911#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0x0000000c 912#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000f0000L 913#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x00000010 914#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00f00000L 915#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x00000014 916#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0f000000L 917#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x00000018 918#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000L 919#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x0000001c 920#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000fL 921#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x00000000 922#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000f0L 923#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x00000004 924#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000f00L 925#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x00000008 926#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000f000L 927#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0x0000000c 928#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000f0000L 929#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x00000010 930#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00f00000L 931#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x00000014 932#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0f000000L 933#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x00000018 934#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000L 935#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x0000001c 936#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x00000006L 937#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x00000001 938#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x00000010L 939#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x00000004 940#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L 941#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010 942#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L 943#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003 944#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L 945#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 946#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000fL 947#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x00000000 948#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000f0L 949#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x00000004 950#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000f00L 951#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x00000008 952#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000f000L 953#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0x0000000c 954#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000f0000L 955#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x00000010 956#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00f00000L 957#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x00000014 958#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0f000000L 959#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x00000018 960#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000L 961#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x0000001c 962#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L 963#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0x0000000c 964#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L 965#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x00000014 966#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000f00L 967#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x00000008 968#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000f0000L 969#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x00000010 970#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L 971#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010 972#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L 973#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014 974#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0x0f000000L 975#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x00000018 976#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000L 977#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x0000001c 978#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001f00L 979#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x00000008 980#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001fL 981#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x00000000 982#define CGTS_RD_REG__READ_DATA_MASK 0x00003fffL 983#define CGTS_RD_REG__READ_DATA__SHIFT 0x00000000 984#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L 985#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x00000010 986#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L 987#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x00000016 988#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L 989#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0x0000000c 990#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000ff0L 991#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x00000004 992#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L 993#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x00000017 994#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000L 995#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x00000018 996#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000fL 997#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x00000000 998#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L 999#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x00000015 1000#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L 1001#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x00000014 1002#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000e0000L 1003#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x00000011 1004#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L 1005#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010 1006#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L 1007#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010 1008#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L 1009#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e 1010#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L 1011#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d 1012#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L 1013#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c 1014#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L 1015#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b 1016#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L 1017#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x0000001a 1018#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L 1019#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x00000019 1020#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L 1021#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x00000018 1022#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1023#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1024#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1025#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1026#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 1027#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f 1028#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x00fff000L 1029#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0x0000000c 1030#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1031#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1032#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1033#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1034#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L 1035#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e 1036#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L 1037#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f 1038#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1039#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1040#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1041#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1042#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 1043#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f 1044#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 1045#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e 1046#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 1047#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d 1048#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 1049#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 1050#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 1051#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 1052#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 1053#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a 1054#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 1055#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 1056#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 1057#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 1058#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L 1059#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001d 1060#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L 1061#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a 1062#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1063#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1064#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1065#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1066#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L 1067#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019 1068#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 1069#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f 1070#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 1071#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d 1072#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 1073#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 1074#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 1075#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 1076#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 1077#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 1078#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L 1079#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x0000001e 1080#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1081#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1082#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1083#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1084#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L 1085#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0000001f 1086#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 1087#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 1088#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 1089#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 1090#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 1091#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a 1092#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 1093#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 1094#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 1095#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 1096#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L 1097#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x0000001d 1098#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x02000000L 1099#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x00000019 1100#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L 1101#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e 1102#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L 1103#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d 1104#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L 1105#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c 1106#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L 1107#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b 1108#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x04000000L 1109#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x0000001a 1110#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L 1111#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012 1112#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L 1113#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018 1114#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1115#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1116#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1117#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1118#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 1119#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f 1120#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1121#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1122#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1123#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1124#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L 1125#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e 1126#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L 1127#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f 1128#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1129#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1130#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1131#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1132#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 1133#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f 1134#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 1135#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e 1136#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 1137#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d 1138#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 1139#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 1140#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 1141#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 1142#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 1143#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a 1144#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 1145#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 1146#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 1147#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 1148#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L 1149#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x0000001a 1150#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L 1151#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x0000001e 1152#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L 1153#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x0000001d 1154#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L 1155#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x0000001c 1156#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L 1157#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x0000001b 1158#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L 1159#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012 1160#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L 1161#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018 1162#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1163#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1164#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1165#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1166#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 1167#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f 1168#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L 1169#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e 1170#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1171#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1172#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1173#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1174#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 1175#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f 1176#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L 1177#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e 1178#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1179#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1180#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1181#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1182#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 1183#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f 1184#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L 1185#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004 1186#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL 1187#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000 1188#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x00fff000L 1189#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0x0000000c 1190#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L 1191#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001f 1192#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L 1193#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001e 1194#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L 1195#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x0000001d 1196#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L 1197#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x0000001c 1198#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L 1199#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x0000001b 1200#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L 1201#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x0000001a 1202#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L 1203#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x00000019 1204#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L 1205#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x00000018 1206#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000ff0L 1207#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x00000004 1208#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000fL 1209#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x00000000 1210#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x00fff000L 1211#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0x0000000c 1212#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L 1213#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x0000001f 1214#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L 1215#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x0000001e 1216#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L 1217#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x0000001d 1218#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L 1219#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x0000001c 1220#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L 1221#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x0000001b 1222#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L 1223#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x0000001a 1224#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L 1225#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x00000019 1226#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L 1227#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x00000018 1228#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000ff0L 1229#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x00000004 1230#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000fL 1231#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x00000000 1232#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x00fff000L 1233#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0x0000000c 1234#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L 1235#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x0000001f 1236#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L 1237#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x0000001e 1238#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L 1239#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x0000001d 1240#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L 1241#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x0000001c 1242#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L 1243#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x0000001b 1244#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L 1245#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x0000001a 1246#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L 1247#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x00000019 1248#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L 1249#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x00000018 1250#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000ff0L 1251#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x00000004 1252#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000fL 1253#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x00000000 1254#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x00fff000L 1255#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0x0000000c 1256#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L 1257#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x0000001f 1258#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L 1259#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x0000001e 1260#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L 1261#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x0000001d 1262#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L 1263#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x0000001c 1264#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L 1265#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x0000001b 1266#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L 1267#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x0000001a 1268#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L 1269#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x00000019 1270#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L 1271#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x00000018 1272#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000ff0L 1273#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x00000004 1274#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000fL 1275#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x00000000 1276#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x00fff000L 1277#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0x0000000c 1278#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L 1279#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x0000001f 1280#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L 1281#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x0000001e 1282#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L 1283#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x0000001d 1284#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L 1285#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x0000001c 1286#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L 1287#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x0000001b 1288#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L 1289#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x0000001a 1290#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L 1291#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x00000019 1292#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x01000000L 1293#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x00000018 1294#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1295#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1296#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1297#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1298#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 1299#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f 1300#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 1301#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e 1302#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 1303#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d 1304#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 1305#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 1306#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 1307#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 1308#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 1309#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a 1310#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 1311#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 1312#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 1313#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 1314#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1315#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1316#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1317#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1318#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 1319#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f 1320#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 1321#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e 1322#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 1323#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d 1324#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 1325#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 1326#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 1327#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 1328#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 1329#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a 1330#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 1331#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 1332#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 1333#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 1334#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L 1335#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e 1336#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L 1337#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a 1338#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L 1339#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x0000001d 1340#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 1341#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 1342#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL 1343#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 1344#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L 1345#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019 1346#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 1347#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f 1348#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 1349#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 1350#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 1351#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 1352#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 1353#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 1354#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0x000000ffL 1355#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000000 1356#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x08000000L 1357#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x0000001b 1358#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000L 1359#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001c 1360#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00200000L 1361#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x00000015 1362#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00400000L 1363#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x00000016 1364#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000100L 1365#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000008 1366#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00001000L 1367#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x0000000c 1368#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000800L 1369#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x0000000b 1370#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00008000L 1371#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x0000000f 1372#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00010000L 1373#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000010 1374#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000L 1375#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x0000001d 1376#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00002000L 1377#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x0000000d 1378#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00004000L 1379#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x0000000e 1380#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x00000600L 1381#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x00000009 1382#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00020000L 1383#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000011 1384#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00040000L 1385#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000012 1386#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000L 1387#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x0000001f 1388#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00080000L 1389#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x00000013 1390#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00100000L 1391#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x00000014 1392#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00800000L 1393#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x00000017 1394#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x01000000L 1395#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x00000018 1396#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x02000000L 1397#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000019 1398#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x04000000L 1399#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x0000001a 1400#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000L 1401#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x0000001e 1402#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0x000000ffL 1403#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000000 1404#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x00000700L 1405#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x00000008 1406#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000L 1407#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x0000001c 1408#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000L 1409#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x0000001d 1410#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x000e0000L 1411#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000011 1412#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00100000L 1413#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000014 1414#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x0001c000L 1415#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0x0000000e 1416#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00003800L 1417#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x0000000b 1418#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000L 1419#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x0000001e 1420#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000L 1421#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000001f 1422#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x01000000L 1423#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x00000018 1424#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x0c000000L 1425#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x0000001a 1426#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x02000000L 1427#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x00000019 1428#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x00800000L 1429#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x00000017 1430#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x00400000L 1431#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x00000016 1432#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x00200000L 1433#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x00000015 1434#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x00000007L 1435#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x00000000 1436#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x04000000L 1437#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x0000001a 1438#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000L 1439#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x0000001c 1440#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x00100000L 1441#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x00000014 1442#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x00200000L 1443#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x00000015 1444#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x08000000L 1445#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x0000001b 1446#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000L 1447#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x0000001d 1448#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x01000000L 1449#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x00000018 1450#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0x000000c0L 1451#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x00000006 1452#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x00400000L 1453#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x00000016 1454#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000L 1455#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x0000001e 1456#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000L 1457#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x0000001f 1458#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x00800000L 1459#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000017 1460#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x02000000L 1461#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x00000019 1462#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0x000f0000L 1463#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x00000010 1464#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0x0000f000L 1465#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000c 1466#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0x00000f00L 1467#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000008 1468#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x00000038L 1469#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x00000003 1470#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x00003fffL 1471#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000000 1472#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00800000L 1473#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000017 1474#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x07000000L 1475#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 1476#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000L 1477#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x0000001c 1478#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0x000fc000L 1479#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0x0000000e 1480#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000L 1481#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d 1482#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L 1483#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b 1484#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L 1485#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e 1486#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L 1487#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1488#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00700000L 1489#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000014 1490#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000L 1491#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d 1492#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L 1493#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e 1494#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL 1495#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 1496#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L 1497#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1498#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L 1499#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 1500#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L 1501#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 1502#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L 1503#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b 1504#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x00003fffL 1505#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x00000000 1506#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x00800000L 1507#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x00000017 1508#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x07000000L 1509#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 1510#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000L 1511#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x0000001c 1512#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0x000fc000L 1513#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0x0000000e 1514#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000L 1515#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d 1516#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L 1517#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b 1518#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L 1519#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e 1520#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L 1521#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1522#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x00700000L 1523#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x00000014 1524#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000L 1525#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d 1526#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L 1527#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e 1528#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL 1529#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 1530#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L 1531#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1532#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L 1533#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 1534#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L 1535#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 1536#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L 1537#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b 1538#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x00003fffL 1539#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x00000000 1540#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x00800000L 1541#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x00000017 1542#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x07000000L 1543#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 1544#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000L 1545#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x0000001c 1546#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0x000fc000L 1547#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0x0000000e 1548#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000L 1549#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d 1550#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L 1551#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b 1552#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L 1553#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e 1554#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L 1555#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1556#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x00700000L 1557#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x00000014 1558#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000L 1559#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d 1560#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L 1561#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e 1562#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL 1563#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 1564#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L 1565#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1566#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L 1567#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 1568#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L 1569#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 1570#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L 1571#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b 1572#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x00003fffL 1573#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x00000000 1574#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x00800000L 1575#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000017 1576#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x07000000L 1577#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 1578#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000L 1579#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x0000001c 1580#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0x000fc000L 1581#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0x0000000e 1582#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000L 1583#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d 1584#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L 1585#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b 1586#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L 1587#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e 1588#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L 1589#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1590#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x00700000L 1591#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x00000014 1592#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000L 1593#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d 1594#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L 1595#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e 1596#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL 1597#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 1598#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L 1599#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1600#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L 1601#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 1602#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L 1603#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 1604#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L 1605#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b 1606#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x00000080L 1607#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x00000007 1608#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00f00000L 1609#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000014 1610#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x00000008L 1611#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x00000003 1612#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x08000000L 1613#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x0000001b 1614#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000L 1615#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001f 1616#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x00000040L 1617#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x00000006 1618#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0x000f0000L 1619#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000010 1620#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x00000004L 1621#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x00000002 1622#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x04000000L 1623#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x0000001a 1624#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000L 1625#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001e 1626#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x00000020L 1627#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x00000005 1628#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0x0000f000L 1629#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000000c 1630#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x00000002L 1631#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x00000001 1632#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x02000000L 1633#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x00000019 1634#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000L 1635#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001d 1636#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x00000010L 1637#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x00000004 1638#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00000f00L 1639#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000008 1640#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x00000001L 1641#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x00000000 1642#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x01000000L 1643#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x00000018 1644#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000L 1645#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001c 1646#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0x000000ffL 1647#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x00000000 1648#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x0003e000L 1649#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x0000000d 1650#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00001f00L 1651#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000008 1652#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0x00c00000L 1653#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x00000016 1654#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0x000c0000L 1655#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x00000012 1656#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x00300000L 1657#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x00000014 1658#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000L 1659#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x0000001e 1660#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L 1661#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1662#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000L 1663#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x0000001c 1664#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000L 1665#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001d 1666#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x04000000L 1667#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x0000001a 1668#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x08000000L 1669#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001b 1670#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x01000000L 1671#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000018 1672#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x02000000L 1673#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000019 1674#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x00010000L 1675#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000010 1676#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x00003000L 1677#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0x0000000c 1678#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x00008000L 1679#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0x0000000f 1680#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x001e0000L 1681#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x00000011 1682#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x00000020L 1683#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x00000005 1684#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x00000040L 1685#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x00000006 1686#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x00000007L 1687#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x00000000 1688#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000L 1689#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x0000001e 1690#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000L 1691#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x00000018 1692#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000L 1693#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x0000001d 1694#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000L 1695#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x0000001f 1696#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x00800000L 1697#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x00000017 1698#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x00600000L 1699#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x00000015 1700#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x00000008L 1701#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x00000003 1702#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x00000080L 1703#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x00000007 1704#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x00000010L 1705#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x00000004 1706#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0x00000f00L 1707#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x00000008 1708#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x00004000L 1709#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0x0000000e 1710#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0x00e00000L 1711#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x00000015 1712#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x00080000L 1713#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x00000013 1714#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000L 1715#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x00000018 1716#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000L 1717#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x0000001e 1718#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x00100000L 1719#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x00000014 1720#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x0003f000L 1721#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000c 1722#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0x00000fc0L 1723#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000006 1724#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x0000003fL 1725#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000000 1726#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x00040000L 1727#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x00000012 1728#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000L 1729#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x0000001f 1730#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000L 1731#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000001a 1732#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x03e00000L 1733#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000015 1734#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x001f0000L 1735#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000010 1736#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000L 1737#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x0000001f 1738#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0x0000ffffL 1739#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 1740#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L 1741#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b 1742#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000L 1743#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x0000001c 1744#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x00001f00L 1745#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x00000008 1746#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000L 1747#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1748#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x07f00000L 1749#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x00000014 1750#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000L 1751#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x0000001d 1752#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L 1753#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 1754#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L 1755#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 1756#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000L 1757#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x0000001e 1758#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x0000007fL 1759#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x00000000 1760#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x00000080L 1761#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x00000007 1762#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x0003e000L 1763#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0x0000000d 1764#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L 1765#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b 1766#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000L 1767#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x0000001c 1768#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x00001f00L 1769#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x00000008 1770#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000L 1771#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1772#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x07f00000L 1773#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x00000014 1774#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000L 1775#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x0000001d 1776#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x00080000L 1777#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x00000013 1778#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x00040000L 1779#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x00000012 1780#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000L 1781#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x0000001e 1782#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x0000007fL 1783#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x00000000 1784#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x00000080L 1785#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x00000007 1786#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x0003e000L 1787#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0x0000000d 1788#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L 1789#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b 1790#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000L 1791#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x0000001c 1792#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x00001f00L 1793#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x00000008 1794#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000L 1795#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1796#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x07f00000L 1797#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x00000014 1798#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000L 1799#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x0000001d 1800#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x00080000L 1801#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x00000013 1802#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x00040000L 1803#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x00000012 1804#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000L 1805#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x0000001e 1806#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x0000007fL 1807#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x00000000 1808#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x00000080L 1809#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x00000007 1810#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x0003e000L 1811#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0x0000000d 1812#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L 1813#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b 1814#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000L 1815#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x0000001c 1816#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x00001f00L 1817#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x00000008 1818#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000L 1819#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f 1820#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x07f00000L 1821#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x00000014 1822#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000L 1823#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x0000001d 1824#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x00080000L 1825#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x00000013 1826#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x00040000L 1827#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x00000012 1828#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000L 1829#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x0000001e 1830#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x0000007fL 1831#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x00000000 1832#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x00000080L 1833#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x00000007 1834#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x0003e000L 1835#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0x0000000d 1836#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffffL 1837#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x00000000 1838#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffffL 1839#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x00000000 1840#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffffL 1841#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x00000000 1842#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffffL 1843#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x00000000 1844#define COMPUTE_DIM_X__SIZE_MASK 0xffffffffL 1845#define COMPUTE_DIM_X__SIZE__SHIFT 0x00000000 1846#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffffL 1847#define COMPUTE_DIM_Y__SIZE__SHIFT 0x00000000 1848#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffffL 1849#define COMPUTE_DIM_Z__SIZE__SHIFT 0x00000000 1850#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L 1851#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x00000000 1852#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x00001000L 1853#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0x0000000c 1854#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x00000380L 1855#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x00000007 1856#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L 1857#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x00000002 1858#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L 1859#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x00000003 1860#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L 1861#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x00000004 1862#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L 1863#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x00000006 1864#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L 1865#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x00000001 1866#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L 1867#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0x0000000e 1868#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L 1869#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0x0000000a 1870#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L 1871#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x00000005 1872#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L 1873#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0x0000000b 1874#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000ffffL 1875#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x00000000 1876#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000L 1877#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x00000010 1878#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000ffffL 1879#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x00000000 1880#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000L 1881#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x00000010 1882#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000ffffL 1883#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x00000000 1884#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000L 1885#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x00000010 1886#define COMPUTE_PGM_HI__DATA_MASK 0x000000ffL 1887#define COMPUTE_PGM_HI__DATA__SHIFT 0x00000000 1888#define COMPUTE_PGM_HI__INST_ATC_MASK 0x00000100L 1889#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x00000008 1890#define COMPUTE_PGM_LO__DATA_MASK 0xffffffffL 1891#define COMPUTE_PGM_LO__DATA__SHIFT 0x00000000 1892#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L 1893#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x00000018 1894#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L 1895#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x00000019 1896#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L 1897#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x00000016 1898#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L 1899#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x00000015 1900#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000ff000L 1901#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0x0000000c 1902#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L 1903#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x00000017 1904#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000c00L 1905#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0x0000000a 1906#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L 1907#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x00000014 1908#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003c0L 1909#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x00000006 1910#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003fL 1911#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x00000000 1912#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000L 1913#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L 1914#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0x0000000d 1915#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x00000018 1916#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00ff8000L 1917#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0x0000000f 1918#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L 1919#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x00000000 1920#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L 1921#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x00000007 1922#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L 1923#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x00000008 1924#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L 1925#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x00000009 1926#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L 1927#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0x0000000a 1928#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L 1929#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0x0000000b 1930#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L 1931#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x00000006 1932#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003eL 1933#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x00000001 1934#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L 1935#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x00000018 1936#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L 1937#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x00000017 1938#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003f0000L 1939#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x00000010 1940#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L 1941#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x00000016 1942#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000f000L 1943#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0x0000000c 1944#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x0000003fL 1945#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x00000000 1946#define COMPUTE_START_X__START_MASK 0xffffffffL 1947#define COMPUTE_START_X__START__SHIFT 0x00000000 1948#define COMPUTE_START_Y__START_MASK 0xffffffffL 1949#define COMPUTE_START_Y__START__SHIFT 0x00000000 1950#define COMPUTE_START_Z__START_MASK 0xffffffffL 1951#define COMPUTE_START_Z__START__SHIFT 0x00000000 1952#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000ffffL 1953#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x00000000 1954#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000L 1955#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x00000010 1956#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000ffffL 1957#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x00000000 1958#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000L 1959#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x00000010 1960#define COMPUTE_TBA_HI__DATA_MASK 0x000000ffL 1961#define COMPUTE_TBA_HI__DATA__SHIFT 0x00000000 1962#define COMPUTE_TBA_LO__DATA_MASK 0xffffffffL 1963#define COMPUTE_TBA_LO__DATA__SHIFT 0x00000000 1964#define COMPUTE_TMA_HI__DATA_MASK 0x000000ffL 1965#define COMPUTE_TMA_HI__DATA__SHIFT 0x00000000 1966#define COMPUTE_TMA_LO__DATA_MASK 0xffffffffL 1967#define COMPUTE_TMA_LO__DATA__SHIFT 0x00000000 1968#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L 1969#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c 1970#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000fffL 1971#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x00000000 1972#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffffL 1973#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x00000000 1974#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffffL 1975#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x00000000 1976#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffffL 1977#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x00000000 1978#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffffL 1979#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x00000000 1980#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffffL 1981#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x00000000 1982#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffffL 1983#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x00000000 1984#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffffL 1985#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x00000000 1986#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffffL 1987#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x00000000 1988#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffffL 1989#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x00000000 1990#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffffL 1991#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x00000000 1992#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffffL 1993#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x00000000 1994#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffffL 1995#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x00000000 1996#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffffL 1997#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x00000000 1998#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffffL 1999#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x00000000 2000#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffffL 2001#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x00000000 2002#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffffL 2003#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x00000000 2004#define COMPUTE_VMID__DATA_MASK 0x0000000fL 2005#define COMPUTE_VMID__DATA__SHIFT 0x00000000 2006#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000L 2007#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x0000001d 2008#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00030000L 2009#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x00000010 2010#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x000000ffL 2011#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x00000000 2012#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffcL 2013#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x00000002 2014#define CP_APPEND_DATA__DATA_MASK 0xffffffffL 2015#define CP_APPEND_DATA__DATA__SHIFT 0x00000000 2016#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffffL 2017#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x00000000 2018#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffffL 2019#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x00000000 2020#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffffL 2021#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x00000000 2022#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffffL 2023#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x00000000 2024#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L 2025#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x00000016 2026#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L 2027#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x00000006 2028#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L 2029#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x00000012 2030#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L 2031#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0x0000000f 2032#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L 2033#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x00000011 2034#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L 2035#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x00000008 2036#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L 2037#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x00000007 2038#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L 2039#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x00000014 2040#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L 2041#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x00000015 2042#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L 2043#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0x0000000a 2044#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L 2045#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x00000009 2046#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L 2047#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x00000000 2048#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L 2049#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0x0000000c 2050#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L 2051#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0x0000000d 2052#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L 2053#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0x0000000e 2054#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L 2055#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x00000013 2056#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffffL 2057#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x00000000 2058#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL 2059#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000 2060#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL 2061#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002 2062#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL 2063#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 2064#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL 2065#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000 2066#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL 2067#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002 2068#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL 2069#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 2070#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x000000ffL 2071#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x00000000 2072#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0L 2073#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x00000005 2074#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000fffL 2075#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x00000000 2076#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07ff0000L 2077#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x00000010 2078#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007ffL 2079#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x00000000 2080#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007ffL 2081#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x00000000 2082#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003ffL 2083#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x00000000 2084#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03ff0000L 2085#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x00000010 2086#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003ffL 2087#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x00000000 2088#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03ff0000L 2089#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x00000010 2090#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003ffL 2091#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x00000000 2092#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03ff0000L 2093#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x00000010 2094#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL 2095#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 2096#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL 2097#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 2098#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL 2099#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 2100#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007ffL 2101#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 2102#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L 2103#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0x0000000c 2104#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L 2105#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 2106#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0ff00000L 2107#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x00000014 2108#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000ffL 2109#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x00000000 2110#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L 2111#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x0000001c 2112#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L 2113#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x00000008 2114#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffffL 2115#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x00000000 2116#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000ffL 2117#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x00000000 2118#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L 2119#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x00000006 2120#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L 2121#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x00000007 2122#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L 2123#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x00000008 2124#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L 2125#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x00000009 2126#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L 2127#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0x0000000a 2128#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L 2129#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0x0000000b 2130#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L 2131#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0x0000000c 2132#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L 2133#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0x0000000d 2134#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L 2135#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x00000019 2136#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L 2137#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x0000001a 2138#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L 2139#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0x0000000e 2140#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L 2141#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x00000000 2142#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L 2143#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x00000001 2144#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L 2145#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x00000013 2146#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L 2147#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x00000015 2148#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L 2149#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x0000001d 2150#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L 2151#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x0000001b 2152#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L 2153#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x0000001c 2154#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L 2155#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x00000017 2156#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L 2157#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x00000016 2158#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L 2159#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0x0000000f 2160#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x00010000L 2161#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x00000010 2162#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L 2163#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x00000012 2164#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffffL 2165#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x00000000 2166#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000ffL 2167#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x00000000 2168#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003fL 2169#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x00000000 2170#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000ffL 2171#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x00000000 2172#define CP_COHER_STATUS__MEID_MASK 0x03000000L 2173#define CP_COHER_STATUS__MEID__SHIFT 0x00000018 2174#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000L 2175#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x0000001e 2176#define CP_COHER_STATUS__STATUS_MASK 0x80000000L 2177#define CP_COHER_STATUS__STATUS__SHIFT 0x0000001f 2178#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0x0000000fL 2179#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x00000000 2180#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x00003f00L 2181#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x00000008 2182#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0x0000000fL 2183#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x00000000 2184#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000f0000L 2185#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x00000010 2186#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L 2187#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x00000004 2188#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000L 2189#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x0000001e 2190#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L 2191#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x0000001c 2192#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L 2193#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x0000001d 2194#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x001fffffL 2195#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x00000000 2196#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L 2197#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x0000001d 2198#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L 2199#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x0000001b 2200#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x00200000L 2201#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x00000015 2202#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x03000000L 2203#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x00000018 2204#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L 2205#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x0000001e 2206#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L 2207#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x0000001c 2208#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L 2209#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x0000001a 2210#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0x00c00000L 2211#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x00000016 2212#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffffL 2213#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x00000000 2214#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL 2215#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 2216#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL 2217#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 2218#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL 2219#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 2220#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x001fffffL 2221#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x00000000 2222#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L 2223#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x0000001d 2224#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L 2225#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x0000001b 2226#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x00200000L 2227#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x00000015 2228#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x03000000L 2229#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x00000018 2230#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L 2231#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x0000001e 2232#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L 2233#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x0000001c 2234#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L 2235#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x0000001a 2236#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0x00c00000L 2237#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x00000016 2238#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffffL 2239#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x00000000 2240#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL 2241#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 2242#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL 2243#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 2244#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL 2245#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 2246#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03ffffffL 2247#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x00000000 2248#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L 2249#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x0000001c 2250#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L 2251#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x00000000 2252#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0x000000f0L 2253#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x00000004 2254#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x00000003L 2255#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x00000000 2256#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0x000000f0L 2257#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x00000004 2258#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x00003c00L 2259#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0x0000000a 2260#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0x000f0000L 2261#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x00000010 2262#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x00000003L 2263#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x00000000 2264#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0x000000f0L 2265#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x00000004 2266#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x00003c00L 2267#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0x0000000a 2268#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0x000f0000L 2269#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x00000010 2270#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x00000003L 2271#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x00000000 2272#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0x000000f0L 2273#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x00000004 2274#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x00003c00L 2275#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0x0000000a 2276#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0x000f0000L 2277#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x00000010 2278#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x00003c00L 2279#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0x0000000a 2280#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000f0000L 2281#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x00000010 2282#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000ffffL 2283#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x00000000 2284#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffcL 2285#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x00000002 2286#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x00000003L 2287#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x00000000 2288#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0x0000ffffL 2289#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x00000000 2290#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000L 2291#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x0000001d 2292#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L 2293#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x00000010 2294#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L 2295#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x00000018 2296#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffffL 2297#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x00000000 2298#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffffL 2299#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x00000000 2300#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffffL 2301#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x00000000 2302#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffffL 2303#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x00000000 2304#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffffL 2305#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x00000000 2306#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffffL 2307#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x00000000 2308#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffffL 2309#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x00000000 2310#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffffL 2311#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x00000000 2312#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003f00L 2313#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x00000008 2314#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003fL 2315#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003f0000L 2316#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x00000010 2317#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x00000000 2318#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL 2319#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000 2320#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL 2321#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002 2322#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL 2323#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 2324#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000fffffL 2325#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x00000000 2326#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000fffffL 2327#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x00000000 2328#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000fffffL 2329#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x00000000 2330#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL 2331#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000 2332#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL 2333#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002 2334#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL 2335#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 2336#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000fffffL 2337#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x00000000 2338#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000fffffL 2339#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x00000000 2340#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000fffffL 2341#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x00000000 2342#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L 2343#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 2344#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L 2345#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 2346#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 2347#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e 2348#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L 2349#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f 2350#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L 2351#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e 2352#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L 2353#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d 2354#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 2355#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 2356#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L 2357#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 2358#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L 2359#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 2360#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 2361#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b 2362#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L 2363#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 2364#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L 2365#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 2366#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 2367#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e 2368#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L 2369#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x0000001f 2370#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L 2371#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x0000001e 2372#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L 2373#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x0000001d 2374#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 2375#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 2376#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L 2377#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 2378#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L 2379#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 2380#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 2381#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b 2382#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 2383#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a 2384#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 2385#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 2386#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L 2387#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 2388#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L 2389#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 2390#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 2391#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e 2392#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L 2393#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x0000001f 2394#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L 2395#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x0000001e 2396#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L 2397#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x0000001d 2398#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 2399#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 2400#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L 2401#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 2402#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L 2403#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 2404#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 2405#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b 2406#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 2407#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a 2408#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 2409#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 2410#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L 2411#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 2412#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L 2413#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 2414#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 2415#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e 2416#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L 2417#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x0000001f 2418#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L 2419#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x0000001e 2420#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L 2421#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x0000001d 2422#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 2423#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 2424#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L 2425#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 2426#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L 2427#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 2428#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 2429#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b 2430#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 2431#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a 2432#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 2433#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 2434#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 2435#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a 2436#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 2437#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 2438#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L 2439#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x00000013 2440#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L 2441#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x00000014 2442#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L 2443#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0x0000000e 2444#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L 2445#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x0000001f 2446#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L 2447#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x0000001e 2448#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L 2449#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x0000001d 2450#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L 2451#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x00000018 2452#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L 2453#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x00000016 2454#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L 2455#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x00000017 2456#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L 2457#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x0000001b 2458#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L 2459#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x0000001a 2460#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L 2461#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x00000011 2462#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L 2463#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 2464#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L 2465#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 2466#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L 2467#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e 2468#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L 2469#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x0000001f 2470#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L 2471#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x0000001e 2472#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L 2473#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x0000001d 2474#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L 2475#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 2476#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L 2477#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 2478#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L 2479#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x00000017 2480#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L 2481#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b 2482#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x00080000L 2483#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 2484#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L 2485#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 2486#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L 2487#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e 2488#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L 2489#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x0000001f 2490#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L 2491#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x0000001e 2492#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L 2493#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x0000001d 2494#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L 2495#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 2496#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L 2497#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 2498#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L 2499#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x00000017 2500#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L 2501#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b 2502#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L 2503#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x0000001a 2504#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L 2505#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 2506#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L 2507#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 2508#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L 2509#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 2510#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L 2511#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e 2512#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L 2513#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x0000001f 2514#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L 2515#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x0000001e 2516#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L 2517#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x0000001d 2518#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L 2519#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 2520#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L 2521#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 2522#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L 2523#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x00000017 2524#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L 2525#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b 2526#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L 2527#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x0000001a 2528#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L 2529#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 2530#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L 2531#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 2532#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L 2533#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 2534#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L 2535#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e 2536#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L 2537#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x0000001f 2538#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L 2539#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x0000001e 2540#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L 2541#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x0000001d 2542#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L 2543#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 2544#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L 2545#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 2546#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L 2547#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x00000017 2548#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L 2549#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b 2550#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L 2551#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x0000001a 2552#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L 2553#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 2554#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L 2555#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x0000001a 2556#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L 2557#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 2558#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x0000001fL 2559#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x00000000 2560#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L 2561#define CP_ME_CNTL__CE_HALT__SHIFT 0x00000018 2562#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L 2563#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x00000004 2564#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L 2565#define CP_ME_CNTL__CE_STEP__SHIFT 0x00000019 2566#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L 2567#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c 2568#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L 2569#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x00000008 2570#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L 2571#define CP_ME_CNTL__ME_STEP__SHIFT 0x0000001d 2572#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L 2573#define CP_ME_CNTL__PFP_HALT__SHIFT 0x0000001a 2574#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L 2575#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x00000006 2576#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L 2577#define CP_ME_CNTL__PFP_STEP__SHIFT 0x0000001b 2578#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffffL 2579#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x00000000 2580#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x000000ffL 2581#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x00000000 2582#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffcL 2583#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x00000002 2584#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x00000003L 2585#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x00000000 2586#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x000000ffL 2587#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x00000000 2588#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffcL 2589#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x00000002 2590#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x00000003L 2591#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x00000000 2592#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffffL 2593#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x00000000 2594#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffffL 2595#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x00000000 2596#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L 2597#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x00000001 2598#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L 2599#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x00000000 2600#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00ff0000L 2601#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x00000010 2602#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000ff00L 2603#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x00000008 2604#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L 2605#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018 2606#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x000000fcL 2607#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002 2608#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x00000001L 2609#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x00000000 2610#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003ffL 2611#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 2612#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL 2613#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 2614#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L 2615#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 2616#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000ffL 2617#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x00000000 2618#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000ff00L 2619#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x00000008 2620#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL 2621#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 2622#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00000fffL 2623#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 2624#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00000fffL 2625#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 2626#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffffL 2627#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x00000000 2628#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffffL 2629#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x00000000 2630#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffffL 2631#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x00000000 2632#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffffL 2633#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x00000000 2634#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffffL 2635#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x00000000 2636#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffffL 2637#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x00000000 2638#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffffL 2639#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x00000000 2640#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffffL 2641#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x00000000 2642#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffffL 2643#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x00000000 2644#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffffL 2645#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x00000000 2646#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffffL 2647#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x00000000 2648#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffffL 2649#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x00000000 2650#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffffL 2651#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x00000000 2652#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffffL 2653#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x00000000 2654#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffffL 2655#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x00000000 2656#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffffL 2657#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x00000000 2658#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffffL 2659#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x00000000 2660#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffffL 2661#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x00000000 2662#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffffL 2663#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x00000000 2664#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffffL 2665#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x00000000 2666#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L 2667#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 2668#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L 2669#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a 2670#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL 2671#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 2672#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000f0L 2673#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x00000004 2674#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L 2675#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x0000001f 2676#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffffL 2677#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x00000000 2678#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x00000001L 2679#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x00000000 2680#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L 2681#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x00000001 2682#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L 2683#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x00000000 2684#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L 2685#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x00000018 2686#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L 2687#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x00000010 2688#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x00008000L 2689#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0x0000000f 2690#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL 2691#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 2692#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL 2693#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 2694#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffffffffL 2695#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x00000000 2696#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffcL 2697#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x00000002 2698#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x00000003L 2699#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x00000000 2700#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x00000001L 2701#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x00000000 2702#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003fL 2703#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x00000000 2704#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003f00L 2705#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x00000008 2706#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000ffL 2707#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x00000000 2708#define CP_RB0_BASE__RB_BASE_MASK 0xffffffffL 2709#define CP_RB0_BASE__RB_BASE__SHIFT 0x00000000 2710#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00030000L 2711#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x00000010 2712#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L 2713#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x00000018 2714#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L 2715#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 2716#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L 2717#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 2718#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003f00L 2719#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x00000008 2720#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003fL 2721#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x00000000 2722#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L 2723#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b 2724#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L 2725#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f 2726#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x04000000L 2727#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x0000001a 2728#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL 2729#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 2730#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL 2731#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 2732#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L 2733#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 2734#define CP_RB0_RPTR__RB_RPTR_MASK 0x000fffffL 2735#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x00000000 2736#define CP_RB0_WPTR__RB_WPTR_MASK 0x000fffffL 2737#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x00000000 2738#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000ffL 2739#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x00000000 2740#define CP_RB1_BASE__RB_BASE_MASK 0xffffffffL 2741#define CP_RB1_BASE__RB_BASE__SHIFT 0x00000000 2742#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L 2743#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x00000018 2744#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L 2745#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 2746#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L 2747#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 2748#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003f00L 2749#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x00000008 2750#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003fL 2751#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x00000000 2752#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L 2753#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b 2754#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L 2755#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f 2756#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x04000000L 2757#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x0000001a 2758#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL 2759#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 2760#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL 2761#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 2762#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L 2763#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 2764#define CP_RB1_RPTR__RB_RPTR_MASK 0x000fffffL 2765#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x00000000 2766#define CP_RB1_WPTR__RB_WPTR_MASK 0x000fffffL 2767#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x00000000 2768#define CP_RB2_BASE__RB_BASE_MASK 0xffffffffL 2769#define CP_RB2_BASE__RB_BASE__SHIFT 0x00000000 2770#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x03000000L 2771#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x00000018 2772#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L 2773#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 2774#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L 2775#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 2776#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003f00L 2777#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x00000008 2778#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003fL 2779#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x00000000 2780#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L 2781#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b 2782#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L 2783#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f 2784#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x04000000L 2785#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x0000001a 2786#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL 2787#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 2788#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL 2789#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 2790#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L 2791#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 2792#define CP_RB2_RPTR__RB_RPTR_MASK 0x000fffffL 2793#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x00000000 2794#define CP_RB2_WPTR__RB_WPTR_MASK 0x000fffffL 2795#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x00000000 2796#define CP_RB_BASE__RB_BASE_MASK 0xffffffffL 2797#define CP_RB_BASE__RB_BASE__SHIFT 0x00000000 2798#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L 2799#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 2800#define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L 2801#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x00000018 2802#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L 2803#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 2804#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L 2805#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 2806#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L 2807#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 2808#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL 2809#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 2810#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L 2811#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b 2812#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L 2813#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f 2814#define CP_RB_CNTL__RB_VOLATILE_MASK 0x04000000L 2815#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x0000001a 2816#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000fffffL 2817#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x00000000 2818#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL 2819#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 2820#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL 2821#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 2822#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L 2823#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 2824#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL 2825#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 2826#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL 2827#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 2828#define CP_RB_VMID__RB0_VMID_MASK 0x0000000fL 2829#define CP_RB_VMID__RB0_VMID__SHIFT 0x00000000 2830#define CP_RB_VMID__RB1_VMID_MASK 0x00000f00L 2831#define CP_RB_VMID__RB1_VMID__SHIFT 0x00000008 2832#define CP_RB_VMID__RB2_VMID_MASK 0x000f0000L 2833#define CP_RB_VMID__RB2_VMID__SHIFT 0x00000010 2834#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L 2835#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c 2836#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL 2837#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 2838#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0x000000ffL 2839#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x00000000 2840#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x000000ffL 2841#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x00000000 2842#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffcL 2843#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x00000002 2844#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffcL 2845#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x00000002 2846#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L 2847#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 2848#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000ffffL 2849#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x00000000 2850#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL 2851#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 2852#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L 2853#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x00000000 2854#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L 2855#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x00000000 2856#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L 2857#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x00000000 2858#define CP_RINGID__RINGID_MASK 0x00000003L 2859#define CP_RINGID__RINGID__SHIFT 0x00000000 2860#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000ffL 2861#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x00000000 2862#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000ff00L 2863#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x00000008 2864#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00ff0000L 2865#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x00000010 2866#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000L 2867#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x00000018 2868#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00ff0000L 2869#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x00000010 2870#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000L 2871#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x00000018 2872#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000ffL 2873#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x00000000 2874#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000ff00L 2875#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x00000008 2876#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007ffL 2877#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x00000000 2878#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000ff00L 2879#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x00000008 2880#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00ff0000L 2881#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x00000010 2882#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000ffL 2883#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x00000000 2884#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000L 2885#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x00000018 2886#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07ff0000L 2887#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x00000010 2888#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007ffL 2889#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x00000000 2890#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003ffL 2891#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x00000000 2892#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03ff0000L 2893#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x00000010 2894#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003ffL 2895#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x00000000 2896#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03ff0000L 2897#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x00000010 2898#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003ffL 2899#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x00000000 2900#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03ff0000L 2901#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x00000010 2902#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffffL 2903#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x00000000 2904#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffffL 2905#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x00000000 2906#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffffL 2907#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x00000000 2908#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffffL 2909#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x00000000 2910#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffffL 2911#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x00000000 2912#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000ffL 2913#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x00000000 2914#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffffL 2915#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x00000000 2916#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x000000ffL 2917#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000 2918#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L 2919#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018 2920#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L 2921#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d 2922#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L 2923#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014 2924#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L 2925#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010 2926#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L 2927#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003 2928#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L 2929#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000 2930#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L 2931#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0x0000000a 2932#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L 2933#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0x0000000b 2934#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L 2935#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x0000000d 2936#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L 2937#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x0000000c 2938#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x00004000L 2939#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0x0000000e 2940#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L 2941#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0x0000000f 2942#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x00010000L 2943#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x00000010 2944#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x00020000L 2945#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x00000011 2946#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L 2947#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x00000000 2948#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L 2949#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x00000004 2950#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L 2951#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x00000002 2952#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x10000000L 2953#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x0000001c 2954#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L 2955#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x0000001c 2956#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L 2957#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x0000001b 2958#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L 2959#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x0000001a 2960#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L 2961#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x00000017 2962#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L 2963#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x00000018 2964#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L 2965#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x00000019 2966#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L 2967#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x0000001c 2968#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L 2969#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x00000019 2970#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L 2971#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x0000001a 2972#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L 2973#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x0000001d 2974#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L 2975#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x0000001b 2976#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L 2977#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x00000015 2978#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L 2979#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x00000016 2980#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L 2981#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0x0000000b 2982#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L 2983#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000010 2984#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L 2985#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0x0000000c 2986#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L 2987#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0x0000000d 2988#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L 2989#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0x0000000e 2990#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L 2991#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x00000012 2992#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L 2993#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0x0000000f 2994#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L 2995#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0x0000000a 2996#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L 2997#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x00000009 2998#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x00000040L 2999#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x00000006 3000#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L 3001#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x00000005 3002#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L 3003#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x00000014 3004#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L 3005#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x00000013 3006#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L 3007#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000 3008#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L 3009#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x00000001 3010#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x00000080L 3011#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x00000007 3012#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L 3013#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x00000002 3014#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L 3015#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x00000004 3016#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L 3017#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x00000008 3018#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L 3019#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x00000018 3020#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L 3021#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000011 3022#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L 3023#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x00000017 3024#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L 3025#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x0000001f 3026#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L 3027#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x0000001e 3028#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L 3029#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000 3030#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L 3031#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000006 3032#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x00000100L 3033#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x00000008 3034#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L 3035#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x00000004 3036#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L 3037#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x00000001 3038#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L 3039#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x00000003 3040#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L 3041#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x00000005 3042#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L 3043#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000007 3044#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L 3045#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0x0000000a 3046#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L 3047#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0x0000000b 3048#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L 3049#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x00000002 3050#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L 3051#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0x0000000c 3052#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L 3053#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0x0000000d 3054#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L 3055#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0x0000000e 3056#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L 3057#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0x0000000f 3058#define CP_STAT__CE_BUSY_MASK 0x04000000L 3059#define CP_STAT__CE_BUSY__SHIFT 0x0000001a 3060#define CP_STAT__CP_BUSY_MASK 0x80000000L 3061#define CP_STAT__CP_BUSY__SHIFT 0x0000001f 3062#define CP_STAT__CPC_CPG_BUSY_MASK 0x02000000L 3063#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x00000019 3064#define CP_STAT__DC_BUSY_MASK 0x00002000L 3065#define CP_STAT__DC_BUSY__SHIFT 0x0000000d 3066#define CP_STAT__DMA_BUSY_MASK 0x00400000L 3067#define CP_STAT__DMA_BUSY__SHIFT 0x00000016 3068#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L 3069#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x00000014 3070#define CP_STAT__ME_BUSY_MASK 0x00020000L 3071#define CP_STAT__ME_BUSY__SHIFT 0x00000011 3072#define CP_STAT__MEQ_BUSY_MASK 0x00010000L 3073#define CP_STAT__MEQ_BUSY__SHIFT 0x00000010 3074#define CP_STAT__MIU_RDREQ_BUSY_MASK 0x00000080L 3075#define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x00000007 3076#define CP_STAT__MIU_WRREQ_BUSY_MASK 0x00000100L 3077#define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x00000008 3078#define CP_STAT__PFP_BUSY_MASK 0x00008000L 3079#define CP_STAT__PFP_BUSY__SHIFT 0x0000000f 3080#define CP_STAT__QUERY_BUSY_MASK 0x00040000L 3081#define CP_STAT__QUERY_BUSY__SHIFT 0x00000012 3082#define CP_STAT__RCIU_BUSY_MASK 0x00800000L 3083#define CP_STAT__RCIU_BUSY__SHIFT 0x00000017 3084#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L 3085#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x0000001d 3086#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L 3087#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x0000001e 3088#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L 3089#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x0000001c 3090#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L 3091#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0x0000000a 3092#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L 3093#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0x0000000b 3094#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L 3095#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x00000009 3096#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L 3097#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0x0000000c 3098#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L 3099#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x00000018 3100#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L 3101#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x00000013 3102#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L 3103#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x00000015 3104#define CP_STAT__TCIU_BUSY_MASK 0x08000000L 3105#define CP_STAT__TCIU_BUSY__SHIFT 0x0000001b 3106#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x000000ffL 3107#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x00000000 3108#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffcL 3109#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x00000002 3110#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL 3111#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 3112#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001ffL 3113#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x00000000 3114#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003ffL 3115#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x00000000 3116#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000ffL 3117#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x00000000 3118#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000ff00L 3119#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x00000008 3120#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00ff0000L 3121#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x00000010 3122#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffffffffL 3123#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x00000000 3124#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffcL 3125#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x00000002 3126#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x00000003L 3127#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x00000000 3128#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L 3129#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x00000000 3130#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffffL 3131#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x00000000 3132#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffffL 3133#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x00000000 3134#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffffL 3135#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x00000000 3136#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffffL 3137#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x00000000 3138#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffffL 3139#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x00000000 3140#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffffL 3141#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x00000000 3142#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffffL 3143#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x00000000 3144#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffffL 3145#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x00000000 3146#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffffL 3147#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x00000000 3148#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffffL 3149#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x00000000 3150#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffffL 3151#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x00000000 3152#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffffL 3153#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x00000000 3154#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffffL 3155#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x00000000 3156#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffffL 3157#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x00000000 3158#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffffL 3159#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x00000000 3160#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffffL 3161#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x00000000 3162#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000ffffL 3163#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x00000000 3164#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000L 3165#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x00000010 3166#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000ffffL 3167#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x00000000 3168#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000L 3169#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x00000010 3170#define CP_VMID__VMID_MASK 0x0000000fL 3171#define CP_VMID__VMID__SHIFT 0x00000000 3172#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffffL 3173#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x00000000 3174#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x000000ffL 3175#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000 3176#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L 3177#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018 3178#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L 3179#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d 3180#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L 3181#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014 3182#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L 3183#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010 3184#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L 3185#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003 3186#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L 3187#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000 3188#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L 3189#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 3190#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L 3191#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000000 3192#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L 3193#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000008 3194#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000c00L 3195#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000000a 3196#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L 3197#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000000c 3198#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000c000L 3199#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000000e 3200#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L 3201#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x00000010 3202#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000ff0L 3203#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x00000004 3204#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000fL 3205#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x00000000 3206#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x00fff000L 3207#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0x0000000c 3208#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L 3209#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x0000001f 3210#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L 3211#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x0000001e 3212#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L 3213#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x0000001d 3214#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L 3215#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x0000001c 3216#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L 3217#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x0000001b 3218#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L 3219#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x0000001a 3220#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L 3221#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x00000019 3222#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L 3223#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x00000018 3224#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00f00000L 3225#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x00000014 3226#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L 3227#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x00000001 3228#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L 3229#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x00000004 3230#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000f0000L 3231#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x00000010 3232#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0f000000L 3233#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x00000018 3234#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000L 3235#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x0000001c 3236#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000f000L 3237#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0x0000000c 3238#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000f00L 3239#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x00000008 3240#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L 3241#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x00000000 3242#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001c00L 3243#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0x0000000a 3244#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000L 3245#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x00000018 3246#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003e0L 3247#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x00000005 3248#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001fL 3249#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x00000000 3250#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L 3251#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x00000000 3252#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003e00L 3253#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x00000009 3254#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L 3255#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x00000012 3256#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L 3257#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x00000010 3258#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L 3259#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x00000011 3260#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x00000100L 3261#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x00000008 3262#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x00000020L 3263#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x00000080L 3264#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x00000007 3265#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x00000005 3266#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L 3267#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x0000001d 3268#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L 3269#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x00000013 3270#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x80000000L 3271#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x0000001f 3272#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L 3273#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x00000002 3274#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L 3275#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x00000001 3276#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L 3277#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0x0000000e 3278#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L 3279#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x0000001f 3280#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L 3281#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x00000004 3282#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L 3283#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x00000003 3284#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x00000040L 3285#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x00000006 3286#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L 3287#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x0000001c 3288#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L 3289#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0x0000000f 3290#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00020000L 3291#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x00000011 3292#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xfc000000L 3293#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x0000001a 3294#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L 3295#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x00000019 3296#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L 3297#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x00000018 3298#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L 3299#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x00000004 3300#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00200000L 3301#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x00000015 3302#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00004000L 3303#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0x0000000e 3304#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00010000L 3305#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0x00000010 3306#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00008000L 3307#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0x0000000f 3308#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00080000L 3309#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x00000013 3310#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00002000L 3311#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0x0000000d 3312#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L 3313#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x0000001b 3314#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L 3315#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x00000017 3316#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000800L 3317#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0x0000000b 3318#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000400L 3319#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x0000000a 3320#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L 3321#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x00000007 3322#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00100000L 3323#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x00000014 3324#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L 3325#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x00000003 3326#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L 3327#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x00000008 3328#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L 3329#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x0000001d 3330#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L 3331#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x0000001c 3332#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L 3333#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x0000001a 3334#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00001000L 3335#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0x0000000c 3336#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00400000L 3337#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x00000016 3338#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00800000L 3339#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x00000017 3340#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L 3341#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x00000005 3342#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L 3343#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x00000006 3344#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L 3345#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x00000002 3346#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00040000L 3347#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x00000012 3348#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xffffffc0L 3349#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x00000006 3350#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000020L 3351#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x00000005 3352#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L 3353#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x00000001 3354#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L 3355#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x00000000 3356#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L 3357#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x00000002 3358#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L 3359#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x00000001 3360#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L 3361#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0x0000000f 3362#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L 3363#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0x0000000e 3364#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L 3365#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x00000006 3366#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L 3367#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x00000013 3368#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000c00L 3369#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0x0000000a 3370#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L 3371#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0x0000000c 3372#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L 3373#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x00000008 3374#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L 3375#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x00000007 3376#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L 3377#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x00000010 3378#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L 3379#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x00000000 3380#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0f000000L 3381#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x00000018 3382#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L 3383#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x00000012 3384#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L 3385#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x0000001e 3386#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L 3387#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x0000001f 3388#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L 3389#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x00000011 3390#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L 3391#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x00000017 3392#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L 3393#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x00000003 3394#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L 3395#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x00000002 3396#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L 3397#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x0000001d 3398#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L 3399#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x00000004 3400#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L 3401#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x00000015 3402#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L 3403#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x0000001c 3404#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L 3405#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x00000016 3406#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffffL 3407#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x00000000 3408#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffffL 3409#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x00000000 3410#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL 3411#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 3412#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L 3413#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 3414#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L 3415#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x00000003 3416#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L 3417#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x0000001f 3418#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L 3419#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x0000001e 3420#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L 3421#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x00000000 3422#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L 3423#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x00000014 3424#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L 3425#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x00000008 3426#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L 3427#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x00000001 3428#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L 3429#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x00000004 3430#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L 3431#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 3432#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0x0000000fL 3433#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x00000000 3434#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0x000000f0L 3435#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x00000004 3436#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x00018000L 3437#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0x0000000f 3438#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x00006000L 3439#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0x0000000d 3440#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x00060000L 3441#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x00000011 3442#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x00180000L 3443#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x00000013 3444#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x00001f00L 3445#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x00000008 3446#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x003ff800L 3447#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0x0000000b 3448#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x000007ffL 3449#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x00000000 3450#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x003fffffL 3451#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x00000000 3452#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00ffe000L 3453#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0x0000000d 3454#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007ffL 3455#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x00000000 3456#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L 3457#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x00000019 3458#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L 3459#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x00000018 3460#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L 3461#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x00000015 3462#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L 3463#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0x0000000c 3464#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L 3465#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x0000001b 3466#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L 3467#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x00000010 3468#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L 3469#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x00000011 3470#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L 3471#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x00000012 3472#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L 3473#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x00000013 3474#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L 3475#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x00000008 3476#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L 3477#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x00000000 3478#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L 3479#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x00000018 3480#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L 3481#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x00000004 3482#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L 3483#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x00000014 3484#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000L 3485#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x00000015 3486#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000fc00L 3487#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x0000000a 3488#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x0000001fL 3489#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x00000000 3490#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x000003e0L 3491#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x00000005 3492#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001f0000L 3493#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x00000010 3494#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000ffL 3495#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x00000000 3496#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007f00L 3497#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x00000008 3498#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01ff8000L 3499#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x0000000f 3500#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000L 3501#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x00000019 3502#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007fL 3503#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x00000000 3504#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x01e00000L 3505#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x00000015 3506#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003f80L 3507#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x00000007 3508#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x001fc000L 3509#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x0000000e 3510#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000L 3511#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x00000019 3512#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffffL 3513#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x00000000 3514#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L 3515#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x00000010 3516#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L 3517#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x00000001 3518#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L 3519#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x00000002 3520#define DB_HTILE_SURFACE__LINEAR_MASK 0x00000001L 3521#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x00000000 3522#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000fc00L 3523#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0x0000000a 3524#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003f0L 3525#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x00000004 3526#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L 3527#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x00000003 3528#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 3529#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 3530#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 3531#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 3532#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L 3533#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c 3534#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L 3535#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 3536#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL 3537#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 3538#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L 3539#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 3540#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 3541#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 3542#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L 3543#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 3544#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L 3545#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c 3546#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L 3547#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a 3548#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL 3549#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 3550#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 3551#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 3552#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 3553#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 3554#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L 3555#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c 3556#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L 3557#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 3558#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL 3559#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 3560#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L 3561#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a 3562#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L 3563#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 3564#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L 3565#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 3566#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L 3567#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c 3568#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L 3569#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a 3570#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL 3571#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 3572#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 3573#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 3574#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 3575#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 3576#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L 3577#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 3578#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0f000000L 3579#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x00000018 3580#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L 3581#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c 3582#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000ffc00L 3583#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a 3584#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL 3585#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 3586#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 3587#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 3588#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 3589#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 3590#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L 3591#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 3592#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0f000000L 3593#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x00000018 3594#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L 3595#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c 3596#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000ffc00L 3597#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0x0000000a 3598#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL 3599#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 3600#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00ff0000L 3601#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x00000010 3602#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000L 3603#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x00000018 3604#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000ffL 3605#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x00000000 3606#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000ff00L 3607#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x00000008 3608#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffffL 3609#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x00000000 3610#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffffL 3611#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x00000000 3612#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffffL 3613#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x00000000 3614#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffffL 3615#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x00000000 3616#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffffL 3617#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x00000000 3618#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffffL 3619#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x00000000 3620#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffffL 3621#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x00000000 3622#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffffL 3623#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x00000000 3624#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffffL 3625#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x00000000 3626#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffffL 3627#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x00000000 3628#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffffL 3629#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x00000000 3630#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffffL 3631#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x00000000 3632#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffffL 3633#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x00000000 3634#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffffL 3635#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x00000000 3636#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffffL 3637#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x00000000 3638#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffffL 3639#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x00000000 3640#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L 3641#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x00000007 3642#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000f00L 3643#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x00000008 3644#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L 3645#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000000 3646#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L 3647#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x00000006 3648#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L 3649#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x00000002 3650#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L 3651#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x00000004 3652#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L 3653#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x00000001 3654#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L 3655#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x00000005 3656#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L 3657#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x00000003 3658#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L 3659#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x00000008 3660#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L 3661#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0x0000000a 3662#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L 3663#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x00000007 3664#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L 3665#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x00000017 3666#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L 3667#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x00000009 3668#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L 3669#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000006 3670#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L 3671#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000005 3672#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001c0000L 3673#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x00000012 3674#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L 3675#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0x0000000f 3676#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L 3677#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0x0000000c 3678#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L 3679#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x00000000 3680#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001cL 3681#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x00000002 3682#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L 3683#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x00000016 3684#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L 3685#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x00000015 3686#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L 3687#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0x0000000b 3688#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L 3689#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x00000012 3690#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L 3691#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x0000001a 3692#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L 3693#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x00000010 3694#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L 3695#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x00000008 3696#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L 3697#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x00000007 3698#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L 3699#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0x0000000a 3700#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L 3701#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0x0000000d 3702#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000cL 3703#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x00000002 3704#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L 3705#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x00000004 3706#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L 3707#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x00000000 3708#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L 3709#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0x0000000f 3710#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L 3711#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x00000006 3712#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L 3713#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x0000001c 3714#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L 3715#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0x0000000c 3716#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L 3717#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x0000001e 3718#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L 3719#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x0000001b 3720#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L 3721#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x00000013 3722#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L 3723#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0x0000000b 3724#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L 3725#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x0000001d 3726#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L 3727#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x00000011 3728#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03e00000L 3729#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x00000015 3730#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L 3731#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x00000009 3732#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L 3733#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x0000001f 3734#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L 3735#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0x0000000b 3736#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L 3737#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0x0000000d 3738#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L 3739#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x00000007 3740#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L 3741#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0x0000000c 3742#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L 3743#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x00000009 3744#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L 3745#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0x0000000a 3746#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L 3747#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x00000006 3748#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L 3749#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x00000008 3750#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L 3751#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x00000002 3752#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L 3753#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x00000001 3754#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L 3755#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x00000000 3756#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L 3757#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x00000004 3758#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L 3759#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x00000000 3760#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000ff000L 3761#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0x0000000c 3762#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000ff0L 3763#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x00000004 3764#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L 3765#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x00000018 3766#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L 3767#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x00000000 3768#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000ff000L 3769#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0x0000000c 3770#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000ff0L 3771#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x00000004 3772#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L 3773#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x00000018 3774#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000ffL 3775#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x00000000 3776#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000f000L 3777#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0x0000000c 3778#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000fL 3779#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x00000000 3780#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00f00000L 3781#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x00000014 3782#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000f00L 3783#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x00000008 3784#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000f0000L 3785#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x00000010 3786#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000f0L 3787#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x00000004 3788#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L 3789#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b 3790#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L 3791#define DB_STENCIL_INFO__FORMAT__SHIFT 0x00000000 3792#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x00700000L 3793#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x00000014 3794#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0x0000e000L 3795#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0x0000000d 3796#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L 3797#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x0000001d 3798#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffffL 3799#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x00000000 3800#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L 3801#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 3802#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000L 3803#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x00000018 3804#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000ffL 3805#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x00000000 3806#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L 3807#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 3808#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L 3809#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 3810#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000L 3811#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x00000018 3812#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000ffL 3813#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x00000000 3814#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L 3815#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 3816#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffffL 3817#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x00000000 3818#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L 3819#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x00000010 3820#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000c0000L 3821#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x00000012 3822#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L 3823#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x00000000 3824#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000cL 3825#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x00000002 3826#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L 3827#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x00000004 3828#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000c0L 3829#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x00000006 3830#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L 3831#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x00000008 3832#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000c00L 3833#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0x0000000a 3834#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L 3835#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0x0000000c 3836#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000c000L 3837#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0x0000000e 3838#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L 3839#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x0000001e 3840#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L 3841#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x0000001f 3842#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x07f00000L 3843#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x00000014 3844#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007e0L 3845#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x00000005 3846#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001fL 3847#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x00000000 3848#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000f8000L 3849#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x0000000f 3850#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x08000000L 3851#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x0000001b 3852#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L 3853#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0x0000000b 3854#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000L 3855#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x0000001c 3856#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000L 3857#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x0000001d 3858#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L 3859#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b 3860#define DB_Z_INFO__FORMAT_MASK 0x00000003L 3861#define DB_Z_INFO__FORMAT__SHIFT 0x00000000 3862#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000cL 3863#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x00000002 3864#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L 3865#define DB_Z_INFO__READ_SIZE__SHIFT 0x0000001c 3866#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x00700000L 3867#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x00000014 3868#define DB_Z_INFO__TILE_SPLIT_MASK 0x0000e000L 3869#define DB_Z_INFO__TILE_SPLIT__SHIFT 0x0000000d 3870#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L 3871#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x0000001d 3872#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L 3873#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x0000001f 3874#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffffL 3875#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x00000000 3876#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffffL 3877#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x00000000 3878#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffffL 3879#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x00000000 3880#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffffL 3881#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x00000000 3882#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffffL 3883#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x00000000 3884#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x0003ffffL 3885#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x00000000 3886#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 3887#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 3888#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 3889#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 3890#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L 3891#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 3892#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 3893#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e 3894#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 3895#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 3896#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L 3897#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c 3898#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 3899#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 3900#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 3901#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c 3902#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 3903#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 3904#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffffL 3905#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x00000000 3906#define GB_EDC_MODE__BYPASS_MASK 0x80000000L 3907#define GB_EDC_MODE__BYPASS__SHIFT 0x0000001f 3908#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L 3909#define GB_EDC_MODE__DED_MODE__SHIFT 0x00000014 3910#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00010000L 3911#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x00000010 3912#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L 3913#define GB_EDC_MODE__PROP_FED__SHIFT 0x0000001d 3914#define GB_GPU_ID__GPU_ID_MASK 0x0000000fL 3915#define GB_GPU_ID__GPU_ID__SHIFT 0x00000000 3916#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003cL 3917#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x00000002 3918#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 3919#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 3920#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007c0L 3921#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x00000006 3922#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L 3923#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x00000019 3924#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L 3925#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0x0000000b 3926#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003cL 3927#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x00000002 3928#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 3929#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 3930#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007c0L 3931#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x00000006 3932#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L 3933#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x00000019 3934#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L 3935#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0x0000000b 3936#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003cL 3937#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x00000002 3938#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 3939#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 3940#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007c0L 3941#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x00000006 3942#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L 3943#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x00000019 3944#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L 3945#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0x0000000b 3946#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003cL 3947#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x00000002 3948#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 3949#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 3950#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007c0L 3951#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x00000006 3952#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L 3953#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x00000019 3954#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L 3955#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0x0000000b 3956#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003cL 3957#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x00000002 3958#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 3959#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 3960#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007c0L 3961#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x00000006 3962#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L 3963#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x00000019 3964#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L 3965#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0x0000000b 3966#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003cL 3967#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x00000002 3968#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 3969#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 3970#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007c0L 3971#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x00000006 3972#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L 3973#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x00000019 3974#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L 3975#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0x0000000b 3976#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003cL 3977#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x00000002 3978#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 3979#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 3980#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007c0L 3981#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x00000006 3982#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L 3983#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x00000019 3984#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L 3985#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0x0000000b 3986#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003cL 3987#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x00000002 3988#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 3989#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 3990#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007c0L 3991#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x00000006 3992#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L 3993#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x00000019 3994#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L 3995#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0x0000000b 3996#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003cL 3997#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x00000002 3998#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 3999#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4000#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007c0L 4001#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x00000006 4002#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L 4003#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x00000019 4004#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L 4005#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0x0000000b 4006#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003cL 4007#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x00000002 4008#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4009#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4010#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007c0L 4011#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x00000006 4012#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L 4013#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x00000019 4014#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L 4015#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0x0000000b 4016#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003cL 4017#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x00000002 4018#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4019#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4020#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007c0L 4021#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x00000006 4022#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L 4023#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x00000019 4024#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L 4025#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0x0000000b 4026#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003cL 4027#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x00000002 4028#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4029#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4030#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007c0L 4031#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x00000006 4032#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L 4033#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x00000019 4034#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L 4035#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0x0000000b 4036#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003cL 4037#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x00000002 4038#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4039#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4040#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007c0L 4041#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x00000006 4042#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L 4043#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x00000019 4044#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L 4045#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0x0000000b 4046#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003cL 4047#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x00000002 4048#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4049#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4050#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007c0L 4051#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x00000006 4052#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L 4053#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x00000019 4054#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L 4055#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0x0000000b 4056#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003cL 4057#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x00000002 4058#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4059#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4060#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007c0L 4061#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x00000006 4062#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L 4063#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x00000019 4064#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L 4065#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0x0000000b 4066#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003cL 4067#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x00000002 4068#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4069#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4070#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007c0L 4071#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x00000006 4072#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L 4073#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x00000019 4074#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L 4075#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0x0000000b 4076#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003cL 4077#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x00000002 4078#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4079#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4080#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007c0L 4081#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x00000006 4082#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L 4083#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x00000019 4084#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L 4085#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0x0000000b 4086#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003cL 4087#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x00000002 4088#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4089#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4090#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007c0L 4091#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x00000006 4092#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L 4093#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x00000019 4094#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L 4095#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0x0000000b 4096#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003cL 4097#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x00000002 4098#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4099#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4100#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007c0L 4101#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x00000006 4102#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L 4103#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x00000019 4104#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L 4105#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0x0000000b 4106#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003cL 4107#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x00000002 4108#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4109#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4110#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007c0L 4111#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x00000006 4112#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L 4113#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x00000019 4114#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L 4115#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0x0000000b 4116#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003cL 4117#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x00000002 4118#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4119#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4120#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007c0L 4121#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x00000006 4122#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L 4123#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x00000019 4124#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L 4125#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0x0000000b 4126#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003cL 4127#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x00000002 4128#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4129#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4130#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007c0L 4131#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x00000006 4132#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L 4133#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x00000019 4134#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L 4135#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0x0000000b 4136#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003cL 4137#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x00000002 4138#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4139#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4140#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007c0L 4141#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x00000006 4142#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L 4143#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x00000019 4144#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L 4145#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0x0000000b 4146#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003cL 4147#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x00000002 4148#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4149#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4150#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007c0L 4151#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x00000006 4152#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L 4153#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x00000019 4154#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L 4155#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0x0000000b 4156#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003cL 4157#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x00000002 4158#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4159#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4160#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007c0L 4161#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x00000006 4162#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L 4163#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x00000019 4164#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L 4165#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0x0000000b 4166#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003cL 4167#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x00000002 4168#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4169#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4170#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007c0L 4171#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x00000006 4172#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L 4173#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x00000019 4174#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L 4175#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0x0000000b 4176#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003cL 4177#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x00000002 4178#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4179#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4180#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007c0L 4181#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x00000006 4182#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L 4183#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x00000019 4184#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L 4185#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0x0000000b 4186#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003cL 4187#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x00000002 4188#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4189#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4190#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007c0L 4191#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x00000006 4192#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L 4193#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x00000019 4194#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L 4195#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0x0000000b 4196#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003cL 4197#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x00000002 4198#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4199#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4200#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007c0L 4201#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x00000006 4202#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L 4203#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x00000019 4204#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L 4205#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0x0000000b 4206#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003cL 4207#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x00000002 4208#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4209#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4210#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007c0L 4211#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x00000006 4212#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L 4213#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x00000019 4214#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L 4215#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0x0000000b 4216#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003cL 4217#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x00000002 4218#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4219#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4220#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007c0L 4221#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x00000006 4222#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L 4223#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x00000019 4224#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L 4225#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0x0000000b 4226#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003cL 4227#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x00000002 4228#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01c00000L 4229#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 4230#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007c0L 4231#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x00000006 4232#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L 4233#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x00000019 4234#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L 4235#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0x0000000b 4236#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L 4237#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 4238#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x00000006L 4239#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x00000001 4240#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x00000010L 4241#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x00000004 4242#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L 4243#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010 4244#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L 4245#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003 4246#define GDS_ATOM_BASE__BASE_MASK 0x0000ffffL 4247#define GDS_ATOM_BASE__BASE__SHIFT 0x00000000 4248#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000L 4249#define GDS_ATOM_BASE__UNUSED__SHIFT 0x00000010 4250#define GDS_ATOM_CNTL__AINC_MASK 0x0000003fL 4251#define GDS_ATOM_CNTL__AINC__SHIFT 0x00000000 4252#define GDS_ATOM_CNTL__DMODE_MASK 0x00000100L 4253#define GDS_ATOM_CNTL__DMODE__SHIFT 0x00000008 4254#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000c0L 4255#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x00000006 4256#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffe00L 4257#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0x00000009 4258#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L 4259#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x00000000 4260#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffeL 4261#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x00000001 4262#define GDS_ATOM_DST__DST_MASK 0xffffffffL 4263#define GDS_ATOM_DST__DST__SHIFT 0x00000000 4264#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000ffL 4265#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x00000000 4266#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00L 4267#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x00000008 4268#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000ffL 4269#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x00000000 4270#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00L 4271#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x00000008 4272#define GDS_ATOM_OP__OP_MASK 0x000000ffL 4273#define GDS_ATOM_OP__OP__SHIFT 0x00000000 4274#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00L 4275#define GDS_ATOM_OP__UNUSED__SHIFT 0x00000008 4276#define GDS_ATOM_READ0__DATA_MASK 0xffffffffL 4277#define GDS_ATOM_READ0__DATA__SHIFT 0x00000000 4278#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffffL 4279#define GDS_ATOM_READ0_U__DATA__SHIFT 0x00000000 4280#define GDS_ATOM_READ1__DATA_MASK 0xffffffffL 4281#define GDS_ATOM_READ1__DATA__SHIFT 0x00000000 4282#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffffL 4283#define GDS_ATOM_READ1_U__DATA__SHIFT 0x00000000 4284#define GDS_ATOM_SIZE__SIZE_MASK 0x0000ffffL 4285#define GDS_ATOM_SIZE__SIZE__SHIFT 0x00000000 4286#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000L 4287#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x00000010 4288#define GDS_ATOM_SRC0__DATA_MASK 0xffffffffL 4289#define GDS_ATOM_SRC0__DATA__SHIFT 0x00000000 4290#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffffL 4291#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x00000000 4292#define GDS_ATOM_SRC1__DATA_MASK 0xffffffffL 4293#define GDS_ATOM_SRC1__DATA__SHIFT 0x00000000 4294#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffffL 4295#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x00000000 4296#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L 4297#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x00000004 4298#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L 4299#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x00000003 4300#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L 4301#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x00000006 4302#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L 4303#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x00000005 4304#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L 4305#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x00000000 4306#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L 4307#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x00000001 4308#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L 4309#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x00000002 4310#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L 4311#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x00000001 4312#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L 4313#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x00000003 4314#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L 4315#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x00000005 4316#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L 4317#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x00000007 4318#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x0000001fL 4319#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x00000000 4320#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0L 4321#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x00000005 4322#define GDS_DEBUG_DATA__DATA_MASK 0xffffffffL 4323#define GDS_DEBUG_DATA__DATA__SHIFT 0x00000000 4324#define GDS_DEBUG_REG0__buff_write_MASK 0x00020000L 4325#define GDS_DEBUG_REG0__buff_write__SHIFT 0x00000011 4326#define GDS_DEBUG_REG0__cstate_MASK 0x0001e000L 4327#define GDS_DEBUG_REG0__cstate__SHIFT 0x0000000d 4328#define GDS_DEBUG_REG0__flush_request_MASK 0x00040000L 4329#define GDS_DEBUG_REG0__flush_request__SHIFT 0x00000012 4330#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x00001000L 4331#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0x0000000c 4332#define GDS_DEBUG_REG0__spare1_MASK 0x00000001L 4333#define GDS_DEBUG_REG0__spare1__SHIFT 0x00000000 4334#define GDS_DEBUG_REG0__spare_MASK 0xff000000L 4335#define GDS_DEBUG_REG0__spare__SHIFT 0x00000018 4336#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x00100000L 4337#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x00000014 4338#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x00200000L 4339#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x00000015 4340#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x00080000L 4341#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x00000013 4342#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x00000040L 4343#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x00000006 4344#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0x00000f80L 4345#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x00000007 4346#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x00200000L 4347#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x00000015 4348#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x00100000L 4349#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x00000014 4350#define GDS_DEBUG_REG1__awaiting_data_MASK 0x00080000L 4351#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x00000013 4352#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x00800000L 4353#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x00000017 4354#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x00400000L 4355#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x00000016 4356#define GDS_DEBUG_REG1__data_ready_MASK 0x00040000L 4357#define GDS_DEBUG_REG1__data_ready__SHIFT 0x00000012 4358#define GDS_DEBUG_REG1__pixel_addr_MASK 0x0001fffcL 4359#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x00000002 4360#define GDS_DEBUG_REG1__pixel_vld_MASK 0x00020000L 4361#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x00000011 4362#define GDS_DEBUG_REG1__spare_MASK 0xff000000L 4363#define GDS_DEBUG_REG1__spare__SHIFT 0x00000018 4364#define GDS_DEBUG_REG1__tag_hit_MASK 0x00000001L 4365#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x00000000 4366#define GDS_DEBUG_REG1__tag_miss_MASK 0x00000002L 4367#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x00000001 4368#define GDS_DEBUG_REG2__app_sel_MASK 0x000000f0L 4369#define GDS_DEBUG_REG2__app_sel__SHIFT 0x00000004 4370#define GDS_DEBUG_REG2__cmd_write_MASK 0x00000008L 4371#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x00000003 4372#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x00000002L 4373#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x00000001 4374#define GDS_DEBUG_REG2__ds_full_MASK 0x00000001L 4375#define GDS_DEBUG_REG2__ds_full__SHIFT 0x00000000 4376#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x00000004L 4377#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x00000002 4378#define GDS_DEBUG_REG2__req_MASK 0x007fff00L 4379#define GDS_DEBUG_REG2__req__SHIFT 0x00000008 4380#define GDS_DEBUG_REG2__spare_MASK 0xff000000L 4381#define GDS_DEBUG_REG2__spare__SHIFT 0x00000018 4382#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x00007800L 4383#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0x0000000b 4384#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x000007ffL 4385#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x00000000 4386#define GDS_DEBUG_REG3__spare_MASK 0xff000000L 4387#define GDS_DEBUG_REG3__spare__SHIFT 0x00000018 4388#define GDS_DEBUG_REG4__cmd_write_MASK 0x00020000L 4389#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x00000011 4390#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x00010000L 4391#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x00000010 4392#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x00002000L 4393#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0x0000000d 4394#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x00008000L 4395#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0x0000000f 4396#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x00001000L 4397#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0x0000000c 4398#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x00004000L 4399#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0x0000000e 4400#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x00000400L 4401#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0x0000000a 4402#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x00000800L 4403#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0x0000000b 4404#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x00000200L 4405#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x00000009 4406#define GDS_DEBUG_REG4__cur_reso_MASK 0x000001f8L 4407#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x00000003 4408#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x00080000L 4409#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x00000013 4410#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x00040000L 4411#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x00000012 4412#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x00200000L 4413#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x00000015 4414#define GDS_DEBUG_REG4__gws_busy_MASK 0x00000001L 4415#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x00000000 4416#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x00000004L 4417#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x00000002 4418#define GDS_DEBUG_REG4__gws_req_MASK 0x00000002L 4419#define GDS_DEBUG_REG4__gws_req__SHIFT 0x00000001 4420#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x00400000L 4421#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x00000016 4422#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x00800000L 4423#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x00000017 4424#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x00100000L 4425#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x00000014 4426#define GDS_DEBUG_REG4__spare_MASK 0xff000000L 4427#define GDS_DEBUG_REG4__spare__SHIFT 0x00000018 4428#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x00000004L 4429#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x00000002 4430#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x00000008L 4431#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x00000003 4432#define GDS_DEBUG_REG5__dec_error_MASK 0x00000002L 4433#define GDS_DEBUG_REG5__dec_error__SHIFT 0x00000001 4434#define GDS_DEBUG_REG5__error_ds_address_MASK 0x003fff00L 4435#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x00000008 4436#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000L 4437#define GDS_DEBUG_REG5__spare1__SHIFT 0x00000016 4438#define GDS_DEBUG_REG5__spare_MASK 0xff000000L 4439#define GDS_DEBUG_REG5__spare__SHIFT 0x00000018 4440#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x00000010L 4441#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x00000004 4442#define GDS_DEBUG_REG5__write_dis_MASK 0x00000001L 4443#define GDS_DEBUG_REG5__write_dis__SHIFT 0x00000000 4444#define GDS_DEBUG_REG6__counters_busy_MASK 0x001fffe0L 4445#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x00000005 4446#define GDS_DEBUG_REG6__counters_enabled_MASK 0x0000001eL 4447#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x00000001 4448#define GDS_DEBUG_REG6__oa_busy_MASK 0x00000001L 4449#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x00000000 4450#define GDS_DEBUG_REG6__spare_MASK 0xff000000L 4451#define GDS_DEBUG_REG6__spare__SHIFT 0x00000018 4452#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L 4453#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x00000010 4454#define GDS_ENHANCE__MISC_MASK 0x0000ffffL 4455#define GDS_ENHANCE__MISC__SHIFT 0x00000000 4456#define GDS_ENHANCE__UNUSED_MASK 0xffff0000L 4457#define GDS_ENHANCE__UNUSED__SHIFT 0x00000010 4458#define GDS_GRBM_SECDED_CNT__DED_MASK 0xffff0000L 4459#define GDS_GRBM_SECDED_CNT__DED__SHIFT 0x00000010 4460#define GDS_GRBM_SECDED_CNT__SEC_MASK 0x0000ffffL 4461#define GDS_GRBM_SECDED_CNT__SEC__SHIFT 0x00000000 4462#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003fL 4463#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x00000000 4464#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0L 4465#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x00000006 4466#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000ffffL 4467#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x00000000 4468#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000L 4469#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x00000010 4470#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001ffeL 4471#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x00000001 4472#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L 4473#define GDS_GWS_RESOURCE__DED__SHIFT 0x0000000e 4474#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L 4475#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x00000000 4476#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000L 4477#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x0000001c 4478#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x07ff0000L 4479#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x00000010 4480#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x08000000L 4481#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x0000001b 4482#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L 4483#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0x0000000f 4484#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L 4485#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x00000000 4486#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000ff00L 4487#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x00000008 4488#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L 4489#define GDS_GWS_RESOURCE__TYPE__SHIFT 0x0000000d 4490#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000L 4491#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x0000001d 4492#define GDS_OA_DED__ME0_CS_DED_MASK 0x00000004L 4493#define GDS_OA_DED__ME0_CS_DED__SHIFT 0x00000002 4494#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L 4495#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x00000000 4496#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L 4497#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x00000001 4498#define GDS_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L 4499#define GDS_OA_DED__ME1_PIPE0_DED__SHIFT 0x00000004 4500#define GDS_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L 4501#define GDS_OA_DED__ME1_PIPE1_DED__SHIFT 0x00000005 4502#define GDS_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L 4503#define GDS_OA_DED__ME1_PIPE2_DED__SHIFT 0x00000006 4504#define GDS_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L 4505#define GDS_OA_DED__ME1_PIPE3_DED__SHIFT 0x00000007 4506#define GDS_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L 4507#define GDS_OA_DED__ME2_PIPE0_DED__SHIFT 0x00000008 4508#define GDS_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L 4509#define GDS_OA_DED__ME2_PIPE1_DED__SHIFT 0x00000009 4510#define GDS_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L 4511#define GDS_OA_DED__ME2_PIPE2_DED__SHIFT 0x0000000a 4512#define GDS_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L 4513#define GDS_OA_DED__ME2_PIPE3_DED__SHIFT 0x0000000b 4514#define GDS_OA_DED__UNUSED0_MASK 0x00000008L 4515#define GDS_OA_DED__UNUSED0__SHIFT 0x00000003 4516#define GDS_OA_DED__UNUSED1_MASK 0xfffff000L 4517#define GDS_OA_DED__UNUSED1__SHIFT 0x0000000c 4518#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 4519#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 4520#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 4521#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 4522#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL 4523#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 4524#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L 4525#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a 4526#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 4527#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 4528#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L 4529#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a 4530#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL 4531#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 4532#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 4533#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 4534#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 4535#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 4536#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L 4537#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 4538#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L 4539#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a 4540#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL 4541#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 4542#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 4543#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 4544#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 4545#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 4546#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L 4547#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 4548#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L 4549#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a 4550#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL 4551#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 4552#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 4553#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 4554#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 4555#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 4556#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L 4557#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 4558#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L 4559#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a 4560#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL 4561#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 4562#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffffL 4563#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x00000000 4564#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffffL 4565#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x00000000 4566#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffffL 4567#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x00000000 4568#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffffL 4569#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x00000000 4570#define GDS_RD_DATA__READ_DATA_MASK 0xffffffffL 4571#define GDS_RD_DATA__READ_DATA__SHIFT 0x00000000 4572#define GDS_SECDED_CNT__DED_MASK 0xffff0000L 4573#define GDS_SECDED_CNT__DED__SHIFT 0x00000010 4574#define GDS_SECDED_CNT__SEC_MASK 0x0000ffffL 4575#define GDS_SECDED_CNT__SEC__SHIFT 0x00000000 4576#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffffL 4577#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x00000000 4578#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffffL 4579#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x00000000 4580#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffffL 4581#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x00000000 4582#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffffL 4583#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x00000000 4584#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffffL 4585#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x00000000 4586#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L 4587#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 4588#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL 4589#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000 4590#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L 4591#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010 4592#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L 4593#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000 4594#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL 4595#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 4596#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x0000003fL 4597#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x00000000 4598#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffffL 4599#define GRBM_DEBUG_DATA__DATA__SHIFT 0x00000000 4600#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000040L 4601#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000006 4602#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x00001000L 4603#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x0000000c 4604#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0x00000f00L 4605#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x00000008 4606#define GRBM_DEBUG__IGNORE_FAO_MASK 0x00000020L 4607#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x00000005 4608#define GRBM_DEBUG__IGNORE_RDY_MASK 0x00000002L 4609#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000001 4610#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x00000001L 4611#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x00000000 4612#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x00000002L 4613#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x00000001 4614#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000080L 4615#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000007 4616#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x00000200L 4617#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x00000009 4618#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x00000040L 4619#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x00000006 4620#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x00004000L 4621#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0x0000000e 4622#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x00000080L 4623#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x00000007 4624#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x00008000L 4625#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0x0000000f 4626#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x00000100L 4627#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x00000008 4628#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x00010000L 4629#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x00000010 4630#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x00000200L 4631#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x00000009 4632#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x00020000L 4633#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x00000011 4634#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x00000400L 4635#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0x0000000a 4636#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x00040000L 4637#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x00000012 4638#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x00000800L 4639#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0x0000000b 4640#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x00080000L 4641#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x00000013 4642#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x00001000L 4643#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0x0000000c 4644#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x00100000L 4645#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x00000014 4646#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x00002000L 4647#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0x0000000d 4648#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x00200000L 4649#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x00000015 4650#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x00000002L 4651#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x00000001 4652#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x00000008L 4653#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x00000003 4654#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x00000010L 4655#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x00000004 4656#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L 4657#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 4658#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL 4659#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 4660#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L 4661#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x0000001e 4662#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000ffL 4663#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x00000000 4664#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L 4665#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x0000001f 4666#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00ff0000L 4667#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x00000010 4668#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L 4669#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x0000001d 4670#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000ff00L 4671#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x00000008 4672#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L 4673#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x00000013 4674#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L 4675#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x00000000 4676#define GRBM_NOWHERE__DATA_MASK 0xffffffffL 4677#define GRBM_NOWHERE__DATA__SHIFT 0x00000000 4678#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 4679#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 4680#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 4681#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 4682#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L 4683#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019 4684#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L 4685#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 4686#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L 4687#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b 4688#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L 4689#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 4690#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L 4691#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 4692#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L 4693#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a 4694#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L 4695#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018 4696#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L 4697#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 4698#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L 4699#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017 4700#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L 4701#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 4702#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL 4703#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 4704#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L 4705#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a 4706#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L 4707#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 4708#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L 4709#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 4710#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L 4711#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e 4712#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L 4713#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d 4714#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L 4715#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b 4716#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L 4717#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c 4718#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L 4719#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001c 4720#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 4721#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 4722#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 4723#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 4724#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L 4725#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019 4726#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L 4727#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 4728#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L 4729#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b 4730#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L 4731#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 4732#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L 4733#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 4734#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L 4735#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a 4736#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L 4737#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018 4738#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L 4739#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 4740#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L 4741#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017 4742#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L 4743#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 4744#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL 4745#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 4746#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L 4747#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a 4748#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L 4749#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 4750#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L 4751#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 4752#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L 4753#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e 4754#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L 4755#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d 4756#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L 4757#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b 4758#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L 4759#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c 4760#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L 4761#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001c 4762#define GRBM_PWR_CNTL__REQ_TYPE_MASK 0x0000000fL 4763#define GRBM_PWR_CNTL__REQ_TYPE__SHIFT 0x00000000 4764#define GRBM_PWR_CNTL__RSP_TYPE_MASK 0x000000f0L 4765#define GRBM_PWR_CNTL__RSP_TYPE__SHIFT 0x00000004 4766#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L 4767#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x00000013 4768#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L 4769#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x00000014 4770#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L 4771#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x00000015 4772#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L 4773#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x00000016 4774#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L 4775#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x00000017 4776#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L 4777#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x00000018 4778#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L 4779#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x00000019 4780#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L 4781#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x0000001a 4782#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L 4783#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x0000001b 4784#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L 4785#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x0000001c 4786#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L 4787#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x0000001d 4788#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L 4789#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x0000001e 4790#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L 4791#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x0000001f 4792#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L 4793#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x00000012 4794#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x00020000L 4795#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x00000011 4796#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL 4797#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 4798#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L 4799#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f 4800#define GRBM_READ_ERROR__READ_MEID_MASK 0x00c00000L 4801#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x00000016 4802#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L 4803#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x00000014 4804#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL 4805#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 4806#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL 4807#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 4808#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL 4809#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 4810#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL 4811#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 4812#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL 4813#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 4814#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL 4815#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 4816#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL 4817#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 4818#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL 4819#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 4820#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL 4821#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 4822#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL 4823#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 4824#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L 4825#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 4826#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L 4827#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 4828#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L 4829#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b 4830#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L 4831#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 4832#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L 4833#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a 4834#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L 4835#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 4836#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL 4837#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 4838#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L 4839#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 4840#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L 4841#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f 4842#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L 4843#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d 4844#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L 4845#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c 4846#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L 4847#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 4848#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL 4849#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 4850#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL 4851#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 4852#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L 4853#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 4854#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L 4855#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 4856#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L 4857#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b 4858#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L 4859#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 4860#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L 4861#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a 4862#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L 4863#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 4864#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL 4865#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 4866#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L 4867#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 4868#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L 4869#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f 4870#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L 4871#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d 4872#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L 4873#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c 4874#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L 4875#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 4876#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000fc0L 4877#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000006 4878#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003fL 4879#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 4880#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L 4881#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x00000012 4882#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L 4883#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x00000011 4884#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L 4885#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x00000013 4886#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L 4887#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 4888#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L 4889#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x00000010 4890#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L 4891#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x00000002 4892#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L 4893#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x0000001d 4894#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L 4895#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x0000001c 4896#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L 4897#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x0000001e 4898#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L 4899#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x00000004 4900#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000fL 4901#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x00000000 4902#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L 4903#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x00000005 4904#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L 4905#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x00000006 4906#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L 4907#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x00000007 4908#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L 4909#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x00000008 4910#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L 4911#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x00000009 4912#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L 4913#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0x0000000a 4914#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L 4915#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0x0000000b 4916#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L 4917#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0x0000000c 4918#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L 4919#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0x0000000d 4920#define GRBM_STATUS2__RLC_BUSY_MASK 0x00000100L 4921#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x00000008 4922#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00000001L 4923#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0x00000000 4924#define GRBM_STATUS2__TC_BUSY_MASK 0x00000200L 4925#define GRBM_STATUS2__TC_BUSY__SHIFT 0x00000009 4926#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L 4927#define GRBM_STATUS__BCI_BUSY__SHIFT 0x00000017 4928#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L 4929#define GRBM_STATUS__CB_BUSY__SHIFT 0x0000001e 4930#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L 4931#define GRBM_STATUS__CB_CLEAN__SHIFT 0x0000000d 4932#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L 4933#define GRBM_STATUS__CP_BUSY__SHIFT 0x0000001d 4934#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L 4935#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x0000001c 4936#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L 4937#define GRBM_STATUS__DB_BUSY__SHIFT 0x0000001a 4938#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L 4939#define GRBM_STATUS__DB_CLEAN__SHIFT 0x0000000c 4940#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L 4941#define GRBM_STATUS__GDS_BUSY__SHIFT 0x0000000f 4942#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L 4943#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x00000009 4944#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L 4945#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f 4946#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L 4947#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L 4948#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x00000012 4949#define GRBM_STATUS__IA_BUSY__SHIFT 0x00000013 4950#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L 4951#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x00000007 4952#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000fL 4953#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x00000000 4954#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L 4955#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x00000008 4956#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L 4957#define GRBM_STATUS__PA_BUSY__SHIFT 0x00000019 4958#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L 4959#define GRBM_STATUS__SC_BUSY__SHIFT 0x00000018 4960#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L 4961#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x00000016 4962#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L 4963#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x0000001f 4964#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L 4965#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x00000002 4966#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L 4967#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x0000001e 4968#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L 4969#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x00000001 4970#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L 4971#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x00000018 4972#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L 4973#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x0000001d 4974#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L 4975#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x0000001b 4976#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L 4977#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x0000001a 4978#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L 4979#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x00000019 4980#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L 4981#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x00000017 4982#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L 4983#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x00000016 4984#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L 4985#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x0000001f 4986#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L 4987#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x00000002 4988#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L 4989#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x0000001e 4990#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L 4991#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x00000001 4992#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L 4993#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x00000018 4994#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L 4995#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x0000001d 4996#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L 4997#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x0000001b 4998#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L 4999#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x0000001a 5000#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L 5001#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x00000019 5002#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L 5003#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x00000017 5004#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L 5005#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x00000016 5006#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L 5007#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x0000001f 5008#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L 5009#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x00000002 5010#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L 5011#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x0000001e 5012#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L 5013#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x00000001 5014#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L 5015#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x00000018 5016#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L 5017#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x0000001d 5018#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L 5019#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x0000001b 5020#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L 5021#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x0000001a 5022#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L 5023#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x00000019 5024#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L 5025#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x00000017 5026#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L 5027#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x00000016 5028#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L 5029#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x0000001f 5030#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L 5031#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x00000002 5032#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L 5033#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x0000001e 5034#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L 5035#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x00000001 5036#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L 5037#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x00000018 5038#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L 5039#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x0000001d 5040#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L 5041#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x0000001b 5042#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L 5043#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x0000001a 5044#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L 5045#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x00000019 5046#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L 5047#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x00000017 5048#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L 5049#define GRBM_STATUS__SPI_BUSY__SHIFT 0x00000016 5050#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x00000020L 5051#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x00000005 5052#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L 5053#define GRBM_STATUS__SX_BUSY__SHIFT 0x00000014 5054#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L 5055#define GRBM_STATUS__TA_BUSY__SHIFT 0x0000000e 5056#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L 5057#define GRBM_STATUS__VGT_BUSY__SHIFT 0x00000011 5058#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L 5059#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L 5060#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x00000010 5061#define GRBM_STATUS__WD_BUSY__SHIFT 0x00000015 5062#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000ffL 5063#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x00000000 5064#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L 5065#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x00000004 5066#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L 5067#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x00000000 5068#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L 5069#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x00000001 5070#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L 5071#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x00000002 5072#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L 5073#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x00000003 5074#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x0000003fL 5075#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x00000000 5076#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x00000040L 5077#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x00000006 5078#define IA_DEBUG_DATA__DATA_MASK 0xffffffffL 5079#define IA_DEBUG_DATA__DATA__SHIFT 0x00000000 5080#define IA_DEBUG_REG0__core_clk_busy_MASK 0x04000000L 5081#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x0000001a 5082#define IA_DEBUG_REG0__dma_busy_MASK 0x00000040L 5083#define IA_DEBUG_REG0__dma_busy__SHIFT 0x00000006 5084#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x00001000L 5085#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0x0000000c 5086#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x00000400L 5087#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0x0000000a 5088#define IA_DEBUG_REG0__dma_req_busy_MASK 0x00000020L 5089#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x00000005 5090#define IA_DEBUG_REG0__grp_busy_MASK 0x00000100L 5091#define IA_DEBUG_REG0__grp_busy__SHIFT 0x00000008 5092#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x00002000L 5093#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0x0000000d 5094#define IA_DEBUG_REG0__grp_dma_read_MASK 0x00000800L 5095#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0x0000000b 5096#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x00000001L 5097#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x00000000 5098#define IA_DEBUG_REG0__ia_busy_MASK 0x00000004L 5099#define IA_DEBUG_REG0__ia_busy__SHIFT 0x00000002 5100#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x00000002L 5101#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x00000001 5102#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x00000008L 5103#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x00000003 5104#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x00000080L 5105#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x00000007 5106#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L 5107#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018 5108#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L 5109#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d 5110#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000L 5111#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x0000001c 5112#define IA_DEBUG_REG0__SPARE0_MASK 0x00000010L 5113#define IA_DEBUG_REG0__SPARE0__SHIFT 0x00000004 5114#define IA_DEBUG_REG0__SPARE1_MASK 0x00000200L 5115#define IA_DEBUG_REG0__SPARE1__SHIFT 0x00000009 5116#define IA_DEBUG_REG0__SPARE2_MASK 0x00ffc000L 5117#define IA_DEBUG_REG0__SPARE2__SHIFT 0x0000000e 5118#define IA_DEBUG_REG0__SPARE3_MASK 0x00100000L 5119#define IA_DEBUG_REG0__SPARE3__SHIFT 0x00000014 5120#define IA_DEBUG_REG0__SPARE4_MASK 0x08000000L 5121#define IA_DEBUG_REG0__SPARE4__SHIFT 0x0000001b 5122#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000L 5123#define IA_DEBUG_REG0__SPARE5__SHIFT 0x0000001e 5124#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000L 5125#define IA_DEBUG_REG0__SPARE6__SHIFT 0x0000001f 5126#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000L 5127#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x0000001c 5128#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x00000100L 5129#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x00000008 5130#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x00000200L 5131#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x00000009 5132#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x00000060L 5133#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x00000005 5134#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x00004000L 5135#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0x0000000e 5136#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x00008000L 5137#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0x0000000f 5138#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x04000000L 5139#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x0000001a 5140#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x00000001L 5141#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x00000000 5142#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x00000002L 5143#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x00000001 5144#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x00002000L 5145#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0x0000000d 5146#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000L 5147#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x0000001e 5148#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x00000008L 5149#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x00000003 5150#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x00010000L 5151#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x00000010 5152#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x00020000L 5153#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x00000011 5154#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x00000080L 5155#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x00000007 5156#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000L 5157#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x0000001f 5158#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x01000000L 5159#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x00000018 5160#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x02000000L 5161#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x00000019 5162#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x00000800L 5163#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0x0000000b 5164#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x00000010L 5165#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x00000004 5166#define IA_DEBUG_REG1__grp_dma_read_MASK 0x08000000L 5167#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x0000001b 5168#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x00001000L 5169#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0x0000000c 5170#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000L 5171#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x0000001d 5172#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x00000400L 5173#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0x0000000a 5174#define IA_DEBUG_REG1__stage2_dr_MASK 0x00040000L 5175#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x00000012 5176#define IA_DEBUG_REG1__stage2_rtr_MASK 0x00080000L 5177#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x00000013 5178#define IA_DEBUG_REG1__stage3_dr_MASK 0x00100000L 5179#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x00000014 5180#define IA_DEBUG_REG1__stage3_rtr_MASK 0x00200000L 5181#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x00000015 5182#define IA_DEBUG_REG1__stage4_dr_MASK 0x00400000L 5183#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x00000016 5184#define IA_DEBUG_REG1__stage4_rtr_MASK 0x00800000L 5185#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x00000017 5186#define IA_DEBUG_REG1__start_new_packet_MASK 0x00000004L 5187#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x00000002 5188#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000L 5189#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x0000001c 5190#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x00000100L 5191#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x00000008 5192#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x00000200L 5193#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x00000009 5194#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x00000060L 5195#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x00000005 5196#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x00004000L 5197#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0x0000000e 5198#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x00008000L 5199#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0x0000000f 5200#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x04000000L 5201#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x0000001a 5202#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x00000001L 5203#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x00000000 5204#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x00000002L 5205#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x00000001 5206#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x00002000L 5207#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0x0000000d 5208#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000L 5209#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x0000001e 5210#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x00000008L 5211#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x00000003 5212#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x00010000L 5213#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x00000010 5214#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x00020000L 5215#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x00000011 5216#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x00000080L 5217#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x00000007 5218#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000L 5219#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x0000001f 5220#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x01000000L 5221#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x00000018 5222#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x02000000L 5223#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x00000019 5224#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x00000800L 5225#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0x0000000b 5226#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x00000010L 5227#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x00000004 5228#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x08000000L 5229#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x0000001b 5230#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x00001000L 5231#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0x0000000c 5232#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000L 5233#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x0000001d 5234#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x00000400L 5235#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0x0000000a 5236#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x00040000L 5237#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x00000012 5238#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x00080000L 5239#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x00000013 5240#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x00100000L 5241#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x00000014 5242#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x00200000L 5243#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x00000015 5244#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x00400000L 5245#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x00000016 5246#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x00800000L 5247#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x00000017 5248#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x00000004L 5249#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x00000002 5250#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x04000000L 5251#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x0000001a 5252#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x08000000L 5253#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x0000001b 5254#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x00000008L 5255#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x00000003 5256#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x00000004L 5257#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x00000002 5258#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x00000002L 5259#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x00000001 5260#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x00000010L 5261#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x00000004 5262#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x00000001L 5263#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x00000000 5264#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x00000800L 5265#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0x0000000b 5266#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x00000400L 5267#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0x0000000a 5268#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x00000200L 5269#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x00000009 5270#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x00001000L 5271#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0x0000000c 5272#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x00000100L 5273#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x00000008 5274#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x00008000L 5275#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0x0000000f 5276#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x00000020L 5277#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x00000005 5278#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x00002000L 5279#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0x0000000d 5280#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x00040000L 5281#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x00000012 5282#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000L 5283#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x0000001d 5284#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000L 5285#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x0000001c 5286#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x00004000L 5287#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0x0000000e 5288#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x00000040L 5289#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x00000006 5290#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x00100000L 5291#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x00000014 5292#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x00200000L 5293#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x00000015 5294#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x00400000L 5295#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x00000016 5296#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x00800000L 5297#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x00000017 5298#define IA_DEBUG_REG3__pipe0_dr_MASK 0x00010000L 5299#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x00000010 5300#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x00020000L 5301#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x00000011 5302#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x00000080L 5303#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x00000007 5304#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000L 5305#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x0000001f 5306#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000L 5307#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x0000001e 5308#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x00080000L 5309#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x00000013 5310#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x03000000L 5311#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x00000018 5312#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000L 5313#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x0000001f 5314#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x00100000L 5315#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x00000014 5316#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000L 5317#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x0000001d 5318#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x00010000L 5319#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x00000010 5320#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0x0c000000L 5321#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x0000001a 5322#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0x00e00000L 5323#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x00000015 5324#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x02000000L 5325#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x00000019 5326#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x01000000L 5327#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x00000018 5328#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x00000040L 5329#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x00000006 5330#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x00000080L 5331#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x00000007 5332#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0x000e0000L 5333#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x00000011 5334#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x00008000L 5335#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0x0000000f 5336#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x00004000L 5337#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0x0000000e 5338#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000L 5339#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x0000001e 5340#define IA_DEBUG_REG4__pipe0_dr_MASK 0x00000001L 5341#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x00000000 5342#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x00000100L 5343#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x00000008 5344#define IA_DEBUG_REG4__pipe1_dr_MASK 0x00000002L 5345#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x00000001 5346#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x00000200L 5347#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x00000009 5348#define IA_DEBUG_REG4__pipe2_dr_MASK 0x00000004L 5349#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x00000002 5350#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x00000400L 5351#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0x0000000a 5352#define IA_DEBUG_REG4__pipe3_dr_MASK 0x00000008L 5353#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x00000003 5354#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x00000800L 5355#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0x0000000b 5356#define IA_DEBUG_REG4__pipe4_dr_MASK 0x00000010L 5357#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x00000004 5358#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x00001000L 5359#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0x0000000c 5360#define IA_DEBUG_REG4__pipe5_dr_MASK 0x00000020L 5361#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x00000005 5362#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x00002000L 5363#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0x0000000d 5364#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000L 5365#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x0000001c 5366#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0x0000ffffL 5367#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x00000000 5368#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000L 5369#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x0000001f 5370#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000L 5371#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x0000001e 5372#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000L 5373#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x00000010 5374#define IA_DEBUG_REG6__after_group_partial_MASK 0x00400000L 5375#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x00000016 5376#define IA_DEBUG_REG6__current_shift_q_MASK 0x0000000fL 5377#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x00000000 5378#define IA_DEBUG_REG6__current_stride_pre_MASK 0x000000f0L 5379#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x00000004 5380#define IA_DEBUG_REG6__current_stride_q_MASK 0x00001f00L 5381#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x00000008 5382#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x00008000L 5383#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0x0000000f 5384#define IA_DEBUG_REG6__extract_group_MASK 0x00800000L 5385#define IA_DEBUG_REG6__extract_group__SHIFT 0x00000017 5386#define IA_DEBUG_REG6__first_group_partial_MASK 0x00002000L 5387#define IA_DEBUG_REG6__first_group_partial__SHIFT 0x0000000d 5388#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000L 5389#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x00000018 5390#define IA_DEBUG_REG6__next_group_partial_MASK 0x00200000L 5391#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x00000015 5392#define IA_DEBUG_REG6__next_stride_q_MASK 0x001f0000L 5393#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x00000010 5394#define IA_DEBUG_REG6__second_group_partial_MASK 0x00004000L 5395#define IA_DEBUG_REG6__second_group_partial__SHIFT 0x0000000e 5396#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x02000000L 5397#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x00000019 5398#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x04000000L 5399#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x0000001a 5400#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x08000000L 5401#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x0000001b 5402#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x00800000L 5403#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x00000017 5404#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x00700000L 5405#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x00000014 5406#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0x0000000fL 5407#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x00000000 5408#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x01000000L 5409#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x00000018 5410#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000L 5411#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x0000001f 5412#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000L 5413#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x0000001e 5414#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000L 5415#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x0000001d 5416#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000L 5417#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x0000001c 5418#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0x0000f000L 5419#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0x0000000c 5420#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0x000f0000L 5421#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x00000010 5422#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0x00000f00L 5423#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x00000008 5424#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0x000000f0L 5425#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x00000004 5426#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x0000001fL 5427#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x00000000 5428#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000L 5429#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x0000001c 5430#define IA_DEBUG_REG8__grp_continued_MASK 0x00000800L 5431#define IA_DEBUG_REG8__grp_continued__SHIFT 0x0000000b 5432#define IA_DEBUG_REG8__grp_eopg_MASK 0x04000000L 5433#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x0000001a 5434#define IA_DEBUG_REG8__grp_eop_MASK 0x02000000L 5435#define IA_DEBUG_REG8__grp_eop__SHIFT 0x00000019 5436#define IA_DEBUG_REG8__grp_event_flag_MASK 0x08000000L 5437#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x0000001b 5438#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x01000000L 5439#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x00000018 5440#define IA_DEBUG_REG8__grp_output_path_MASK 0x00e00000L 5441#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x00000015 5442#define IA_DEBUG_REG8__grp_state_sel_MASK 0x00007000L 5443#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0x0000000c 5444#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x001f8000L 5445#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0x0000000f 5446#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x00000100L 5447#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x00000008 5448#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x00000400L 5449#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0x0000000a 5450#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x00000200L 5451#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x00000009 5452#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x00000080L 5453#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x00000007 5454#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x00000020L 5455#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x00000005 5456#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x00000040L 5457#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x00000006 5458#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x00000400L 5459#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0x0000000a 5460#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x00000200L 5461#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x00000009 5462#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x00000002L 5463#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x00000001 5464#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x00040000L 5465#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x00000012 5466#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x00080000L 5467#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x00000013 5468#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x00000008L 5469#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x00000003 5470#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x00000004L 5471#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x00000002 5472#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x00000020L 5473#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x00000005 5474#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x00000080L 5475#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x00000007 5476#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x00000010L 5477#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x00000004 5478#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x00000100L 5479#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x00000008 5480#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x00000040L 5481#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x00000006 5482#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x00020000L 5483#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x00000011 5484#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x00000800L 5485#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0x0000000b 5486#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfffc0000L 5487#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x00000012 5488#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x00001000L 5489#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0x0000000c 5490#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x00000001L 5491#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x00000000 5492#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x00010000L 5493#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x00000010 5494#define IA_DEBUG_REG9__SPARE0_MASK 0x00004000L 5495#define IA_DEBUG_REG9__SPARE0__SHIFT 0x0000000e 5496#define IA_DEBUG_REG9__SPARE1_MASK 0x00008000L 5497#define IA_DEBUG_REG9__SPARE1__SHIFT 0x0000000f 5498#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x00002000L 5499#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0x0000000d 5500#define IA_ENHANCE__MISC_MASK 0xffffffffL 5501#define IA_ENHANCE__MISC__SHIFT 0x00000000 5502#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L 5503#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x00000012 5504#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L 5505#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x00000010 5506#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000ffffL 5507#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x00000000 5508#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L 5509#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x00000013 5510#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L 5511#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x00000011 5512#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L 5513#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x00000014 5514#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 5515#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 5516#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 5517#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 5518#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L 5519#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c 5520#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L 5521#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 5522#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL 5523#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 5524#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L 5525#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 5526#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 5527#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 5528#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L 5529#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 5530#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L 5531#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c 5532#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L 5533#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a 5534#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL 5535#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 5536#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 5537#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 5538#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 5539#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 5540#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L 5541#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c 5542#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL 5543#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 5544#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 5545#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 5546#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 5547#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 5548#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L 5549#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c 5550#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL 5551#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 5552#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 5553#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 5554#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 5555#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 5556#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L 5557#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c 5558#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL 5559#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 5560#define IA_VMID_OVERRIDE__ENABLE_MASK 0x00000001L 5561#define IA_VMID_OVERRIDE__ENABLE__SHIFT 0x00000000 5562#define IA_VMID_OVERRIDE__VMID_MASK 0x0000001eL 5563#define IA_VMID_OVERRIDE__VMID__SHIFT 0x00000001 5564#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L 5565#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 5566#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L 5567#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 5568#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L 5569#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 5570#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L 5571#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 5572#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L 5573#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x00000018 5574#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L 5575#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x00000016 5576#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000c000L 5577#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0x0000000e 5578#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L 5579#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0x0000000d 5580#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L 5581#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x00000011 5582#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L 5583#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x00000000 5584#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L 5585#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x00000001 5586#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L 5587#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x00000002 5588#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L 5589#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x00000003 5590#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L 5591#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x00000004 5592#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L 5593#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x00000005 5594#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L 5595#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x00000019 5596#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L 5597#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 5598#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L 5599#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x0000001b 5600#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L 5601#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x0000001a 5602#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L 5603#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f 5604#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L 5605#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x00000003 5606#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L 5607#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 5608#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L 5609#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f 5610#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L 5611#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e 5612#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L 5613#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d 5614#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L 5615#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c 5616#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L 5617#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x00000001 5618#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L 5619#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x00000004 5620#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L 5621#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x00000005 5622#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL 5623#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 5624#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL 5625#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 5626#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL 5627#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 5628#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL 5629#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 5630#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L 5631#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0x0000000e 5632#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L 5633#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0x0000000d 5634#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L 5635#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0x0000000c 5636#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L 5637#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x00000009 5638#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L 5639#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x00000008 5640#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L 5641#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0x0000000b 5642#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L 5643#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0x0000000a 5644#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L 5645#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x00000003 5646#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L 5647#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x00000014 5648#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L 5649#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x00000002 5650#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L 5651#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x00000006 5652#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L 5653#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x00000007 5654#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L 5655#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x00000000 5656#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L 5657#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x00000004 5658#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L 5659#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x00000001 5660#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L 5661#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x00000005 5662#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffffL 5663#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x00000000 5664#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffffL 5665#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x00000000 5666#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffffL 5667#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x00000000 5668#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffffL 5669#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x00000000 5670#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffffL 5671#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x00000000 5672#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffffL 5673#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x00000000 5674#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffffL 5675#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x00000000 5676#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffffL 5677#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x00000000 5678#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffffL 5679#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x00000000 5680#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffffL 5681#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x00000000 5682#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffffL 5683#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x00000000 5684#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffffL 5685#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x00000000 5686#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffffL 5687#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x00000000 5688#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffffL 5689#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x00000000 5690#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffffL 5691#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x00000000 5692#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffffL 5693#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x00000000 5694#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffffL 5695#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x00000000 5696#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffffL 5697#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x00000000 5698#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffffL 5699#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x00000000 5700#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffffL 5701#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x00000000 5702#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffffL 5703#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x00000000 5704#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffffL 5705#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x00000000 5706#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffffL 5707#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x00000000 5708#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffffL 5709#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x00000000 5710#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffffL 5711#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x00000000 5712#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffffL 5713#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x00000000 5714#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffffL 5715#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x00000000 5716#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffffL 5717#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x00000000 5718#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffffL 5719#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x00000000 5720#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffffL 5721#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x00000000 5722#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffffL 5723#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x00000000 5724#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffffL 5725#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x00000000 5726#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffffL 5727#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x00000000 5728#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffffL 5729#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x00000000 5730#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffffL 5731#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x00000000 5732#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffffL 5733#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x00000000 5734#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffffL 5735#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x00000000 5736#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffffL 5737#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x00000000 5738#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffffL 5739#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x00000000 5740#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffffL 5741#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x00000000 5742#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffffL 5743#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x00000000 5744#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffffL 5745#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x00000000 5746#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffffL 5747#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x00000000 5748#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL 5749#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 5750#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffffL 5751#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x00000000 5752#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffffL 5753#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x00000000 5754#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffffL 5755#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x00000000 5756#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffffL 5757#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x00000000 5758#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffffL 5759#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x00000000 5760#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffffL 5761#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x00000000 5762#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffffL 5763#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x00000000 5764#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffffL 5765#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x00000000 5766#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffffL 5767#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x00000000 5768#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffffL 5769#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x00000000 5770#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffffL 5771#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x00000000 5772#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffffL 5773#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x00000000 5774#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffffL 5775#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x00000000 5776#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffffL 5777#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x00000000 5778#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffffL 5779#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x00000000 5780#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL 5781#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 5782#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffffL 5783#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x00000000 5784#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffffL 5785#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x00000000 5786#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffffL 5787#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x00000000 5788#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffffL 5789#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x00000000 5790#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffffL 5791#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x00000000 5792#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffffL 5793#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x00000000 5794#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffffL 5795#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x00000000 5796#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffffL 5797#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x00000000 5798#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffffL 5799#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x00000000 5800#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffffL 5801#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x00000000 5802#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffffL 5803#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x00000000 5804#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffffL 5805#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x00000000 5806#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffffL 5807#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x00000000 5808#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffffL 5809#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x00000000 5810#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffffL 5811#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x00000000 5812#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL 5813#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 5814#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffffL 5815#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x00000000 5816#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffffL 5817#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x00000000 5818#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffffL 5819#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x00000000 5820#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffffL 5821#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x00000000 5822#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffffL 5823#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x00000000 5824#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffffL 5825#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x00000000 5826#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffffL 5827#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x00000000 5828#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffffL 5829#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x00000000 5830#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffffL 5831#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x00000000 5832#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffffL 5833#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x00000000 5834#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffffL 5835#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x00000000 5836#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffffL 5837#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x00000000 5838#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffffL 5839#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x00000000 5840#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffffL 5841#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x00000000 5842#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffffL 5843#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x00000000 5844#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL 5845#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 5846#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffffL 5847#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x00000000 5848#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffffL 5849#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x00000000 5850#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffffL 5851#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x00000000 5852#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffffL 5853#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x00000000 5854#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffffL 5855#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x00000000 5856#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffffL 5857#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x00000000 5858#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffffL 5859#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x00000000 5860#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffffL 5861#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x00000000 5862#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffffL 5863#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x00000000 5864#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffffL 5865#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x00000000 5866#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffffL 5867#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x00000000 5868#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffffL 5869#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x00000000 5870#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffffL 5871#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x00000000 5872#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffffL 5873#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x00000000 5874#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffffL 5875#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x00000000 5876#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL 5877#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 5878#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffffL 5879#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x00000000 5880#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffffL 5881#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x00000000 5882#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffffL 5883#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x00000000 5884#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffffL 5885#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x00000000 5886#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffffL 5887#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x00000000 5888#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffffL 5889#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x00000000 5890#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffffL 5891#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x00000000 5892#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffffL 5893#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x00000000 5894#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffffL 5895#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x00000000 5896#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffffL 5897#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x00000000 5898#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffffL 5899#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x00000000 5900#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffffL 5901#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x00000000 5902#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffffL 5903#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x00000000 5904#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffffL 5905#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x00000000 5906#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffffL 5907#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x00000000 5908#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL 5909#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 5910#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L 5911#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x00000000 5912#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L 5913#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x00000001 5914#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L 5915#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x00000002 5916#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L 5917#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x00000003 5918#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L 5919#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x00000004 5920#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L 5921#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x00000005 5922#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L 5923#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x00000006 5924#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L 5925#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x00000007 5926#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L 5927#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x00000008 5928#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L 5929#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x00000009 5930#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L 5931#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0x0000000a 5932#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L 5933#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0x0000000b 5934#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L 5935#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0x0000000c 5936#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L 5937#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0x0000000d 5938#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L 5939#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0x0000000e 5940#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L 5941#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0x0000000f 5942#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L 5943#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x00000011 5944#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L 5945#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x00000019 5946#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L 5947#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x00000014 5948#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L 5949#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x00000010 5950#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L 5951#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x00000012 5952#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L 5953#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x00000013 5954#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L 5955#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x00000016 5956#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L 5957#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x00000017 5958#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L 5959#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x00000018 5960#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L 5961#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x00000015 5962#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L 5963#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b 5964#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L 5965#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 5966#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L 5967#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 5968#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L 5969#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 5970#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L 5971#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 5972#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L 5973#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 5974#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L 5975#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 5976#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L 5977#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a 5978#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L 5979#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 5980#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L 5981#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 5982#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L 5983#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x00000004 5984#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L 5985#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x00000018 5986#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L 5987#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d 5988#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L 5989#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x00000014 5990#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L 5991#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 5992#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000ffffL 5993#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x00000000 5994#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000L 5995#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x00000010 5996#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000ffffL 5997#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x00000000 5998#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000L 5999#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x00000010 6000#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000fL 6001#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x00000000 6002#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000f0L 6003#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x00000004 6004#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000f00L 6005#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x00000008 6006#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000f000L 6007#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0x0000000c 6008#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000f0000L 6009#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x00000010 6010#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00f00000L 6011#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x00000014 6012#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0f000000L 6013#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x00000018 6014#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000L 6015#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x0000001c 6016#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000fL 6017#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x00000000 6018#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000f0L 6019#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x00000004 6020#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000f00L 6021#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x00000008 6022#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000f000L 6023#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0x0000000c 6024#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000f0000L 6025#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x00000010 6026#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00f00000L 6027#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x00000014 6028#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0f000000L 6029#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x00000018 6030#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000L 6031#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x0000001c 6032#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000f0000L 6033#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x00000010 6034#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00f00000L 6035#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x00000014 6036#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0f000000L 6037#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x00000018 6038#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000L 6039#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x0000001c 6040#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000fL 6041#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x00000000 6042#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000f0L 6043#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x00000004 6044#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000f00L 6045#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x00000008 6046#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000f000L 6047#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0x0000000c 6048#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000fL 6049#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x00000000 6050#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000f0L 6051#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x00000004 6052#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000f00L 6053#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x00000008 6054#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000f000L 6055#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0x0000000c 6056#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000f0000L 6057#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x00000010 6058#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00f00000L 6059#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x00000014 6060#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0f000000L 6061#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x00000018 6062#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000L 6063#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x0000001c 6064#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000fL 6065#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x00000000 6066#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000f0L 6067#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x00000004 6068#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000f00L 6069#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x00000008 6070#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000f000L 6071#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0x0000000c 6072#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000f0000L 6073#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x00000010 6074#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00f00000L 6075#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x00000014 6076#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0f000000L 6077#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x00000018 6078#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000L 6079#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x0000001c 6080#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000fL 6081#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x00000000 6082#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000f0L 6083#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x00000004 6084#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000f00L 6085#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x00000008 6086#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000f000L 6087#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0x0000000c 6088#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000f0000L 6089#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x00000010 6090#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00f00000L 6091#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x00000014 6092#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0f000000L 6093#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x00000018 6094#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000L 6095#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x0000001c 6096#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000f0000L 6097#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x00000010 6098#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00f00000L 6099#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x00000014 6100#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0f000000L 6101#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x00000018 6102#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000L 6103#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x0000001c 6104#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000fL 6105#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x00000000 6106#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000f0L 6107#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x00000004 6108#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000f00L 6109#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x00000008 6110#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000f000L 6111#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0x0000000c 6112#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000fL 6113#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x00000000 6114#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000f0L 6115#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x00000004 6116#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000f00L 6117#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x00000008 6118#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000f000L 6119#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0x0000000c 6120#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000f0000L 6121#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x00000010 6122#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00f00000L 6123#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x00000014 6124#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0f000000L 6125#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x00000018 6126#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000L 6127#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x0000001c 6128#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000fL 6129#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x00000000 6130#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000f0L 6131#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x00000004 6132#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000f00L 6133#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x00000008 6134#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000f000L 6135#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0x0000000c 6136#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000f0000L 6137#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x00000010 6138#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00f00000L 6139#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x00000014 6140#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0f000000L 6141#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x00000018 6142#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000L 6143#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x0000001c 6144#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000fL 6145#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x00000000 6146#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000f0L 6147#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x00000004 6148#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000f00L 6149#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x00000008 6150#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000f000L 6151#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0x0000000c 6152#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000f0000L 6153#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x00000010 6154#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00f00000L 6155#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x00000014 6156#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0f000000L 6157#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x00000018 6158#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000L 6159#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x0000001c 6160#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000f0000L 6161#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x00000010 6162#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00f00000L 6163#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x00000014 6164#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0f000000L 6165#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x00000018 6166#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000L 6167#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x0000001c 6168#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000fL 6169#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x00000000 6170#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000f0L 6171#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x00000004 6172#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000f00L 6173#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x00000008 6174#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000f000L 6175#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0x0000000c 6176#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000fL 6177#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x00000000 6178#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000f0L 6179#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x00000004 6180#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000f00L 6181#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x00000008 6182#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000f000L 6183#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0x0000000c 6184#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000f0000L 6185#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x00000010 6186#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00f00000L 6187#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x00000014 6188#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0f000000L 6189#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x00000018 6190#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000L 6191#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x0000001c 6192#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000fL 6193#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x00000000 6194#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000f0L 6195#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x00000004 6196#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000f00L 6197#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x00000008 6198#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000f000L 6199#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0x0000000c 6200#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000f0000L 6201#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x00000010 6202#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00f00000L 6203#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x00000014 6204#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0f000000L 6205#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x00000018 6206#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000L 6207#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x0000001c 6208#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000fL 6209#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x00000000 6210#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000f0L 6211#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x00000004 6212#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000f00L 6213#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x00000008 6214#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000f000L 6215#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0x0000000c 6216#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000f0000L 6217#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x00000010 6218#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00f00000L 6219#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x00000014 6220#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0f000000L 6221#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x00000018 6222#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000L 6223#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x0000001c 6224#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000f0000L 6225#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x00000010 6226#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00f00000L 6227#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x00000014 6228#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0f000000L 6229#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x00000018 6230#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000L 6231#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x0000001c 6232#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000fL 6233#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x00000000 6234#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000f0L 6235#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x00000004 6236#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000f00L 6237#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x00000008 6238#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000f000L 6239#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0x0000000c 6240#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000fL 6241#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x00000000 6242#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000f0L 6243#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x00000004 6244#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000f00L 6245#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x00000008 6246#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000f000L 6247#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0x0000000c 6248#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000f0000L 6249#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x00000010 6250#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00f00000L 6251#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x00000014 6252#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0f000000L 6253#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x00000018 6254#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000L 6255#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x0000001c 6256#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000fL 6257#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x00000000 6258#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000f0L 6259#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x00000004 6260#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000f00L 6261#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x00000008 6262#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000f000L 6263#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0x0000000c 6264#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000f0000L 6265#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x00000010 6266#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00f00000L 6267#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x00000014 6268#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0f000000L 6269#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x00000018 6270#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000L 6271#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x0000001c 6272#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000f00L 6273#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x00000008 6274#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000f000L 6275#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0x0000000c 6276#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000f0000L 6277#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x00000010 6278#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00f00000L 6279#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x00000014 6280#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0f000000L 6281#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x00000018 6282#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000L 6283#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x0000001c 6284#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000fL 6285#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x00000000 6286#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000f0L 6287#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x00000004 6288#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007fffL 6289#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x00000000 6290#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000L 6291#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x00000010 6292#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007fffL 6293#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x00000000 6294#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000L 6295#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x00000010 6296#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007fffL 6297#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x00000000 6298#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000L 6299#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x00000010 6300#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007fffL 6301#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x00000000 6302#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000L 6303#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x00000010 6304#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007fffL 6305#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x00000000 6306#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000L 6307#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x00000010 6308#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007fffL 6309#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x00000000 6310#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000L 6311#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x00000010 6312#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007fffL 6313#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x00000000 6314#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000L 6315#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x00000010 6316#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007fffL 6317#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x00000000 6318#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000L 6319#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x00000010 6320#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000ffffL 6321#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x00000000 6322#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000003fL 6323#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 6324#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL 6325#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 6326#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x00000003L 6327#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x00000000 6328#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0x0000000cL 6329#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x00000002 6330#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x00000003L 6331#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x00000000 6332#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0x0000000cL 6333#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x00000002 6334#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000L 6335#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x0000001c 6336#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003f000L 6337#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0x0000000c 6338#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00fc0000L 6339#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x00000012 6340#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0f000000L 6341#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x00000018 6342#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000f0L 6343#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x00000004 6344#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000f00L 6345#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x00000008 6346#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000fL 6347#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x00000000 6348#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L 6349#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x00000002 6350#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000200L 6351#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x00000009 6352#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00004000L 6353#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0x0000000e 6354#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00200000L 6355#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x00000015 6356#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00800000L 6357#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x00000017 6358#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00040000L 6359#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x00000012 6360#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00010000L 6361#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x00000010 6362#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00400000L 6363#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x00000016 6364#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00080000L 6365#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x00000013 6366#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00002000L 6367#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0x0000000d 6368#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0x000000c0L 6369#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x00000006 6370#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L 6371#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x00000001 6372#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L 6373#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x00000005 6374#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000400L 6375#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x0000000a 6376#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000800L 6377#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x0000000b 6378#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00001000L 6379#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0x0000000c 6380#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L 6381#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f 6382#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L 6383#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e 6384#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L 6385#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x00000003 6386#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L 6387#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x00000004 6388#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00008000L 6389#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0x0000000f 6390#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x01000000L 6391#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x00000018 6392#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00020000L 6393#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x00000011 6394#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00100000L 6395#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x00000014 6396#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L 6397#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x00000000 6398#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000100L 6399#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x00000008 6400#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000000ffL 6401#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x00000000 6402#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007fc0L 6403#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x00000006 6404#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000L 6405#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x00000017 6406#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003fL 6407#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x00000000 6408#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001f8000L 6409#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0x0000000f 6410#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000ffffL 6411#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x00000000 6412#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000L 6413#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x00000010 6414#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007fffL 6415#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x00000000 6416#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000L 6417#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x00000010 6418#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007fffL 6419#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x00000000 6420#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000L 6421#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x00000010 6422#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6423#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6424#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00fc0000L 6425#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x00000012 6426#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000fc0L 6427#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x00000006 6428#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003fL 6429#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x00000000 6430#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003f000L 6431#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0x0000000c 6432#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L 6433#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0x0000000c 6434#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L 6435#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 6436#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L 6437#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a 6438#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L 6439#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0x0000000b 6440#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L 6441#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d 6442#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL 6443#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 6444#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L 6445#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c 6446#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L 6447#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 6448#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L 6449#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 6450#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL 6451#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 6452#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L 6453#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x00000002 6454#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L 6455#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x00000000 6456#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L 6457#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x00000003 6458#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L 6459#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x00000001 6460#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L 6461#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x00000019 6462#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L 6463#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x0000001a 6464#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L 6465#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x00000013 6466#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00f00000L 6467#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x00000014 6468#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L 6469#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0x0000000f 6470#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L 6471#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0x0000000e 6472#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L 6473#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x00000018 6474#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L 6475#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x00000012 6476#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L 6477#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x00000011 6478#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L 6479#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x0000001b 6480#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L 6481#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x0000001c 6482#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L 6483#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x00000010 6484#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L 6485#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x00000007 6486#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L 6487#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x00000009 6488#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L 6489#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0x0000000a 6490#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L 6491#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x00000008 6492#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L 6493#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x00000002 6494#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L 6495#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x00000001 6496#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L 6497#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x00000003 6498#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L 6499#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x00000004 6500#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L 6501#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x00000000 6502#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L 6503#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0x0000000b 6504#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L 6505#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0x0000000c 6506#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L 6507#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0x0000000d 6508#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 6509#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6510#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6511#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6512#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL 6513#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 6514#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L 6515#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 6516#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 6517#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 6518#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L 6519#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a 6520#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001ffL 6521#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 6522#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 6523#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6524#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6525#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6526#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001ffL 6527#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 6528#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 6529#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6530#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6531#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6532#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001ffL 6533#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 6534#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 6535#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6536#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6537#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6538#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001ffL 6539#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 6540#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL 6541#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6542#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6543#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6544#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001ffL 6545#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000 6546#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL 6547#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6548#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6549#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6550#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001ffL 6551#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000 6552#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL 6553#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6554#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6555#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6556#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001ffL 6557#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000 6558#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL 6559#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6560#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6561#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6562#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001ffL 6563#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000 6564#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L 6565#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x00000000 6566#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000000cL 6567#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x00000002 6568#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x00000030L 6569#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x00000004 6570#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L 6571#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x00000008 6572#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000c000L 6573#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0x0000000e 6574#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000c00L 6575#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0x0000000a 6576#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L 6577#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0x0000000c 6578#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L 6579#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x00000000 6580#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000cL 6581#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x00000002 6582#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L 6583#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x00000004 6584#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L 6585#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x00000006 6586#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L 6587#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x00000007 6588#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L 6589#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x00000010 6590#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000c0000L 6591#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x00000012 6592#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L 6593#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x00000014 6594#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L 6595#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x00000018 6596#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0c000000L 6597#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x0000001a 6598#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L 6599#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x0000001c 6600#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000ffffL 6601#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 6602#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000L 6603#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 6604#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000ffffL 6605#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 6606#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000L 6607#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 6608#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007fffL 6609#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x00000000 6610#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000L 6611#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x00000010 6612#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007fffL 6613#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x00000000 6614#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000L 6615#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x00000010 6616#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6617#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6618#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007fffL 6619#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x00000000 6620#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000L 6621#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x00000010 6622#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007fffL 6623#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x00000000 6624#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000L 6625#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x00000010 6626#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6627#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6628#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007fffL 6629#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x00000000 6630#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000L 6631#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x00000010 6632#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007fffL 6633#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x00000000 6634#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000L 6635#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x00000010 6636#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6637#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6638#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007fffL 6639#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x00000000 6640#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000L 6641#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x00000010 6642#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007fffL 6643#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x00000000 6644#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000L 6645#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x00000010 6646#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6647#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6648#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007fffL 6649#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x00000000 6650#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000L 6651#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x00000010 6652#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007fffL 6653#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x00000000 6654#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000L 6655#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x00000010 6656#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6657#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6658#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007fffL 6659#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x00000000 6660#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000L 6661#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x00000010 6662#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007fffL 6663#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x00000000 6664#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000L 6665#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x00000010 6666#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6667#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6668#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007fffL 6669#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x00000000 6670#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000L 6671#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x00000010 6672#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007fffL 6673#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x00000000 6674#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000L 6675#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x00000010 6676#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6677#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6678#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007fffL 6679#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x00000000 6680#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000L 6681#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x00000010 6682#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007fffL 6683#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x00000000 6684#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000L 6685#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x00000010 6686#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6687#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6688#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007fffL 6689#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x00000000 6690#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000L 6691#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x00000010 6692#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007fffL 6693#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x00000000 6694#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000L 6695#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x00000010 6696#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6697#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6698#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007fffL 6699#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x00000000 6700#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000L 6701#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x00000010 6702#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007fffL 6703#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x00000000 6704#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000L 6705#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x00000010 6706#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6707#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6708#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007fffL 6709#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x00000000 6710#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000L 6711#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x00000010 6712#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007fffL 6713#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x00000000 6714#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000L 6715#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x00000010 6716#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6717#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6718#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007fffL 6719#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x00000000 6720#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000L 6721#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x00000010 6722#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007fffL 6723#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x00000000 6724#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000L 6725#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x00000010 6726#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6727#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6728#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007fffL 6729#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x00000000 6730#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000L 6731#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x00000010 6732#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007fffL 6733#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x00000000 6734#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000L 6735#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x00000010 6736#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6737#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6738#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007fffL 6739#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x00000000 6740#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000L 6741#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x00000010 6742#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007fffL 6743#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x00000000 6744#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000L 6745#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x00000010 6746#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6747#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6748#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007fffL 6749#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x00000000 6750#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000L 6751#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x00000010 6752#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007fffL 6753#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x00000000 6754#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000L 6755#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x00000010 6756#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6757#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6758#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007fffL 6759#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x00000000 6760#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000L 6761#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x00000010 6762#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007fffL 6763#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x00000000 6764#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000L 6765#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x00000010 6766#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6767#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6768#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffffL 6769#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x00000000 6770#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffffL 6771#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x00000000 6772#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffffL 6773#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x00000000 6774#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffffL 6775#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x00000000 6776#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffffL 6777#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x00000000 6778#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffffL 6779#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x00000000 6780#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffffL 6781#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x00000000 6782#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffffL 6783#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x00000000 6784#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffffL 6785#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x00000000 6786#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffffL 6787#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x00000000 6788#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffffL 6789#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x00000000 6790#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffffL 6791#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x00000000 6792#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffffL 6793#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x00000000 6794#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffffL 6795#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x00000000 6796#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffffL 6797#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x00000000 6798#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffffL 6799#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x00000000 6800#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffffL 6801#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x00000000 6802#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffffL 6803#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x00000000 6804#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffffL 6805#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x00000000 6806#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffffL 6807#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x00000000 6808#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffffL 6809#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x00000000 6810#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffffL 6811#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x00000000 6812#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffffL 6813#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x00000000 6814#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffffL 6815#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x00000000 6816#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffffL 6817#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x00000000 6818#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffffL 6819#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x00000000 6820#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffffL 6821#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x00000000 6822#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffffL 6823#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x00000000 6824#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffffL 6825#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x00000000 6826#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffffL 6827#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x00000000 6828#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffffL 6829#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x00000000 6830#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffffL 6831#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x00000000 6832#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000ffffL 6833#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 6834#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000L 6835#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 6836#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007fffL 6837#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 6838#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000L 6839#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 6840#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007fffL 6841#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 6842#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000L 6843#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 6844#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 6845#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f 6846#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L 6847#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f 6848#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL 6849#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 6850#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL 6851#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 6852#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001ffL 6853#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x00000000 6854#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01ff0000L 6855#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x00000010 6856#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL 6857#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 6858#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L 6859#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x00000004 6860#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L 6861#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x00000002 6862#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L 6863#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x00000003 6864#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L 6865#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x00000000 6866#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffffL 6867#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x00000000 6868#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00ffffffL 6869#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x00000000 6870#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL 6871#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6872#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6873#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6874#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL 6875#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 6876#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L 6877#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 6878#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 6879#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 6880#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L 6881#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a 6882#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL 6883#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 6884#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL 6885#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6886#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6887#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6888#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL 6889#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 6890#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L 6891#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a 6892#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L 6893#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 6894#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L 6895#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a 6896#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL 6897#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 6898#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL 6899#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6900#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6901#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6902#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L 6903#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 6904#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL 6905#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 6906#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL 6907#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 6908#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 6909#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 6910#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L 6911#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 6912#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL 6913#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 6914#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L 6915#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 6916#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL 6917#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 6918#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL 6919#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 6920#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L 6921#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 6922#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL 6923#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 6924#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL 6925#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 6926#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffffL 6927#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x00000000 6928#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L 6929#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x00000008 6930#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000ffL 6931#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x00000000 6932#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL 6933#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 6934#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL 6935#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 6936#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L 6937#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x00000005 6938#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L 6939#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x00000001 6940#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L 6941#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x00000006 6942#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L 6943#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x00000002 6944#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000ff00L 6945#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x00000008 6946#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L 6947#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x00000007 6948#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L 6949#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x00000003 6950#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L 6951#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x00000004 6952#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L 6953#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x00000000 6954#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L 6955#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x0000001e 6956#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L 6957#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x0000001f 6958#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L 6959#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 6960#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L 6961#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 6962#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L 6963#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 6964#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L 6965#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 6966#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L 6967#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 6968#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L 6969#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 6970#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L 6971#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 6972#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L 6973#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 6974#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L 6975#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c 6976#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L 6977#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b 6978#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L 6979#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d 6980#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L 6981#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 6982#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L 6983#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 6984#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L 6985#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 6986#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L 6987#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 6988#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L 6989#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 6990#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 6991#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 6992#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL 6993#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 6994#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 6995#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 6996#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 6997#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 6998#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 6999#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 7000#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffffL 7001#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 7002#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 7003#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 7004#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 7005#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 7006#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffffL 7007#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 7008#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffffL 7009#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x00000000 7010#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffffL 7011#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x00000000 7012#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffffL 7013#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x00000000 7014#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffffL 7015#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x00000000 7016#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffffL 7017#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x00000000 7018#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffffL 7019#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x00000000 7020#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L 7021#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x00000000 7022#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffffL 7023#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x00000000 7024#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 7025#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 7026#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL 7027#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 7028#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 7029#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 7030#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 7031#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 7032#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffffL 7033#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 7034#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffffL 7035#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x00000000 7036#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffffL 7037#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x00000000 7038#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 7039#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 7040#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 7041#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 7042#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffffL 7043#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 7044#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L 7045#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x00000001 7046#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L 7047#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x00000000 7048#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L 7049#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x00000002 7050#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007fff8L 7051#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x00000003 7052#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000L 7053#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x00000013 7054#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L 7055#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x00000000 7056#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffeL 7057#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x00000001 7058#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L 7059#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x0000001b 7060#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L 7061#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x00000000 7062#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x0000ff00L 7063#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x00000008 7064#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L 7065#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x0000001c 7066#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L 7067#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x00000001 7068#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000fcL 7069#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x00000002 7070#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L 7071#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x0000001d 7072#define RLC_CGCG_CGLS_CTRL__SPARE_MASK 0x80000000L 7073#define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT 0x0000001f 7074#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000fL 7075#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x00000000 7076#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000f0L 7077#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x00000004 7078#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0fff0000L 7079#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x00000010 7080#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000L 7081#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x0000001c 7082#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000f00L 7083#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x00000008 7084#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000f000L 7085#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0x0000000c 7086#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffffL 7087#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x00000000 7088#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L 7089#define RLC_CNTL__FORCE_RETRY__SHIFT 0x00000001 7090#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L 7091#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x00000002 7092#define RLC_CNTL__RESERVED_MASK 0xffffff00L 7093#define RLC_CNTL__RESERVED__SHIFT 0x00000008 7094#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L 7095#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x00000000 7096#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L 7097#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x00000003 7098#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x00000010L 7099#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x00000004 7100#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffffL 7101#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x00000000 7102#define RLC_DEBUG__DATA_MASK 0xffffffffL 7103#define RLC_DEBUG__DATA__SHIFT 0x00000000 7104#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffff8000L 7105#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x0000000f 7106#define RLC_DEBUG_SELECT__SELECT_MASK 0x000000ffL 7107#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x00000000 7108#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x00000010L 7109#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x00000004 7110#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x00000001L 7111#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x00000000 7112#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0x0000000eL 7113#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x00000001 7114#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0L 7115#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x00000005 7116#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffffL 7117#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x00000000 7118#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffffL 7119#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x00000000 7120#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001ffL 7121#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x00000000 7122#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00L 7123#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x00000009 7124#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffffL 7125#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x00000000 7126#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0L 7127#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x00000006 7128#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003fL 7129#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x00000000 7130#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffffL 7131#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x00000000 7132#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffffL 7133#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x00000000 7134#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffffL 7135#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x00000000 7136#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000ff0L 7137#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x00000004 7138#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L 7139#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x00000001 7140#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L 7141#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x00000003 7142#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L 7143#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x00000002 7144#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L 7145#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x00000000 7146#define RLC_LB_CNTL__RESERVED_MASK 0xfffffff0L 7147#define RLC_LB_CNTL__RESERVED__SHIFT 0x00000004 7148#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffffL 7149#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x00000000 7150#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffffL 7151#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x00000000 7152#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffffL 7153#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x00000000 7154#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000feL 7155#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x00000001 7156#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000L 7157#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x00000010 7158#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000ff00L 7159#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x00000008 7160#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L 7161#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x00000000 7162#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffffL 7163#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x00000000 7164#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000ffL 7165#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x00000000 7166#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00L 7167#define RLC_MAX_PG_CU__SPARE__SHIFT 0x00000008 7168#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000L 7169#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x0000001c 7170#define RLC_MC_CNTL__RDNFO_URG_MASK 0x00f00000L 7171#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x00000014 7172#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x08000000L 7173#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x0000001b 7174#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x03000000L 7175#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x00000018 7176#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x04000000L 7177#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x0000001a 7178#define RLC_MC_CNTL__RESERVED_B_MASK 0x000fe000L 7179#define RLC_MC_CNTL__RESERVED_B__SHIFT 0x0000000d 7180#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000L 7181#define RLC_MC_CNTL__RESERVED__SHIFT 0x0000001d 7182#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x00000010L 7183#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x00000004 7184#define RLC_MC_CNTL__WRNFO_URG_MASK 0x000001e0L 7185#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x00000005 7186#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x00001e00L 7187#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x00000009 7188#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x00000008L 7189#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x00000003 7190#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x00000003L 7191#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x00000000 7192#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x00000004L 7193#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x00000002 7194#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L 7195#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018 7196#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x000000fcL 7197#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002 7198#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L 7199#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x00000001 7200#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L 7201#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x00000000 7202#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00ff0000L 7203#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x00000010 7204#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000ff00L 7205#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x00000008 7206#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 7207#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 7208#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 7209#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 7210#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL 7211#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 7212#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 7213#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 7214#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 7215#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 7216#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL 7217#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 7218#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L 7219#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a 7220#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L 7221#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 7222#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffffL 7223#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x00000000 7224#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L 7225#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x00000010 7226#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L 7227#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x00000002 7228#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L 7229#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x00000000 7230#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L 7231#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x00000001 7232#define RLC_PG_CNTL__PG_ERROR_STATUS_MASK 0xff000000L 7233#define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT 0x00000018 7234#define RLC_PG_CNTL__RESERVED1_MASK 0x00f80000L 7235#define RLC_PG_CNTL__RESERVED1__SHIFT 0x00000013 7236#define RLC_PG_CNTL__RESERVED_MASK 0xfffffff0L 7237#define RLC_PG_CNTL__RESERVED__SHIFT 0x00000004 7238#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L 7239#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x00000012 7240#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L 7241#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x00000011 7242#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L 7243#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x00000003 7244#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffffL 7245#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x00000000 7246#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffffL 7247#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x00000000 7248#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffffL 7249#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x00000000 7250#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffffL 7251#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x00000000 7252#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000fL 7253#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x00000000 7254#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x0000c000L 7255#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x0000000e 7256#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x00003800L 7257#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0x0000000b 7258#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001c0L 7259#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x00000006 7260#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000200L 7261#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x00000009 7262#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00000400L 7263#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0x0000000a 7264#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L 7265#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x00000004 7266#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xffffc000L 7267#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x0000000e 7268#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000ffL 7269#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x00000000 7270#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK 0x00100000L 7271#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT 0x00000014 7272#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK 0x00200000L 7273#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT 0x00000015 7274#define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK 0x00020000L 7275#define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT 0x00000011 7276#define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK 0x00010000L 7277#define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT 0x00000010 7278#define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK 0x00080000L 7279#define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT 0x00000013 7280#define RLC_SERDES_WR_CTRL__CGLS_ON_MASK 0x00040000L 7281#define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT 0x00000012 7282#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK 0x00400000L 7283#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT 0x00000016 7284#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK 0x00800000L 7285#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT 0x00000017 7286#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L 7287#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0x0000000a 7288#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L 7289#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0x0000000b 7290#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L 7291#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x00000008 7292#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L 7293#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x00000009 7294#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L 7295#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0x0000000d 7296#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000L 7297#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x0000001c 7298#define RLC_SERDES_WR_CTRL__RESERVED_1_MASK 0x0000c000L 7299#define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT 0x0000000e 7300#define RLC_SERDES_WR_CTRL__RESERVED_2_MASK 0x0f000000L 7301#define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT 0x00000018 7302#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L 7303#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0x0000000c 7304#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffffL 7305#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x00000000 7306#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffeL 7307#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x00000001 7308#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L 7309#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x00000000 7310#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffeL 7311#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x00000001 7312#define RLC_SMU_PG_CTRL__START_PG_MASK 0x00000001L 7313#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x00000000 7314#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffeL 7315#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x00000001 7316#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x00000001L 7317#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x00000000 7318#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffeL 7319#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x00000001 7320#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x00000001L 7321#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x00000000 7322#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffffL 7323#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x00000000 7324#define RLC_STAT__RESERVED_MASK 0xfffffff0L 7325#define RLC_STAT__RESERVED__SHIFT 0x00000004 7326#define RLC_STAT__RLC_BUSY_MASK 0x00000001L 7327#define RLC_STAT__RLC_BUSY__SHIFT 0x00000000 7328#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L 7329#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x00000001 7330#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L 7331#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x00000002 7332#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000ffL 7333#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x00000000 7334#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000ff00L 7335#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x00000008 7336#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00ff0000L 7337#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x00000010 7338#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000L 7339#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x00000018 7340#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffffL 7341#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x00000000 7342#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffffL 7343#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x00000000 7344#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL 7345#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 7346#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL 7347#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 7348#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL 7349#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 7350#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL 7351#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 7352#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL 7353#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 7354#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL 7355#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 7356#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL 7357#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 7358#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL 7359#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 7360#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L 7361#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x00000010 7362#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000ffL 7363#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x00000000 7364#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000L 7365#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x0000001f 7366#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000L 7367#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x0000001c 7368#define SETUP_DEBUG_REG0__event_id_gated_MASK 0x0fc00000L 7369#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x00000016 7370#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00200000L 7371#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000015 7372#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00008000L 7373#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000f 7374#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00004000L 7375#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000e 7376#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00080000L 7377#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x00000013 7378#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000L 7379#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x0000001d 7380#define SETUP_DEBUG_REG0__pmode_state_MASK 0x00003f00L 7381#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000008 7382#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x00000003L 7383#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x00000000 7384#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x00030000L 7385#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x00000010 7386#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00040000L 7387#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x00000012 7388#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00100000L 7389#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000014 7390#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000003cL 7391#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000002 7392#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000L 7393#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x0000001e 7394#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000L 7395#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x00000010 7396#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0x0000ffffL 7397#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x00000000 7398#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000L 7399#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x00000010 7400#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0x0000ffffL 7401#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x00000000 7402#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000L 7403#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x00000010 7404#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0x0000ffffL 7405#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x00000000 7406#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x00003fffL 7407#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 7408#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00008000L 7409#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000f 7410#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00080000L 7411#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000013 7412#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x00700000L 7413#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000014 7414#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x03000000L 7415#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000018 7416#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000L 7417#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001f 7418#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000L 7419#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001d 7420#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00004000L 7421#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000e 7422#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x00070000L 7423#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x00000010 7424#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000L 7425#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x0000001a 7426#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00800000L 7427#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000017 7428#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x0fffc000L 7429#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000e 7430#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x00003fffL 7431#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 7432#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000L 7433#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x0000001f 7434#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000L 7435#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x0000001c 7436#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000L 7437#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x0000001e 7438#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000ffffL 7439#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x00000000 7440#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000L 7441#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x00000010 7442#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000ffffL 7443#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x00000000 7444#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000L 7445#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x00000010 7446#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L 7447#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x00000000 7448#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L 7449#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x00000003 7450#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001c0L 7451#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x00000006 7452#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000e00L 7453#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x00000009 7454#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L 7455#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0x0000000c 7456#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000c000L 7457#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0x0000000e 7458#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L 7459#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x00000010 7460#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000c0000L 7461#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x00000012 7462#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L 7463#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x00000018 7464#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L 7465#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x00000008 7466#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L 7467#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0x0000000c 7468#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L 7469#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x00000000 7470#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L 7471#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x00000004 7472#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L 7473#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x00000010 7474#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L 7475#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x00000014 7476#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L 7477#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x00000008 7478#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L 7479#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x00000004 7480#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003c00L 7481#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0x0000000a 7482#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L 7483#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x00000009 7484#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L 7485#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x00000006 7486#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000L 7487#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x00000010 7488#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L 7489#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x00000007 7490#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000fL 7491#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x00000000 7492#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L 7493#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x00000019 7494#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L 7495#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x00000018 7496#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00e00000L 7497#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x00000015 7498#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001fffffL 7499#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x00000000 7500#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L 7501#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x0000001a 7502#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L 7503#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x0000001b 7504#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000080L 7505#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x00000007 7506#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000100L 7507#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x00000008 7508#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000200L 7509#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0x00000009 7510#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L 7511#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0x0000000b 7512#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L 7513#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0x0000000c 7514#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L 7515#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0x0000000d 7516#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L 7517#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0x0000000e 7518#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L 7519#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0x0000000f 7520#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000080L 7521#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x00000007 7522#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x00000004L 7523#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x00000002 7524#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00008000L 7525#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x0000000f 7526#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00010000L 7527#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x00000010 7528#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000008L 7529#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x00000003 7530#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000002L 7531#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x00000001 7532#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00000400L 7533#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x0000000a 7534#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00000800L 7535#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x0000000b 7536#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x00000001L 7537#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x00000000 7538#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00100000L 7539#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x00000014 7540#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000020L 7541#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x00000005 7542#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000040L 7543#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x00000006 7544#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00001000L 7545#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x0000000c 7546#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00002000L 7547#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x0000000d 7548#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00020000L 7549#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x00000011 7550#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000010L 7551#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x00000004 7552#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x00000001L 7553#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x00000000 7554#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x000003e0L 7555#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x00000005 7556#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0x0e000000L 7557#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x00000019 7558#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000L 7559#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x0000001f 7560#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x00010000L 7561#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x00000010 7562#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0x0000fc00L 7563#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0x0000000a 7564#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0x0000001eL 7565#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x00000001 7566#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x00020000L 7567#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x00000011 7568#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x00040000L 7569#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x00000012 7570#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x00080000L 7571#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x00000013 7572#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x00100000L 7573#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x00000014 7574#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x00200000L 7575#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x00000015 7576#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x00400000L 7577#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x00000016 7578#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x00800000L 7579#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x00000017 7580#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x01000000L 7581#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x00000018 7582#define SPI_DEBUG_READ__DATA_MASK 0x00ffffffL 7583#define SPI_DEBUG_READ__DATA__SHIFT 0x00000000 7584#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000ff00L 7585#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x00000008 7586#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000ffL 7587#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x00000000 7588#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000L 7589#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x00000010 7590#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L 7591#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x00000000 7592#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L 7593#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x00000001 7594#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L 7595#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0x0000000b 7596#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001cL 7597#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x00000002 7598#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000e0L 7599#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x00000005 7600#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L 7601#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x00000008 7602#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L 7603#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0x0000000e 7604#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L 7605#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x00000000 7606#define SPI_LB_CU_MASK__CU_MASK_MASK 0x0000ffffL 7607#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x00000000 7608#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffffL 7609#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x00000000 7610#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 7611#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 7612#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 7613#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 7614#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL 7615#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 7616#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L 7617#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 7618#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 7619#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 7620#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L 7621#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a 7622#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL 7623#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 7624#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 7625#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 7626#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 7627#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 7628#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL 7629#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 7630#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L 7631#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a 7632#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L 7633#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 7634#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L 7635#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a 7636#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL 7637#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 7638#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 7639#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 7640#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 7641#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 7642#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003ffL 7643#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x00000000 7644#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000ffc00L 7645#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0x0000000a 7646#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L 7647#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 7648#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000ffc00L 7649#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a 7650#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL 7651#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 7652#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 7653#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 7654#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 7655#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 7656#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003ffL 7657#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x00000000 7658#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000ffc00L 7659#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0x0000000a 7660#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L 7661#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 7662#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000ffc00L 7663#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0x0000000a 7664#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL 7665#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 7666#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000f0L 7667#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x00000004 7668#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000fL 7669#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x00000000 7670#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000f000L 7671#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0x0000000c 7672#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000f00L 7673#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x00000008 7674#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00f00000L 7675#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x00000014 7676#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000f0000L 7677#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x00000010 7678#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000L 7679#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x0000001c 7680#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0f000000L 7681#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x00000018 7682#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0x0000ffffL 7683#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x00000000 7684#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L 7685#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0x0000000e 7686#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003fL 7687#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x00000000 7688#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L 7689#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x00000006 7690#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L 7691#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0x0000000d 7692#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L 7693#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0x0000000c 7694#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L 7695#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x00000005 7696#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L 7697#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x00000006 7698#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L 7699#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x00000004 7700#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L 7701#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007 7702#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L 7703#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x00000001 7704#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L 7705#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x00000002 7706#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L 7707#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003 7708#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L 7709#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x00000000 7710#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L 7711#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0x0000000f 7712#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L 7713#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0x0000000b 7714#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L 7715#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x00000008 7716#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L 7717#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x00000009 7718#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L 7719#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0x0000000a 7720#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L 7721#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e 7722#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001e000L 7723#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0x0000000d 7724#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L 7725#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x00000008 7726#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L 7727#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x00000012 7728#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L 7729#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0x0000000a 7730#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003fL 7731#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x00000000 7732#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L 7733#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x00000011 7734#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001e000L 7735#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0x0000000d 7736#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L 7737#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x00000008 7738#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L 7739#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x00000012 7740#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L 7741#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0x0000000a 7742#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003fL 7743#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x00000000 7744#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L 7745#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x00000011 7746#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001e000L 7747#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0x0000000d 7748#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L 7749#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x00000008 7750#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L 7751#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x00000012 7752#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L 7753#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0x0000000a 7754#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003fL 7755#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x00000000 7756#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L 7757#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x00000011 7758#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001e000L 7759#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0x0000000d 7760#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L 7761#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x00000008 7762#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L 7763#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x00000012 7764#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L 7765#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0x0000000a 7766#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003fL 7767#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x00000000 7768#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L 7769#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x00000011 7770#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001e000L 7771#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0x0000000d 7772#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L 7773#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x00000008 7774#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L 7775#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x00000012 7776#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L 7777#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0x0000000a 7778#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003fL 7779#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x00000000 7780#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L 7781#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x00000011 7782#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001e000L 7783#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0x0000000d 7784#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L 7785#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x00000008 7786#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L 7787#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x00000012 7788#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L 7789#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0x0000000a 7790#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003fL 7791#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x00000000 7792#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L 7793#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x00000011 7794#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001e000L 7795#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0x0000000d 7796#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L 7797#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x00000008 7798#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L 7799#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x00000012 7800#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L 7801#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0x0000000a 7802#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003fL 7803#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x00000000 7804#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L 7805#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x00000011 7806#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001e000L 7807#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0x0000000d 7808#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L 7809#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x00000008 7810#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L 7811#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x00000012 7812#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L 7813#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0x0000000a 7814#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003fL 7815#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x00000000 7816#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L 7817#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x00000011 7818#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001e000L 7819#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0x0000000d 7820#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L 7821#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x00000008 7822#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L 7823#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x00000012 7824#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L 7825#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0x0000000a 7826#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003fL 7827#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x00000000 7828#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L 7829#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x00000011 7830#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001e000L 7831#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0x0000000d 7832#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L 7833#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x00000008 7834#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L 7835#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x00000012 7836#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L 7837#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0x0000000a 7838#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003fL 7839#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x00000000 7840#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L 7841#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x00000011 7842#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001e000L 7843#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0x0000000d 7844#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L 7845#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x00000008 7846#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L 7847#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x00000012 7848#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L 7849#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0x0000000a 7850#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003fL 7851#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x00000000 7852#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L 7853#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x00000011 7854#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001e000L 7855#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0x0000000d 7856#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L 7857#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x00000008 7858#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L 7859#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x00000012 7860#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L 7861#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0x0000000a 7862#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003fL 7863#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x00000000 7864#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L 7865#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x00000011 7866#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L 7867#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x00000008 7868#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L 7869#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x00000012 7870#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L 7871#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0x0000000a 7872#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003fL 7873#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x00000000 7874#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L 7875#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x00000008 7876#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L 7877#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x00000012 7878#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L 7879#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0x0000000a 7880#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003fL 7881#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x00000000 7882#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L 7883#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x00000008 7884#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L 7885#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x00000012 7886#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L 7887#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0x0000000a 7888#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003fL 7889#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x00000000 7890#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L 7891#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x00000008 7892#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L 7893#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x00000012 7894#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L 7895#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0x0000000a 7896#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003fL 7897#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x00000000 7898#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L 7899#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x00000008 7900#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L 7901#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x00000012 7902#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L 7903#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0x0000000a 7904#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003fL 7905#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x00000000 7906#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L 7907#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x00000008 7908#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L 7909#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x00000012 7910#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L 7911#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0x0000000a 7912#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003fL 7913#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x00000000 7914#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L 7915#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x00000008 7916#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L 7917#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x00000012 7918#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L 7919#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0x0000000a 7920#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003fL 7921#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x00000000 7922#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L 7923#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x00000008 7924#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L 7925#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x00000012 7926#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L 7927#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0x0000000a 7928#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003fL 7929#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x00000000 7930#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L 7931#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x00000008 7932#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L 7933#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x00000012 7934#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L 7935#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0x0000000a 7936#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003fL 7937#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x00000000 7938#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L 7939#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x00000008 7940#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L 7941#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x00000012 7942#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L 7943#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0x0000000a 7944#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003fL 7945#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x00000000 7946#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001e000L 7947#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0x0000000d 7948#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L 7949#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x00000008 7950#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L 7951#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x00000012 7952#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L 7953#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0x0000000a 7954#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003fL 7955#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x00000000 7956#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L 7957#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x00000011 7958#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L 7959#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x00000008 7960#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L 7961#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x00000012 7962#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L 7963#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0x0000000a 7964#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003fL 7965#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x00000000 7966#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L 7967#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x00000008 7968#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L 7969#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x00000012 7970#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L 7971#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0x0000000a 7972#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003fL 7973#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x00000000 7974#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001e000L 7975#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0x0000000d 7976#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L 7977#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x00000008 7978#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L 7979#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x00000012 7980#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L 7981#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0x0000000a 7982#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003fL 7983#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x00000000 7984#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L 7985#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x00000011 7986#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001e000L 7987#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0x0000000d 7988#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L 7989#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x00000008 7990#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L 7991#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x00000012 7992#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L 7993#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0x0000000a 7994#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003fL 7995#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x00000000 7996#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L 7997#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x00000011 7998#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001e000L 7999#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0x0000000d 8000#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L 8001#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x00000008 8002#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L 8003#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x00000012 8004#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L 8005#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0x0000000a 8006#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003fL 8007#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x00000000 8008#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L 8009#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x00000011 8010#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001e000L 8011#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0x0000000d 8012#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L 8013#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x00000008 8014#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L 8015#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x00000012 8016#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L 8017#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0x0000000a 8018#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003fL 8019#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x00000000 8020#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L 8021#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x00000011 8022#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001e000L 8023#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0x0000000d 8024#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L 8025#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x00000008 8026#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L 8027#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x00000012 8028#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L 8029#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0x0000000a 8030#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003fL 8031#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x00000000 8032#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L 8033#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x00000011 8034#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001e000L 8035#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0x0000000d 8036#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L 8037#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x00000008 8038#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L 8039#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x00000012 8040#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L 8041#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0x0000000a 8042#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003fL 8043#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x00000000 8044#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L 8045#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x00000011 8046#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001e000L 8047#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0x0000000d 8048#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L 8049#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x00000008 8050#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L 8051#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x00000012 8052#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L 8053#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0x0000000a 8054#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003fL 8055#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x00000000 8056#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L 8057#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x00000011 8058#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L 8059#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0x0000000d 8060#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L 8061#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0x0000000c 8062#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L 8063#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x00000005 8064#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L 8065#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x00000006 8066#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L 8067#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x00000004 8068#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L 8069#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007 8070#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L 8071#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x00000001 8072#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L 8073#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x00000002 8074#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L 8075#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003 8076#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L 8077#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x00000000 8078#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L 8079#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0x0000000f 8080#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L 8081#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0x0000000b 8082#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L 8083#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x00000008 8084#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L 8085#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x00000009 8086#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L 8087#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0x0000000a 8088#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L 8089#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e 8090#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000fffL 8091#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x00000000 8092#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000fL 8093#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x00000000 8094#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000f0L 8095#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x00000004 8096#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000f00L 8097#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x00000008 8098#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000f000L 8099#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0x0000000c 8100#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000f0000L 8101#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x00000010 8102#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00f00000L 8103#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x00000014 8104#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0f000000L 8105#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x00000018 8106#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000L 8107#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x0000001c 8108#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0x000000ffL 8109#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x00000000 8110#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0x000000ffL 8111#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x00000000 8112#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0x000000ffL 8113#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x00000000 8114#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0x000000ffL 8115#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x00000000 8116#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0x000000ffL 8117#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x00000000 8118#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0x000000ffL 8119#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x00000000 8120#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffffL 8121#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x00000000 8122#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffffL 8123#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x00000000 8124#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffffL 8125#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x00000000 8126#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffffL 8127#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x00000000 8128#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffffL 8129#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x00000000 8130#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffffL 8131#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x00000000 8132#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000L 8133#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x0000001b 8134#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000L 8135#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x0000001e 8136#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x04000000L 8137#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x0000001a 8138#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x00400000L 8139#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x00000016 8140#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x00200000L 8141#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x00000015 8142#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0x000ff000L 8143#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0x0000000c 8144#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x00800000L 8145#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x00000017 8146#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0x00000c00L 8147#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0x0000000a 8148#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x00100000L 8149#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x00000014 8150#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x000003c0L 8151#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x00000006 8152#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x03000000L 8153#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x00000018 8154#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x0000003fL 8155#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x00000000 8156#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0x0e000000L 8157#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x00000019 8158#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L 8159#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x0000001c 8160#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L 8161#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x00000018 8162#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L 8163#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x00000016 8164#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L 8165#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x00000015 8166#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000ff000L 8167#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0x0000000c 8168#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L 8169#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x00000017 8170#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000c00L 8171#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0x0000000a 8172#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L 8173#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x00000014 8174#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003c0L 8175#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x00000006 8176#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003fL 8177#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x00000000 8178#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x07000000L 8179#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x00000018 8180#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L 8181#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x0000001b 8182#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L 8183#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x00000016 8184#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L 8185#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x00000015 8186#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000ff000L 8187#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0x0000000c 8188#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L 8189#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x00000017 8190#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000c00L 8191#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0x0000000a 8192#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L 8193#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x00000014 8194#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003c0L 8195#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x00000006 8196#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003fL 8197#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x00000000 8198#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000L 8199#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x0000001a 8200#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000L 8201#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x0000001d 8202#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x00400000L 8203#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x00000016 8204#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x00200000L 8205#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x00000015 8206#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0x000ff000L 8207#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0x0000000c 8208#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x00800000L 8209#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x00000017 8210#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0x00000c00L 8211#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0x0000000a 8212#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x00100000L 8213#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x00000014 8214#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x000003c0L 8215#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x00000006 8216#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x03000000L 8217#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x00000018 8218#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x0000003fL 8219#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x00000000 8220#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0x0e000000L 8221#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x00000019 8222#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L 8223#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x0000001c 8224#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L 8225#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x00000018 8226#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L 8227#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x00000016 8228#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L 8229#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x00000015 8230#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000ff000L 8231#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0x0000000c 8232#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L 8233#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x00000017 8234#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000c00L 8235#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0x0000000a 8236#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L 8237#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x00000014 8238#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003c0L 8239#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x00000006 8240#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003fL 8241#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x00000000 8242#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000L 8243#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x0000001b 8244#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000L 8245#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x0000001e 8246#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L 8247#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x0000001a 8248#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x00400000L 8249#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x00000016 8250#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L 8251#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x00000015 8252#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000ff000L 8253#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0x0000000c 8254#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L 8255#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x00000017 8256#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000c00L 8257#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0x0000000a 8258#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L 8259#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x00000014 8260#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003c0L 8261#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x00000006 8262#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L 8263#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x00000018 8264#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003fL 8265#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x00000000 8266#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x00007f00L 8267#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x00000008 8268#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x0001ff00L 8269#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x00000008 8270#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000L 8271#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x00000014 8272#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x00000080L 8273#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x00000007 8274#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x00000001L 8275#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x00000000 8276#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x00000040L 8277#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x00000006 8278#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x0000003eL 8279#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x00000001 8280#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000L 8281#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x00000014 8282#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x00000080L 8283#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x00000007 8284#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x00000001L 8285#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x00000000 8286#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x00000040L 8287#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x00000006 8288#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x0000003eL 8289#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x00000001 8290#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x0001ff00L 8291#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x00000008 8292#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000L 8293#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x00000014 8294#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x00000080L 8295#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x00000007 8296#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x00000001L 8297#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x00000000 8298#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x00000040L 8299#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x00000006 8300#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x0000003eL 8301#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x00000001 8302#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x00003f80L 8303#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x00000007 8304#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L 8305#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x00000000 8306#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L 8307#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x00000006 8308#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003eL 8309#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x00000001 8310#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000fe00L 8311#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x00000009 8312#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L 8313#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x00000007 8314#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L 8315#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x00000000 8316#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L 8317#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x00000008 8318#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L 8319#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x00000006 8320#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003eL 8321#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x00000001 8322#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x01ff0000L 8323#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x00000010 8324#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0x0000ff80L 8325#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x00000007 8326#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x00000001L 8327#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x00000000 8328#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x00000040L 8329#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x00000006 8330#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x0000003eL 8331#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x00000001 8332#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x007f0000L 8333#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x00000010 8334#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x01ff0000L 8335#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x00000010 8336#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0x0000ff80L 8337#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x00000007 8338#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x00000001L 8339#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x00000000 8340#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x00000040L 8341#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x00000006 8342#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x0000003eL 8343#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x00000001 8344#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0x0000ff80L 8345#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x00000007 8346#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x00000001L 8347#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x00000000 8348#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x00000040L 8349#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x00000006 8350#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x0000003eL 8351#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x00000001 8352#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x01ff0000L 8353#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x00000010 8354#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0x0000ff80L 8355#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x00000007 8356#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x00000001L 8357#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x00000000 8358#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x00000040L 8359#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x00000006 8360#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x0000003eL 8361#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x00000001 8362#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x007f0000L 8363#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x00000010 8364#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000ff00L 8365#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x00000008 8366#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L 8367#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x00000000 8368#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L 8369#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x00000006 8370#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003eL 8371#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x00000001 8372#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L 8373#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x00000007 8374#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x000fe000L 8375#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0x0000000d 8376#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L 8377#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x00000007 8378#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L 8379#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x00000000 8380#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L 8381#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x00000008 8382#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L 8383#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x00000009 8384#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L 8385#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0x0000000a 8386#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L 8387#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0x0000000b 8388#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L 8389#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0x0000000c 8390#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L 8391#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x00000006 8392#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003eL 8393#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x00000001 8394#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000fL 8395#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x00000000 8396#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000f0L 8397#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x00000004 8398#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000f00L 8399#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x00000008 8400#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000f000L 8401#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0x0000000c 8402#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0x000000ffL 8403#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x00000000 8404#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0x000000ffL 8405#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x00000000 8406#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0x000000ffL 8407#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x00000000 8408#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0x000000ffL 8409#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x00000000 8410#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0x000000ffL 8411#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x00000000 8412#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0x000000ffL 8413#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x00000000 8414#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffffL 8415#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x00000000 8416#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffffL 8417#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x00000000 8418#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffffL 8419#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x00000000 8420#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffffL 8421#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x00000000 8422#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffffL 8423#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x00000000 8424#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffffL 8425#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x00000000 8426#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0x000000ffL 8427#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x00000000 8428#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0x000000ffL 8429#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x00000000 8430#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0x000000ffL 8431#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x00000000 8432#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0x000000ffL 8433#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x00000000 8434#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0x000000ffL 8435#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x00000000 8436#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0x000000ffL 8437#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x00000000 8438#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffffL 8439#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x00000000 8440#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffffL 8441#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x00000000 8442#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffffL 8443#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x00000000 8444#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffffL 8445#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x00000000 8446#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffffL 8447#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x00000000 8448#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffffL 8449#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x00000000 8450#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffffL 8451#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x00000000 8452#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffffL 8453#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x00000000 8454#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffffL 8455#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x00000000 8456#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffffL 8457#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x00000000 8458#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffffL 8459#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x00000000 8460#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffffL 8461#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x00000000 8462#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffffL 8463#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x00000000 8464#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffffL 8465#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x00000000 8466#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffffL 8467#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x00000000 8468#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffffL 8469#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x00000000 8470#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffffL 8471#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x00000000 8472#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffffL 8473#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x00000000 8474#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffffL 8475#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x00000000 8476#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffffL 8477#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x00000000 8478#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffffL 8479#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x00000000 8480#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffffL 8481#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x00000000 8482#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffffL 8483#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x00000000 8484#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffffL 8485#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x00000000 8486#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffffL 8487#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x00000000 8488#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffffL 8489#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x00000000 8490#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffffL 8491#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x00000000 8492#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffffL 8493#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x00000000 8494#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffffL 8495#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x00000000 8496#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffffL 8497#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x00000000 8498#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffffL 8499#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x00000000 8500#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffffL 8501#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x00000000 8502#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffffL 8503#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x00000000 8504#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffffL 8505#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x00000000 8506#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffffL 8507#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x00000000 8508#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffffL 8509#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x00000000 8510#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffffL 8511#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x00000000 8512#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffffL 8513#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x00000000 8514#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffffL 8515#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x00000000 8516#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffffL 8517#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x00000000 8518#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffffL 8519#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x00000000 8520#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffffL 8521#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x00000000 8522#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffffL 8523#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x00000000 8524#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffffL 8525#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x00000000 8526#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffffL 8527#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x00000000 8528#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffffL 8529#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x00000000 8530#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffffL 8531#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x00000000 8532#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffffL 8533#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x00000000 8534#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffffL 8535#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x00000000 8536#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffffL 8537#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x00000000 8538#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffffL 8539#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x00000000 8540#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffffL 8541#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x00000000 8542#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffffL 8543#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x00000000 8544#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffffL 8545#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x00000000 8546#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffffL 8547#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x00000000 8548#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffffL 8549#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x00000000 8550#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffffL 8551#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x00000000 8552#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffffL 8553#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x00000000 8554#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffffL 8555#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x00000000 8556#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffffL 8557#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x00000000 8558#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffffL 8559#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x00000000 8560#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffffL 8561#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x00000000 8562#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffffL 8563#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x00000000 8564#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffffL 8565#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x00000000 8566#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffffL 8567#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x00000000 8568#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffffL 8569#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x00000000 8570#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffffL 8571#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x00000000 8572#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffffL 8573#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x00000000 8574#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffffL 8575#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x00000000 8576#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffffL 8577#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x00000000 8578#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffffL 8579#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x00000000 8580#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffffL 8581#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x00000000 8582#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffffL 8583#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x00000000 8584#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffffL 8585#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x00000000 8586#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffffL 8587#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x00000000 8588#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffffL 8589#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x00000000 8590#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffffL 8591#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x00000000 8592#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffffL 8593#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x00000000 8594#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffffL 8595#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x00000000 8596#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffffL 8597#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x00000000 8598#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffffL 8599#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x00000000 8600#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffffL 8601#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x00000000 8602#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffffL 8603#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x00000000 8604#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffffL 8605#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x00000000 8606#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffffL 8607#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x00000000 8608#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffffL 8609#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x00000000 8610#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffffL 8611#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x00000000 8612#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffffL 8613#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x00000000 8614#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffffL 8615#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x00000000 8616#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffffL 8617#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x00000000 8618#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffffL 8619#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x00000000 8620#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffffL 8621#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x00000000 8622#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffffL 8623#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x00000000 8624#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffffL 8625#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x00000000 8626#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffffL 8627#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x00000000 8628#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffffL 8629#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x00000000 8630#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffffL 8631#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x00000000 8632#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffffL 8633#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x00000000 8634#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffffL 8635#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x00000000 8636#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffffL 8637#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x00000000 8638#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffffL 8639#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x00000000 8640#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffffL 8641#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x00000000 8642#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000fL 8643#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x00000000 8644#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x00000004L 8645#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x00000002 8646#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x00200000L 8647#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x00000015 8648#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x00000008L 8649#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x00000003 8650#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x00000002L 8651#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x00000001 8652#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x00000001L 8653#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x00000000 8654#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x00000200L 8655#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x00000009 8656#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x00000400L 8657#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0x0000000a 8658#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x00000800L 8659#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0x0000000b 8660#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x00001000L 8661#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0x0000000c 8662#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x00002000L 8663#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0x0000000d 8664#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x00004000L 8665#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0x0000000e 8666#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x00008000L 8667#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0x0000000f 8668#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x00010000L 8669#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x00000010 8670#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x00000020L 8671#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x00000005 8672#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x00000040L 8673#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x00000006 8674#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x00000080L 8675#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x00000007 8676#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x00000100L 8677#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x00000008 8678#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x00000010L 8679#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x00000004 8680#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x00020000L 8681#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x00000011 8682#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x00040000L 8683#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x00000012 8684#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x00080000L 8685#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x00000013 8686#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x00100000L 8687#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x00000014 8688#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000ffffL 8689#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x00000000 8690#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000L 8691#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x00000010 8692#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000ffffL 8693#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x00000000 8694#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000L 8695#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x00000010 8696#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L 8697#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c 8698#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000fffL 8699#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x00000000 8700#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003eL 8701#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x00000001 8702#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L 8703#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x00000006 8704#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL 8705#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000 8706#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L 8707#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010 8708#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL 8709#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000 8710#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000ffffL 8711#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000 8712#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L 8713#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x0000001e 8714#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000L 8715#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x00000010 8716#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L 8717#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x0000001f 8718#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffffL 8719#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x00000000 8720#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L 8721#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x00000017 8722#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x01000000L 8723#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x00000018 8724#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L 8725#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0x0000000f 8726#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L 8727#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009 8728#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L 8729#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000 8730#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L 8731#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003 8732#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L 8733#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006 8734#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x00180000L 8735#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x00000013 8736#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x02000000L 8737#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x00000019 8738#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x04000000L 8739#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x0000001a 8740#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L 8741#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x00000015 8742#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000L 8743#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x0000001b 8744#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L 8745#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0x0000000c 8746#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000L 8747#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x0000001e 8748#define SQC_CACHES__DATA_INVALIDATE_MASK 0x00000002L 8749#define SQC_CACHES__DATA_INVALIDATE__SHIFT 0x00000001 8750#define SQC_CACHES__INST_INVALIDATE_MASK 0x00000001L 8751#define SQC_CACHES__INST_INVALIDATE__SHIFT 0x00000000 8752#define SQC_CACHES__INVALIDATE_VOLATILE_MASK 0x00000004L 8753#define SQC_CACHES__INVALIDATE_VOLATILE__SHIFT 0x00000002 8754#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000cL 8755#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x00000002 8756#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L 8757#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x00000007 8758#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L 8759#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x00000008 8760#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L 8761#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x00000006 8762#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L 8763#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x00000009 8764#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L 8765#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0x0000000a 8766#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L 8767#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x00000000 8768#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L 8769#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x00000004 8770#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L 8771#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0x0000000b 8772#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L 8773#define SQ_CONFIG__DEBUG_EN__SHIFT 0x00000008 8774#define SQ_CONFIG__DISABLE_IB_DEP_CHECK_MASK 0x00000400L 8775#define SQ_CONFIG__DISABLE_IB_DEP_CHECK__SHIFT 0x0000000a 8776#define SQ_CONFIG__DISABLE_SCA_BYPASS_MASK 0x00000200L 8777#define SQ_CONFIG__DISABLE_SCA_BYPASS__SHIFT 0x00000009 8778#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L 8779#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0x0000000f 8780#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L 8781#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0x0000000d 8782#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L 8783#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0x0000000e 8784#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L 8785#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0x0000000c 8786#define SQ_CONFIG__ENABLE_SOFT_CLAUSE_MASK 0x00000800L 8787#define SQ_CONFIG__ENABLE_SOFT_CLAUSE__SHIFT 0x0000000b 8788#define SQ_CONFIG__UNUSED_MASK 0x000000ffL 8789#define SQ_CONFIG__UNUSED__SHIFT 0x00000000 8790#define SQC_SECDED_CNT__DATA_DED_MASK 0xff000000L 8791#define SQC_SECDED_CNT__DATA_DED__SHIFT 0x00000018 8792#define SQC_SECDED_CNT__DATA_SEC_MASK 0x00ff0000L 8793#define SQC_SECDED_CNT__DATA_SEC__SHIFT 0x00000010 8794#define SQC_SECDED_CNT__INST_DED_MASK 0x0000ff00L 8795#define SQC_SECDED_CNT__INST_DED__SHIFT 0x00000008 8796#define SQC_SECDED_CNT__INST_SEC_MASK 0x000000ffL 8797#define SQC_SECDED_CNT__INST_SEC__SHIFT 0x00000000 8798#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000ffL 8799#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x00000000 8800#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL 8801#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 8802#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L 8803#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 8804#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L 8805#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018 8806#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L 8807#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010 8808#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL 8809#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000 8810#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L 8811#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004 8812#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L 8813#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 8814#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L 8815#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 8816#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L 8817#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004 8818#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L 8819#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010 8820#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L 8821#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 8822#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L 8823#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004 8824#define SQ_DED_CNT__LDS_DED_MASK 0x0000003fL 8825#define SQ_DED_CNT__LDS_DED__SHIFT 0x00000000 8826#define SQ_DED_CNT__SGPR_DED_MASK 0x00001f00L 8827#define SQ_DED_CNT__SGPR_DED__SHIFT 0x00000008 8828#define SQ_DED_CNT__VGPR_DED_MASK 0x01ff0000L 8829#define SQ_DED_CNT__VGPR_DED__SHIFT 0x00000010 8830#define SQ_DED_INFO__SIMD_ID_MASK 0x00000030L 8831#define SQ_DED_INFO__SIMD_ID__SHIFT 0x00000004 8832#define SQ_DED_INFO__SOURCE_MASK 0x000001c0L 8833#define SQ_DED_INFO__SOURCE__SHIFT 0x00000006 8834#define SQ_DED_INFO__VM_ID_MASK 0x00001e00L 8835#define SQ_DED_INFO__VM_ID__SHIFT 0x00000009 8836#define SQ_DED_INFO__WAVE_ID_MASK 0x0000000fL 8837#define SQ_DED_INFO__WAVE_ID__SHIFT 0x00000000 8838#define SQ_DS_0__ENCODING_MASK 0xfc000000L 8839#define SQ_DS_0__ENCODING__SHIFT 0x0000001a 8840#define SQ_DS_0__GDS_MASK 0x00020000L 8841#define SQ_DS_0__GDS__SHIFT 0x00000011 8842#define SQ_DS_0__OFFSET0_MASK 0x000000ffL 8843#define SQ_DS_0__OFFSET0__SHIFT 0x00000000 8844#define SQ_DS_0__OFFSET1_MASK 0x0000ff00L 8845#define SQ_DS_0__OFFSET1__SHIFT 0x00000008 8846#define SQ_DS_0__OP_MASK 0x03fc0000L 8847#define SQ_DS_0__OP__SHIFT 0x00000012 8848#define SQ_DS_1__ADDR_MASK 0x000000ffL 8849#define SQ_DS_1__ADDR__SHIFT 0x00000000 8850#define SQ_DS_1__DATA0_MASK 0x0000ff00L 8851#define SQ_DS_1__DATA0__SHIFT 0x00000008 8852#define SQ_DS_1__DATA1_MASK 0x00ff0000L 8853#define SQ_DS_1__DATA1__SHIFT 0x00000010 8854#define SQ_DS_1__VDST_MASK 0xff000000L 8855#define SQ_DS_1__VDST__SHIFT 0x00000018 8856#define SQ_EXP_0__COMPR_MASK 0x00000400L 8857#define SQ_EXP_0__COMPR__SHIFT 0x0000000a 8858#define SQ_EXP_0__DONE_MASK 0x00000800L 8859#define SQ_EXP_0__DONE__SHIFT 0x0000000b 8860#define SQ_EXP_0__ENCODING_MASK 0xfc000000L 8861#define SQ_EXP_0__ENCODING__SHIFT 0x0000001a 8862#define SQ_EXP_0__EN_MASK 0x0000000fL 8863#define SQ_EXP_0__EN__SHIFT 0x00000000 8864#define SQ_EXP_0__TGT_MASK 0x000003f0L 8865#define SQ_EXP_0__TGT__SHIFT 0x00000004 8866#define SQ_EXP_0__VM_MASK 0x00001000L 8867#define SQ_EXP_0__VM__SHIFT 0x0000000c 8868#define SQ_EXP_1__VSRC0_MASK 0x000000ffL 8869#define SQ_EXP_1__VSRC0__SHIFT 0x00000000 8870#define SQ_EXP_1__VSRC1_MASK 0x0000ff00L 8871#define SQ_EXP_1__VSRC1__SHIFT 0x00000008 8872#define SQ_EXP_1__VSRC2_MASK 0x00ff0000L 8873#define SQ_EXP_1__VSRC2__SHIFT 0x00000010 8874#define SQ_EXP_1__VSRC3_MASK 0xff000000L 8875#define SQ_EXP_1__VSRC3__SHIFT 0x00000018 8876#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L 8877#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x00000010 8878#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000fL 8879#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x00000000 8880#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000f00L 8881#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x00000008 8882#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000c0000L 8883#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x00000012 8884#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL 8885#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000 8886#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000ffL 8887#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000 8888#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03f00000L 8889#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x00000014 8890#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000fff00L 8891#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x00000008 8892#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000L 8893#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x0000001e 8894#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000L 8895#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x0000001a 8896#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0fffc000L 8897#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0x0000000e 8898#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000L 8899#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x0000001f 8900#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L 8901#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x0000001c 8902#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003fffL 8903#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x00000000 8904#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x08000000L 8905#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x0000001b 8906#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000f000L 8907#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0x0000000c 8908#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L 8909#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009 8910#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L 8911#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000 8912#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L 8913#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003 8914#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L 8915#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006 8916#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000f0000L 8917#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x00000010 8918#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x04000000L 8919#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x0000001a 8920#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x02000000L 8921#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x00000019 8922#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x01f00000L 8923#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x00000014 8924#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000L 8925#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x0000001c 8926#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001fffL 8927#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x00000000 8928#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x07ffe000L 8929#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0x0000000d 8930#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001fffL 8931#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x00000000 8932#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x03ffe000L 8933#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0x0000000d 8934#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000ff000L 8935#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0x0000000c 8936#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L 8937#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x00000014 8938#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000fffL 8939#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x00000000 8940#define SQ_IMG_RSRC_WORD6__UNUNSED_MASK 0xffe00000L 8941#define SQ_IMG_RSRC_WORD6__UNUNSED__SHIFT 0x00000015 8942#define SQ_IMG_RSRC_WORD7__UNUNSED_MASK 0xffffffffL 8943#define SQ_IMG_RSRC_WORD7__UNUNSED__SHIFT 0x00000000 8944#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07e00000L 8945#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x00000015 8946#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L 8947#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x00000010 8948#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L 8949#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x00000000 8950#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L 8951#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x00000003 8952#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001c0L 8953#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x00000006 8954#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L 8955#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0x0000000c 8956#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L 8957#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x0000001c 8958#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L 8959#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x0000001d 8960#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L 8961#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x00000014 8962#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L 8963#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0x0000000f 8964#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000e00L 8965#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x00000009 8966#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L 8967#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x00000013 8968#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L 8969#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x0000001b 8970#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00fff000L 8971#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0x0000000c 8972#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000fffL 8973#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x00000000 8974#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0f000000L 8975#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x00000018 8976#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000L 8977#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x0000001c 8978#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000L 8979#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x0000001d 8980#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L 8981#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x0000001e 8982#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003fffL 8983#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000fc000L 8984#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0x0000000e 8985#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x00000000 8986#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0c000000L 8987#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x0000001a 8988#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L 8989#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x0000001c 8990#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L 8991#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x00000014 8992#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00c00000L 8993#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x00000016 8994#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L 8995#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x00000018 8996#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000fffL 8997#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x00000000 8998#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000L 8999#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x0000001e 9000#define SQ_IND_DATA__DATA_MASK 0xffffffffL 9001#define SQ_IND_DATA__DATA__SHIFT 0x00000000 9002#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L 9003#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0x0000000c 9004#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L 9005#define SQ_IND_INDEX__FORCE_READ__SHIFT 0x0000000d 9006#define SQ_IND_INDEX__INDEX_MASK 0xffff0000L 9007#define SQ_IND_INDEX__INDEX__SHIFT 0x00000010 9008#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L 9009#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0x0000000e 9010#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L 9011#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x00000004 9012#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000fc0L 9013#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x00000006 9014#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L 9015#define SQ_IND_INDEX__UNINDEXED__SHIFT 0x0000000f 9016#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000fL 9017#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x00000000 9018#define SQ_INST__ENCODING_MASK 0xffffffffL 9019#define SQ_INST__ENCODING__SHIFT 0x00000000 9020#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x00000010L 9021#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x00000004 9022#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0x0c000000L 9023#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x0000001a 9024#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x00000020L 9025#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x00000005 9026#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x00000040L 9027#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x00000006 9028#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x00000080L 9029#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x00000007 9030#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x00000008L 9031#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x00000003 9032#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x02000000L 9033#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x00000019 9034#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x00000004L 9035#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x00000002 9036#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x00000001L 9037#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x00000000 9038#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x00000002L 9039#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x00000001 9040#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0x0c000000L 9041#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x0000001a 9042#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x02000000L 9043#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x00000019 9044#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0x00f00000L 9045#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x00000014 9046#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0x000000ffL 9047#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x00000000 9048#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0x0c000000L 9049#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x0000001a 9050#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x00000200L 9051#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x00000009 9052#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x02000000L 9053#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x00000019 9054#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x01000000L 9055#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x00000018 9056#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0x000c0000L 9057#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x00000012 9058#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x00003c00L 9059#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0x0000000a 9060#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x0003c000L 9061#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0x0000000e 9062#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L 9063#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x00000002 9064#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L 9065#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x00000001 9066#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L 9067#define SQ_LB_CTR_CTRL__START__SHIFT 0x00000000 9068#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffffL 9069#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x00000000 9070#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffffL 9071#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x00000000 9072#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffffL 9073#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x00000000 9074#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffffL 9075#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x00000000 9076#define SQ_MIMG_0__DA_MASK 0x00004000L 9077#define SQ_MIMG_0__DA__SHIFT 0x0000000e 9078#define SQ_MIMG_0__DMASK_MASK 0x00000f00L 9079#define SQ_MIMG_0__DMASK__SHIFT 0x00000008 9080#define SQ_MIMG_0__ENCODING_MASK 0xfc000000L 9081#define SQ_MIMG_0__ENCODING__SHIFT 0x0000001a 9082#define SQ_MIMG_0__GLC_MASK 0x00002000L 9083#define SQ_MIMG_0__GLC__SHIFT 0x0000000d 9084#define SQ_MIMG_0__LWE_MASK 0x00020000L 9085#define SQ_MIMG_0__LWE__SHIFT 0x00000011 9086#define SQ_MIMG_0__OP_MASK 0x01fc0000L 9087#define SQ_MIMG_0__OP__SHIFT 0x00000012 9088#define SQ_MIMG_0__R128_MASK 0x00008000L 9089#define SQ_MIMG_0__R128__SHIFT 0x0000000f 9090#define SQ_MIMG_0__SLC_MASK 0x02000000L 9091#define SQ_MIMG_0__SLC__SHIFT 0x00000019 9092#define SQ_MIMG_0__TFE_MASK 0x00010000L 9093#define SQ_MIMG_0__TFE__SHIFT 0x00000010 9094#define SQ_MIMG_0__UNORM_MASK 0x00001000L 9095#define SQ_MIMG_0__UNORM__SHIFT 0x0000000c 9096#define SQ_MIMG_1__SRSRC_MASK 0x001f0000L 9097#define SQ_MIMG_1__SRSRC__SHIFT 0x00000010 9098#define SQ_MIMG_1__SSAMP_MASK 0x03e00000L 9099#define SQ_MIMG_1__SSAMP__SHIFT 0x00000015 9100#define SQ_MIMG_1__VADDR_MASK 0x000000ffL 9101#define SQ_MIMG_1__VADDR__SHIFT 0x00000000 9102#define SQ_MIMG_1__VDATA_MASK 0x0000ff00L 9103#define SQ_MIMG_1__VDATA__SHIFT 0x00000008 9104#define SQ_MTBUF_0__ADDR64_MASK 0x00008000L 9105#define SQ_MTBUF_0__ADDR64__SHIFT 0x0000000f 9106#define SQ_MTBUF_0__DFMT_MASK 0x00780000L 9107#define SQ_MTBUF_0__DFMT__SHIFT 0x00000013 9108#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000L 9109#define SQ_MTBUF_0__ENCODING__SHIFT 0x0000001a 9110#define SQ_MTBUF_0__GLC_MASK 0x00004000L 9111#define SQ_MTBUF_0__GLC__SHIFT 0x0000000e 9112#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L 9113#define SQ_MTBUF_0__IDXEN__SHIFT 0x0000000d 9114#define SQ_MTBUF_0__NFMT_MASK 0x03800000L 9115#define SQ_MTBUF_0__NFMT__SHIFT 0x00000017 9116#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L 9117#define SQ_MTBUF_0__OFFEN__SHIFT 0x0000000c 9118#define SQ_MTBUF_0__OFFSET_MASK 0x00000fffL 9119#define SQ_MTBUF_0__OFFSET__SHIFT 0x00000000 9120#define SQ_MTBUF_0__OP_MASK 0x00070000L 9121#define SQ_MTBUF_0__OP__SHIFT 0x00000010 9122#define SQ_MTBUF_1__SLC_MASK 0x00400000L 9123#define SQ_MTBUF_1__SLC__SHIFT 0x00000016 9124#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000L 9125#define SQ_MTBUF_1__SOFFSET__SHIFT 0x00000018 9126#define SQ_MTBUF_1__SRSRC_MASK 0x001f0000L 9127#define SQ_MTBUF_1__SRSRC__SHIFT 0x00000010 9128#define SQ_MTBUF_1__TFE_MASK 0x00800000L 9129#define SQ_MTBUF_1__TFE__SHIFT 0x00000017 9130#define SQ_MTBUF_1__VADDR_MASK 0x000000ffL 9131#define SQ_MTBUF_1__VADDR__SHIFT 0x00000000 9132#define SQ_MTBUF_1__VDATA_MASK 0x0000ff00L 9133#define SQ_MTBUF_1__VDATA__SHIFT 0x00000008 9134#define SQ_MUBUF_0__ADDR64_MASK 0x00008000L 9135#define SQ_MUBUF_0__ADDR64__SHIFT 0x0000000f 9136#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000L 9137#define SQ_MUBUF_0__ENCODING__SHIFT 0x0000001a 9138#define SQ_MUBUF_0__GLC_MASK 0x00004000L 9139#define SQ_MUBUF_0__GLC__SHIFT 0x0000000e 9140#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L 9141#define SQ_MUBUF_0__IDXEN__SHIFT 0x0000000d 9142#define SQ_MUBUF_0__LDS_MASK 0x00010000L 9143#define SQ_MUBUF_0__LDS__SHIFT 0x00000010 9144#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L 9145#define SQ_MUBUF_0__OFFEN__SHIFT 0x0000000c 9146#define SQ_MUBUF_0__OFFSET_MASK 0x00000fffL 9147#define SQ_MUBUF_0__OFFSET__SHIFT 0x00000000 9148#define SQ_MUBUF_0__OP_MASK 0x01fc0000L 9149#define SQ_MUBUF_0__OP__SHIFT 0x00000012 9150#define SQ_MUBUF_1__SLC_MASK 0x00400000L 9151#define SQ_MUBUF_1__SLC__SHIFT 0x00000016 9152#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000L 9153#define SQ_MUBUF_1__SOFFSET__SHIFT 0x00000018 9154#define SQ_MUBUF_1__SRSRC_MASK 0x001f0000L 9155#define SQ_MUBUF_1__SRSRC__SHIFT 0x00000010 9156#define SQ_MUBUF_1__TFE_MASK 0x00800000L 9157#define SQ_MUBUF_1__TFE__SHIFT 0x00000017 9158#define SQ_MUBUF_1__VADDR_MASK 0x000000ffL 9159#define SQ_MUBUF_1__VADDR__SHIFT 0x00000000 9160#define SQ_MUBUF_1__VDATA_MASK 0x0000ff00L 9161#define SQ_MUBUF_1__VDATA__SHIFT 0x00000008 9162#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9163#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9164#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9165#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9166#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L 9167#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c 9168#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001ffL 9169#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 9170#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0f000000L 9171#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x00000018 9172#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00f00000L 9173#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x00000014 9174#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9175#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9176#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9177#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9178#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9179#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9180#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9181#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9182#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000L 9183#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x0000001c 9184#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001ffL 9185#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x00000000 9186#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0f000000L 9187#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x00000018 9188#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00f00000L 9189#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x00000014 9190#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9191#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9192#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9193#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9194#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9195#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9196#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9197#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9198#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000L 9199#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x0000001c 9200#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001ffL 9201#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x00000000 9202#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0f000000L 9203#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x00000018 9204#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00f00000L 9205#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x00000014 9206#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9207#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9208#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9209#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9210#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9211#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9212#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9213#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9214#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000L 9215#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x0000001c 9216#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001ffL 9217#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x00000000 9218#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0f000000L 9219#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x00000018 9220#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00f00000L 9221#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x00000014 9222#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9223#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9224#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9225#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9226#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9227#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9228#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9229#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9230#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000L 9231#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x0000001c 9232#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001ffL 9233#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x00000000 9234#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0f000000L 9235#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x00000018 9236#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00f00000L 9237#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x00000014 9238#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9239#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9240#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9241#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9242#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9243#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9244#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9245#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9246#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000L 9247#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x0000001c 9248#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001ffL 9249#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x00000000 9250#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0f000000L 9251#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x00000018 9252#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00f00000L 9253#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x00000014 9254#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9255#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9256#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9257#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9258#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9259#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9260#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9261#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9262#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000L 9263#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x0000001c 9264#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001ffL 9265#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x00000000 9266#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0f000000L 9267#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x00000018 9268#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00f00000L 9269#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x00000014 9270#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9271#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9272#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9273#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9274#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9275#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9276#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9277#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9278#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L 9279#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c 9280#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001ffL 9281#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 9282#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0f000000L 9283#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x00000018 9284#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00f00000L 9285#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x00000014 9286#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9287#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9288#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9289#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9290#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9291#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9292#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9293#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9294#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L 9295#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c 9296#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001ffL 9297#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 9298#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0f000000L 9299#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x00000018 9300#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00f00000L 9301#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x00000014 9302#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9303#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9304#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9305#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9306#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9307#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9308#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9309#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9310#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L 9311#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c 9312#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001ffL 9313#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 9314#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0f000000L 9315#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x00000018 9316#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00f00000L 9317#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x00000014 9318#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9319#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9320#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9321#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9322#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9323#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9324#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9325#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9326#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000L 9327#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x0000001c 9328#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001ffL 9329#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000 9330#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0f000000L 9331#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x00000018 9332#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00f00000L 9333#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x00000014 9334#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9335#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9336#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9337#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9338#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9339#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9340#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9341#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9342#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000L 9343#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x0000001c 9344#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001ffL 9345#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000 9346#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0f000000L 9347#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x00000018 9348#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00f00000L 9349#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x00000014 9350#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9351#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9352#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9353#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9354#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9355#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9356#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9357#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9358#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000L 9359#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x0000001c 9360#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001ffL 9361#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000 9362#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0f000000L 9363#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x00000018 9364#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00f00000L 9365#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x00000014 9366#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9367#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9368#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9369#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9370#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9371#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9372#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9373#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9374#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000L 9375#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x0000001c 9376#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001ffL 9377#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000 9378#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0f000000L 9379#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x00000018 9380#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00f00000L 9381#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x00000014 9382#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9383#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9384#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9385#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9386#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9387#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9388#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9389#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9390#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000L 9391#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x0000001c 9392#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001ffL 9393#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x00000000 9394#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0f000000L 9395#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x00000018 9396#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00f00000L 9397#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x00000014 9398#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9399#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9400#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9401#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9402#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffffL 9403#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 9404#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffffL 9405#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x00000000 9406#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000L 9407#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x0000001c 9408#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001ffL 9409#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x00000000 9410#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0f000000L 9411#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x00000018 9412#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00f00000L 9413#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x00000014 9414#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000f000L 9415#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c 9416#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L 9417#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 9418#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L 9419#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x00000000 9420#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001f00L 9421#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x00000008 9422#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L 9423#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x00000006 9424#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L 9425#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0x0000000d 9426#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L 9427#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x00000003 9428#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L 9429#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x00000002 9430#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L 9431#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x00000004 9432#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L 9433#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x00000005 9434#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L 9435#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x00000000 9436#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L 9437#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x00000001 9438#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L 9439#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b 9440#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003fffL 9441#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x00000000 9442#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L 9443#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010 9444#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L 9445#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x0000001f 9446#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000L 9447#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x00000010 9448#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003fffL 9449#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x00000000 9450#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000L 9451#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x0000001e 9452#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007fL 9453#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x00000000 9454#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x001ffc00L 9455#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0x0000000a 9456#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L 9457#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x00000007 9458#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000f00L 9459#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x00000008 9460#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L 9461#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x0000001f 9462#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L 9463#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x0000001e 9464#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L 9465#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x0000001c 9466#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003fL 9467#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x00000000 9468#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L 9469#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x0000001d 9470#define SQ_SEC_CNT__LDS_SEC_MASK 0x0000003fL 9471#define SQ_SEC_CNT__LDS_SEC__SHIFT 0x00000000 9472#define SQ_SEC_CNT__SGPR_SEC_MASK 0x00001f00L 9473#define SQ_SEC_CNT__SGPR_SEC__SHIFT 0x00000008 9474#define SQ_SEC_CNT__VGPR_SEC_MASK 0x01ff0000L 9475#define SQ_SEC_CNT__VGPR_SEC__SHIFT 0x00000010 9476#define SQ_SMRD__ENCODING_MASK 0xf8000000L 9477#define SQ_SMRD__ENCODING__SHIFT 0x0000001b 9478#define SQ_SMRD__IMM_MASK 0x00000100L 9479#define SQ_SMRD__IMM__SHIFT 0x00000008 9480#define SQ_SMRD__OFFSET_MASK 0x000000ffL 9481#define SQ_SMRD__OFFSET__SHIFT 0x00000000 9482#define SQ_SMRD__OP_MASK 0x07c00000L 9483#define SQ_SMRD__OP__SHIFT 0x00000016 9484#define SQ_SMRD__SBASE_MASK 0x00007e00L 9485#define SQ_SMRD__SBASE__SHIFT 0x00000009 9486#define SQ_SMRD__SDST_MASK 0x003f8000L 9487#define SQ_SMRD__SDST__SHIFT 0x0000000f 9488#define SQ_SOP1__ENCODING_MASK 0xff800000L 9489#define SQ_SOP1__ENCODING__SHIFT 0x00000017 9490#define SQ_SOP1__OP_MASK 0x0000ff00L 9491#define SQ_SOP1__OP__SHIFT 0x00000008 9492#define SQ_SOP1__SDST_MASK 0x007f0000L 9493#define SQ_SOP1__SDST__SHIFT 0x00000010 9494#define SQ_SOP1__SSRC0_MASK 0x000000ffL 9495#define SQ_SOP1__SSRC0__SHIFT 0x00000000 9496#define SQ_SOP2__ENCODING_MASK 0xc0000000L 9497#define SQ_SOP2__ENCODING__SHIFT 0x0000001e 9498#define SQ_SOP2__OP_MASK 0x3f800000L 9499#define SQ_SOP2__OP__SHIFT 0x00000017 9500#define SQ_SOP2__SDST_MASK 0x007f0000L 9501#define SQ_SOP2__SDST__SHIFT 0x00000010 9502#define SQ_SOP2__SSRC0_MASK 0x000000ffL 9503#define SQ_SOP2__SSRC0__SHIFT 0x00000000 9504#define SQ_SOP2__SSRC1_MASK 0x0000ff00L 9505#define SQ_SOP2__SSRC1__SHIFT 0x00000008 9506#define SQ_SOPC__ENCODING_MASK 0xff800000L 9507#define SQ_SOPC__ENCODING__SHIFT 0x00000017 9508#define SQ_SOPC__OP_MASK 0x007f0000L 9509#define SQ_SOPC__OP__SHIFT 0x00000010 9510#define SQ_SOPC__SSRC0_MASK 0x000000ffL 9511#define SQ_SOPC__SSRC0__SHIFT 0x00000000 9512#define SQ_SOPC__SSRC1_MASK 0x0000ff00L 9513#define SQ_SOPC__SSRC1__SHIFT 0x00000008 9514#define SQ_SOPK__ENCODING_MASK 0xf0000000L 9515#define SQ_SOPK__ENCODING__SHIFT 0x0000001c 9516#define SQ_SOPK__OP_MASK 0x0f800000L 9517#define SQ_SOPK__OP__SHIFT 0x00000017 9518#define SQ_SOPK__SDST_MASK 0x007f0000L 9519#define SQ_SOPK__SDST__SHIFT 0x00000010 9520#define SQ_SOPK__SIMM16_MASK 0x0000ffffL 9521#define SQ_SOPK__SIMM16__SHIFT 0x00000000 9522#define SQ_SOPP__ENCODING_MASK 0xff800000L 9523#define SQ_SOPP__ENCODING__SHIFT 0x00000017 9524#define SQ_SOPP__OP_MASK 0x007f0000L 9525#define SQ_SOPP__OP__SHIFT 0x00000010 9526#define SQ_SOPP__SIMM16_MASK 0x0000ffffL 9527#define SQ_SOPP__SIMM16__SHIFT 0x00000000 9528#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL 9529#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000 9530#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L 9531#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010 9532#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000fL 9533#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x00000000 9534#define SQ_THREAD_TRACE_BASE2__ATC_MASK 0x00000010L 9535#define SQ_THREAD_TRACE_BASE2__ATC__SHIFT 0x00000004 9536#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffffL 9537#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x00000000 9538#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffffL 9539#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x00000000 9540#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L 9541#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x0000001f 9542#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L 9543#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x00000000 9544#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001fL 9545#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x00000000 9546#define SQ_THREAD_TRACE_MASK__RANDOM_SEED_MASK 0xffff0000L 9547#define SQ_THREAD_TRACE_MASK__RANDOM_SEED__SHIFT 0x00000010 9548#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L 9549#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x00000007 9550#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L 9551#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x00000005 9552#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L 9553#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0x0000000e 9554#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L 9555#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0x0000000f 9556#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L 9557#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0x0000000c 9558#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L 9559#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x00000019 9560#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L 9561#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x00000017 9562#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L 9563#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x0000001e 9564#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L 9565#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x0000001b 9566#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001c0000L 9567#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x00000012 9568#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000e00L 9569#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x00000009 9570#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001c0L 9571#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x00000006 9572#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L 9573#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0x0000000c 9574#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L 9575#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0x0000000f 9576#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L 9577#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x00000000 9578#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L 9579#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x00000003 9580#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L 9581#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x00000015 9582#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x04000000L 9583#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x0000001a 9584#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L 9585#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x0000001d 9586#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L 9587#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x0000001f 9588#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000ffffL 9589#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x00000000 9590#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000L 9591#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x00000010 9592#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003fffffL 9593#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x00000000 9594#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L 9595#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x0000001e 9596#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00070000L 9597#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x00000010 9598#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000007L 9599#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x00000000 9600#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L 9601#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x0000001f 9602#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L 9603#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x0000001d 9604#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0x0000ffffL 9605#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x00000000 9606#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L 9607#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x00000018 9608#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00ff0000L 9609#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x00000010 9610#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000ffffL 9611#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x00000000 9612#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffffL 9613#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x00000000 9614#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffffL 9615#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x00000000 9616#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffffL 9617#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x00000000 9618#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffffL 9619#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x00000000 9620#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x00000010L 9621#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x00000004 9622#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x0000000fL 9623#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x00000000 9624#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0x0000fc00L 9625#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0x0000000a 9626#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x00000020L 9627#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x00000005 9628#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x000001c0L 9629#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x00000006 9630#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x00000010L 9631#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x00000004 9632#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x0000000fL 9633#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x00000000 9634#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0x0000f000L 9635#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0x0000000c 9636#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000L 9637#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x00000010 9638#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L 9639#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x00000009 9640#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L 9641#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x00000004 9642#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL 9643#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 9644#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001e0L 9645#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x00000005 9646#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00ffffffL 9647#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x00000000 9648#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x00000600L 9649#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x00000009 9650#define SQ_THREAD_TRACE_WORD_INST__SIZE_MASK 0x00000800L 9651#define SQ_THREAD_TRACE_WORD_INST__SIZE__SHIFT 0x0000000b 9652#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x00000010L 9653#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x00000004 9654#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x0000000fL 9655#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x00000000 9656#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003c0L 9657#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x00000006 9658#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000L 9659#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x00000010 9660#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L 9661#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x00000005 9662#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000c000L 9663#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0x0000000e 9664#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L 9665#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x00000004 9666#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL 9667#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 9668#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003c00L 9669#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0x0000000a 9670#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0x0000ffffL 9671#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x00000000 9672#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x000001e0L 9673#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x00000005 9674#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L 9675#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x00000008 9676#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000c00L 9677#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0x0000000a 9678#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L 9679#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0x0000000c 9680#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000c000L 9681#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0x0000000e 9682#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L 9683#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x00000010 9684#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000c0000L 9685#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x00000012 9686#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L 9687#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x00000014 9688#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00c00000L 9689#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x00000016 9690#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L 9691#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x00000018 9692#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0c000000L 9693#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x0000001a 9694#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L 9695#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x00000005 9696#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L 9697#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x00000004 9698#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000fL 9699#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x00000000 9700#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0x000000c0L 9701#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0x00000006 9702#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x00000020L 9703#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0x00000005 9704#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x00000010L 9705#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x00000004 9706#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x0000000fL 9707#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x00000000 9708#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01fff000L 9709#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0x0000000c 9710#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000L 9711#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x00000019 9712#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000c00L 9713#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0x0000000a 9714#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003c0L 9715#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x00000006 9716#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L 9717#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x00000005 9718#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L 9719#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x00000004 9720#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL 9721#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 9722#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003fL 9723#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x00000000 9724#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007ffc0L 9725#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x00000006 9726#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000L 9727#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x00000013 9728#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L 9729#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x00000007 9730#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L 9731#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x00000005 9732#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000L 9733#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x00000010 9734#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L 9735#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x00000009 9736#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L 9737#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0x0000000f 9738#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L 9739#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0x0000000e 9740#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001c00L 9741#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0x0000000a 9742#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L 9743#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x00000004 9744#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL 9745#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 9746#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffffL 9747#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x00000000 9748#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000L 9749#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x00000010 9750#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL 9751#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 9752#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffffL 9753#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x00000000 9754#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x000003c0L 9755#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x00000006 9756#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x00000020L 9757#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x00000005 9758#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0x0000c000L 9759#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0x0000000e 9760#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000L 9761#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x00000016 9762#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003c0L 9763#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x00000006 9764#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001f0000L 9765#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x00000010 9766#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L 9767#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x00000005 9768#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000c000L 9769#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0x0000000e 9770#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000L 9771#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x0000001d 9772#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L 9773#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x00000004 9774#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000fL 9775#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x00000000 9776#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L 9777#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x00000015 9778#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003c00L 9779#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0x0000000a 9780#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x00000010L 9781#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x00000004 9782#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x0000000fL 9783#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x00000000 9784#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x00003c00L 9785#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0x0000000a 9786#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000L 9787#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x0000001e 9788#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffffL 9789#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x00000000 9790#define SQ_TIME_HI__TIME_MASK 0xffffffffL 9791#define SQ_TIME_HI__TIME__SHIFT 0x00000000 9792#define SQ_TIME_LO__TIME_MASK 0xffffffffL 9793#define SQ_TIME_LO__TIME__SHIFT 0x00000000 9794#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L 9795#define SQ_VINTRP__ATTRCHAN__SHIFT 0x00000008 9796#define SQ_VINTRP__ATTR_MASK 0x0000fc00L 9797#define SQ_VINTRP__ATTR__SHIFT 0x0000000a 9798#define SQ_VINTRP__ENCODING_MASK 0xfc000000L 9799#define SQ_VINTRP__ENCODING__SHIFT 0x0000001a 9800#define SQ_VINTRP__OP_MASK 0x00030000L 9801#define SQ_VINTRP__OP__SHIFT 0x00000010 9802#define SQ_VINTRP__VDST_MASK 0x03fc0000L 9803#define SQ_VINTRP__VDST__SHIFT 0x00000012 9804#define SQ_VINTRP__VSRC_MASK 0x000000ffL 9805#define SQ_VINTRP__VSRC__SHIFT 0x00000000 9806#define SQ_VOP1__ENCODING_MASK 0xfe000000L 9807#define SQ_VOP1__ENCODING__SHIFT 0x00000019 9808#define SQ_VOP1__OP_MASK 0x0001fe00L 9809#define SQ_VOP1__OP__SHIFT 0x00000009 9810#define SQ_VOP1__SRC0_MASK 0x000001ffL 9811#define SQ_VOP1__SRC0__SHIFT 0x00000000 9812#define SQ_VOP1__VDST_MASK 0x01fe0000L 9813#define SQ_VOP1__VDST__SHIFT 0x00000011 9814#define SQ_VOP2__ENCODING_MASK 0x80000000L 9815#define SQ_VOP2__ENCODING__SHIFT 0x0000001f 9816#define SQ_VOP2__OP_MASK 0x7e000000L 9817#define SQ_VOP2__OP__SHIFT 0x00000019 9818#define SQ_VOP2__SRC0_MASK 0x000001ffL 9819#define SQ_VOP2__SRC0__SHIFT 0x00000000 9820#define SQ_VOP2__VDST_MASK 0x01fe0000L 9821#define SQ_VOP2__VDST__SHIFT 0x00000011 9822#define SQ_VOP2__VSRC1_MASK 0x0001fe00L 9823#define SQ_VOP2__VSRC1__SHIFT 0x00000009 9824#define SQ_VOP3_0__ABS_MASK 0x00000700L 9825#define SQ_VOP3_0__ABS__SHIFT 0x00000008 9826#define SQ_VOP3_0__CLAMP_MASK 0x00000800L 9827#define SQ_VOP3_0__CLAMP__SHIFT 0x0000000b 9828#define SQ_VOP3_0__ENCODING_MASK 0xfc000000L 9829#define SQ_VOP3_0__ENCODING__SHIFT 0x0000001a 9830#define SQ_VOP3_0__OP_MASK 0x03fe0000L 9831#define SQ_VOP3_0__OP__SHIFT 0x00000011 9832#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000L 9833#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x0000001a 9834#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03fe0000L 9835#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x00000011 9836#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007f00L 9837#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x00000008 9838#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000ffL 9839#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x00000000 9840#define SQ_VOP3_0__VDST_MASK 0x000000ffL 9841#define SQ_VOP3_0__VDST__SHIFT 0x00000000 9842#define SQ_VOP3_1__NEG_MASK 0xe0000000L 9843#define SQ_VOP3_1__NEG__SHIFT 0x0000001d 9844#define SQ_VOP3_1__OMOD_MASK 0x18000000L 9845#define SQ_VOP3_1__OMOD__SHIFT 0x0000001b 9846#define SQ_VOP3_1__SRC0_MASK 0x000001ffL 9847#define SQ_VOP3_1__SRC0__SHIFT 0x00000000 9848#define SQ_VOP3_1__SRC1_MASK 0x0003fe00L 9849#define SQ_VOP3_1__SRC1__SHIFT 0x00000009 9850#define SQ_VOP3_1__SRC2_MASK 0x07fc0000L 9851#define SQ_VOP3_1__SRC2__SHIFT 0x00000012 9852#define SQ_VOPC__ENCODING_MASK 0xfe000000L 9853#define SQ_VOPC__ENCODING__SHIFT 0x00000019 9854#define SQ_VOPC__OP_MASK 0x01fe0000L 9855#define SQ_VOPC__OP__SHIFT 0x00000011 9856#define SQ_VOPC__SRC0_MASK 0x000001ffL 9857#define SQ_VOPC__SRC0__SHIFT 0x00000000 9858#define SQ_VOPC__VSRC1_MASK 0x0001fe00L 9859#define SQ_VOPC__VSRC1__SHIFT 0x00000009 9860#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffffL 9861#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x00000000 9862#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffffL 9863#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x00000000 9864#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003f0000L 9865#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x00000010 9866#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0f000000L 9867#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x00000018 9868#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003fL 9869#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x00000000 9870#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003f00L 9871#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x00000008 9872#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000f00L 9873#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x00000008 9874#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000L 9875#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x0000001e 9876#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000c0L 9877#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x00000006 9878#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L 9879#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x00000018 9880#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00002000L 9881#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0x0000000d 9882#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L 9883#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0x0000000c 9884#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L 9885#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x00000004 9886#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L 9887#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x0000001b 9888#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000f0000L 9889#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x00000010 9890#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00f00000L 9891#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x00000014 9892#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000fL 9893#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x00000000 9894#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x00c00000L 9895#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x00000016 9896#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x06000000L 9897#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x00000019 9898#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L 9899#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x00000008 9900#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L 9901#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x00000000 9902#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000c00L 9903#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0x0000000a 9904#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x00070000L 9905#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x00000010 9906#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x01000000L 9907#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x00000018 9908#define SQ_WAVE_IB_DBG0__KILL_MASK 0x08000000L 9909#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x0000001b 9910#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0x00380000L 9911#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x00000013 9912#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x10000000L 9913#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x0000001c 9914#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L 9915#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x00000004 9916#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000e0L 9917#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x00000005 9918#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L 9919#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x00000003 9920#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L 9921#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x00000004 9922#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00001f00L 9923#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x00000008 9924#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x0000e000L 9925#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0x0000000d 9926#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000fL 9927#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x00000000 9928#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffffL 9929#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x00000000 9930#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffffL 9931#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x00000000 9932#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000ffL 9933#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x00000000 9934#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001ff000L 9935#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0x0000000c 9936#define SQ_WAVE_M0__M0_MASK 0xffffffffL 9937#define SQ_WAVE_M0__M0__SHIFT 0x00000000 9938#define SQ_WAVE_MODE__CSP_MASK 0xe0000000L 9939#define SQ_WAVE_MODE__CSP__SHIFT 0x0000001d 9940#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x00000800L 9941#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0x0000000b 9942#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L 9943#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x00000008 9944#define SQ_WAVE_MODE__EXCP_EN_MASK 0x0007f000L 9945#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0x0000000c 9946#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000f0L 9947#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x00000004 9948#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000fL 9949#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x00000000 9950#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L 9951#define SQ_WAVE_MODE__IEEE__SHIFT 0x00000009 9952#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L 9953#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0x0000000a 9954#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L 9955#define SQ_WAVE_MODE__VSKIP__SHIFT 0x0000001c 9956#define SQ_WAVE_PC_HI__PC_HI_MASK 0x000000ffL 9957#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x00000000 9958#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffffL 9959#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x00000000 9960#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x00200000L 9961#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x00000015 9962#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x00100000L 9963#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x00000014 9964#define SQ_WAVE_STATUS__DATA_ATC_MASK 0x00400000L 9965#define SQ_WAVE_STATUS__DATA_ATC__SHIFT 0x00000016 9966#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL_MASK 0x07000000L 9967#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL__SHIFT 0x00000018 9968#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L 9969#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x00000011 9970#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L 9971#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x00000009 9972#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L 9973#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x00000008 9974#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L 9975#define SQ_WAVE_STATUS__HALT__SHIFT 0x0000000d 9976#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L 9977#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0x0000000c 9978#define SQ_WAVE_STATUS__INST_ATC_MASK 0x00800000L 9979#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x00000017 9980#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L 9981#define SQ_WAVE_STATUS__IN_TG__SHIFT 0x0000000b 9982#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L 9983#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x0000001b 9984#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L 9985#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x00000013 9986#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L 9987#define SQ_WAVE_STATUS__PRIV__SHIFT 0x00000005 9988#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L 9989#define SQ_WAVE_STATUS__SCC__SHIFT 0x00000000 9990#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L 9991#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x00000012 9992#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L 9993#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x00000001 9994#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L 9995#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x00000006 9996#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L 9997#define SQ_WAVE_STATUS__TRAP__SHIFT 0x0000000e 9998#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L 9999#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0x0000000f 10000#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L 10001#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x00000007 10002#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L 10003#define SQ_WAVE_STATUS__VALID__SHIFT 0x00000010 10004#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L 10005#define SQ_WAVE_STATUS__VCCZ__SHIFT 0x0000000a 10006#define SQ_WAVE_STATUS__WAVE_PRIO_MASK 0x00000018L 10007#define SQ_WAVE_STATUS__WAVE_PRIO__SHIFT 0x00000003 10008#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0x000000ffL 10009#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x00000000 10010#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffffL 10011#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x00000000 10012#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0x000000ffL 10013#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x00000000 10014#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffffL 10015#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x00000000 10016#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000L 10017#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x0000001d 10018#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003f0000L 10019#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x00000010 10020#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x0000007fL 10021#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x00000000 10022#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffffL 10023#define SQ_WAVE_TTMP0__DATA__SHIFT 0x00000000 10024#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffffL 10025#define SQ_WAVE_TTMP10__DATA__SHIFT 0x00000000 10026#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffffL 10027#define SQ_WAVE_TTMP11__DATA__SHIFT 0x00000000 10028#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffffL 10029#define SQ_WAVE_TTMP1__DATA__SHIFT 0x00000000 10030#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffffL 10031#define SQ_WAVE_TTMP2__DATA__SHIFT 0x00000000 10032#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffffL 10033#define SQ_WAVE_TTMP3__DATA__SHIFT 0x00000000 10034#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffffL 10035#define SQ_WAVE_TTMP4__DATA__SHIFT 0x00000000 10036#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffffL 10037#define SQ_WAVE_TTMP5__DATA__SHIFT 0x00000000 10038#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffffL 10039#define SQ_WAVE_TTMP6__DATA__SHIFT 0x00000000 10040#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffffL 10041#define SQ_WAVE_TTMP7__DATA__SHIFT 0x00000000 10042#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffffL 10043#define SQ_WAVE_TTMP8__DATA__SHIFT 0x00000000 10044#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffffL 10045#define SQ_WAVE_TTMP9__DATA__SHIFT 0x00000000 10046#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80L 10047#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x00000007 10048#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007fL 10049#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x00000000 10050#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000L 10051#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x0000001f 10052#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000L 10053#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x0000001e 10054#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000L 10055#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x0000001d 10056#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000L 10057#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x0000001c 10058#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x08000000L 10059#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x0000001b 10060#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x04000000L 10061#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x0000001a 10062#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x02000000L 10063#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x00000019 10064#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x00800000L 10065#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x00000017 10066#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x01000000L 10067#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x00000018 10068#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x00400000L 10069#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x00000016 10070#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x00100000L 10071#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x00000014 10072#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x00200000L 10073#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x00000015 10074#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x00080000L 10075#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x00000013 10076#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x00020000L 10077#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x00000011 10078#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x00040000L 10079#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x00000012 10080#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x00010000L 10081#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x00000010 10082#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x00004000L 10083#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0x0000000e 10084#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x00008000L 10085#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0x0000000f 10086#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x00002000L 10087#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0x0000000d 10088#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x00001000L 10089#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0x0000000c 10090#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x00000400L 10091#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0x0000000a 10092#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x00000800L 10093#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0x0000000b 10094#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x00000200L 10095#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x00000009 10096#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x00000080L 10097#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x00000007 10098#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x00000100L 10099#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x00000008 10100#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x00000040L 10101#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x00000006 10102#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x00000010L 10103#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x00000004 10104#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x00000020L 10105#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x00000005 10106#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x00000008L 10107#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x00000003 10108#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x00000002L 10109#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x00000001 10110#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x00000004L 10111#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x00000002 10112#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x00000001L 10113#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x00000000 10114#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000L 10115#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x0000001f 10116#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000L 10117#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x0000001e 10118#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000L 10119#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x0000001d 10120#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000L 10121#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x0000001c 10122#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x08000000L 10123#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x0000001b 10124#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x04000000L 10125#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x0000001a 10126#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x02000000L 10127#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x00000019 10128#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x01000000L 10129#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x00000018 10130#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x00800000L 10131#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x00000017 10132#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x00400000L 10133#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x00000016 10134#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x00200000L 10135#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x00000015 10136#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x00100000L 10137#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x00000014 10138#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x00080000L 10139#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x00000013 10140#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x00040000L 10141#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x00000012 10142#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x00020000L 10143#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x00000011 10144#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00010000L 10145#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x00000010 10146#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00008000L 10147#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0x0000000f 10148#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00004000L 10149#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0x0000000e 10150#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00002000L 10151#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0x0000000d 10152#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00001000L 10153#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0x0000000c 10154#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00000800L 10155#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0x0000000b 10156#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00000400L 10157#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0x0000000a 10158#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00000200L 10159#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x00000009 10160#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00000100L 10161#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x00000008 10162#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00000080L 10163#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x00000007 10164#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00000040L 10165#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x00000006 10166#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00000020L 10167#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x00000005 10168#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000010L 10169#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x00000004 10170#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000008L 10171#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x00000003 10172#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000004L 10173#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x00000002 10174#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000002L 10175#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x00000001 10176#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000001L 10177#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x00000000 10178#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x01000000L 10179#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x00000018 10180#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x00800000L 10181#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x00000017 10182#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x00400000L 10183#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x00000016 10184#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x00200000L 10185#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x00000015 10186#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x00100000L 10187#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x00000014 10188#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x00080000L 10189#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x00000013 10190#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x00040000L 10191#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x00000012 10192#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x00020000L 10193#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x00000011 10194#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00010000L 10195#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x00000010 10196#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00008000L 10197#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0x0000000f 10198#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00004000L 10199#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0x0000000e 10200#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00002000L 10201#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0x0000000d 10202#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00001000L 10203#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0x0000000c 10204#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00000800L 10205#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0x0000000b 10206#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00000400L 10207#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0x0000000a 10208#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00000200L 10209#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x00000009 10210#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00000100L 10211#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x00000008 10212#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00000080L 10213#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x00000007 10214#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00000040L 10215#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x00000006 10216#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00000020L 10217#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x00000005 10218#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000010L 10219#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x00000004 10220#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000008L 10221#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x00000003 10222#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000004L 10223#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x00000002 10224#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000002L 10225#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x00000001 10226#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000001L 10227#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x00000000 10228#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000L 10229#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x00000019 10230#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000L 10231#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x0000001f 10232#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L 10233#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x0000001e 10234#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x00000004L 10235#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x00000002 10236#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L 10237#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x0000001b 10238#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x00080000L 10239#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x00000013 10240#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x00040000L 10241#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x00000012 10242#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x00020000L 10243#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x00000011 10244#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x00010000L 10245#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x00000010 10246#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x00008000L 10247#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0x0000000f 10248#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x00004000L 10249#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0x0000000e 10250#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x00002000L 10251#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0x0000000d 10252#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x00001000L 10253#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0x0000000c 10254#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x00000800L 10255#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0x0000000b 10256#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x00000400L 10257#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0x0000000a 10258#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x00000200L 10259#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x00000009 10260#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x00000100L 10261#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x00000008 10262#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x00000080L 10263#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x00000007 10264#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x00000040L 10265#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x00000006 10266#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x00000020L 10267#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x00000005 10268#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x00000010L 10269#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x00000004 10270#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x00000001L 10271#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x00000000 10272#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x00100000L 10273#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x00000014 10274#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x00000002L 10275#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x00000001 10276#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x00000008L 10277#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x00000003 10278#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L 10279#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x0000001d 10280#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L 10281#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x0000001c 10282#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x04000000L 10283#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x0000001a 10284#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x02000000L 10285#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x00000019 10286#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x01000000L 10287#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x00000018 10288#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x00800000L 10289#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x00000017 10290#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x00400000L 10291#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x00000016 10292#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x00200000L 10293#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x00000015 10294#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x000001c0L 10295#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x00000006 10296#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x0000003fL 10297#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000000 10298#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000L 10299#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x0000001f 10300#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L 10301#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e 10302#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x0c000000L 10303#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001a 10304#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x03ff0000L 10305#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000010 10306#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x0000f000L 10307#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x0000000c 10308#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000L 10309#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x0000001c 10310#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00000e00L 10311#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000009 10312#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00300000L 10313#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 10314#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x0000007fL 10315#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000000 10316#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000L 10317#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x0000001c 10318#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0x0f000000L 10319#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x00000018 10320#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0x000f0000L 10321#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x00000010 10322#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x00008000L 10323#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0x0000000f 10324#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x00007c00L 10325#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0x0000000a 10326#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00000380L 10327#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x00000007 10328#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x00800000L 10329#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x00000017 10330#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x00400000L 10331#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x00000016 10332#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x0000007fL 10333#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x00000000 10334#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x00008000L 10335#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000000f 10336#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x007f0000L 10337#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000010 10338#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000180L 10339#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000007 10340#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x00007e00L 10341#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000009 10342#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000L 10343#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x0000001a 10344#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x03800000L 10345#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000017 10346#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0x000000ffL 10347#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x00000000 10348#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x001fc000L 10349#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x0000000e 10350#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000L 10351#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001d 10352#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000L 10353#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x0000001f 10354#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00600000L 10355#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x00000015 10356#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x00002000L 10357#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0x0000000d 10358#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x00001000L 10359#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0x0000000c 10360#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x02000000L 10361#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000019 10362#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x04000000L 10363#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x0000001a 10364#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000L 10365#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x0000001e 10366#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00800000L 10367#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x00000017 10368#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x00000f00L 10369#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000008 10370#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x01000000L 10371#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x00000018 10372#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x08000000L 10373#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x0000001b 10374#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000L 10375#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x0000001c 10376#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10377#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10378#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10379#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10380#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL 10381#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 10382#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L 10383#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a 10384#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 10385#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 10386#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L 10387#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a 10388#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL 10389#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 10390#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10391#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10392#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10393#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10394#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL 10395#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 10396#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L 10397#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a 10398#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L 10399#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 10400#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L 10401#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a 10402#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL 10403#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 10404#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10405#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10406#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10407#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10408#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L 10409#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 10410#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L 10411#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a 10412#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL 10413#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 10414#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10415#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10416#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10417#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10418#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L 10419#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 10420#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L 10421#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a 10422#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL 10423#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 10424#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL 10425#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000 10426#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000ffL 10427#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x00000000 10428#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 10429#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 10430#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL 10431#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000 10432#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 10433#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f 10434#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 10435#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e 10436#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 10437#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d 10438#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 10439#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 10440#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 10441#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 10442#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 10443#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a 10444#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 10445#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 10446#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 10447#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 10448#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001f0000L 10449#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x00000010 10450#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L 10451#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x00000010 10452#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000e000L 10453#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0x0000000d 10454#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000L 10455#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x00000016 10456#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL 10457#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000 10458#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000ffL 10459#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x00000000 10460#define TA_DEBUG_DATA__DATA_MASK 0xffffffffL 10461#define TA_DEBUG_DATA__DATA__SHIFT 0x00000000 10462#define TA_DEBUG_INDEX__INDEX_MASK 0x0000001fL 10463#define TA_DEBUG_INDEX__INDEX__SHIFT 0x00000000 10464#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10465#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10466#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10467#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10468#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L 10469#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c 10470#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L 10471#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 10472#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000ffL 10473#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 10474#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003fc00L 10475#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 10476#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 10477#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 10478#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L 10479#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 10480#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L 10481#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c 10482#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003fc00L 10483#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a 10484#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL 10485#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 10486#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10487#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10488#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10489#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10490#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L 10491#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 10492#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L 10493#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 10494#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L 10495#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c 10496#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003fc00L 10497#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a 10498#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL 10499#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 10500#define TA_SCRATCH__SCRATCH_MASK 0xffffffffL 10501#define TA_SCRATCH__SCRATCH__SHIFT 0x00000000 10502#define TA_STATUS__AL_BUSY_MASK 0x40000000L 10503#define TA_STATUS__AL_BUSY__SHIFT 0x0000001e 10504#define TA_STATUS__BUSY_MASK 0x80000000L 10505#define TA_STATUS__BUSY__SHIFT 0x0000001f 10506#define TA_STATUS__FA_BUSY_MASK 0x20000000L 10507#define TA_STATUS__FA_BUSY__SHIFT 0x0000001d 10508#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L 10509#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x00000015 10510#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L 10511#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x00000014 10512#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L 10513#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x00000016 10514#define TA_STATUS__FG_BUSY_MASK 0x02000000L 10515#define TA_STATUS__FG_BUSY__SHIFT 0x00000019 10516#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L 10517#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0x0000000d 10518#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L 10519#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0x0000000c 10520#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L 10521#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0x0000000e 10522#define TA_STATUS__FL_BUSY_MASK 0x08000000L 10523#define TA_STATUS__FL_BUSY__SHIFT 0x0000001b 10524#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L 10525#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x00000011 10526#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L 10527#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x00000010 10528#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L 10529#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x00000012 10530#define TA_STATUS__IN_BUSY_MASK 0x01000000L 10531#define TA_STATUS__IN_BUSY__SHIFT 0x00000018 10532#define TA_STATUS__LA_BUSY_MASK 0x04000000L 10533#define TA_STATUS__LA_BUSY__SHIFT 0x0000001a 10534#define TA_STATUS__TA_BUSY_MASK 0x10000000L 10535#define TA_STATUS__TA_BUSY__SHIFT 0x0000001c 10536#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 10537#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 10538#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL 10539#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 10540#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 10541#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f 10542#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 10543#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e 10544#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 10545#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d 10546#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 10547#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 10548#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 10549#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 10550#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 10551#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a 10552#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 10553#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 10554#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 10555#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 10556#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000fL 10557#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x00000000 10558#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10559#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10560#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10561#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10562#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0f000000L 10563#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x00000018 10564#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000L 10565#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x0000001c 10566#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL 10567#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 10568#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L 10569#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 10570#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 10571#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 10572#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L 10573#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 10574#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L 10575#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c 10576#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L 10577#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a 10578#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL 10579#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 10580#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10581#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10582#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10583#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10584#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0f000000L 10585#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x00000018 10586#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000L 10587#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x0000001c 10588#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL 10589#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 10590#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L 10591#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a 10592#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L 10593#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 10594#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L 10595#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 10596#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L 10597#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c 10598#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L 10599#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a 10600#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL 10601#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 10602#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10603#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10604#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10605#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10606#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L 10607#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 10608#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L 10609#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c 10610#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL 10611#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 10612#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10613#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10614#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10615#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10616#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L 10617#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 10618#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L 10619#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c 10620#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL 10621#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 10622#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 10623#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 10624#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL 10625#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 10626#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 10627#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f 10628#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 10629#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e 10630#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 10631#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d 10632#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 10633#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 10634#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 10635#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 10636#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 10637#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a 10638#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 10639#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 10640#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 10641#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 10642#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L 10643#define TCC_CTRL__CACHE_SIZE__SHIFT 0x00000000 10644#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000f0000L 10645#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x00000010 10646#define TCC_CTRL__RATE_MASK 0x0000000cL 10647#define TCC_CTRL__RATE__SHIFT 0x00000002 10648#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000f000L 10649#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0x0000000c 10650#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x00100000L 10651#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x00000014 10652#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000f0L 10653#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x00000004 10654#define TCC_EDC_COUNTER__DED_COUNT_MASK 0x000f0000L 10655#define TCC_EDC_COUNTER__DED_COUNT__SHIFT 0x00000010 10656#define TCC_EDC_COUNTER__SEC_COUNT_MASK 0x0000000fL 10657#define TCC_EDC_COUNTER__SEC_COUNT__SHIFT 0x00000000 10658#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10659#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10660#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10661#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10662#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0f000000L 10663#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x00000018 10664#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000L 10665#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x0000001c 10666#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL 10667#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 10668#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L 10669#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 10670#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 10671#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 10672#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L 10673#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 10674#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L 10675#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c 10676#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L 10677#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a 10678#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL 10679#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 10680#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10681#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10682#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10683#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10684#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0f000000L 10685#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x00000018 10686#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000L 10687#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x0000001c 10688#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL 10689#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 10690#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L 10691#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a 10692#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L 10693#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 10694#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L 10695#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 10696#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L 10697#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c 10698#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L 10699#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a 10700#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL 10701#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 10702#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10703#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10704#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10705#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10706#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L 10707#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 10708#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L 10709#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c 10710#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL 10711#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 10712#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10713#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10714#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10715#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10716#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L 10717#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 10718#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L 10719#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c 10720#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL 10721#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 10722#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00ff0000L 10723#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x00000010 10724#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000ffffL 10725#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x00000000 10726#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000L 10727#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x00000018 10728#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L 10729#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x00000000 10730#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001feL 10731#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x00000001 10732#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L 10733#define TCI_STATUS__TCI_BUSY__SHIFT 0x00000000 10734#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001c0L 10735#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x00000006 10736#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L 10737#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x00000004 10738#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000fL 10739#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x00000000 10740#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L 10741#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x00000009 10742#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L 10743#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x00000008 10744#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L 10745#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x00000018 10746#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L 10747#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x00000000 10748#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L 10749#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x00000010 10750#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000fL 10751#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x00000000 10752#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000f0L 10753#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x00000004 10754#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000f00L 10755#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x00000008 10756#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000f000L 10757#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0x0000000c 10758#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000f0000L 10759#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x00000010 10760#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00f00000L 10761#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x00000014 10762#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0f000000L 10763#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x00000018 10764#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000L 10765#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x0000001c 10766#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000fL 10767#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x00000000 10768#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000f0L 10769#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x00000004 10770#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000f00L 10771#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x00000008 10772#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000f000L 10773#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0x0000000c 10774#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000f0000L 10775#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x00000010 10776#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00f00000L 10777#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x00000014 10778#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0f000000L 10779#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x00000018 10780#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000L 10781#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x0000001c 10782#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L 10783#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x0000001c 10784#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L 10785#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x00000005 10786#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L 10787#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x00000004 10788#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0fc00000L 10789#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x00000016 10790#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001f8000L 10791#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0x0000000f 10792#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L 10793#define TCP_CNTL__FORCE_HIT__SHIFT 0x00000000 10794#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L 10795#define TCP_CNTL__FORCE_MISS__SHIFT 0x00000001 10796#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L 10797#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x0000001d 10798#define TCP_CNTL__L1_SIZE_MASK 0x0000000cL 10799#define TCP_CNTL__L1_SIZE__SHIFT 0x00000002 10800#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003ffL 10801#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x00000000 10802#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007f0000L 10803#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x00000010 10804#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000L 10805#define TCP_CREDIT__TD_CREDIT__SHIFT 0x0000001d 10806#define TCP_EDC_COUNTER__DED_COUNT_MASK 0x000f0000L 10807#define TCP_EDC_COUNTER__DED_COUNT__SHIFT 0x00000010 10808#define TCP_EDC_COUNTER__SEC_COUNT_MASK 0x0000000fL 10809#define TCP_EDC_COUNTER__SEC_COUNT__SHIFT 0x00000000 10810#define TCP_INVALIDATE__START_MASK 0x00000001L 10811#define TCP_INVALIDATE__START__SHIFT 0x00000000 10812#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10813#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10814#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10815#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10816#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L 10817#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c 10818#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L 10819#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 10820#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL 10821#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 10822#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L 10823#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 10824#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 10825#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 10826#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L 10827#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 10828#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L 10829#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c 10830#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L 10831#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a 10832#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL 10833#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 10834#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10835#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10836#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10837#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10838#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L 10839#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c 10840#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L 10841#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 10842#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL 10843#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 10844#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L 10845#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a 10846#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L 10847#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 10848#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L 10849#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 10850#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L 10851#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c 10852#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L 10853#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a 10854#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL 10855#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 10856#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10857#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10858#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10859#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10860#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L 10861#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 10862#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L 10863#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c 10864#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL 10865#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 10866#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10867#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10868#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10869#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10870#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L 10871#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 10872#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L 10873#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c 10874#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL 10875#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 10876#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L 10877#define TCP_STATUS__TCP_BUSY__SHIFT 0x00000000 10878#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L 10879#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 10880#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL 10881#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000 10882#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 10883#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f 10884#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 10885#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e 10886#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 10887#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d 10888#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 10889#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c 10890#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 10891#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b 10892#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 10893#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a 10894#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 10895#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 10896#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 10897#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 10898#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L 10899#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x00000014 10900#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L 10901#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x00000009 10902#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L 10903#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x00000013 10904#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L 10905#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x00000010 10906#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L 10907#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x00000012 10908#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L 10909#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0x0000000b 10910#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L 10911#define TD_CNTL__PAD_STALL_EN__SHIFT 0x00000008 10912#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L 10913#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0x0000000f 10914#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L 10915#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x00000000 10916#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L 10917#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x00000004 10918#define TD_DEBUG_DATA__DATA_MASK 0x00ffffffL 10919#define TD_DEBUG_DATA__DATA__SHIFT 0x00000000 10920#define TD_DEBUG_INDEX__INDEX_MASK 0x0000001fL 10921#define TD_DEBUG_INDEX__INDEX__SHIFT 0x00000000 10922#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 10923#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 10924#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 10925#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 10926#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L 10927#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c 10928#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L 10929#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 10930#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000ffL 10931#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 10932#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003fc00L 10933#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 10934#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 10935#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 10936#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L 10937#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 10938#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L 10939#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c 10940#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003fc00L 10941#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a 10942#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL 10943#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 10944#define TD_SCRATCH__SCRATCH_MASK 0xffffffffL 10945#define TD_SCRATCH__SCRATCH__SHIFT 0x00000000 10946#define TD_STATUS__BUSY_MASK 0x80000000L 10947#define TD_STATUS__BUSY__SHIFT 0x0000001f 10948#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L 10949#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010 10950#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L 10951#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014 10952#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0x0f000000L 10953#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x00000018 10954#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000L 10955#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x0000001c 10956#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000c0L 10957#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x00000006 10958#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L 10959#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x00000000 10960#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L 10961#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0x0000000b 10962#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001f0000L 10963#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x00000010 10964#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L 10965#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0x0000000c 10966#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L 10967#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0x0000000d 10968#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L 10969#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x00000009 10970#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L 10971#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x00000005 10972#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L 10973#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 10974#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L 10975#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x00000007 10976#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L 10977#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x00000008 10978#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L 10979#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000002 10980#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L 10981#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000001 10982#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L 10983#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x00000006 10984#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L 10985#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000003 10986#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L 10987#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x00000009 10988#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L 10989#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x00000004 10990#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L 10991#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000005 10992#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000003fL 10993#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 10994#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x00000040L 10995#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x00000006 10996#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL 10997#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 10998#define VGT_DEBUG_REG0__cm_busy_MASK 0x00008000L 10999#define VGT_DEBUG_REG0__cm_busy__SHIFT 0x0000000f 11000#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x00200000L 11001#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x00000015 11002#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x04000000L 11003#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x0000001a 11004#define VGT_DEBUG_REG0__frmt_busy_MASK 0x00020000L 11005#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x00000011 11006#define VGT_DEBUG_REG0__gog_busy_MASK 0x00010000L 11007#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x00000010 11008#define VGT_DEBUG_REG0__gs_busy_MASK 0x00001000L 11009#define VGT_DEBUG_REG0__gs_busy__SHIFT 0x0000000c 11010#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x08000000L 11011#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x0000001b 11012#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x00800000L 11013#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x00000017 11014#define VGT_DEBUG_REG0__pi_busy_MASK 0x00000100L 11015#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x00000008 11016#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x00000400L 11017#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0x0000000a 11018#define VGT_DEBUG_REG0__rcm_busy_MASK 0x00002000L 11019#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0x0000000d 11020#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L 11021#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018 11022#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L 11023#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d 11024#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000L 11025#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x0000001e 11026#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000L 11027#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x0000001f 11028#define VGT_DEBUG_REG0__SPARE10_MASK 0x00040000L 11029#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x00000012 11030#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000L 11031#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x0000001c 11032#define VGT_DEBUG_REG0__SPARE2_MASK 0x02000000L 11033#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x00000019 11034#define VGT_DEBUG_REG0__SPARE3_MASK 0x00100000L 11035#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x00000014 11036#define VGT_DEBUG_REG0__SPARE4_MASK 0x00000080L 11037#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x00000007 11038#define VGT_DEBUG_REG0__SPARE5_MASK 0x00000040L 11039#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x00000006 11040#define VGT_DEBUG_REG0__SPARE6_MASK 0x00000020L 11041#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x00000005 11042#define VGT_DEBUG_REG0__SPARE7_MASK 0x00000010L 11043#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x00000004 11044#define VGT_DEBUG_REG0__SPARE8_MASK 0x00000008L 11045#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x00000003 11046#define VGT_DEBUG_REG0__SPARE9_MASK 0x00000002L 11047#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x00000001 11048#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x00400000L 11049#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x00000016 11050#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x00080000L 11051#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x00000013 11052#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x00000800L 11053#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0x0000000b 11054#define VGT_DEBUG_REG0__tm_busy_MASK 0x00004000L 11055#define VGT_DEBUG_REG0__tm_busy__SHIFT 0x0000000e 11056#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00000001L 11057#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x00000000 11058#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00000004L 11059#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x00000002 11060#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x00000200L 11061#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x00000009 11062#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x00000020L 11063#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x00000005 11064#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x00000040L 11065#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x00000006 11066#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000L 11067#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x00000017 11068#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x007fe000L 11069#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0x0000000d 11070#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x0000001fL 11071#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x00000000 11072#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x00000180L 11073#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x00000007 11074#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x00001000L 11075#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x00000800L 11076#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0x0000000b 11077#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0x0000000c 11078#define VGT_DEBUG_REG10__SPARE2_MASK 0x00000600L 11079#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x00000009 11080#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x00001000L 11081#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0x0000000c 11082#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x00000800L 11083#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0x0000000b 11084#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x00000400L 11085#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0x0000000a 11086#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x00100000L 11087#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x00000014 11088#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x00000008L 11089#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x00000003 11090#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x08000000L 11091#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x0000001b 11092#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x00000200L 11093#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x00000009 11094#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000L 11095#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x0000001e 11096#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x00200000L 11097#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x00000015 11098#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x00010000L 11099#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x00000010 11100#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x00080000L 11101#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x00000013 11102#define VGT_DEBUG_REG11__hold_eswave_MASK 0x00000100L 11103#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x00000008 11104#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000L 11105#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x0000001f 11106#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000L 11107#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x0000001d 11108#define VGT_DEBUG_REG11__SPARE0_MASK 0x00040000L 11109#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x00000012 11110#define VGT_DEBUG_REG11__SPARE1_MASK 0x00000020L 11111#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x00000005 11112#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x00000080L 11113#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x00000007 11114#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x00000040L 11115#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x00000006 11116#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x00000001L 11117#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x00000000 11118#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x00000002L 11119#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x00000001 11120#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x00000004L 11121#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x00000002 11122#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x00020000L 11123#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x00000011 11124#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x01000000L 11125#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x00000018 11126#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x00400000L 11127#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x00000016 11128#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x00800000L 11129#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x00000017 11130#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x00008000L 11131#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0x0000000f 11132#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x00004000L 11133#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0x0000000e 11134#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x00000010L 11135#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x00000004 11136#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000L 11137#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x0000001c 11138#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x02000000L 11139#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x00000019 11140#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x04000000L 11141#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x0000001a 11142#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x00002000L 11143#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0x0000000d 11144#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x00000007L 11145#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x00000000 11146#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x00000038L 11147#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x00000003 11148#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x000001c0L 11149#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x00000006 11150#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0x00000e00L 11151#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x00000009 11152#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x00007000L 11153#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0x0000000c 11154#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x00038000L 11155#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0x0000000f 11156#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x001c0000L 11157#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x00000012 11158#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0x00e00000L 11159#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x00000015 11160#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x07000000L 11161#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x00000018 11162#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000L 11163#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x0000001b 11164#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000L 11165#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x0000001e 11166#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000L 11167#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x0000001f 11168#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000L 11169#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x0000001b 11170#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x01000000L 11171#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x00000018 11172#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x00800000L 11173#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x00000017 11174#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x00400000L 11175#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x00000016 11176#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x00000007L 11177#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x00000000 11178#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x00000038L 11179#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x00000003 11180#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x000001c0L 11181#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x00000006 11182#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0x00000e00L 11183#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x00000009 11184#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x00007000L 11185#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0x0000000c 11186#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x00038000L 11187#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0x0000000f 11188#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x003c0000L 11189#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x00000012 11190#define VGT_DEBUG_REG13__SPARE0_MASK 0x04000000L 11191#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x0000001a 11192#define VGT_DEBUG_REG13__SPARE1_MASK 0x02000000L 11193#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x00000019 11194#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x00000400L 11195#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0x0000000a 11196#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x00000010L 11197#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x00000004 11198#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000L 11199#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x0000001d 11200#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x00000020L 11201#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x00000005 11202#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x00000800L 11203#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0x0000000b 11204#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x08000000L 11205#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x0000001b 11206#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x00200000L 11207#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x00000015 11208#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x04000000L 11209#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x0000001a 11210#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x00000040L 11211#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x00000006 11212#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000L 11213#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x0000001e 11214#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000L 11215#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x0000001c 11216#define VGT_DEBUG_REG14__SPARE2_MASK 0x001ff000L 11217#define VGT_DEBUG_REG14__SPARE2__SHIFT 0x0000000c 11218#define VGT_DEBUG_REG14__SPARE3_MASK 0x0000000fL 11219#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x00000000 11220#define VGT_DEBUG_REG14__SPARE8_MASK 0x00000180L 11221#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x00000007 11222#define VGT_DEBUG_REG14__SPARE_MASK 0x01c00000L 11223#define VGT_DEBUG_REG14__SPARE__SHIFT 0x00000016 11224#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000L 11225#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x0000001f 11226#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x02000000L 11227#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x00000019 11228#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x00000200L 11229#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x00000009 11230#define VGT_DEBUG_REG15__active_sm_q_MASK 0x000003e0L 11231#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x00000005 11232#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x00000001L 11233#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x00000000 11234#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0x000f8000L 11235#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0x0000000f 11236#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x00000002L 11237#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x00000001 11238#define VGT_DEBUG_REG15__counters_full_MASK 0x00000010L 11239#define VGT_DEBUG_REG15__counters_full__SHIFT 0x00000004 11240#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x00007c00L 11241#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0x0000000a 11242#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000L 11243#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x0000001c 11244#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x00000004L 11245#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x00000002 11246#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x00000008L 11247#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x00000003 11248#define VGT_DEBUG_REG15__SPARE25_MASK 0x03f00000L 11249#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x00000014 11250#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000L 11251#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x0000001d 11252#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0x0c000000L 11253#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x0000001a 11254#define VGT_DEBUG_REG16__gog_busy_MASK 0x00000001L 11255#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x00000000 11256#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0x0e000000L 11257#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x00000019 11258#define VGT_DEBUG_REG16__gog_state_q_MASK 0x0000000eL 11259#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x00000001 11260#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x00000800L 11261#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0x0000000b 11262#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x00080000L 11263#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x00000013 11264#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x00020000L 11265#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x00000011 11266#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x00002000L 11267#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0x0000000d 11268#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000L 11269#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x0000001c 11270#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000L 11271#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x0000001f 11272#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000L 11273#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x0000001e 11274#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x00100000L 11275#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x00000014 11276#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x00010000L 11277#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x00000010 11278#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x00004000L 11279#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0x0000000e 11280#define VGT_DEBUG_REG16__r0_rtr_MASK 0x00000010L 11281#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x00000004 11282#define VGT_DEBUG_REG16__r1_rtr_MASK 0x00000020L 11283#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x00000005 11284#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x00000040L 11285#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x00000006 11286#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x00000200L 11287#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x00000009 11288#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x00000100L 11289#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x00000008 11290#define VGT_DEBUG_REG16__r2_rtr_MASK 0x00000400L 11291#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0x0000000a 11292#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x00000080L 11293#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x00000007 11294#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x00001000L 11295#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0x0000000c 11296#define VGT_DEBUG_REG16__send_event_q_MASK 0x00400000L 11297#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x00000016 11298#define VGT_DEBUG_REG16__SPARE24_MASK 0x01800000L 11299#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x00000017 11300#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x00200000L 11301#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x00000015 11302#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x00040000L 11303#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x00000012 11304#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x00008000L 11305#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0x0000000f 11306#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x01000000L 11307#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x00000018 11308#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000L 11309#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x0000001d 11310#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000L 11311#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x00000012 11312#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x0003f000L 11313#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0x0000000c 11314#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0x00000fc0L 11315#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x00000006 11316#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x0000003fL 11317#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x00000000 11318#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000L 11319#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x0000001d 11320#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x00800000L 11321#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x00000017 11322#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x00400000L 11323#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x00000016 11324#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x00000001L 11325#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x00000000 11326#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x08000000L 11327#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x0000001b 11328#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000L 11329#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x0000001c 11330#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x00000700L 11331#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x00000008 11332#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x00040000L 11333#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x00000012 11334#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x00002000L 11335#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0x0000000d 11336#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x00020000L 11337#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x00000011 11338#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x00004000L 11339#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0x0000000e 11340#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x00010000L 11341#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x00000010 11342#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x00008000L 11343#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0x0000000f 11344#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x00100000L 11345#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x00000014 11346#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x00001000L 11347#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0x0000000c 11348#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x00200000L 11349#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x00000015 11350#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x00000040L 11351#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x00000006 11352#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x00000080L 11353#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x00000007 11354#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x00000002L 11355#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x00000001 11356#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x00000010L 11357#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x00000004 11358#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x00000004L 11359#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x00000002 11360#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x00000020L 11361#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x00000005 11362#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x00080000L 11363#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x00000013 11364#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x07000000L 11365#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x00000018 11366#define VGT_DEBUG_REG18__valid_indices_MASK 0x00000800L 11367#define VGT_DEBUG_REG18__valid_indices__SHIFT 0x0000000b 11368#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x00000008L 11369#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x00000003 11370#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x00080000L 11371#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x00000013 11372#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x00040000L 11373#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x00000012 11374#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x00010000L 11375#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x00000010 11376#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x00020000L 11377#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x00000011 11378#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x03f00000L 11379#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x00000014 11380#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000L 11381#define VGT_DEBUG_REG19__filter_event__SHIFT 0x0000001f 11382#define VGT_DEBUG_REG19__hold_prim_MASK 0x00000800L 11383#define VGT_DEBUG_REG19__hold_prim__SHIFT 0x0000000b 11384#define VGT_DEBUG_REG19__new_packet_q_MASK 0x00008000L 11385#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0x0000000f 11386#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000L 11387#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x0000001e 11388#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000L 11389#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x0000001c 11390#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x00000020L 11391#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x00000005 11392#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x00000010L 11393#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x00000004 11394#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x00000400L 11395#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0x0000000a 11396#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x00000004L 11397#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x00000002 11398#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x00000008L 11399#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x00000003 11400#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x00000001L 11401#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x00000000 11402#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x00000002L 11403#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x00000001 11404#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x00000100L 11405#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x00000008 11406#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x00000200L 11407#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x00000009 11408#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x00000080L 11409#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x00000007 11410#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x00000040L 11411#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x00000006 11412#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x00004000L 11413#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0x0000000e 11414#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x08000000L 11415#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x0000001b 11416#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x04000000L 11417#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x0000001a 11418#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x00001000L 11419#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0x0000000c 11420#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x00002000L 11421#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0x0000000d 11422#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000L 11423#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x0000001c 11424#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000L 11425#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x0000001e 11426#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x08000000L 11427#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x0000001b 11428#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000L 11429#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x0000001d 11430#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000L 11431#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x0000001f 11432#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x04000000L 11433#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x0000001a 11434#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x00001000L 11435#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0x0000000c 11436#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x00004000L 11437#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0x0000000e 11438#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x00000400L 11439#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0x0000000a 11440#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00100000L 11441#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000014 11442#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00400000L 11443#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000016 11444#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x00002000L 11445#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0x0000000d 11446#define VGT_DEBUG_REG1__SPARE0_MASK 0x00000200L 11447#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x00000009 11448#define VGT_DEBUG_REG1__SPARE10_MASK 0x00200000L 11449#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x00000015 11450#define VGT_DEBUG_REG1__SPARE11_MASK 0x00080000L 11451#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x00000013 11452#define VGT_DEBUG_REG1__SPARE12_MASK 0x00020000L 11453#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x00000011 11454#define VGT_DEBUG_REG1__SPARE1_MASK 0x00000100L 11455#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x00000008 11456#define VGT_DEBUG_REG1__SPARE23_MASK 0x00800000L 11457#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x00000017 11458#define VGT_DEBUG_REG1__SPARE25_MASK 0x02000000L 11459#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x00000019 11460#define VGT_DEBUG_REG1__SPARE2_MASK 0x00000080L 11461#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x00000007 11462#define VGT_DEBUG_REG1__SPARE3_MASK 0x00000040L 11463#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x00000006 11464#define VGT_DEBUG_REG1__SPARE4_MASK 0x00000020L 11465#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x00000005 11466#define VGT_DEBUG_REG1__SPARE5_MASK 0x00000010L 11467#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x00000004 11468#define VGT_DEBUG_REG1__SPARE6_MASK 0x00000008L 11469#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x00000003 11470#define VGT_DEBUG_REG1__SPARE7_MASK 0x00000004L 11471#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x00000002 11472#define VGT_DEBUG_REG1__SPARE8_MASK 0x00000002L 11473#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x00000001 11474#define VGT_DEBUG_REG1__SPARE9_MASK 0x00000001L 11475#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x00000000 11476#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00008000L 11477#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000f 11478#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x01000000L 11479#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000018 11480#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00010000L 11481#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000010 11482#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00040000L 11483#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000012 11484#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x00000800L 11485#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0x0000000b 11486#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x003c0000L 11487#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x00000012 11488#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000L 11489#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x00000016 11490#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000L 11491#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x0000001e 11492#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x00010000L 11493#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x00000010 11494#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0x0000ffffL 11495#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x00000000 11496#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000L 11497#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x0000001f 11498#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000L 11499#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x0000001d 11500#define VGT_DEBUG_REG20__SPARE17_MASK 0x00020000L 11501#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x00000011 11502#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x01000000L 11503#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x00000018 11504#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000L 11505#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x0000001e 11506#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x04000000L 11507#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x0000001a 11508#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x00008000L 11509#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0x0000000f 11510#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x00002000L 11511#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0x0000000d 11512#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x00000002L 11513#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x00000001 11514#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x00000080L 11515#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x00000007 11516#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x00010000L 11517#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x00000010 11518#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x00001000L 11519#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0x0000000c 11520#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x00100000L 11521#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x00000014 11522#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x00200000L 11523#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x00000015 11524#define VGT_DEBUG_REG21__null_r2_q_MASK 0x08000000L 11525#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x0000001b 11526#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x00000001L 11527#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x00000000 11528#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x00000040L 11529#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x00000006 11530#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000L 11531#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x0000001c 11532#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000L 11533#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x0000001f 11534#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000L 11535#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x0000001d 11536#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x00000004L 11537#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x00000002 11538#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x00000100L 11539#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x00000008 11540#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x00000008L 11541#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x00000003 11542#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x00000200L 11543#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x00000009 11544#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x00000010L 11545#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x00000004 11546#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x00000400L 11547#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0x0000000a 11548#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0x000e0000L 11549#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x00000011 11550#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x00400000L 11551#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x00000016 11552#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x02000000L 11553#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x00000019 11554#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x00000020L 11555#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x00000005 11556#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x00000800L 11557#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0x0000000b 11558#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x00800000L 11559#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x00000017 11560#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x00004000L 11561#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0x0000000e 11562#define VGT_DEBUG_REG22__cm_state16_MASK 0x00000003L 11563#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x00000000 11564#define VGT_DEBUG_REG22__cm_state17_MASK 0x0000000cL 11565#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x00000002 11566#define VGT_DEBUG_REG22__cm_state18_MASK 0x00000030L 11567#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x00000004 11568#define VGT_DEBUG_REG22__cm_state19_MASK 0x000000c0L 11569#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x00000006 11570#define VGT_DEBUG_REG22__cm_state20_MASK 0x00000300L 11571#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x00000008 11572#define VGT_DEBUG_REG22__cm_state21_MASK 0x00000c00L 11573#define VGT_DEBUG_REG22__cm_state21__SHIFT 0x0000000a 11574#define VGT_DEBUG_REG22__cm_state22_MASK 0x00003000L 11575#define VGT_DEBUG_REG22__cm_state22__SHIFT 0x0000000c 11576#define VGT_DEBUG_REG22__cm_state23_MASK 0x0000c000L 11577#define VGT_DEBUG_REG22__cm_state23__SHIFT 0x0000000e 11578#define VGT_DEBUG_REG22__cm_state24_MASK 0x00030000L 11579#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x00000010 11580#define VGT_DEBUG_REG22__cm_state25_MASK 0x000c0000L 11581#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x00000012 11582#define VGT_DEBUG_REG22__cm_state26_MASK 0x00300000L 11583#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x00000014 11584#define VGT_DEBUG_REG22__cm_state27_MASK 0x00c00000L 11585#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x00000016 11586#define VGT_DEBUG_REG22__cm_state28_MASK 0x03000000L 11587#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x00000018 11588#define VGT_DEBUG_REG22__cm_state29_MASK 0x0c000000L 11589#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x0000001a 11590#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000L 11591#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x0000001c 11592#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000L 11593#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x0000001e 11594#define VGT_DEBUG_REG23__frmt_busy_MASK 0x00000001L 11595#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x00000000 11596#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x00018000L 11597#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0x0000000f 11598#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x00001000L 11599#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0x0000000c 11600#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x00000200L 11601#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x00000009 11602#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x00000400L 11603#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0x0000000a 11604#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x00000010L 11605#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x00000004 11606#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x00000008L 11607#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x00000003 11608#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0x00e00000L 11609#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x00000015 11610#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x00000004L 11611#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x00000002 11612#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x00000002L 11613#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x00000001 11614#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000L 11615#define VGT_DEBUG_REG23__SPARE__SHIFT 0x00000018 11616#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x00004000L 11617#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0x0000000e 11618#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x00002000L 11619#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0x0000000d 11620#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x00000800L 11621#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0x0000000b 11622#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x00000100L 11623#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x00000008 11624#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x00000080L 11625#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x00000007 11626#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x00000040L 11627#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x00000006 11628#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x00000020L 11629#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x00000005 11630#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x001e0000L 11631#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x00000011 11632#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0x00ffffffL 11633#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x00000000 11634#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x03000000L 11635#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x00000018 11636#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000L 11637#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x0000001a 11638#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000L 11639#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x0000001a 11640#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000L 11641#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x0000001f 11642#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000L 11643#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x0000001e 11644#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x03ffffffL 11645#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x00000000 11646#define VGT_DEBUG_REG26__cm_state0_MASK 0x00000003L 11647#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x00000000 11648#define VGT_DEBUG_REG26__cm_state10_MASK 0x00300000L 11649#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x00000014 11650#define VGT_DEBUG_REG26__cm_state11_MASK 0x00c00000L 11651#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x00000016 11652#define VGT_DEBUG_REG26__cm_state12_MASK 0x03000000L 11653#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x00000018 11654#define VGT_DEBUG_REG26__cm_state13_MASK 0x0c000000L 11655#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x0000001a 11656#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000L 11657#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x0000001c 11658#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000L 11659#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x0000001e 11660#define VGT_DEBUG_REG26__cm_state1_MASK 0x0000000cL 11661#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x00000002 11662#define VGT_DEBUG_REG26__cm_state2_MASK 0x00000030L 11663#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x00000004 11664#define VGT_DEBUG_REG26__cm_state3_MASK 0x000000c0L 11665#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x00000006 11666#define VGT_DEBUG_REG26__cm_state4_MASK 0x00000300L 11667#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x00000008 11668#define VGT_DEBUG_REG26__cm_state5_MASK 0x00000c00L 11669#define VGT_DEBUG_REG26__cm_state5__SHIFT 0x0000000a 11670#define VGT_DEBUG_REG26__cm_state6_MASK 0x00003000L 11671#define VGT_DEBUG_REG26__cm_state6__SHIFT 0x0000000c 11672#define VGT_DEBUG_REG26__cm_state7_MASK 0x0000c000L 11673#define VGT_DEBUG_REG26__cm_state7__SHIFT 0x0000000e 11674#define VGT_DEBUG_REG26__cm_state8_MASK 0x00030000L 11675#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x00000010 11676#define VGT_DEBUG_REG26__cm_state9_MASK 0x000c0000L 11677#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x00000012 11678#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x00000800L 11679#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0x0000000b 11680#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x00000400L 11681#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0x0000000a 11682#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x00080000L 11683#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x00000013 11684#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x00000002L 11685#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x00000001 11686#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x00000020L 11687#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x00000005 11688#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x00010000L 11689#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x00000010 11690#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x00020000L 11691#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x00000011 11692#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x00008000L 11693#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0x0000000f 11694#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000L 11695#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x00000014 11696#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x00004000L 11697#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0x0000000e 11698#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x00003000L 11699#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0x0000000c 11700#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x00000300L 11701#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x00000008 11702#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x00000080L 11703#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x00000007 11704#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x00040000L 11705#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x00000012 11706#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000L 11707#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x0000001f 11708#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x00000001L 11709#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x00000000 11710#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x00000010L 11711#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x00000004 11712#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x00000004L 11713#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x00000002 11714#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x00000040L 11715#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x00000006 11716#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x00000008L 11717#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x00000003 11718#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x00800000L 11719#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x00000017 11720#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x00400000L 11721#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x00000016 11722#define VGT_DEBUG_REG28__con_state_q_MASK 0x0000000fL 11723#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x00000000 11724#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x00010000L 11725#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x00000010 11726#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x00040000L 11727#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 11728#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x00100000L 11729#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x00000014 11730#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x00080000L 11731#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x00000013 11732#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x00020000L 11733#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x00000011 11734#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x01000000L 11735#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x00000018 11736#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L 11737#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 11738#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x00004000L 11739#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0x0000000e 11740#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x00008000L 11741#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0x0000000f 11742#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x00000200L 11743#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x00000009 11744#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x00001000L 11745#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0x0000000c 11746#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x00000100L 11747#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x00000008 11748#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x00000800L 11749#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0x0000000b 11750#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x00000400L 11751#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0x0000000a 11752#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000L 11753#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x0000001e 11754#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x08000000L 11755#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x0000001b 11756#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000L 11757#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x0000001c 11758#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x02000000L 11759#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x00000019 11760#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x04000000L 11761#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x0000001a 11762#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000L 11763#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x0000001d 11764#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x00002000L 11765#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0x0000000d 11766#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L 11767#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 11768#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x00000080L 11769#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x00000007 11770#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x00000020L 11771#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x00000005 11772#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x00000010L 11773#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x00000004 11774#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000L 11775#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x0000001f 11776#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x00800000L 11777#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x00000017 11778#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x00400000L 11779#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x00000016 11780#define VGT_DEBUG_REG29__con_state_q_MASK 0x0000000fL 11781#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x00000000 11782#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x00010000L 11783#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x00000010 11784#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x00040000L 11785#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 11786#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x00100000L 11787#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x00000014 11788#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x00080000L 11789#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x00000013 11790#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x00020000L 11791#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x00000011 11792#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x01000000L 11793#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x00000018 11794#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L 11795#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 11796#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x00004000L 11797#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0x0000000e 11798#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x00008000L 11799#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0x0000000f 11800#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x00000200L 11801#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x00000009 11802#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x00001000L 11803#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0x0000000c 11804#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x00000100L 11805#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x00000008 11806#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x00000800L 11807#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0x0000000b 11808#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x00000400L 11809#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0x0000000a 11810#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000L 11811#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x0000001e 11812#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x08000000L 11813#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x0000001b 11814#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000L 11815#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x0000001c 11816#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x02000000L 11817#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x00000019 11818#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x04000000L 11819#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x0000001a 11820#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000L 11821#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x0000001d 11822#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x00002000L 11823#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0x0000000d 11824#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L 11825#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 11826#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x00000080L 11827#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x00000007 11828#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x00000020L 11829#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x00000005 11830#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x00000010L 11831#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x00000004 11832#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000L 11833#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x0000001f 11834#define VGT_DEBUG_REG2__grpModBusy_MASK 0x00000080L 11835#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x00000007 11836#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x00000001L 11837#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x00000000 11838#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x00001000L 11839#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0x0000000c 11840#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x00040000L 11841#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x00000012 11842#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x00000002L 11843#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x00000001 11844#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x00000040L 11845#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x00000006 11846#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x00002000L 11847#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0x0000000d 11848#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x00080000L 11849#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x00000013 11850#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x00000400L 11851#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0x0000000a 11852#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x00010000L 11853#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x00000010 11854#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x00000800L 11855#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0x0000000b 11856#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x00020000L 11857#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x00000011 11858#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x08000000L 11859#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x0000001b 11860#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x04000000L 11861#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x0000001a 11862#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x00000100L 11863#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x00000008 11864#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x00004000L 11865#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0x0000000e 11866#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x00000008L 11867#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x00000003 11868#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x00000200L 11869#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x00000009 11870#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x00008000L 11871#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0x0000000f 11872#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x00000020L 11873#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x00000005 11874#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000L 11875#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x0000001c 11876#define VGT_DEBUG_REG2__p0_dr_MASK 0x00400000L 11877#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x00000016 11878#define VGT_DEBUG_REG2__p0_rtr_MASK 0x00100000L 11879#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x00000014 11880#define VGT_DEBUG_REG2__p0_rts_MASK 0x01000000L 11881#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x00000018 11882#define VGT_DEBUG_REG2__p1_dr_MASK 0x00800000L 11883#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x00000017 11884#define VGT_DEBUG_REG2__p1_rtr_MASK 0x00200000L 11885#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x00000015 11886#define VGT_DEBUG_REG2__p1_rts_MASK 0x02000000L 11887#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x00000019 11888#define VGT_DEBUG_REG2__SPARE_MASK 0xffffffffL 11889#define VGT_DEBUG_REG2__SPARE__SHIFT 0x00000000 11890#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x00000010L 11891#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x00000004 11892#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x00000004L 11893#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x00000002 11894#define VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK 0x01000000L 11895#define VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT 0x00000018 11896#define VGT_DEBUG_REG30__event_or_null_p0_q_MASK 0x00000008L 11897#define VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT 0x00000003 11898#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK 0x08000000L 11899#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT 0x0000001b 11900#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK 0x04000000L 11901#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT 0x0000001a 11902#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK 0x02000000L 11903#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT 0x00000019 11904#define VGT_DEBUG_REG30__last_tf_of_tg_MASK 0x00080000L 11905#define VGT_DEBUG_REG30__last_tf_of_tg__SHIFT 0x00000013 11906#define VGT_DEBUG_REG30__pipe0_dr_MASK 0x00000001L 11907#define VGT_DEBUG_REG30__pipe0_dr__SHIFT 0x00000000 11908#define VGT_DEBUG_REG30__pipe0_rtr_MASK 0x00000010L 11909#define VGT_DEBUG_REG30__pipe0_rtr__SHIFT 0x00000004 11910#define VGT_DEBUG_REG30__pipe0_tf_dr_MASK 0x00000002L 11911#define VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT 0x00000001 11912#define VGT_DEBUG_REG30__pipe1_rtr_MASK 0x00000020L 11913#define VGT_DEBUG_REG30__pipe1_rtr__SHIFT 0x00000005 11914#define VGT_DEBUG_REG30__pipe1_tf_rtr_MASK 0x00000040L 11915#define VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT 0x00000006 11916#define VGT_DEBUG_REG30__pipe2_dr_MASK 0x00000004L 11917#define VGT_DEBUG_REG30__pipe2_dr__SHIFT 0x00000002 11918#define VGT_DEBUG_REG30__pipe2_rtr_MASK 0x00000080L 11919#define VGT_DEBUG_REG30__pipe2_rtr__SHIFT 0x00000007 11920#define VGT_DEBUG_REG30__pipe4_dr_MASK 0x40000000L 11921#define VGT_DEBUG_REG30__pipe4_dr__SHIFT 0x0000001e 11922#define VGT_DEBUG_REG30__pipe4_rtr_MASK 0x80000000L 11923#define VGT_DEBUG_REG30__pipe4_rtr__SHIFT 0x0000001f 11924#define VGT_DEBUG_REG30__tf_fetch_state_q_MASK 0x00070000L 11925#define VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT 0x00000010 11926#define VGT_DEBUG_REG30__tf_pointer_p0_q_MASK 0x00f00000L 11927#define VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT 0x00000014 11928#define VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK 0x30000000L 11929#define VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT 0x0000001c 11930#define VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK 0x00000200L 11931#define VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT 0x00000009 11932#define VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK 0x00000100L 11933#define VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT 0x00000008 11934#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK 0x00000400L 11935#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT 0x0000000a 11936#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK 0x00000800L 11937#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT 0x0000000b 11938#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK 0x00001000L 11939#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT 0x0000000c 11940#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK 0x00002000L 11941#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT 0x0000000d 11942#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK 0x00004000L 11943#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT 0x0000000e 11944#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK 0x00008000L 11945#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT 0x0000000f 11946#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000L 11947#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x0000001f 11948#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000L 11949#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x0000001e 11950#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x00400000L 11951#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x00000016 11952#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x00800000L 11953#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x00000017 11954#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x00100000L 11955#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x00000014 11956#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x00200000L 11957#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x00000015 11958#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x02000000L 11959#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x00000019 11960#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000L 11961#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x0000001c 11962#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x04000000L 11963#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x0000001a 11964#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000L 11965#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x0000001d 11966#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x01000000L 11967#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x00000018 11968#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x08000000L 11969#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x0000001b 11970#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x00000001L 11971#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x00000000 11972#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x00000002L 11973#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x00000001 11974#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x00000008L 11975#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x00000003 11976#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x00000004L 11977#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x00000002 11978#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x00000020L 11979#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x00000005 11980#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x00002000L 11981#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0x0000000d 11982#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x00000010L 11983#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x00000004 11984#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x00001000L 11985#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0x0000000c 11986#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x00000080L 11987#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x00000007 11988#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x00008000L 11989#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0x0000000f 11990#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x00000040L 11991#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x00000006 11992#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x00004000L 11993#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0x0000000e 11994#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x00000200L 11995#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x00000009 11996#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x00020000L 11997#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x00000011 11998#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x00000100L 11999#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x00000008 12000#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x00010000L 12001#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x00000010 12002#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x00000800L 12003#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0x0000000b 12004#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x00080000L 12005#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x00000013 12006#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x00000400L 12007#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0x0000000a 12008#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x00040000L 12009#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x00000012 12010#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x00000100L 12011#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x00000008 12012#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x00000080L 12013#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x00000007 12014#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x08000000L 12015#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x0000001b 12016#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x00000400L 12017#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0x0000000a 12018#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x00000200L 12019#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x00000009 12020#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x00000001L 12021#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x00000000 12022#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x01000000L 12023#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x00000018 12024#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x02000000L 12025#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x00000019 12026#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x00000010L 12027#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x00000004 12028#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x00000004L 12029#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x00000002 12030#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x00000040L 12031#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x00000006 12032#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x00000800L 12033#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0x0000000b 12034#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x00000020L 12035#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x00000005 12036#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x00000008L 12037#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x00000003 12038#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x00000002L 12039#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x00000001 12040#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x04000000L 12041#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x0000001a 12042#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x00020000L 12043#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x00000011 12044#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x00010000L 12045#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x00000010 12046#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x00100000L 12047#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x00000014 12048#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x00040000L 12049#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x00000012 12050#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x00400000L 12051#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x00000016 12052#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x00200000L 12053#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x00000015 12054#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x00080000L 12055#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x00000013 12056#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x00800000L 12057#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x00000017 12058#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x00008000L 12059#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0x0000000f 12060#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x00004000L 12061#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0x0000000e 12062#define VGT_DEBUG_REG32__SPARE_MASK 0x80000000L 12063#define VGT_DEBUG_REG32__SPARE__SHIFT 0x0000001f 12064#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x00003000L 12065#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0x0000000c 12066#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x00040000L 12067#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x00000012 12068#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x00010000L 12069#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x00000010 12070#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000L 12071#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x0000001f 12072#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000L 12073#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x0000001e 12074#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000L 12075#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x0000001d 12076#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x00080000L 12077#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x00000013 12078#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x00020000L 12079#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x00000011 12080#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x00008000L 12081#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0x0000000f 12082#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x00100000L 12083#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x00000014 12084#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x00000001L 12085#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x00000000 12086#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x00000010L 12087#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x00000004 12088#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x00000004L 12089#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x00000002 12090#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x00001000L 12091#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0x0000000c 12092#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x00000008L 12093#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x00000003 12094#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x00000080L 12095#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x00000007 12096#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x00000100L 12097#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x00000008 12098#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x00000200L 12099#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x00000009 12100#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x00000800L 12101#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0x0000000b 12102#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x00000040L 12103#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x00000006 12104#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x00800000L 12105#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x00000017 12106#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x00000400L 12107#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0x0000000a 12108#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x00000020L 12109#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x00000005 12110#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x00400000L 12111#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x00000016 12112#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x00002000L 12113#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0x0000000d 12114#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x00000002L 12115#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x00000001 12116#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x00200000L 12117#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x00000015 12118#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000L 12119#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x0000001c 12120#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0x0c000000L 12121#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x0000001a 12122#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x03000000L 12123#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x00000018 12124#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x00004000L 12125#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0x0000000e 12126#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x00800000L 12127#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x00000017 12128#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x00400000L 12129#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x00000016 12130#define VGT_DEBUG_REG34__con_state_q_MASK 0x0000000fL 12131#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x00000000 12132#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x00010000L 12133#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x00000010 12134#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x00040000L 12135#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 12136#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x00100000L 12137#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x00000014 12138#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x00080000L 12139#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x00000013 12140#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x00020000L 12141#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x00000011 12142#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x01000000L 12143#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x00000018 12144#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L 12145#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 12146#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x00004000L 12147#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0x0000000e 12148#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x00008000L 12149#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0x0000000f 12150#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x00000200L 12151#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x00000009 12152#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x00001000L 12153#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0x0000000c 12154#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x00000100L 12155#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x00000008 12156#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x00000800L 12157#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0x0000000b 12158#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x00000400L 12159#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0x0000000a 12160#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000L 12161#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x0000001e 12162#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x08000000L 12163#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x0000001b 12164#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000L 12165#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x0000001c 12166#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x02000000L 12167#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x00000019 12168#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x04000000L 12169#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x0000001a 12170#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000L 12171#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x0000001d 12172#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x00002000L 12173#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0x0000000d 12174#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L 12175#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 12176#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x00000080L 12177#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x00000007 12178#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x00000020L 12179#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x00000005 12180#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x00000010L 12181#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x00000004 12182#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000L 12183#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x0000001f 12184#define VGT_DEBUG_REG35__event_flag_p1_q_MASK 0x00040000L 12185#define VGT_DEBUG_REG35__event_flag_p1_q__SHIFT 0x00000012 12186#define VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK 0x10000000L 12187#define VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT 0x0000001c 12188#define VGT_DEBUG_REG35__last_req_of_tg_p2_MASK 0x00000800L 12189#define VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT 0x0000000b 12190#define VGT_DEBUG_REG35__null_flag_p1_q_MASK 0x00080000L 12191#define VGT_DEBUG_REG35__null_flag_p1_q__SHIFT 0x00000013 12192#define VGT_DEBUG_REG35__pipe0_dr_MASK 0x00000001L 12193#define VGT_DEBUG_REG35__pipe0_dr__SHIFT 0x00000000 12194#define VGT_DEBUG_REG35__pipe0_rtr_MASK 0x00000004L 12195#define VGT_DEBUG_REG35__pipe0_rtr__SHIFT 0x00000002 12196#define VGT_DEBUG_REG35__pipe1_dr_MASK 0x00000002L 12197#define VGT_DEBUG_REG35__pipe1_dr__SHIFT 0x00000001 12198#define VGT_DEBUG_REG35__pipe1_rtr_MASK 0x00000008L 12199#define VGT_DEBUG_REG35__pipe1_rtr__SHIFT 0x00000003 12200#define VGT_DEBUG_REG35__second_tf_ret_data_q_MASK 0x08000000L 12201#define VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT 0x0000001b 12202#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK 0x0003f000L 12203#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT 0x0000000c 12204#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK 0x80000000L 12205#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT 0x0000001f 12206#define VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK 0x00000040L 12207#define VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT 0x00000006 12208#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK 0x07f00000L 12209#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT 0x00000014 12210#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK 0x00000080L 12211#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT 0x00000007 12212#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK 0x00000010L 12213#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT 0x00000004 12214#define VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK 0x00000020L 12215#define VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT 0x00000005 12216#define VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK 0x00000100L 12217#define VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT 0x00000008 12218#define VGT_DEBUG_REG35__tf_skid_fifo_full_MASK 0x00000200L 12219#define VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT 0x00000009 12220#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK 0x40000000L 12221#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT 0x0000001e 12222#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK 0x00000400L 12223#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT 0x0000000a 12224#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK 0x20000000L 12225#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT 0x0000001d 12226#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000L 12227#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x0000001a 12228#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x03fc0000L 12229#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x00000012 12230#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0x00000fffL 12231#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x00000000 12232#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x0003f000L 12233#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0x0000000c 12234#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000L 12235#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x00000018 12236#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000L 12237#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x0000001e 12238#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0x000000ffL 12239#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x00000000 12240#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0x00ffff00L 12241#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x00000008 12242#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000L 12243#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x0000001d 12244#define VGT_DEBUG_REG4__SPARE_MASK 0xffffffffL 12245#define VGT_DEBUG_REG4__SPARE__SHIFT 0x00000000 12246#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0x0000f800L 12247#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0x0000000b 12248#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0x000000f8L 12249#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x00000003 12250#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000L 12251#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x0000001b 12252#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0x00f80000L 12253#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x00000013 12254#define VGT_DEBUG_REG5__SPARE1_MASK 0x07000000L 12255#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x00000018 12256#define VGT_DEBUG_REG5__SPARE2_MASK 0x00070000L 12257#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x00000010 12258#define VGT_DEBUG_REG5__SPARE3_MASK 0x00000700L 12259#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x00000008 12260#define VGT_DEBUG_REG5__SPARE4_MASK 0x00000007L 12261#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x00000000 12262#define VGT_DEBUG_REG6__debug_BASE_MASK 0x0000ffffL 12263#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x00000000 12264#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000L 12265#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x00000010 12266#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x00000001L 12267#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x00000000 12268#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x00000002L 12269#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x00000001 12270#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x00000004L 12271#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x00000002 12272#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x00000008L 12273#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x00000003 12274#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x00000010L 12275#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x00000004 12276#define VGT_DEBUG_REG7__SPARE_MASK 0x0000ffe0L 12277#define VGT_DEBUG_REG7__SPARE__SHIFT 0x00000005 12278#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000L 12279#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x00000010 12280#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x00004000L 12281#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0x0000000e 12282#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x02000000L 12283#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x00000019 12284#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x00008000L 12285#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0x0000000f 12286#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x04000000L 12287#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x0000001a 12288#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x08000000L 12289#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x0000001b 12290#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x00020000L 12291#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x00000011 12292#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x00000020L 12293#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x00000005 12294#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x01000000L 12295#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x00000018 12296#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x00040000L 12297#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x00000012 12298#define VGT_DEBUG_REG8__r0_rtr_MASK 0x00000400L 12299#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0x0000000a 12300#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x00000004L 12301#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x00000002 12302#define VGT_DEBUG_REG8__r1_rtr_MASK 0x00000800L 12303#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0x0000000b 12304#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x00001000L 12305#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0x0000000c 12306#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x00800000L 12307#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x00000017 12308#define VGT_DEBUG_REG8__r2_rtr_MASK 0x00002000L 12309#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0x0000000d 12310#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x00000001L 12311#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x00000000 12312#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x00000002L 12313#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x00000001 12314#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x00000010L 12315#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x00000004 12316#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x00000008L 12317#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x00000003 12318#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000L 12319#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x0000001c 12320#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000L 12321#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x0000001d 12322#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000L 12323#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x0000001e 12324#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000L 12325#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x0000001f 12326#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x00200000L 12327#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x00000015 12328#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x00010000L 12329#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x00000010 12330#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x00100000L 12331#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x00000014 12332#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x00000040L 12333#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x00000006 12334#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x00000080L 12335#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x00000007 12336#define VGT_DEBUG_REG8__valid_r2_MASK 0x00000100L 12337#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x00000200L 12338#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x00000009 12339#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x00000008 12340#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x00400000L 12341#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x00000016 12342#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x00080000L 12343#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x00000013 12344#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x00000010L 12345#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x00000004 12346#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x00000020L 12347#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x00000005 12348#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x00000040L 12349#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x00000006 12350#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x02000000L 12351#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x00000019 12352#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x00000080L 12353#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x00000007 12354#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x00000008L 12355#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x00000003 12356#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x01000000L 12357#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x00000018 12358#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x00400000L 12359#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x00000016 12360#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x04000000L 12361#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x0000001a 12362#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x00040000L 12363#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x00000012 12364#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x00000400L 12365#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0x0000000a 12366#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x0003f800L 12367#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0x0000000b 12368#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x00380000L 12369#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x00000013 12370#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x00000003L 12371#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x00000000 12372#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x00800000L 12373#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x00000017 12374#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000L 12375#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x0000001f 12376#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x00000200L 12377#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x00000009 12378#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x00000100L 12379#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x00000008 12380#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x08000000L 12381#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x0000001b 12382#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000L 12383#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x0000001e 12384#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x00000004L 12385#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x00000002 12386#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000L 12387#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x0000001d 12388#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000L 12389#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x0000001c 12390#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL 12391#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 12392#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x000000ffL 12393#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x00000000 12394#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001ffL 12395#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x00000000 12396#define VGT_DMA_INDEX_TYPE__ATC_MASK 0x00000100L 12397#define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x00000008 12398#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L 12399#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x00000004 12400#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L 12401#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000 12402#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L 12403#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x00000009 12404#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x000000c0L 12405#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x00000006 12406#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L 12407#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0x0000000a 12408#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000cL 12409#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x00000002 12410#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffffL 12411#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x00000000 12412#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL 12413#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000 12414#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003fL 12415#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x00000000 12416#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffffL 12417#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x00000000 12418#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003fL 12419#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x00000000 12420#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000cL 12421#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x00000002 12422#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L 12423#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x00000005 12424#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L 12425#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000000 12426#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L 12427#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x00000004 12428#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L 12429#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x00000006 12430#define VGT_ENHANCE__MISC_MASK 0xffffffffL 12431#define VGT_ENHANCE__MISC__SHIFT 0x00000000 12432#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL 12433#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 12434#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL 12435#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x00000000 12436#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007ffL 12437#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x00000000 12438#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0fffffffL 12439#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x00000000 12440#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07fc0000L 12441#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x00000012 12442#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL 12443#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 12444#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L 12445#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x0000001b 12446#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003fff00L 12447#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x00000008 12448#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L 12449#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x00000007 12450#define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0xffc00000L 12451#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x00000016 12452#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007fL 12453#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x00000000 12454#define VGT_GROUP_DECR__DECR_MASK 0x0000000fL 12455#define VGT_GROUP_DECR__DECR__SHIFT 0x00000000 12456#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000fL 12457#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x00000000 12458#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L 12459#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x00000010 12460#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001fL 12461#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x00000000 12462#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L 12463#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0x0000000e 12464#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L 12465#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0x0000000f 12466#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L 12467#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x00000003 12468#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L 12469#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x00000000 12470#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L 12471#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x00000001 12472#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L 12473#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x00000002 12474#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00ff0000L 12475#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x00000010 12476#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000ff00L 12477#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x00000008 12478#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0f000000L 12479#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x00000018 12480#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000L 12481#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c 12482#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000fL 12483#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x00000000 12484#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000f0L 12485#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x00000004 12486#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000f00L 12487#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x00000008 12488#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L 12489#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c 12490#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000f0000L 12491#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x00000010 12492#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L 12493#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014 12494#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L 12495#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x00000003 12496#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L 12497#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x00000000 12498#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L 12499#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x00000001 12500#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L 12501#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x00000002 12502#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00ff0000L 12503#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x00000010 12504#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000ff00L 12505#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x00000008 12506#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0f000000L 12507#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x00000018 12508#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000L 12509#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c 12510#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000fL 12511#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x00000000 12512#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000f0L 12513#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x00000004 12514#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000f00L 12515#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x00000008 12516#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L 12517#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c 12518#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000f0000L 12519#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x00000010 12520#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L 12521#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014 12522#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001fcL 12523#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x00000002 12524#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L 12525#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x00000000 12526#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007ffL 12527#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x00000000 12528#define VGT_GS_MODE__COMPUTE_MODE_MASK 0x00004000L 12529#define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0x0000000e 12530#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L 12531#define VGT_GS_MODE__CUT_MODE__SHIFT 0x00000004 12532#define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x00010000L 12533#define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x00000010 12534#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L 12535#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0x0000000d 12536#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L 12537#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x00000013 12538#define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x00008000L 12539#define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0x0000000f 12540#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L 12541#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0x0000000b 12542#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L 12543#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x00000014 12544#define VGT_GS_MODE__MODE_MASK 0x00000007L 12545#define VGT_GS_MODE__MODE__SHIFT 0x00000000 12546#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L 12547#define VGT_GS_MODE__ONCHIP__SHIFT 0x00000015 12548#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L 12549#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x00000011 12550#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L 12551#define VGT_GS_MODE__RESERVED_0__SHIFT 0x00000003 12552#define VGT_GS_MODE__RESERVED_1_MASK 0x000007c0L 12553#define VGT_GS_MODE__RESERVED_1__SHIFT 0x00000006 12554#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L 12555#define VGT_GS_MODE__RESERVED_2__SHIFT 0x0000000c 12556#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L 12557#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x00000012 12558#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003f00L 12559#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x00000008 12560#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003f0000L 12561#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x00000010 12562#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0fc00000L 12563#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x00000016 12564#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003fL 12565#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x00000000 12566#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L 12567#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x0000001f 12568#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007ffL 12569#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x00000000 12570#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000fL 12571#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x00000000 12572#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001fL 12573#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x00000000 12574#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007fffL 12575#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x00000000 12576#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007fffL 12577#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x00000000 12578#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007fffL 12579#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x00000000 12580#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL 12581#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 12582#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL 12583#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 12584#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007fffL 12585#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x00000000 12586#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007fffL 12587#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x00000000 12588#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007fffL 12589#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x00000000 12590#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL 12591#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x00000000 12592#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L 12593#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x00000000 12594#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffffL 12595#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x00000000 12596#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffffL 12597#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x00000000 12598#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000ffL 12599#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x00000000 12600#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x0000007fL 12601#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x00000000 12602#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L 12603#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x00000009 12604#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL 12605#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 12606#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L 12607#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000 12608#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffffL 12609#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 12610#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffffL 12611#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x00000000 12612#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffffL 12613#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x00000000 12614#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L 12615#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 12616#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L 12617#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 12618#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003f00L 12619#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x00000008 12620#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000fc000L 12621#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0x0000000e 12622#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000ffL 12623#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x00000000 12624#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffffL 12625#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 12626#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x00000003L 12627#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x00000000 12628#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffffL 12629#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 12630#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L 12631#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x00000000 12632#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffffL 12633#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 12634#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffffL 12635#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x00000000 12636#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL 12637#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000 12638#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007fL 12639#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 12640#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L 12641#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x00000000 12642#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL 12643#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 12644#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL 12645#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 12646#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L 12647#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c 12648#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L 12649#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 12650#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL 12651#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 12652#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L 12653#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a 12654#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L 12655#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 12656#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L 12657#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 12658#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L 12659#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c 12660#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L 12661#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a 12662#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL 12663#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 12664#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL 12665#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 12666#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL 12667#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 12668#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L 12669#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c 12670#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L 12671#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 12672#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL 12673#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 12674#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L 12675#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a 12676#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L 12677#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 12678#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L 12679#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 12680#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L 12681#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c 12682#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L 12683#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a 12684#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL 12685#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 12686#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL 12687#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 12688#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL 12689#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 12690#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L 12691#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c 12692#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL 12693#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 12694#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL 12695#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 12696#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL 12697#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 12698#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L 12699#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c 12700#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL 12701#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 12702#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000ffL 12703#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x00000000 12704#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L 12705#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x00000001 12706#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L 12707#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x00000000 12708#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffffL 12709#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x00000000 12710#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003fL 12711#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x00000000 12712#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L 12713#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x00000000 12714#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x00000100L 12715#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x00000008 12716#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L 12717#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x00000003 12718#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L 12719#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x00000005 12720#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L 12721#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x00000002 12722#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L 12723#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x00000000 12724#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000c0L 12725#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x00000006 12726#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000fL 12727#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x00000000 12728#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000f0L 12729#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x00000004 12730#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000f00L 12731#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x00000008 12732#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000f000L 12733#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0x0000000c 12734#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffffL 12735#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x00000000 12736#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffffL 12737#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x00000000 12738#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffffL 12739#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x00000000 12740#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffffL 12741#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x00000000 12742#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffffL 12743#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x00000000 12744#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffffL 12745#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x00000000 12746#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffffL 12747#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x00000000 12748#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffffL 12749#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x00000000 12750#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffffL 12751#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x00000000 12752#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffffL 12753#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x00000000 12754#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffffL 12755#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x00000000 12756#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffffL 12757#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x00000000 12758#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L 12759#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000f00L 12760#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x00000008 12761#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x00000004 12762#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L 12763#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x00000000 12764#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L 12765#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x00000001 12766#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L 12767#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x00000002 12768#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L 12769#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x00000003 12770#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L 12771#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x0000001f 12772#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffffL 12773#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x00000000 12774#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffffL 12775#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x00000000 12776#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001ffL 12777#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x00000000 12778#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003ffL 12779#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x00000000 12780#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003ffL 12781#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x00000000 12782#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003ffL 12783#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x00000000 12784#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003ffL 12785#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x00000000 12786#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L 12787#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x00000007 12788#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L 12789#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x00000000 12790#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007eL 12791#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x00000001 12792#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffffL 12793#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x00000000 12794#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L 12795#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x00000009 12796#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L 12797#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0x0000000e 12798#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x00003c00L 12799#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0x0000000a 12800#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001cL 12801#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x00000002 12802#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00018000L 12803#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0x0000000f 12804#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L 12805#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x00000008 12806#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000e0L 12807#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x00000005 12808#define VGT_TF_PARAM__TYPE_MASK 0x00000003L 12809#define VGT_TF_PARAM__TYPE__SHIFT 0x00000000 12810#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000ffffL 12811#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x00000000 12812#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000ffL 12813#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 12814#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L 12815#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x00000000 12816#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x000003ffL 12817#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 12818#define WD_DEBUG_DATA__DATA_MASK 0xffffffffL 12819#define WD_DEBUG_DATA__DATA__SHIFT 0x00000000 12820 12821#endif
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