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dpcs_3_0_0_offset.h

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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_offset.h C
  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright (C) 2020 Advanced Micro Devices, Inc.
  4 *
  5 * Authors: AMD
  6 */
  7
  8#ifndef _dpcs_3_0_0_OFFSET_HEADER
  9#define _dpcs_3_0_0_OFFSET_HEADER
 10
 11
 12
 13// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
 14// base address: 0x0
 15#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL                                                                 0x2928
 16#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
 17#define mmDPCSTX0_DPCSTX_TX_CNTL                                                                       0x2929
 18#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX                                                              2
 19#define mmDPCSTX0_DPCSTX_CBUS_CNTL                                                                     0x292a
 20#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
 21#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL                                                                0x292b
 22#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
 23#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR                                                               0x292c
 24#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
 25#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA                                                               0x292d
 26#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
 27#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG                                                                  0x292e
 28#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
 29
 30
 31// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
 32// base address: 0x0
 33#define mmRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930
 34#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2
 35#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931
 36#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
 37#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932
 38#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
 39#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA                                                             0x2933
 40#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
 41#define mmRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934
 42#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
 43#define mmRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935
 44#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
 45#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936
 46#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
 47#define mmRDPCSTX0_RDPCSTX_SCRATCH                                                                     0x2937
 48#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX                                                            2
 49#define mmRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938
 50#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2
 51#define mmRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939
 52#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2
 53#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c
 54#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
 55#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG                                                                0x293d
 56#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
 57#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940
 58#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
 59#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
 60#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
 61#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942
 62#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
 63#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943
 64#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
 65#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944
 66#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
 67#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945
 68#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
 69#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946
 70#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
 71#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947
 72#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
 73#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948
 74#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
 75#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949
 76#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
 77#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a
 78#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
 79#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b
 80#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
 81#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c
 82#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
 83#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d
 84#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
 85#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e
 86#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
 87#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f
 88#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
 89#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950
 90#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
 91#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951
 92#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
 93#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952
 94#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
 95#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953
 96#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
 97#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2954
 98#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
 99#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2955
100#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
101#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG                                                           0x2956
102#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
103
104
105// addressBlock: dpcssys_dpcssys_cr0_dispdec
106// base address: 0x0
107#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934
108#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
109#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935
110#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2
111
112
113// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
114// base address: 0x360
115#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL                                                                 0x2a00
116#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
117#define mmDPCSTX1_DPCSTX_TX_CNTL                                                                       0x2a01
118#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX                                                              2
119#define mmDPCSTX1_DPCSTX_CBUS_CNTL                                                                     0x2a02
120#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
121#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL                                                                0x2a03
122#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
123#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR                                                               0x2a04
124#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
125#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA                                                               0x2a05
126#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
127#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG                                                                  0x2a06
128#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
129
130
131// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
132// base address: 0x360
133#define mmRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08
134#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2
135#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09
136#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
137#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a
138#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
139#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA                                                             0x2a0b
140#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
141#define mmRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c
142#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
143#define mmRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d
144#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
145#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e
146#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
147#define mmRDPCSTX1_RDPCSTX_SCRATCH                                                                     0x2a0f
148#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX                                                            2
149#define mmRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10
150#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2
151#define mmRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11
152#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2
153#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14
154#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
155#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG                                                                0x2a15
156#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
157#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18
158#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
159#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
160#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
161#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a
162#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
163#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b
164#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
165#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c
166#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
167#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d
168#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
169#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e
170#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
171#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f
172#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
173#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20
174#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
175#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21
176#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
177#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22
178#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
179#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23
180#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
181#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24
182#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
183#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25
184#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
185#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26
186#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
187#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27
188#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
189#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28
190#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
191#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29
192#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
193#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a
194#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
195#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b
196#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
197#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2a2c
198#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
199#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2a2d
200#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
201#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG                                                           0x2a2e
202#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
203
204
205// addressBlock: dpcssys_dpcssys_cr1_dispdec
206// base address: 0x360
207#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c
208#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
209#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d
210#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2
211
212
213// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
214// base address: 0x6c0
215#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL                                                                 0x2ad8
216#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
217#define mmDPCSTX2_DPCSTX_TX_CNTL                                                                       0x2ad9
218#define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX                                                              2
219#define mmDPCSTX2_DPCSTX_CBUS_CNTL                                                                     0x2ada
220#define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
221#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL                                                                0x2adb
222#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
223#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR                                                               0x2adc
224#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
225#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA                                                               0x2add
226#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
227#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG                                                                  0x2ade
228#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
229
230
231// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
232// base address: 0x6c0
233#define mmRDPCSTX2_RDPCSTX_CNTL                                                                        0x2ae0
234#define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX                                                               2
235#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL                                                                  0x2ae1
236#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
237#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL                                                           0x2ae2
238#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
239#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA                                                             0x2ae3
240#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
241#define mmRDPCSTX2_RDPCS_TX_CR_ADDR                                                                    0x2ae4
242#define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
243#define mmRDPCSTX2_RDPCS_TX_CR_DATA                                                                    0x2ae5
244#define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
245#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL                                                                  0x2ae6
246#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
247#define mmRDPCSTX2_RDPCSTX_SCRATCH                                                                     0x2ae7
248#define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX                                                            2
249#define mmRDPCSTX2_RDPCSTX_SPARE                                                                       0x2ae8
250#define mmRDPCSTX2_RDPCSTX_SPARE_BASE_IDX                                                              2
251#define mmRDPCSTX2_RDPCSTX_CNTL2                                                                       0x2ae9
252#define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX                                                              2
253#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2aec
254#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
255#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG                                                                0x2aed
256#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
257#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0                                                                   0x2af0
258#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
259#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1                                                                   0x2af1
260#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
261#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2                                                                   0x2af2
262#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
263#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3                                                                   0x2af3
264#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
265#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4                                                                   0x2af4
266#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
267#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5                                                                   0x2af5
268#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
269#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6                                                                   0x2af6
270#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
271#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7                                                                   0x2af7
272#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
273#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8                                                                   0x2af8
274#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
275#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9                                                                   0x2af9
276#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
277#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10                                                                  0x2afa
278#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
279#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11                                                                  0x2afb
280#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
281#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12                                                                  0x2afc
282#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
283#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13                                                                  0x2afd
284#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
285#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14                                                                  0x2afe
286#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
287#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0                                                                   0x2aff
288#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
289#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1                                                                   0x2b00
290#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
291#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2                                                                   0x2b01
292#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
293#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3                                                                   0x2b02
294#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
295#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL                                                               0x2b03
296#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
297#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2b04
298#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
299#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2b05
300#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
301#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG                                                           0x2b06
302#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
303
304
305// addressBlock: dpcssys_dpcssys_cr2_dispdec
306// base address: 0x6c0
307#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR                                                                  0x2ae4
308#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
309#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA                                                                  0x2ae5
310#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX                                                         2
311
312
313// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
314// base address: 0xa20
315#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL                                                                 0x2bb0
316#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
317#define mmDPCSTX3_DPCSTX_TX_CNTL                                                                       0x2bb1
318#define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX                                                              2
319#define mmDPCSTX3_DPCSTX_CBUS_CNTL                                                                     0x2bb2
320#define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
321#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL                                                                0x2bb3
322#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
323#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR                                                               0x2bb4
324#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
325#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA                                                               0x2bb5
326#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
327#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG                                                                  0x2bb6
328#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
329
330
331// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
332// base address: 0xa20
333#define mmRDPCSTX3_RDPCSTX_CNTL                                                                        0x2bb8
334#define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX                                                               2
335#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL                                                                  0x2bb9
336#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
337#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL                                                           0x2bba
338#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
339#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA                                                             0x2bbb
340#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
341#define mmRDPCSTX3_RDPCS_TX_CR_ADDR                                                                    0x2bbc
342#define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
343#define mmRDPCSTX3_RDPCS_TX_CR_DATA                                                                    0x2bbd
344#define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
345#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL                                                                  0x2bbe
346#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
347#define mmRDPCSTX3_RDPCSTX_SCRATCH                                                                     0x2bbf
348#define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX                                                            2
349#define mmRDPCSTX3_RDPCSTX_SPARE                                                                       0x2bc0
350#define mmRDPCSTX3_RDPCSTX_SPARE_BASE_IDX                                                              2
351#define mmRDPCSTX3_RDPCSTX_CNTL2                                                                       0x2bc1
352#define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX                                                              2
353#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2bc4
354#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
355#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG                                                                0x2bc5
356#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
357#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0                                                                   0x2bc8
358#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
359#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1                                                                   0x2bc9
360#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
361#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2                                                                   0x2bca
362#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
363#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3                                                                   0x2bcb
364#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
365#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4                                                                   0x2bcc
366#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
367#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5                                                                   0x2bcd
368#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
369#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6                                                                   0x2bce
370#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
371#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7                                                                   0x2bcf
372#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
373#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8                                                                   0x2bd0
374#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
375#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9                                                                   0x2bd1
376#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
377#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10                                                                  0x2bd2
378#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
379#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11                                                                  0x2bd3
380#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
381#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12                                                                  0x2bd4
382#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
383#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13                                                                  0x2bd5
384#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
385#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14                                                                  0x2bd6
386#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
387#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0                                                                   0x2bd7
388#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
389#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1                                                                   0x2bd8
390#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
391#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2                                                                   0x2bd9
392#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
393#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3                                                                   0x2bda
394#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
395#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL                                                               0x2bdb
396#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
397#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2bdc
398#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
399#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2bdd
400#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
401#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG                                                           0x2bde
402#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
403
404
405// addressBlock: dpcssys_dpcssys_cr3_dispdec
406// base address: 0xa20
407#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR                                                                  0x2bbc
408#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
409#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA                                                                  0x2bbd
410#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX                                                         2
411
412
413// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
414// base address: 0xd80
415#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL                                                                 0x2c88
416#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
417#define mmDPCSTX4_DPCSTX_TX_CNTL                                                                       0x2c89
418#define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX                                                              2
419#define mmDPCSTX4_DPCSTX_CBUS_CNTL                                                                     0x2c8a
420#define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
421#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL                                                                0x2c8b
422#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
423#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR                                                               0x2c8c
424#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
425#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA                                                               0x2c8d
426#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
427#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG                                                                  0x2c8e
428#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
429
430
431// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
432// base address: 0xd80
433#define mmRDPCSTX4_RDPCSTX_CNTL                                                                        0x2c90
434#define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX                                                               2
435#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL                                                                  0x2c91
436#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
437#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL                                                           0x2c92
438#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
439#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA                                                             0x2c93
440#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
441#define mmRDPCSTX4_RDPCS_TX_CR_ADDR                                                                    0x2c94
442#define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
443#define mmRDPCSTX4_RDPCS_TX_CR_DATA                                                                    0x2c95
444#define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
445#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL                                                                  0x2c96
446#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
447#define mmRDPCSTX4_RDPCSTX_SCRATCH                                                                     0x2c97
448#define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX                                                            2
449#define mmRDPCSTX4_RDPCSTX_SPARE                                                                       0x2c98
450#define mmRDPCSTX4_RDPCSTX_SPARE_BASE_IDX                                                              2
451#define mmRDPCSTX4_RDPCSTX_CNTL2                                                                       0x2c99
452#define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX                                                              2
453#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2c9c
454#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
455#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG                                                                0x2c9d
456#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
457#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0                                                                   0x2ca0
458#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
459#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1                                                                   0x2ca1
460#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
461#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2                                                                   0x2ca2
462#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
463#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3                                                                   0x2ca3
464#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
465#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4                                                                   0x2ca4
466#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
467#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5                                                                   0x2ca5
468#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
469#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6                                                                   0x2ca6
470#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
471#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7                                                                   0x2ca7
472#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
473#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8                                                                   0x2ca8
474#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
475#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9                                                                   0x2ca9
476#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
477#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10                                                                  0x2caa
478#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
479#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11                                                                  0x2cab
480#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
481#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12                                                                  0x2cac
482#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
483#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13                                                                  0x2cad
484#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
485#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14                                                                  0x2cae
486#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
487#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0                                                                   0x2caf
488#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
489#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1                                                                   0x2cb0
490#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
491#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2                                                                   0x2cb1
492#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
493#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3                                                                   0x2cb2
494#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
495#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL                                                               0x2cb3
496#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
497#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2cb4
498#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
499#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2cb5
500#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
501#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG                                                           0x2cb6
502#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
503
504
505// addressBlock: dpcssys_dpcssys_cr4_dispdec
506// base address: 0xd80
507#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR                                                                  0x2c94
508#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
509#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA                                                                  0x2c95
510#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX                                                         2
511
512
513// addressBlock: dpcssys_dpcs0_dpcstx5_dispdec
514// base address: 0x10e0
515#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL                                                                 0x2d60
516#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
517#define mmDPCSTX5_DPCSTX_TX_CNTL                                                                       0x2d61
518#define mmDPCSTX5_DPCSTX_TX_CNTL_BASE_IDX                                                              2
519#define mmDPCSTX5_DPCSTX_CBUS_CNTL                                                                     0x2d62
520#define mmDPCSTX5_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
521#define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL                                                                0x2d63
522#define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
523#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR                                                               0x2d64
524#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
525#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA                                                               0x2d65
526#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
527#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG                                                                  0x2d66
528#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
529
530
531// addressBlock: dpcssys_dpcs0_rdpcstx5_dispdec
532// base address: 0x10e0
533#define mmRDPCSTX5_RDPCSTX_CNTL                                                                        0x2d68
534#define mmRDPCSTX5_RDPCSTX_CNTL_BASE_IDX                                                               2
535#define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL                                                                  0x2d69
536#define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
537#define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL                                                           0x2d6a
538#define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
539#define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA                                                             0x2d6b
540#define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
541#define mmRDPCSTX5_RDPCS_TX_CR_ADDR                                                                    0x2d6c
542#define mmRDPCSTX5_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
543#define mmRDPCSTX5_RDPCS_TX_CR_DATA                                                                    0x2d6d
544#define mmRDPCSTX5_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
545#define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL                                                                  0x2d6e
546#define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
547#define mmRDPCSTX5_RDPCSTX_SCRATCH                                                                     0x2d6f
548#define mmRDPCSTX5_RDPCSTX_SCRATCH_BASE_IDX                                                            2
549#define mmRDPCSTX5_RDPCSTX_SPARE                                                                       0x2d70
550#define mmRDPCSTX5_RDPCSTX_SPARE_BASE_IDX                                                              2
551#define mmRDPCSTX5_RDPCSTX_CNTL2                                                                       0x2d71
552#define mmRDPCSTX5_RDPCSTX_CNTL2_BASE_IDX                                                              2
553#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2d74
554#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
555#define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG                                                                0x2d75
556#define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
557#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0                                                                   0x2d78
558#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
559#define mmRDPCSTX5_RDPCSTX_PHY_CNTL1                                                                   0x2d79
560#define mmRDPCSTX5_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
561#define mmRDPCSTX5_RDPCSTX_PHY_CNTL2                                                                   0x2d7a
562#define mmRDPCSTX5_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
563#define mmRDPCSTX5_RDPCSTX_PHY_CNTL3                                                                   0x2d7b
564#define mmRDPCSTX5_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
565#define mmRDPCSTX5_RDPCSTX_PHY_CNTL4                                                                   0x2d7c
566#define mmRDPCSTX5_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
567#define mmRDPCSTX5_RDPCSTX_PHY_CNTL5                                                                   0x2d7d
568#define mmRDPCSTX5_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
569#define mmRDPCSTX5_RDPCSTX_PHY_CNTL6                                                                   0x2d7e
570#define mmRDPCSTX5_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
571#define mmRDPCSTX5_RDPCSTX_PHY_CNTL7                                                                   0x2d7f
572#define mmRDPCSTX5_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
573#define mmRDPCSTX5_RDPCSTX_PHY_CNTL8                                                                   0x2d80
574#define mmRDPCSTX5_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
575#define mmRDPCSTX5_RDPCSTX_PHY_CNTL9                                                                   0x2d81
576#define mmRDPCSTX5_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
577#define mmRDPCSTX5_RDPCSTX_PHY_CNTL10                                                                  0x2d82
578#define mmRDPCSTX5_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
579#define mmRDPCSTX5_RDPCSTX_PHY_CNTL11                                                                  0x2d83
580#define mmRDPCSTX5_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
581#define mmRDPCSTX5_RDPCSTX_PHY_CNTL12                                                                  0x2d84
582#define mmRDPCSTX5_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
583#define mmRDPCSTX5_RDPCSTX_PHY_CNTL13                                                                  0x2d85
584#define mmRDPCSTX5_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
585#define mmRDPCSTX5_RDPCSTX_PHY_CNTL14                                                                  0x2d86
586#define mmRDPCSTX5_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
587#define mmRDPCSTX5_RDPCSTX_PHY_FUSE0                                                                   0x2d87
588#define mmRDPCSTX5_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
589#define mmRDPCSTX5_RDPCSTX_PHY_FUSE1                                                                   0x2d88
590#define mmRDPCSTX5_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
591#define mmRDPCSTX5_RDPCSTX_PHY_FUSE2                                                                   0x2d89
592#define mmRDPCSTX5_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
593#define mmRDPCSTX5_RDPCSTX_PHY_FUSE3                                                                   0x2d8a
594#define mmRDPCSTX5_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
595#define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL                                                               0x2d8b
596#define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
597#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2d8c
598#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
599#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2d8d
600#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
601#define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG                                                           0x2d8e
602#define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
603
604#endif
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