FILE
dpcs_2_0_3_offset.h
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_3_offset.h
1/* 2 * Copyright (C) 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 22#ifndef _dpcs_2_0_3_OFFSET_HEADER 23#define _dpcs_2_0_3_OFFSET_HEADER 24// addressBlock: dpcssysa_dpcs0_dpcstx0_dispdec 25// base address: 0x0 26#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928 27#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 28#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929 29#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2 30#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a 31#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2 32#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b 33#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 34#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c 35#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 36#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d 37#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 38 39 40// addressBlock: dpcssysa_dpcs0_rdpcstx0_dispdec 41// base address: 0x0 42#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930 43#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2 44#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931 45#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 46#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932 47#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 48#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933 49#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 50#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934 51#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2 52#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935 53#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2 54#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2939 55#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2 56#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 57#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 58#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 59#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2 60#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942 61#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2 62#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943 63#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2 64#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944 65#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2 66#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945 67#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2 68#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946 69#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2 70#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947 71#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2 72#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948 73#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2 74#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949 75#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2 76#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a 77#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2 78#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b 79#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2 80#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c 81#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2 82#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d 83#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2 84#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e 85#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2 86 87 88// addressBlock: dpcssysa_dpcs0_dpcstx1_dispdec 89// base address: 0x360 90#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00 91#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 92#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01 93#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2 94#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02 95#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2 96#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03 97#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 98#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04 99#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 100#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05 101#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 102 103 104// addressBlock: dpcssysa_dpcs0_rdpcstx1_dispdec 105// base address: 0x360 106#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08 107#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2 108#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09 109#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 110#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a 111#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 112#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b 113#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 114#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c 115#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2 116#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d 117#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2 118#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a11 119#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2 120#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 121#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 122#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 123#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2 124#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a 125#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2 126#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b 127#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2 128#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c 129#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2 130#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d 131#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2 132#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e 133#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2 134#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f 135#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2 136#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20 137#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2 138#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21 139#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2 140#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22 141#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 142#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23 143#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2 144#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24 145#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2 146#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25 147#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2 148#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26 149#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2 150 151#endif
~/
Read-only file preview.