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dcn_3_0_3_offset.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h
1// SPDX-License-Identifier: MIT 2/* 3 * Copyright (C) 2021 Advanced Micro Devices, Inc. 4 * 5 * Authors: AMD 6 */ 7 8#ifndef _dcn_3_0_3_OFFSET_HEADER 9#define _dcn_3_0_3_OFFSET_HEADER 10 11// addressBlock: dce_dc_mmhubbub_vga_dispdec 12// base address: 0x0 13#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 14#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 15#define mmVGA_MEM_READ_PAGE_ADDR 0x0001 16#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 17#define mmVGA_RENDER_CONTROL 0x0000 18#define mmVGA_RENDER_CONTROL_BASE_IDX 1 19#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001 20#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 21#define mmVGA_MODE_CONTROL 0x0002 22#define mmVGA_MODE_CONTROL_BASE_IDX 1 23#define mmVGA_SURFACE_PITCH_SELECT 0x0003 24#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 25#define mmVGA_MEMORY_BASE_ADDRESS 0x0004 26#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 27#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006 28#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 29#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008 30#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 31#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 32#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 33#define mmVGA_HDP_CONTROL 0x000a 34#define mmVGA_HDP_CONTROL_BASE_IDX 1 35#define mmVGA_CACHE_CONTROL 0x000b 36#define mmVGA_CACHE_CONTROL_BASE_IDX 1 37#define mmD1VGA_CONTROL 0x000c 38#define mmD1VGA_CONTROL_BASE_IDX 1 39#define mmD2VGA_CONTROL 0x000e 40#define mmD2VGA_CONTROL_BASE_IDX 1 41#define mmVGA_STATUS 0x0010 42#define mmVGA_STATUS_BASE_IDX 1 43#define mmVGA_INTERRUPT_CONTROL 0x0011 44#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1 45#define mmVGA_STATUS_CLEAR 0x0012 46#define mmVGA_STATUS_CLEAR_BASE_IDX 1 47#define mmVGA_INTERRUPT_STATUS 0x0013 48#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1 49#define mmVGA_MAIN_CONTROL 0x0014 50#define mmVGA_MAIN_CONTROL_BASE_IDX 1 51#define mmVGA_TEST_CONTROL 0x0015 52#define mmVGA_TEST_CONTROL_BASE_IDX 1 53#define mmVGA_QOS_CTRL 0x0018 54#define mmVGA_QOS_CTRL_BASE_IDX 1 55#define mmCRTC8_IDX 0x002d 56#define mmCRTC8_IDX_BASE_IDX 1 57#define mmCRTC8_DATA 0x002d 58#define mmCRTC8_DATA_BASE_IDX 1 59#define mmGENFC_WT 0x002e 60#define mmGENFC_WT_BASE_IDX 1 61#define mmGENS1 0x002e 62#define mmGENS1_BASE_IDX 1 63#define mmATTRDW 0x0030 64#define mmATTRDW_BASE_IDX 1 65#define mmATTRX 0x0030 66#define mmATTRX_BASE_IDX 1 67#define mmATTRDR 0x0030 68#define mmATTRDR_BASE_IDX 1 69#define mmGENMO_WT 0x0030 70#define mmGENMO_WT_BASE_IDX 1 71#define mmGENS0 0x0030 72#define mmGENS0_BASE_IDX 1 73#define mmGENENB 0x0030 74#define mmGENENB_BASE_IDX 1 75#define mmSEQ8_IDX 0x0031 76#define mmSEQ8_IDX_BASE_IDX 1 77#define mmSEQ8_DATA 0x0031 78#define mmSEQ8_DATA_BASE_IDX 1 79#define mmDAC_MASK 0x0031 80#define mmDAC_MASK_BASE_IDX 1 81#define mmDAC_R_INDEX 0x0031 82#define mmDAC_R_INDEX_BASE_IDX 1 83#define mmDAC_W_INDEX 0x0032 84#define mmDAC_W_INDEX_BASE_IDX 1 85#define mmDAC_DATA 0x0032 86#define mmDAC_DATA_BASE_IDX 1 87#define mmGENFC_RD 0x0032 88#define mmGENFC_RD_BASE_IDX 1 89#define mmGENMO_RD 0x0033 90#define mmGENMO_RD_BASE_IDX 1 91#define mmGRPH8_IDX 0x0033 92#define mmGRPH8_IDX_BASE_IDX 1 93#define mmGRPH8_DATA 0x0033 94#define mmGRPH8_DATA_BASE_IDX 1 95#define mmCRTC8_IDX_1 0x0035 96#define mmCRTC8_IDX_1_BASE_IDX 1 97#define mmCRTC8_DATA_1 0x0035 98#define mmCRTC8_DATA_1_BASE_IDX 1 99#define mmGENFC_WT_1 0x0036 100#define mmGENFC_WT_1_BASE_IDX 1 101#define mmGENS1_1 0x0036 102#define mmGENS1_1_BASE_IDX 1 103#define mmD3VGA_CONTROL 0x0038 104#define mmD3VGA_CONTROL_BASE_IDX 1 105#define mmD4VGA_CONTROL 0x0039 106#define mmD4VGA_CONTROL_BASE_IDX 1 107#define mmD5VGA_CONTROL 0x003a 108#define mmD5VGA_CONTROL_BASE_IDX 1 109#define mmD6VGA_CONTROL 0x003b 110#define mmD6VGA_CONTROL_BASE_IDX 1 111#define mmVGA_SOURCE_SELECT 0x003c 112#define mmVGA_SOURCE_SELECT_BASE_IDX 1 113 114 115// addressBlock: dce_dc_dccg_dccg_dispdec 116// base address: 0x0 117#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 118#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 119#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 120#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 121#define mmDP_DTO_DBUF_EN 0x0044 122#define mmDP_DTO_DBUF_EN_BASE_IDX 1 123#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 124#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 125#define mmREFCLK_CNTL 0x0049 126#define mmREFCLK_CNTL_BASE_IDX 1 127#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b 128#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 129#define mmDCCG_PERFMON_CNTL2 0x004e 130#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1 131#define mmDCCG_DS_DTO_INCR 0x0053 132#define mmDCCG_DS_DTO_INCR_BASE_IDX 1 133#define mmDCCG_DS_DTO_MODULO 0x0054 134#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1 135#define mmDCCG_DS_CNTL 0x0055 136#define mmDCCG_DS_CNTL_BASE_IDX 1 137#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056 138#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 139#define mmDPREFCLK_CNTL 0x0058 140#define mmDPREFCLK_CNTL_BASE_IDX 1 141#define mmDCE_VERSION 0x005e 142#define mmDCE_VERSION_BASE_IDX 1 143#define mmDCCG_GTC_CNTL 0x0060 144#define mmDCCG_GTC_CNTL_BASE_IDX 1 145#define mmDCCG_GTC_DTO_INCR 0x0061 146#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1 147#define mmDCCG_GTC_DTO_MODULO 0x0062 148#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 149#define mmDCCG_GTC_CURRENT 0x0063 150#define mmDCCG_GTC_CURRENT_BASE_IDX 1 151#define mmDSCCLK0_DTO_PARAM 0x006c 152#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1 153#define mmDSCCLK1_DTO_PARAM 0x006d 154#define mmDSCCLK1_DTO_PARAM_BASE_IDX 1 155#define mmMILLISECOND_TIME_BASE_DIV 0x0070 156#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 157#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 158#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 159#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 160#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 161#define mmDCCG_PERFMON_CNTL 0x0073 162#define mmDCCG_PERFMON_CNTL_BASE_IDX 1 163#define mmDCCG_GATE_DISABLE_CNTL 0x0074 164#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 165#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 166#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 167#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076 168#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 169#define mmDCCG_CAC_STATUS 0x0077 170#define mmDCCG_CAC_STATUS_BASE_IDX 1 171#define mmMICROSECOND_TIME_BASE_DIV 0x007b 172#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 173#define mmDCCG_GATE_DISABLE_CNTL2 0x007c 174#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 175#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d 176#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 177#define mmDCCG_DISP_CNTL_REG 0x007f 178#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1 179#define mmOTG0_PIXEL_RATE_CNTL 0x0080 180#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 181#define mmDP_DTO0_PHASE 0x0081 182#define mmDP_DTO0_PHASE_BASE_IDX 1 183#define mmDP_DTO0_MODULO 0x0082 184#define mmDP_DTO0_MODULO_BASE_IDX 1 185#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 186#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 187#define mmOTG1_PIXEL_RATE_CNTL 0x0084 188#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 189#define mmDP_DTO1_PHASE 0x0085 190#define mmDP_DTO1_PHASE_BASE_IDX 1 191#define mmDP_DTO1_MODULO 0x0086 192#define mmDP_DTO1_MODULO_BASE_IDX 1 193#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 194#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 195#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098 196#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 197#define mmDPPCLK0_DTO_PARAM 0x0099 198#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1 199#define mmDPPCLK1_DTO_PARAM 0x009a 200#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1 201#define mmDCCG_CAC_STATUS2 0x009f 202#define mmDCCG_CAC_STATUS2_BASE_IDX 1 203#define mmSYMCLKA_CLOCK_ENABLE 0x00a0 204#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 205#define mmSYMCLKB_CLOCK_ENABLE 0x00a1 206#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 207#define mmDCCG_SOFT_RESET 0x00a6 208#define mmDCCG_SOFT_RESET_BASE_IDX 1 209#define mmDSCCLK_DTO_CTRL 0x00a7 210#define mmDSCCLK_DTO_CTRL_BASE_IDX 1 211#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab 212#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 213#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac 214#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 215#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad 216#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 217#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae 218#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 219#define mmDCCG_AUDIO_DTO1_MODULE 0x00af 220#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 221#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 222#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 223#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 224#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 225#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 226#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 227#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 228#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 229#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 230#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 231#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 232#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 233#define mmDPPCLK_DTO_CTRL 0x00b6 234#define mmDPPCLK_DTO_CTRL_BASE_IDX 1 235#define mmDCCG_VSYNC_CNT_CTRL 0x00b8 236#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 237#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9 238#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 239#define mmFORCE_SYMCLK_DISABLE 0x00ba 240#define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1 241#define mmPHYASYMCLK_CLOCK_CNTL 0x0052 242#define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 243#define mmPHYBSYMCLK_CLOCK_CNTL 0x0053 244#define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 245 246 247// addressBlock: dce_dc_dccg_dccg_dfs_dispdec 248// base address: 0x0 249#define mmDENTIST_DISPCLK_CNTL 0x0064 250#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 251 252 253// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec 254// base address: 0x0 255#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 256#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 257#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 258#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 259#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002 260#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 261#define mmDC_PERFMON0_PERFMON_CNTL 0x0003 262#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 263#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004 264#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 265#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 266#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 267#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 268#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 269#define mmDC_PERFMON0_PERFMON_HI 0x0007 270#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2 271#define mmDC_PERFMON0_PERFMON_LOW 0x0008 272#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 273 274 275// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec 276// base address: 0x2f8 277#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x00be 278#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 279#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x00bf 280#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 281#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x00c0 282#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 283#define mmDC_PERFMON1_PERFMON_CNTL 0x00c1 284#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 285#define mmDC_PERFMON1_PERFMON_CNTL2 0x00c2 286#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 287#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x00c3 288#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 289#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x00c4 290#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 291#define mmDC_PERFMON1_PERFMON_HI 0x00c5 292#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2 293#define mmDC_PERFMON1_PERFMON_LOW 0x00c6 294#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 295 296 297// addressBlock: dce_dc_dmu_dmu_misc_dispdec 298// base address: 0x0 299#define mmCC_DC_PIPE_DIS 0x00ca 300#define mmCC_DC_PIPE_DIS_BASE_IDX 2 301#define mmDMU_CLK_CNTL 0x00cb 302#define mmDMU_CLK_CNTL_BASE_IDX 2 303#define mmDMU_MEM_PWR_CNTL 0x00cc 304#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2 305#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd 306#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 307#define mmSMU_INTERRUPT_CONTROL 0x00ce 308#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2 309#define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6 310#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 311 312 313// addressBlock: dce_dc_dmu_dmcu_dispdec 314// base address: 0x0 315#define mmDMCU_CTRL 0x00da 316#define mmDMCU_CTRL_BASE_IDX 2 317#define mmDMCU_STATUS 0x00db 318#define mmDMCU_STATUS_BASE_IDX 2 319#define mmDMCU_PC_START_ADDR 0x00dc 320#define mmDMCU_PC_START_ADDR_BASE_IDX 2 321#define mmDMCU_FW_START_ADDR 0x00dd 322#define mmDMCU_FW_START_ADDR_BASE_IDX 2 323#define mmDMCU_FW_END_ADDR 0x00de 324#define mmDMCU_FW_END_ADDR_BASE_IDX 2 325#define mmDMCU_FW_ISR_START_ADDR 0x00df 326#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2 327#define mmDMCU_FW_CS_HI 0x00e0 328#define mmDMCU_FW_CS_HI_BASE_IDX 2 329#define mmDMCU_FW_CS_LO 0x00e1 330#define mmDMCU_FW_CS_LO_BASE_IDX 2 331#define mmDMCU_RAM_ACCESS_CTRL 0x00e2 332#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 333#define mmDMCU_ERAM_WR_CTRL 0x00e3 334#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2 335#define mmDMCU_ERAM_WR_DATA 0x00e4 336#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2 337#define mmDMCU_ERAM_RD_CTRL 0x00e5 338#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2 339#define mmDMCU_ERAM_RD_DATA 0x00e6 340#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2 341#define mmDMCU_IRAM_WR_CTRL 0x00e7 342#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2 343#define mmDMCU_IRAM_WR_DATA 0x00e8 344#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2 345#define mmDMCU_IRAM_RD_CTRL 0x00e9 346#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2 347#define mmDMCU_IRAM_RD_DATA 0x00ea 348#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2 349#define mmDMCU_EVENT_TRIGGER 0x00eb 350#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2 351#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec 352#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 353#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed 354#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 355#define mmDMCU_INTERRUPT_STATUS 0x00ee 356#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2 357#define mmDMCU_INTERRUPT_STATUS_1 0x00ef 358#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 359#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 360#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 361#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 362#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 363#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 364#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 365#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 366#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 367#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 368#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 369#define mmDC_DMCU_SCRATCH 0x00f5 370#define mmDC_DMCU_SCRATCH_BASE_IDX 2 371#define mmDMCU_INT_CNT 0x00f6 372#define mmDMCU_INT_CNT_BASE_IDX 2 373#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 374#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 375#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8 376#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 377#define mmMASTER_COMM_DATA_REG1 0x00f9 378#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2 379#define mmMASTER_COMM_DATA_REG2 0x00fa 380#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2 381#define mmMASTER_COMM_DATA_REG3 0x00fb 382#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2 383#define mmMASTER_COMM_CMD_REG 0x00fc 384#define mmMASTER_COMM_CMD_REG_BASE_IDX 2 385#define mmMASTER_COMM_CNTL_REG 0x00fd 386#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2 387#define mmSLAVE_COMM_DATA_REG1 0x00fe 388#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2 389#define mmSLAVE_COMM_DATA_REG2 0x00ff 390#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2 391#define mmSLAVE_COMM_DATA_REG3 0x0100 392#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2 393#define mmSLAVE_COMM_CMD_REG 0x0101 394#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2 395#define mmSLAVE_COMM_CNTL_REG 0x0102 396#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2 397#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 398#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 399#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 400#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 401#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 402#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 403#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 404#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 405#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 406#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 407#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a 408#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 409#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b 410#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 411#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c 412#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 413#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d 414#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 415#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e 416#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 417#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f 418#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 419#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 420#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 421#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 422#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 423#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 424#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 425#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 426#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 427#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114 428#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 429#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 430#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 431#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 432#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 433#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 434#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 435#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a 436#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 437#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b 438#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 439#define mmDMCU_INT_CNT_CONTINUE 0x011c 440#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2 441#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d 442#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 443#define mmDMCU_INTERRUPT_STATUS_2 0x011e 444#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 445#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f 446#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 447 448 449// addressBlock: dce_dc_dmu_ihc_dispdec 450// base address: 0x0 451#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 452#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 453#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 454#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 455#define mmDC_GPU_TIMER_READ 0x0128 456#define mmDC_GPU_TIMER_READ_BASE_IDX 2 457#define mmDC_GPU_TIMER_READ_CNTL 0x0129 458#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 459#define mmDISP_INTERRUPT_STATUS 0x012a 460#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2 461#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b 462#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 463#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 464#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 465#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 466#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 467#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 468#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 469#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 470#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 471#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 472#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 473#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 474#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 475#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 476#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 477#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 478#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 479#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 480#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 481#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 482#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 483#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 484#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 485#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 486#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 487#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 488#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 489#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 490#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 491#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 492#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 493#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 494#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 495#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 496#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 497#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 498#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 499#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 500#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 501#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 502#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 503#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 504#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 505#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141 506#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 507#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142 508#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 509#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 510#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 511#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 512#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 513#define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 514#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 515#define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 516#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 517#define mmDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 518#define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 519#define mmDCCG_INTERRUPT_DEST 0x0148 520#define mmDCCG_INTERRUPT_DEST_BASE_IDX 2 521#define mmDMU_INTERRUPT_DEST 0x0149 522#define mmDMU_INTERRUPT_DEST_BASE_IDX 2 523#define mmDMU_INTERRUPT_DEST2 0x014a 524#define mmDMU_INTERRUPT_DEST2_BASE_IDX 2 525#define mmDCPG_INTERRUPT_DEST 0x014b 526#define mmDCPG_INTERRUPT_DEST_BASE_IDX 2 527#define mmDCPG_INTERRUPT_DEST2 0x014c 528#define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2 529#define mmMMHUBBUB_INTERRUPT_DEST 0x014d 530#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 531#define mmWB_INTERRUPT_DEST 0x014e 532#define mmWB_INTERRUPT_DEST_BASE_IDX 2 533#define mmDCHUB_INTERRUPT_DEST 0x014f 534#define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2 535#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 536#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 537#define mmDCHUB_INTERRUPT_DEST2 0x0151 538#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2 539#define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 540#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 541#define mmMPC_INTERRUPT_DEST 0x0153 542#define mmMPC_INTERRUPT_DEST_BASE_IDX 2 543#define mmOPP_INTERRUPT_DEST 0x0154 544#define mmOPP_INTERRUPT_DEST_BASE_IDX 2 545#define mmOPTC_INTERRUPT_DEST 0x0155 546#define mmOPTC_INTERRUPT_DEST_BASE_IDX 2 547#define mmOTG0_INTERRUPT_DEST 0x0156 548#define mmOTG0_INTERRUPT_DEST_BASE_IDX 2 549#define mmOTG1_INTERRUPT_DEST 0x0157 550#define mmOTG1_INTERRUPT_DEST_BASE_IDX 2 551#define mmOTG2_INTERRUPT_DEST 0x0158 552#define mmOTG2_INTERRUPT_DEST_BASE_IDX 2 553#define mmOTG3_INTERRUPT_DEST 0x0159 554#define mmOTG3_INTERRUPT_DEST_BASE_IDX 2 555#define mmOTG4_INTERRUPT_DEST 0x015a 556#define mmOTG4_INTERRUPT_DEST_BASE_IDX 2 557#define mmOTG5_INTERRUPT_DEST 0x015b 558#define mmOTG5_INTERRUPT_DEST_BASE_IDX 2 559#define mmDIG_INTERRUPT_DEST 0x015c 560#define mmDIG_INTERRUPT_DEST_BASE_IDX 2 561#define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015d 562#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 563#define mmDIO_INTERRUPT_DEST 0x015f 564#define mmDIO_INTERRUPT_DEST_BASE_IDX 2 565#define mmDCIO_INTERRUPT_DEST 0x0160 566#define mmDCIO_INTERRUPT_DEST_BASE_IDX 2 567#define mmHPD_INTERRUPT_DEST 0x0161 568#define mmHPD_INTERRUPT_DEST_BASE_IDX 2 569#define mmAZ_INTERRUPT_DEST 0x0162 570#define mmAZ_INTERRUPT_DEST_BASE_IDX 2 571#define mmAUX_INTERRUPT_DEST 0x0163 572#define mmAUX_INTERRUPT_DEST_BASE_IDX 2 573#define mmDSC_INTERRUPT_DEST 0x0164 574#define mmDSC_INTERRUPT_DEST_BASE_IDX 2 575 576 577// addressBlock: dce_dc_dmu_fgsec_dispdec 578// base address: 0x0 579#define mmDMCUB_RBBMIF_SEC_CNTL 0x017a 580#define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 581 582 583// addressBlock: dce_dc_dmu_rbbmif_dispdec 584// base address: 0x0 585#define mmRBBMIF_TIMEOUT 0x017f 586#define mmRBBMIF_TIMEOUT_BASE_IDX 2 587#define mmRBBMIF_STATUS 0x0180 588#define mmRBBMIF_STATUS_BASE_IDX 2 589#define mmRBBMIF_STATUS_2 0x0181 590#define mmRBBMIF_STATUS_2_BASE_IDX 2 591#define mmRBBMIF_INT_STATUS 0x0182 592#define mmRBBMIF_INT_STATUS_BASE_IDX 2 593#define mmRBBMIF_TIMEOUT_DIS 0x0183 594#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 595#define mmRBBMIF_TIMEOUT_DIS_2 0x0184 596#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 597#define mmRBBMIF_STATUS_FLAG 0x0185 598#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2 599 600 601// addressBlock: dce_dc_dmu_dmcub_dispdec 602// base address: 0x0 603#define mmDMCUB_REGION0_OFFSET 0x018e 604#define mmDMCUB_REGION0_OFFSET_BASE_IDX 2 605#define mmDMCUB_REGION0_OFFSET_HIGH 0x018f 606#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 607#define mmDMCUB_REGION1_OFFSET 0x0190 608#define mmDMCUB_REGION1_OFFSET_BASE_IDX 2 609#define mmDMCUB_REGION1_OFFSET_HIGH 0x0191 610#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 611#define mmDMCUB_REGION2_OFFSET 0x0192 612#define mmDMCUB_REGION2_OFFSET_BASE_IDX 2 613#define mmDMCUB_REGION2_OFFSET_HIGH 0x0193 614#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 615#define mmDMCUB_REGION4_OFFSET 0x0196 616#define mmDMCUB_REGION4_OFFSET_BASE_IDX 2 617#define mmDMCUB_REGION4_OFFSET_HIGH 0x0197 618#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 619#define mmDMCUB_REGION5_OFFSET 0x0198 620#define mmDMCUB_REGION5_OFFSET_BASE_IDX 2 621#define mmDMCUB_REGION5_OFFSET_HIGH 0x0199 622#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 623#define mmDMCUB_REGION6_OFFSET 0x019a 624#define mmDMCUB_REGION6_OFFSET_BASE_IDX 2 625#define mmDMCUB_REGION6_OFFSET_HIGH 0x019b 626#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 627#define mmDMCUB_REGION7_OFFSET 0x019c 628#define mmDMCUB_REGION7_OFFSET_BASE_IDX 2 629#define mmDMCUB_REGION7_OFFSET_HIGH 0x019d 630#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 631#define mmDMCUB_REGION0_TOP_ADDRESS 0x019e 632#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 633#define mmDMCUB_REGION1_TOP_ADDRESS 0x019f 634#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 635#define mmDMCUB_REGION2_TOP_ADDRESS 0x01a0 636#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 637#define mmDMCUB_REGION4_TOP_ADDRESS 0x01a1 638#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 639#define mmDMCUB_REGION5_TOP_ADDRESS 0x01a2 640#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 641#define mmDMCUB_REGION6_TOP_ADDRESS 0x01a3 642#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 643#define mmDMCUB_REGION7_TOP_ADDRESS 0x01a4 644#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 645#define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 646#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 647#define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 648#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 649#define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 650#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 651#define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 652#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 653#define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 654#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 655#define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 656#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 657#define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 658#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 659#define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 660#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 661#define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 662#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 663#define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 664#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 665#define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 666#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 667#define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 668#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 669#define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 670#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 671#define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 672#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 673#define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 674#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 675#define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 676#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 677#define mmDMCUB_REGION3_CW0_OFFSET 0x01b5 678#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 679#define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 680#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 681#define mmDMCUB_REGION3_CW1_OFFSET 0x01b7 682#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 683#define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 684#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 685#define mmDMCUB_REGION3_CW2_OFFSET 0x01b9 686#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 687#define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 688#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 689#define mmDMCUB_REGION3_CW3_OFFSET 0x01bb 690#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 691#define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 692#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 693#define mmDMCUB_REGION3_CW4_OFFSET 0x01bd 694#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 695#define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 696#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 697#define mmDMCUB_REGION3_CW5_OFFSET 0x01bf 698#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 699#define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 700#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 701#define mmDMCUB_REGION3_CW6_OFFSET 0x01c1 702#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 703#define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 704#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 705#define mmDMCUB_REGION3_CW7_OFFSET 0x01c3 706#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 707#define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 708#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 709#define mmDMCUB_INTERRUPT_ENABLE 0x01c5 710#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 711#define mmDMCUB_INTERRUPT_ACK 0x01c6 712#define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2 713#define mmDMCUB_INTERRUPT_STATUS 0x01c7 714#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2 715#define mmDMCUB_INTERRUPT_TYPE 0x01c8 716#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2 717#define mmDMCUB_EXT_INTERRUPT_STATUS 0x01c9 718#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 719#define mmDMCUB_EXT_INTERRUPT_CTXID 0x01ca 720#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 721#define mmDMCUB_EXT_INTERRUPT_ACK 0x01cb 722#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 723#define mmDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 724#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 725#define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 726#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 727#define mmDMCUB_SEC_CNTL 0x01ce 728#define mmDMCUB_SEC_CNTL_BASE_IDX 2 729#define mmDMCUB_MEM_CNTL 0x01cf 730#define mmDMCUB_MEM_CNTL_BASE_IDX 2 731#define mmDMCUB_INBOX0_BASE_ADDRESS 0x01d0 732#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 733#define mmDMCUB_INBOX0_SIZE 0x01d1 734#define mmDMCUB_INBOX0_SIZE_BASE_IDX 2 735#define mmDMCUB_INBOX0_WPTR 0x01d2 736#define mmDMCUB_INBOX0_WPTR_BASE_IDX 2 737#define mmDMCUB_INBOX0_RPTR 0x01d3 738#define mmDMCUB_INBOX0_RPTR_BASE_IDX 2 739#define mmDMCUB_INBOX1_BASE_ADDRESS 0x01d4 740#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 741#define mmDMCUB_INBOX1_SIZE 0x01d5 742#define mmDMCUB_INBOX1_SIZE_BASE_IDX 2 743#define mmDMCUB_INBOX1_WPTR 0x01d6 744#define mmDMCUB_INBOX1_WPTR_BASE_IDX 2 745#define mmDMCUB_INBOX1_RPTR 0x01d7 746#define mmDMCUB_INBOX1_RPTR_BASE_IDX 2 747#define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 748#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 749#define mmDMCUB_OUTBOX0_SIZE 0x01d9 750#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2 751#define mmDMCUB_OUTBOX0_WPTR 0x01da 752#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2 753#define mmDMCUB_OUTBOX0_RPTR 0x01db 754#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2 755#define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 756#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 757#define mmDMCUB_OUTBOX1_SIZE 0x01dd 758#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2 759#define mmDMCUB_OUTBOX1_WPTR 0x01de 760#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2 761#define mmDMCUB_OUTBOX1_RPTR 0x01df 762#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2 763#define mmDMCUB_TIMER_TRIGGER0 0x01e0 764#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2 765#define mmDMCUB_TIMER_TRIGGER1 0x01e1 766#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2 767#define mmDMCUB_TIMER_WINDOW 0x01e2 768#define mmDMCUB_TIMER_WINDOW_BASE_IDX 2 769#define mmDMCUB_SCRATCH0 0x01e3 770#define mmDMCUB_SCRATCH0_BASE_IDX 2 771#define mmDMCUB_SCRATCH1 0x01e4 772#define mmDMCUB_SCRATCH1_BASE_IDX 2 773#define mmDMCUB_SCRATCH2 0x01e5 774#define mmDMCUB_SCRATCH2_BASE_IDX 2 775#define mmDMCUB_SCRATCH3 0x01e6 776#define mmDMCUB_SCRATCH3_BASE_IDX 2 777#define mmDMCUB_SCRATCH4 0x01e7 778#define mmDMCUB_SCRATCH4_BASE_IDX 2 779#define mmDMCUB_SCRATCH5 0x01e8 780#define mmDMCUB_SCRATCH5_BASE_IDX 2 781#define mmDMCUB_SCRATCH6 0x01e9 782#define mmDMCUB_SCRATCH6_BASE_IDX 2 783#define mmDMCUB_SCRATCH7 0x01ea 784#define mmDMCUB_SCRATCH7_BASE_IDX 2 785#define mmDMCUB_SCRATCH8 0x01eb 786#define mmDMCUB_SCRATCH8_BASE_IDX 2 787#define mmDMCUB_SCRATCH9 0x01ec 788#define mmDMCUB_SCRATCH9_BASE_IDX 2 789#define mmDMCUB_SCRATCH10 0x01ed 790#define mmDMCUB_SCRATCH10_BASE_IDX 2 791#define mmDMCUB_SCRATCH11 0x01ee 792#define mmDMCUB_SCRATCH11_BASE_IDX 2 793#define mmDMCUB_SCRATCH12 0x01ef 794#define mmDMCUB_SCRATCH12_BASE_IDX 2 795#define mmDMCUB_SCRATCH13 0x01f0 796#define mmDMCUB_SCRATCH13_BASE_IDX 2 797#define mmDMCUB_SCRATCH14 0x01f1 798#define mmDMCUB_SCRATCH14_BASE_IDX 2 799#define mmDMCUB_SCRATCH15 0x01f2 800#define mmDMCUB_SCRATCH15_BASE_IDX 2 801#define mmDMCUB_CNTL 0x01f6 802#define mmDMCUB_CNTL_BASE_IDX 2 803#define mmDMCUB_GPINT_DATAIN0 0x01f7 804#define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2 805#define mmDMCUB_GPINT_DATAIN1 0x01f8 806#define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2 807#define mmDMCUB_GPINT_DATAOUT 0x01f9 808#define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2 809#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 810#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 811#define mmDMCUB_LS_WAKE_INT_ENABLE 0x01fb 812#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 813#define mmDMCUB_MEM_PWR_CNTL 0x01fc 814#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2 815#define mmDMCUB_TIMER_CURRENT 0x01fd 816#define mmDMCUB_TIMER_CURRENT_BASE_IDX 2 817#define mmDMCUB_PROC_ID 0x01ff 818#define mmDMCUB_PROC_ID_BASE_IDX 2 819 820 821// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec 822// base address: 0x0 823#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x0272 824#define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 825#define mmMCIF_WB_BUFMGR_STATUS 0x0274 826#define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 827#define mmMCIF_WB_BUF_PITCH 0x0275 828#define mmMCIF_WB_BUF_PITCH_BASE_IDX 2 829#define mmMCIF_WB_BUF_1_STATUS 0x0276 830#define mmMCIF_WB_BUF_1_STATUS_BASE_IDX 2 831#define mmMCIF_WB_BUF_1_STATUS2 0x0277 832#define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 833#define mmMCIF_WB_BUF_2_STATUS 0x0278 834#define mmMCIF_WB_BUF_2_STATUS_BASE_IDX 2 835#define mmMCIF_WB_BUF_2_STATUS2 0x0279 836#define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 837#define mmMCIF_WB_BUF_3_STATUS 0x027a 838#define mmMCIF_WB_BUF_3_STATUS_BASE_IDX 2 839#define mmMCIF_WB_BUF_3_STATUS2 0x027b 840#define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 841#define mmMCIF_WB_BUF_4_STATUS 0x027c 842#define mmMCIF_WB_BUF_4_STATUS_BASE_IDX 2 843#define mmMCIF_WB_BUF_4_STATUS2 0x027d 844#define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 845#define mmMCIF_WB_ARBITRATION_CONTROL 0x027e 846#define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 847#define mmMCIF_WB_SCLK_CHANGE 0x027f 848#define mmMCIF_WB_SCLK_CHANGE_BASE_IDX 2 849#define mmMCIF_WB_BUF_1_ADDR_Y 0x0282 850#define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 851#define mmMCIF_WB_BUF_1_ADDR_C 0x0284 852#define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 853#define mmMCIF_WB_BUF_2_ADDR_Y 0x0286 854#define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 855#define mmMCIF_WB_BUF_2_ADDR_C 0x0288 856#define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 857#define mmMCIF_WB_BUF_3_ADDR_Y 0x028a 858#define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 859#define mmMCIF_WB_BUF_3_ADDR_C 0x028c 860#define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 861#define mmMCIF_WB_BUF_4_ADDR_Y 0x028e 862#define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 863#define mmMCIF_WB_BUF_4_ADDR_C 0x0290 864#define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 865#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 866#define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 867#define mmMCIF_WB_NB_PSTATE_CONTROL 0x0293 868#define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 869#define mmMCIF_WB_CLOCK_GATER_CONTROL 0x0294 870#define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 871#define mmMCIF_WB_SELF_REFRESH_CONTROL 0x0296 872#define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 873#define mmMULTI_LEVEL_QOS_CTRL 0x0297 874#define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 875#define mmMCIF_WB_BUF_LUMA_SIZE 0x0299 876#define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 877#define mmMCIF_WB_BUF_CHROMA_SIZE 0x029a 878#define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 879#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 880#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 881#define mmMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 882#define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 883#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 884#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 885#define mmMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 886#define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 887#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 888#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 889#define mmMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 890#define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 891#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 892#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 893#define mmMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 894#define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 895#define mmMCIF_WB_BUF_1_RESOLUTION 0x02a3 896#define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 897#define mmMCIF_WB_BUF_2_RESOLUTION 0x02a4 898#define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 899#define mmMCIF_WB_BUF_3_RESOLUTION 0x02a5 900#define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 901#define mmMCIF_WB_BUF_4_RESOLUTION 0x02a6 902#define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 903#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7 904#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2 905#define mmMCIF_WB_VMID_CONTROL 0x02a8 906#define mmMCIF_WB_VMID_CONTROL_BASE_IDX 2 907#define mmMCIF_WB_MIN_TTO 0x02a9 908#define mmMCIF_WB_MIN_TTO_BASE_IDX 2 909 910 911// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec 912// base address: 0x0 913#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 914#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 915#define mmMCIF_WB_WATERMARK 0x02ab 916#define mmMCIF_WB_WATERMARK_BASE_IDX 2 917#define mmMMHUBBUB_WARMUP_CONFIG 0x02ac 918#define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 919#define mmMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 920#define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 921#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 922#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 923#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 924#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 925#define mmMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 926#define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 927#define mmMMHUBBUB_MIN_TTO 0x02b1 928#define mmMMHUBBUB_MIN_TTO_BASE_IDX 2 929#define mmWBIF_SMU_WM_CONTROL 0x0333 930#define mmWBIF_SMU_WM_CONTROL_BASE_IDX 2 931#define mmWBIF0_MISC_CTRL 0x0334 932#define mmWBIF0_MISC_CTRL_BASE_IDX 2 933#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335 934#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 935#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336 936#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 937#define mmVGA_SRC_SPLIT_CNTL 0x033d 938#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2 939#define mmMMHUBBUB_MEM_PWR_STATUS 0x033e 940#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 941#define mmMMHUBBUB_MEM_PWR_CNTL 0x033f 942#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 943#define mmMMHUBBUB_CLOCK_CNTL 0x0340 944#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 945#define mmMMHUBBUB_SOFT_RESET 0x0341 946#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2 947#define mmDMU_IF_ERR_STATUS 0x0345 948#define mmDMU_IF_ERR_STATUS_BASE_IDX 2 949#define mmMMHUBBUB_CLIENT_UNIT_ID 0x0346 950#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 951#define mmMMHUBBUB_WARMUP_VMID_CONTROL 0x0348 952#define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 953 954 955// addressBlock: dce_dc_mmhubbub_vgaif_dispdec 956// base address: 0x0 957#define mmMCIF_CONTROL 0x034a 958#define mmMCIF_CONTROL_BASE_IDX 2 959#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b 960#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 961#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e 962#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 963#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f 964#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 965#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 966#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 967 968 969// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec 970// base address: 0xd48 971#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x0352 972#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 973#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x0353 974#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 975#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x0354 976#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 977#define mmDC_PERFMON2_PERFMON_CNTL 0x0355 978#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 979#define mmDC_PERFMON2_PERFMON_CNTL2 0x0356 980#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 981#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x0357 982#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 983#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x0358 984#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 985#define mmDC_PERFMON2_PERFMON_HI 0x0359 986#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2 987#define mmDC_PERFMON2_PERFMON_LOW 0x035a 988#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 989 990 991// addressBlock: dce_dc_hda_azf0stream0_dispdec 992// base address: 0x0 993#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 994#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 995#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 996#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 997 998 999// addressBlock: dce_dc_hda_azf0stream1_dispdec 1000// base address: 0x8 1001#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 1002#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 1003#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 1004#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 1005 1006 1007// addressBlock: dce_dc_hda_azf0stream2_dispdec 1008// base address: 0x10 1009#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 1010#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 1011#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 1012#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 1013 1014 1015// addressBlock: dce_dc_hda_azf0stream3_dispdec 1016// base address: 0x18 1017#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 1018#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 1019#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 1020#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 1021 1022 1023// addressBlock: dce_dc_hda_azf0stream4_dispdec 1024// base address: 0x20 1025#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 1026#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 1027#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 1028#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 1029 1030 1031// addressBlock: dce_dc_hda_azf0stream5_dispdec 1032// base address: 0x28 1033#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 1034#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 1035#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 1036#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 1037 1038 1039// addressBlock: dce_dc_hda_azf0stream6_dispdec 1040// base address: 0x30 1041#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 1042#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 1043#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 1044#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 1045 1046 1047// addressBlock: dce_dc_hda_azf0stream7_dispdec 1048// base address: 0x38 1049#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 1050#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 1051#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 1052#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 1053 1054 1055// addressBlock: dce_dc_hda_az_misc_dispdec 1056// base address: 0x0 1057#define mmAZ_CLOCK_CNTL 0x0372 1058#define mmAZ_CLOCK_CNTL_BASE_IDX 2 1059 1060 1061// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec 1062// base address: 0xde8 1063#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x037a 1064#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 1065#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x037b 1066#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 1067#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x037c 1068#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 1069#define mmDC_PERFMON3_PERFMON_CNTL 0x037d 1070#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 1071#define mmDC_PERFMON3_PERFMON_CNTL2 0x037e 1072#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 1073#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x037f 1074#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1075#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0380 1076#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 1077#define mmDC_PERFMON3_PERFMON_HI 0x0381 1078#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2 1079#define mmDC_PERFMON3_PERFMON_LOW 0x0382 1080#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 1081 1082 1083// addressBlock: dce_dc_hda_azf0endpoint0_dispdec 1084// base address: 0x0 1085#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 1086#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1087#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 1088#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1089 1090 1091// addressBlock: dce_dc_hda_azf0endpoint1_dispdec 1092// base address: 0x18 1093#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 1094#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1095#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 1096#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1097 1098 1099// addressBlock: dce_dc_hda_azf0endpoint2_dispdec 1100// base address: 0x30 1101#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 1102#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1103#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 1104#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1105 1106 1107// addressBlock: dce_dc_hda_azf0endpoint3_dispdec 1108// base address: 0x48 1109#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 1110#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1111#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 1112#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1113 1114 1115// addressBlock: dce_dc_hda_azf0endpoint4_dispdec 1116// base address: 0x60 1117#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 1118#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1119#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 1120#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1121 1122 1123// addressBlock: dce_dc_hda_azf0endpoint5_dispdec 1124// base address: 0x78 1125#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 1126#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1127#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 1128#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1129 1130 1131// addressBlock: dce_dc_hda_azf0endpoint6_dispdec 1132// base address: 0x90 1133#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 1134#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1135#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 1136#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1137 1138 1139// addressBlock: dce_dc_hda_azf0endpoint7_dispdec 1140// base address: 0xa8 1141#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 1142#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1143#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 1144#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1145 1146 1147// addressBlock: dce_dc_hda_azf0controller_dispdec 1148// base address: 0x0 1149#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 1150#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 1151#define mmAZALIA_AUDIO_DTO 0x03c3 1152#define mmAZALIA_AUDIO_DTO_BASE_IDX 2 1153#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4 1154#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 1155#define mmAZALIA_SOCCLK_CONTROL 0x03c5 1156#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 1157#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 1158#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 1159#define mmAZALIA_DATA_DMA_CONTROL 0x03c7 1160#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 1161#define mmAZALIA_BDL_DMA_CONTROL 0x03c8 1162#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 1163#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9 1164#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 1165#define mmAZALIA_CORB_DMA_CONTROL 0x03ca 1166#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 1167#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 1168#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 1169#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 1170#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 1171#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3 1172#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 1173#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 1174#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1175#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 1176#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 1177#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 1178#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1179#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9 1180#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 1181#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da 1182#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 1183#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db 1184#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 1185#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc 1186#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 1187#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd 1188#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 1189#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de 1190#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 1191#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df 1192#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 1193#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0 1194#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 1195#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1 1196#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 1197#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2 1198#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 1199#define mmAZALIA_CRC0_CONTROL0 0x03e3 1200#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2 1201#define mmAZALIA_CRC0_CONTROL1 0x03e4 1202#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2 1203#define mmAZALIA_CRC0_CONTROL2 0x03e5 1204#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2 1205#define mmAZALIA_CRC0_CONTROL3 0x03e6 1206#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2 1207#define mmAZALIA_CRC0_RESULT 0x03e7 1208#define mmAZALIA_CRC0_RESULT_BASE_IDX 2 1209#define mmAZALIA_CRC1_CONTROL0 0x03e8 1210#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2 1211#define mmAZALIA_CRC1_CONTROL1 0x03e9 1212#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2 1213#define mmAZALIA_CRC1_CONTROL2 0x03ea 1214#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2 1215#define mmAZALIA_CRC1_CONTROL3 0x03eb 1216#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2 1217#define mmAZALIA_CRC1_RESULT 0x03ec 1218#define mmAZALIA_CRC1_RESULT_BASE_IDX 2 1219#define mmAZALIA_MEM_PWR_CTRL 0x03ee 1220#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 1221#define mmAZALIA_MEM_PWR_STATUS 0x03ef 1222#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 1223 1224 1225// addressBlock: dce_dc_hda_azf0root_dispdec 1226// base address: 0x0 1227#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 1228#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 1229#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 1230#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 1231#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 1232#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 1233#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 1234#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 1235#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 1236#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 1237#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 1238#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 1239#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 1240#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 1241#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 1242#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 1243#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 1244#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 1245#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 1246#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 1247#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 1248#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 1249#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 1250#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 1251#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 1252#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1253#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 1254#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1255#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 1256#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 1257#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 1258#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 1259#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 1260#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 1261#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 1262#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 1263#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 1264#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 1265#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 1266#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 1267#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 1268#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 1269#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 1270#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1271#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 1272#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1273 1274 1275// addressBlock: dce_dc_hda_azf0stream8_dispdec 1276// base address: 0x320 1277#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 1278#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 1279#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 1280#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 1281 1282 1283// addressBlock: dce_dc_hda_azf0stream9_dispdec 1284// base address: 0x328 1285#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 1286#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 1287#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 1288#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 1289 1290 1291// addressBlock: dce_dc_hda_azf0stream10_dispdec 1292// base address: 0x330 1293#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 1294#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 1295#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 1296#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 1297 1298 1299// addressBlock: dce_dc_hda_azf0stream11_dispdec 1300// base address: 0x338 1301#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 1302#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 1303#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 1304#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 1305 1306 1307// addressBlock: dce_dc_hda_azf0stream12_dispdec 1308// base address: 0x340 1309#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 1310#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 1311#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 1312#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 1313 1314 1315// addressBlock: dce_dc_hda_azf0stream13_dispdec 1316// base address: 0x348 1317#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 1318#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 1319#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 1320#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 1321 1322 1323// addressBlock: dce_dc_hda_azf0stream14_dispdec 1324// base address: 0x350 1325#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 1326#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 1327#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 1328#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 1329 1330 1331// addressBlock: dce_dc_hda_azf0stream15_dispdec 1332// base address: 0x358 1333#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 1334#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 1335#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 1336#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 1337 1338 1339// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 1340// base address: 0x0 1341#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 1342#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1343#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 1344#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1345 1346 1347// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 1348// base address: 0x10 1349#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 1350#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1351#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 1352#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1353 1354 1355// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec 1356// base address: 0x20 1357#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 1358#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1359#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 1360#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1361 1362 1363// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec 1364// base address: 0x30 1365#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 1366#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1367#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 1368#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1369 1370 1371// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec 1372// base address: 0x40 1373#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 1374#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1375#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 1376#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1377 1378 1379// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec 1380// base address: 0x50 1381#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 1382#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1383#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 1384#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1385 1386 1387// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec 1388// base address: 0x60 1389#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 1390#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1391#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 1392#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1393 1394 1395// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec 1396// base address: 0x70 1397#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 1398#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1399#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 1400#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1401 1402 1403// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec 1404// base address: 0x0 1405#define mmDCHUBBUB_SDPIF_CFG0 0x048f 1406#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 1407#define mmVM_REQUEST_PHYSICAL 0x0490 1408#define mmVM_REQUEST_PHYSICAL_BASE_IDX 2 1409#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491 1410#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 1411#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492 1412#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 1413#define mmDCN_VM_FB_LOCATION_BASE 0x0493 1414#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 1415#define mmDCN_VM_FB_LOCATION_TOP 0x0494 1416#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 1417#define mmDCN_VM_FB_OFFSET 0x0495 1418#define mmDCN_VM_FB_OFFSET_BASE_IDX 2 1419#define mmDCN_VM_AGP_BOT 0x0496 1420#define mmDCN_VM_AGP_BOT_BASE_IDX 2 1421#define mmDCN_VM_AGP_TOP 0x0497 1422#define mmDCN_VM_AGP_TOP_BASE_IDX 2 1423#define mmDCN_VM_AGP_BASE 0x0498 1424#define mmDCN_VM_AGP_BASE_BASE_IDX 2 1425#define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499 1426#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 1427#define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a 1428#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 1429#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b 1430#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 1431#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba 1432#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 1433#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb 1434#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 1435#define mmDCHUBBUB_SDPIF_CFG1 0x04bf 1436#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 1437#define mmDCHUBBUB_SDPIF_CFG2 0x04c0 1438#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 1439 1440 1441// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec 1442// base address: 0x0 1443#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf 1444#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 1445#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0 1446#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 1447#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1 1448#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 1449#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2 1450#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 1451#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3 1452#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 1453#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4 1454#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 1455#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5 1456#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 1457#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6 1458#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 1459#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7 1460#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 1461#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef 1462#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 1463#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0 1464#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 1465#define mmDCHUBBUB_CRC_CTRL 0x04f1 1466#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2 1467#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2 1468#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 1469#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3 1470#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 1471#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4 1472#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 1473#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5 1474#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 1475 1476 1477// addressBlock: dce_dc_dchubbub_hubbub_dispdec 1478// base address: 0x0 1479#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505 1480#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 1481#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506 1482#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 1483#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507 1484#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 1485#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508 1486#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 1487#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509 1488#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 1489#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x050a 1490#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 1491#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b 1492#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 1493#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c 1494#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 1495#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d 1496#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 1497#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e 1498#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 1499#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050f 1500#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 1501#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510 1502#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 1503#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511 1504#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 1505#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512 1506#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 1507#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513 1508#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 1509#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0514 1510#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 1511#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515 1512#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 1513#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516 1514#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 1515#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517 1516#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 1517#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 1518#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 1519#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 1520#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 1521#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a 1522#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 1523#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b 1524#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 1525#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c 1526#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 1527#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d 1528#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 1529#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e 1530#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 1531#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f 1532#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 1533#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520 1534#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 1535#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521 1536#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 1537#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522 1538#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 1539#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523 1540#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 1541#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524 1542#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 1543#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525 1544#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 1545#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526 1546#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 1547#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527 1548#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 1549#define mmVTG0_CONTROL 0x0528 1550#define mmVTG0_CONTROL_BASE_IDX 2 1551#define mmVTG1_CONTROL 0x0529 1552#define mmVTG1_CONTROL_BASE_IDX 2 1553#define mmDCHUBBUB_SOFT_RESET 0x052e 1554#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2 1555#define mmDCHUBBUB_CLOCK_CNTL 0x052f 1556#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 1557#define mmDCFCLK_CNTL 0x0530 1558#define mmDCFCLK_CNTL_BASE_IDX 2 1559#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531 1560#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 1561#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532 1562#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 1563#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533 1564#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 1565#define mmDCHUBBUB_CTRL_STATUS 0x0534 1566#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2 1567#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a 1568#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 1569#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b 1570#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 1571#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c 1572#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 1573#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d 1574#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 1575#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e 1576#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 1577#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x053f 1578#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 1579#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0540 1580#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 1581#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0541 1582#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 1583#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0542 1584#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 1585#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0543 1586#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 1587#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0544 1588#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 1589#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0545 1590#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 1591#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0546 1592#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 1593#define mmFMON_CTRL 0x0548 1594#define mmFMON_CTRL_BASE_IDX 2 1595#define mmFMON_CTRL_1 0x0548 1596#define mmFMON_CTRL_1_BASE_IDX 2 1597 1598 1599// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec 1600// base address: 0x1534 1601#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x054d 1602#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 1603#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x054e 1604#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 1605#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x054f 1606#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 1607#define mmDC_PERFMON4_PERFMON_CNTL 0x0550 1608#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 1609#define mmDC_PERFMON4_PERFMON_CNTL2 0x0551 1610#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 1611#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0552 1612#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1613#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0553 1614#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 1615#define mmDC_PERFMON4_PERFMON_HI 0x0554 1616#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2 1617#define mmDC_PERFMON4_PERFMON_LOW 0x0555 1618#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 1619 1620 1621// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec 1622// base address: 0x0 1623#define mmDCN_VM_CONTEXT0_CNTL 0x0559 1624#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 1625#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 1626#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1627#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 1628#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1629#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 1630#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1631#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 1632#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1633#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 1634#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1635#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 1636#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1637#define mmDCN_VM_CONTEXT1_CNTL 0x0560 1638#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 1639#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 1640#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1641#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 1642#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1643#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 1644#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1645#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 1646#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1647#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 1648#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1649#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 1650#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1651#define mmDCN_VM_CONTEXT2_CNTL 0x0567 1652#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 1653#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 1654#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1655#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 1656#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1657#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 1658#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1659#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 1660#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1661#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 1662#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1663#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 1664#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1665#define mmDCN_VM_CONTEXT3_CNTL 0x056e 1666#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 1667#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 1668#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1669#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 1670#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1671#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 1672#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1673#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 1674#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1675#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 1676#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1677#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 1678#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1679#define mmDCN_VM_CONTEXT4_CNTL 0x0575 1680#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 1681#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 1682#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1683#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 1684#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1685#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 1686#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1687#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 1688#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1689#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 1690#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1691#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 1692#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1693#define mmDCN_VM_CONTEXT5_CNTL 0x057c 1694#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 1695#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 1696#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1697#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 1698#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1699#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 1700#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1701#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 1702#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1703#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 1704#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1705#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 1706#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1707#define mmDCN_VM_CONTEXT6_CNTL 0x0583 1708#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 1709#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 1710#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1711#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 1712#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1713#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 1714#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1715#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 1716#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1717#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 1718#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1719#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 1720#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1721#define mmDCN_VM_CONTEXT7_CNTL 0x058a 1722#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 1723#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 1724#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1725#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 1726#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1727#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 1728#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1729#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 1730#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1731#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 1732#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1733#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 1734#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1735#define mmDCN_VM_CONTEXT8_CNTL 0x0591 1736#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 1737#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 1738#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1739#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 1740#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1741#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 1742#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1743#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 1744#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1745#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 1746#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1747#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 1748#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1749#define mmDCN_VM_CONTEXT9_CNTL 0x0598 1750#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 1751#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 1752#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1753#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 1754#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1755#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 1756#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1757#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 1758#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1759#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 1760#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1761#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 1762#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1763#define mmDCN_VM_CONTEXT10_CNTL 0x059f 1764#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 1765#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 1766#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1767#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 1768#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1769#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 1770#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1771#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 1772#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1773#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 1774#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1775#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 1776#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1777#define mmDCN_VM_CONTEXT11_CNTL 0x05a6 1778#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 1779#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 1780#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1781#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 1782#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1783#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 1784#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1785#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 1786#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1787#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 1788#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1789#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 1790#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1791#define mmDCN_VM_CONTEXT12_CNTL 0x05ad 1792#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 1793#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 1794#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1795#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 1796#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1797#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 1798#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1799#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 1800#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1801#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 1802#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1803#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 1804#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1805#define mmDCN_VM_CONTEXT13_CNTL 0x05b4 1806#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 1807#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 1808#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1809#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 1810#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1811#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 1812#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1813#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 1814#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1815#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 1816#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1817#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 1818#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1819#define mmDCN_VM_CONTEXT14_CNTL 0x05bb 1820#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 1821#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 1822#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1823#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 1824#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1825#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 1826#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1827#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 1828#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1829#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 1830#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1831#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 1832#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1833#define mmDCN_VM_CONTEXT15_CNTL 0x05c2 1834#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 1835#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 1836#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1837#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 1838#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1839#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 1840#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1841#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 1842#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1843#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 1844#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1845#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 1846#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1847#define mmDCN_VM_DEFAULT_ADDR_MSB 0x05c9 1848#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 1849#define mmDCN_VM_DEFAULT_ADDR_LSB 0x05ca 1850#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 1851#define mmDCN_VM_FAULT_CNTL 0x05cb 1852#define mmDCN_VM_FAULT_CNTL_BASE_IDX 2 1853#define mmDCN_VM_FAULT_STATUS 0x05cc 1854#define mmDCN_VM_FAULT_STATUS_BASE_IDX 2 1855#define mmDCN_VM_FAULT_ADDR_MSB 0x05cd 1856#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 1857#define mmDCN_VM_FAULT_ADDR_LSB 0x05ce 1858#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 1859 1860 1861// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 1862// base address: 0x0 1863#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 1864#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 1865#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6 1866#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 1867#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7 1868#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 1869#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 1870#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 1871#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 1872#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 1873#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 1874#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 1875#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 1876#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 1877#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 1878#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 1879#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 1880#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 1881#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 1882#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 1883#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 1884#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 1885#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 1886#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 1887#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 1888#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 1889#define mmHUBP0_DCHUBP_CNTL 0x05f3 1890#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2 1891#define mmHUBP0_HUBP_CLK_CNTL 0x05f4 1892#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 1893#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 1894#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 1895#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6 1896#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 1897#define mmHUBP0_HUBPREQ_DEBUG 0x05f7 1898#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 1899#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb 1900#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 1901#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc 1902#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 1903 1904 1905// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 1906// base address: 0x0 1907#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 1908#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 1909#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 1910#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 1911#define mmHUBPREQ0_VMID_SETTINGS_0 0x0609 1912#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 1913#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 1914#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 1915#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 1916#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 1917#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 1918#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 1919#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 1920#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 1921#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 1922#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 1923#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 1924#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 1925#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 1926#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 1927#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 1928#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 1929#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 1930#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 1931#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 1932#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 1933#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 1934#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 1935#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 1936#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 1937#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 1938#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 1939#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 1940#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 1941#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 1942#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 1943#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 1944#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 1945#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 1946#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 1947#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 1948#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 1949#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 1950#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 1951#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 1952#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 1953#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 1954#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 1955#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 1956#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 1957#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 1958#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 1959#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 1960#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 1961#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 1962#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 1963#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 1964#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 1965#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 1966#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 1967#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 1968#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 1969#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x0629 1970#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 1971#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062a 1972#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 1973#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b 1974#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 1975#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c 1976#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 1977#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d 1978#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 1979#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e 1980#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 1981#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f 1982#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 1983#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630 1984#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 1985#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631 1986#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 1987#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632 1988#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 1989#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633 1990#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 1991#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634 1992#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 1993#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635 1994#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 1995#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636 1996#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 1997#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643 1998#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 1999#define mmHUBPREQ0_BLANK_OFFSET_0 0x0644 2000#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 2001#define mmHUBPREQ0_BLANK_OFFSET_1 0x0645 2002#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 2003#define mmHUBPREQ0_DST_DIMENSIONS 0x0646 2004#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 2005#define mmHUBPREQ0_DST_AFTER_SCALER 0x0647 2006#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 2007#define mmHUBPREQ0_PREFETCH_SETTINGS 0x0648 2008#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 2009#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x0649 2010#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 2011#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064a 2012#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 2013#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064b 2014#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 2015#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064c 2016#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 2017#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064d 2018#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 2019#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x064e 2020#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 2021#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x064f 2022#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 2023#define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0650 2024#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 2025#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0651 2026#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 2027#define mmHUBPREQ0_NOM_PARAMETERS_0 0x0652 2028#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 2029#define mmHUBPREQ0_NOM_PARAMETERS_1 0x0653 2030#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 2031#define mmHUBPREQ0_NOM_PARAMETERS_2 0x0654 2032#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 2033#define mmHUBPREQ0_NOM_PARAMETERS_3 0x0655 2034#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 2035#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0656 2036#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 2037#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0657 2038#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 2039#define mmHUBPREQ0_NOM_PARAMETERS_6 0x0658 2040#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 2041#define mmHUBPREQ0_NOM_PARAMETERS_7 0x0659 2042#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 2043#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a 2044#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2045#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065b 2046#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 2047#define mmHUBPREQ0_CURSOR_SETTINGS 0x065c 2048#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 2049#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d 2050#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2051#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e 2052#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2053#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f 2054#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2055#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660 2056#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2057#define mmHUBPREQ0_VBLANK_PARAMETERS_5 0x0663 2058#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 2059#define mmHUBPREQ0_VBLANK_PARAMETERS_6 0x0664 2060#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 2061#define mmHUBPREQ0_FLIP_PARAMETERS_3 0x0665 2062#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 2063#define mmHUBPREQ0_FLIP_PARAMETERS_4 0x0666 2064#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 2065#define mmHUBPREQ0_FLIP_PARAMETERS_5 0x0667 2066#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 2067#define mmHUBPREQ0_FLIP_PARAMETERS_6 0x0668 2068#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 2069 2070 2071// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 2072// base address: 0x0 2073#define mmHUBPRET0_HUBPRET_CONTROL 0x066c 2074#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 2075#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d 2076#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2077#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e 2078#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2079#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f 2080#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2081#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 2082#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2083#define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671 2084#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 2085#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672 2086#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 2087#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673 2088#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 2089#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 2090#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2091#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 2092#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2093 2094 2095// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec 2096// base address: 0x0 2097#define mmCURSOR0_0_CURSOR_CONTROL 0x0678 2098#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 2099#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 2100#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2101#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 2102#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2103#define mmCURSOR0_0_CURSOR_SIZE 0x067b 2104#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 2105#define mmCURSOR0_0_CURSOR_POSITION 0x067c 2106#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 2107#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d 2108#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 2109#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 2110#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 2111#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f 2112#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 2113#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 2114#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2115#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 2116#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2117#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 2118#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2119#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 2120#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 2121#define mmCURSOR0_0_DMDATA_CNTL 0x0684 2122#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 2123#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685 2124#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 2125#define mmCURSOR0_0_DMDATA_STATUS 0x0686 2126#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 2127#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687 2128#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 2129#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688 2130#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 2131 2132 2133// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2134// base address: 0x1a74 2135#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x069d 2136#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 2137#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x069e 2138#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 2139#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x069f 2140#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 2141#define mmDC_PERFMON5_PERFMON_CNTL 0x06a0 2142#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 2143#define mmDC_PERFMON5_PERFMON_CNTL2 0x06a1 2144#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 2145#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x06a2 2146#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2147#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x06a3 2148#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 2149#define mmDC_PERFMON5_PERFMON_HI 0x06a4 2150#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2 2151#define mmDC_PERFMON5_PERFMON_LOW 0x06a5 2152#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 2153 2154 2155// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 2156// base address: 0x370 2157#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 2158#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2159#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2 2160#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 2161#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3 2162#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 2163#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 2164#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2165#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 2166#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2167#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 2168#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2169#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 2170#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2171#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 2172#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2173#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 2174#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2175#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 2176#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2177#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 2178#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2179#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 2180#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2181#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 2182#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2183#define mmHUBP1_DCHUBP_CNTL 0x06cf 2184#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2 2185#define mmHUBP1_HUBP_CLK_CNTL 0x06d0 2186#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 2187#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 2188#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2189#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2 2190#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 2191#define mmHUBP1_HUBPREQ_DEBUG 0x06d3 2192#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 2193#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 2194#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2195#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 2196#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2197 2198 2199// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 2200// base address: 0x370 2201#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 2202#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 2203#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 2204#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2205#define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5 2206#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 2207#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 2208#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2209#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 2210#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2211#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 2212#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2213#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 2214#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2215#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 2216#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2217#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 2218#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2219#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 2220#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2221#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 2222#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2223#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 2224#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2225#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 2226#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2227#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 2228#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2229#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 2230#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2231#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 2232#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2233#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 2234#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2235#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 2236#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2237#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 2238#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2239#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 2240#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2241#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 2242#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 2243#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 2244#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2245#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc 2246#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2247#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd 2248#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 2249#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe 2250#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2251#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff 2252#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2253#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 2254#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2255#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 2256#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2257#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 2258#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2259#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 2260#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2261#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 2262#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2263#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0705 2264#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 2265#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0706 2266#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 2267#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707 2268#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2269#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708 2270#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2271#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709 2272#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2273#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a 2274#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2275#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b 2276#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2277#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c 2278#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2279#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d 2280#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2281#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e 2282#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2283#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f 2284#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2285#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710 2286#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2287#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711 2288#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2289#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712 2290#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2291#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f 2292#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2293#define mmHUBPREQ1_BLANK_OFFSET_0 0x0720 2294#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 2295#define mmHUBPREQ1_BLANK_OFFSET_1 0x0721 2296#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 2297#define mmHUBPREQ1_DST_DIMENSIONS 0x0722 2298#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 2299#define mmHUBPREQ1_DST_AFTER_SCALER 0x0723 2300#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 2301#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0724 2302#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 2303#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0725 2304#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 2305#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0726 2306#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 2307#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0727 2308#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 2309#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0728 2310#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 2311#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0729 2312#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 2313#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072a 2314#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 2315#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072b 2316#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 2317#define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072c 2318#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 2319#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072d 2320#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 2321#define mmHUBPREQ1_NOM_PARAMETERS_0 0x072e 2322#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 2323#define mmHUBPREQ1_NOM_PARAMETERS_1 0x072f 2324#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 2325#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0730 2326#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 2327#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0731 2328#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 2329#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0732 2330#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 2331#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0733 2332#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 2333#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0734 2334#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 2335#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0735 2336#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 2337#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736 2338#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2339#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0737 2340#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 2341#define mmHUBPREQ1_CURSOR_SETTINGS 0x0738 2342#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 2343#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739 2344#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2345#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a 2346#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2347#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b 2348#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2349#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c 2350#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2351#define mmHUBPREQ1_VBLANK_PARAMETERS_5 0x073f 2352#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 2353#define mmHUBPREQ1_VBLANK_PARAMETERS_6 0x0740 2354#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 2355#define mmHUBPREQ1_FLIP_PARAMETERS_3 0x0741 2356#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 2357#define mmHUBPREQ1_FLIP_PARAMETERS_4 0x0742 2358#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 2359#define mmHUBPREQ1_FLIP_PARAMETERS_5 0x0743 2360#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 2361#define mmHUBPREQ1_FLIP_PARAMETERS_6 0x0744 2362#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 2363 2364 2365// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 2366// base address: 0x370 2367#define mmHUBPRET1_HUBPRET_CONTROL 0x0748 2368#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 2369#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 2370#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2371#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a 2372#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2373#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b 2374#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2375#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c 2376#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2377#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d 2378#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 2379#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e 2380#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 2381#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f 2382#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 2383#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 2384#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2385#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 2386#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2387 2388 2389// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec 2390// base address: 0x370 2391#define mmCURSOR0_1_CURSOR_CONTROL 0x0754 2392#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 2393#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 2394#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2395#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 2396#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2397#define mmCURSOR0_1_CURSOR_SIZE 0x0757 2398#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 2399#define mmCURSOR0_1_CURSOR_POSITION 0x0758 2400#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 2401#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759 2402#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 2403#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 2404#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 2405#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b 2406#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 2407#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 2408#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2409#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 2410#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2411#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 2412#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2413#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 2414#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 2415#define mmCURSOR0_1_DMDATA_CNTL 0x0760 2416#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 2417#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761 2418#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 2419#define mmCURSOR0_1_DMDATA_STATUS 0x0762 2420#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 2421#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763 2422#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 2423#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764 2424#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 2425 2426 2427// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2428// base address: 0x1de4 2429#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x0779 2430#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 2431#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x077a 2432#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 2433#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x077b 2434#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 2435#define mmDC_PERFMON6_PERFMON_CNTL 0x077c 2436#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 2437#define mmDC_PERFMON6_PERFMON_CNTL2 0x077d 2438#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 2439#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x077e 2440#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2441#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x077f 2442#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 2443#define mmDC_PERFMON6_PERFMON_HI 0x0780 2444#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2 2445#define mmDC_PERFMON6_PERFMON_LOW 0x0781 2446#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 2447 2448 2449// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 2450// base address: 0x0 2451#define mmDPP_TOP0_DPP_CONTROL 0x0cc5 2452#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2 2453#define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6 2454#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 2455#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 2456#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 2457#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 2458#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 2459#define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9 2460#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 2461#define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca 2462#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 2463 2464 2465// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 2466// base address: 0x0 2467#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 2468#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 2469#define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0 2470#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 2471#define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 2472#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 2473#define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 2474#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 2475#define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 2476#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 2477#define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 2478#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 2479#define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 2480#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 2481#define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 2482#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 2483#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 2484#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 2485#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 2486#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 2487#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 2488#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 2489#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 2490#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 2491#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 2492#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 2493#define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 2494#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 2495#define mmCNVC_CFG0_PRE_DEALPHA 0x0cde 2496#define mmCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 2497#define mmCNVC_CFG0_PRE_CSC_MODE 0x0cdf 2498#define mmCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 2499#define mmCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 2500#define mmCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 2501#define mmCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 2502#define mmCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 2503#define mmCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 2504#define mmCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 2505#define mmCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 2506#define mmCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 2507#define mmCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 2508#define mmCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 2509#define mmCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 2510#define mmCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 2511#define mmCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 2512#define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 2513#define mmCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 2514#define mmCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 2515#define mmCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 2516#define mmCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 2517#define mmCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 2518#define mmCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 2519#define mmCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 2520#define mmCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 2521#define mmCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 2522#define mmCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 2523#define mmCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 2524#define mmCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 2525#define mmCNVC_CFG0_PRE_DEGAM 0x0ced 2526#define mmCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 2527#define mmCNVC_CFG0_PRE_REALPHA 0x0cee 2528#define mmCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 2529 2530 2531// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 2532// base address: 0x0 2533#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 2534#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 2535#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 2536#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 2537#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 2538#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 2539#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 2540#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 2541 2542 2543// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 2544// base address: 0x0 2545#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 2546#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 2547#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa 2548#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 2549#define mmDSCL0_SCL_MODE 0x0cfb 2550#define mmDSCL0_SCL_MODE_BASE_IDX 2 2551#define mmDSCL0_SCL_TAP_CONTROL 0x0cfc 2552#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 2553#define mmDSCL0_DSCL_CONTROL 0x0cfd 2554#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2 2555#define mmDSCL0_DSCL_2TAP_CONTROL 0x0cfe 2556#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 2557#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff 2558#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 2559#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 2560#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 2561#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 2562#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 2563#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 2564#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 2565#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 2566#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 2567#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 2568#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 2569#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0d05 2570#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 2571#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 2572#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 2573#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 2574#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 2575#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 2576#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 2577#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 2578#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 2579#define mmDSCL0_SCL_BLACK_COLOR 0x0d0a 2580#define mmDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 2581#define mmDSCL0_DSCL_UPDATE 0x0d0b 2582#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2 2583#define mmDSCL0_DSCL_AUTOCAL 0x0d0c 2584#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2 2585#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d 2586#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 2587#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e 2588#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 2589#define mmDSCL0_OTG_H_BLANK 0x0d0f 2590#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2 2591#define mmDSCL0_OTG_V_BLANK 0x0d10 2592#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2 2593#define mmDSCL0_RECOUT_START 0x0d11 2594#define mmDSCL0_RECOUT_START_BASE_IDX 2 2595#define mmDSCL0_RECOUT_SIZE 0x0d12 2596#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2 2597#define mmDSCL0_MPC_SIZE 0x0d13 2598#define mmDSCL0_MPC_SIZE_BASE_IDX 2 2599#define mmDSCL0_LB_DATA_FORMAT 0x0d14 2600#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2 2601#define mmDSCL0_LB_MEMORY_CTRL 0x0d15 2602#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 2603#define mmDSCL0_LB_V_COUNTER 0x0d16 2604#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2 2605#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 2606#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 2607#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 2608#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 2609#define mmDSCL0_OBUF_CONTROL 0x0d19 2610#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2 2611#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a 2612#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 2613 2614 2615// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 2616// base address: 0x0 2617#define mmCM0_CM_CONTROL 0x0d20 2618#define mmCM0_CM_CONTROL_BASE_IDX 2 2619#define mmCM0_CM_POST_CSC_CONTROL 0x0d21 2620#define mmCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 2621#define mmCM0_CM_POST_CSC_C11_C12 0x0d22 2622#define mmCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 2623#define mmCM0_CM_POST_CSC_C13_C14 0x0d23 2624#define mmCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 2625#define mmCM0_CM_POST_CSC_C21_C22 0x0d24 2626#define mmCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 2627#define mmCM0_CM_POST_CSC_C23_C24 0x0d25 2628#define mmCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 2629#define mmCM0_CM_POST_CSC_C31_C32 0x0d26 2630#define mmCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 2631#define mmCM0_CM_POST_CSC_C33_C34 0x0d27 2632#define mmCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 2633#define mmCM0_CM_POST_CSC_B_C11_C12 0x0d28 2634#define mmCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 2635#define mmCM0_CM_POST_CSC_B_C13_C14 0x0d29 2636#define mmCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 2637#define mmCM0_CM_POST_CSC_B_C21_C22 0x0d2a 2638#define mmCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 2639#define mmCM0_CM_POST_CSC_B_C23_C24 0x0d2b 2640#define mmCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 2641#define mmCM0_CM_POST_CSC_B_C31_C32 0x0d2c 2642#define mmCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 2643#define mmCM0_CM_POST_CSC_B_C33_C34 0x0d2d 2644#define mmCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 2645#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e 2646#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 2647#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f 2648#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 2649#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 2650#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 2651#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 2652#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 2653#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 2654#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 2655#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 2656#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 2657#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 2658#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 2659#define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 2660#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 2661#define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 2662#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 2663#define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 2664#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 2665#define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 2666#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 2667#define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 2668#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 2669#define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a 2670#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 2671#define mmCM0_CM_BIAS_CR_R 0x0d3b 2672#define mmCM0_CM_BIAS_CR_R_BASE_IDX 2 2673#define mmCM0_CM_BIAS_Y_G_CB_B 0x0d3c 2674#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 2675#define mmCM0_CM_GAMCOR_CONTROL 0x0d3d 2676#define mmCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 2677#define mmCM0_CM_GAMCOR_LUT_INDEX 0x0d3e 2678#define mmCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 2679#define mmCM0_CM_GAMCOR_LUT_DATA 0x0d3f 2680#define mmCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 2681#define mmCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 2682#define mmCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 2683#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 2684#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 2685#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 2686#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 2687#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 2688#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 2689#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 2690#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 2691#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 2692#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 2693#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 2694#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 2695#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 2696#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 2697#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 2698#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 2699#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 2700#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 2701#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a 2702#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 2703#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b 2704#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 2705#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c 2706#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 2707#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d 2708#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 2709#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e 2710#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 2711#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f 2712#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 2713#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 2714#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 2715#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 2716#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 2717#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 2718#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 2719#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 2720#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 2721#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 2722#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 2723#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 2724#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 2725#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 2726#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 2727#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 2728#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 2729#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 2730#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 2731#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 2732#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 2733#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a 2734#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 2735#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b 2736#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 2737#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c 2738#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 2739#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d 2740#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 2741#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e 2742#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 2743#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f 2744#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 2745#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 2746#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 2747#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 2748#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 2749#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 2750#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 2751#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 2752#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 2753#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 2754#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 2755#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 2756#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 2757#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 2758#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 2759#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 2760#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 2761#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 2762#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 2763#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 2764#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 2765#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a 2766#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 2767#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b 2768#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 2769#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c 2770#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 2771#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d 2772#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 2773#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e 2774#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 2775#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f 2776#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 2777#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 2778#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 2779#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 2780#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 2781#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 2782#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 2783#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 2784#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 2785#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 2786#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 2787#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 2788#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 2789#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 2790#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 2791#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 2792#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 2793#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 2794#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 2795#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 2796#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 2797#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a 2798#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 2799#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b 2800#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 2801#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c 2802#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 2803#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d 2804#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 2805#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e 2806#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 2807#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f 2808#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 2809#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 2810#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 2811#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 2812#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 2813#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 2814#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 2815#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 2816#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 2817#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 2818#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 2819#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 2820#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 2821#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 2822#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 2823#define mmCM0_CM_BLNDGAM_CONTROL 0x0d87 2824#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 2825#define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d88 2826#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 2827#define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d89 2828#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 2829#define mmCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a 2830#define mmCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 2831#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b 2832#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 2833#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c 2834#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 2835#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d 2836#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 2837#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e 2838#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 2839#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f 2840#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 2841#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90 2842#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 2843#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91 2844#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 2845#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92 2846#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 2847#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93 2848#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 2849#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94 2850#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 2851#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95 2852#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 2853#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96 2854#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 2855#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97 2856#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 2857#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98 2858#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 2859#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99 2860#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 2861#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a 2862#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 2863#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b 2864#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 2865#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c 2866#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 2867#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d 2868#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 2869#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e 2870#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 2871#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f 2872#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 2873#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0 2874#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 2875#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1 2876#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 2877#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2 2878#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 2879#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3 2880#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 2881#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4 2882#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 2883#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5 2884#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 2885#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6 2886#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 2887#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7 2888#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 2889#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8 2890#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 2891#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9 2892#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 2893#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa 2894#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 2895#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab 2896#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 2897#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac 2898#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 2899#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad 2900#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 2901#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae 2902#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 2903#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf 2904#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 2905#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0 2906#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 2907#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1 2908#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 2909#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2 2910#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 2911#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3 2912#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 2913#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4 2914#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 2915#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5 2916#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 2917#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6 2918#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 2919#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7 2920#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 2921#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8 2922#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 2923#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9 2924#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 2925#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba 2926#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 2927#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb 2928#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 2929#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc 2930#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 2931#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd 2932#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 2933#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe 2934#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 2935#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf 2936#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 2937#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0 2938#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 2939#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1 2940#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 2941#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2 2942#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 2943#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3 2944#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 2945#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4 2946#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 2947#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5 2948#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 2949#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6 2950#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 2951#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7 2952#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 2953#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8 2954#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 2955#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9 2956#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 2957#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca 2958#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 2959#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb 2960#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 2961#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc 2962#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 2963#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd 2964#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 2965#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce 2966#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 2967#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf 2968#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 2969#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0 2970#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 2971#define mmCM0_CM_HDR_MULT_COEF 0x0dd1 2972#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2 2973#define mmCM0_CM_MEM_PWR_CTRL 0x0dd2 2974#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 2975#define mmCM0_CM_MEM_PWR_STATUS 0x0dd3 2976#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 2977#define mmCM0_CM_DEALPHA 0x0dd5 2978#define mmCM0_CM_DEALPHA_BASE_IDX 2 2979#define mmCM0_CM_COEF_FORMAT 0x0dd6 2980#define mmCM0_CM_COEF_FORMAT_BASE_IDX 2 2981#define mmCM0_CM_SHAPER_CONTROL 0x0dd7 2982#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2 2983#define mmCM0_CM_SHAPER_OFFSET_R 0x0dd8 2984#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 2985#define mmCM0_CM_SHAPER_OFFSET_G 0x0dd9 2986#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 2987#define mmCM0_CM_SHAPER_OFFSET_B 0x0dda 2988#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 2989#define mmCM0_CM_SHAPER_SCALE_R 0x0ddb 2990#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 2991#define mmCM0_CM_SHAPER_SCALE_G_B 0x0ddc 2992#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 2993#define mmCM0_CM_SHAPER_LUT_INDEX 0x0ddd 2994#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 2995#define mmCM0_CM_SHAPER_LUT_DATA 0x0dde 2996#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 2997#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf 2998#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 2999#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0 3000#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 3001#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1 3002#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 3003#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2 3004#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 3005#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3 3006#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 3007#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4 3008#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 3009#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5 3010#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 3011#define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6 3012#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 3013#define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7 3014#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 3015#define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8 3016#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 3017#define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9 3018#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 3019#define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea 3020#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 3021#define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb 3022#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 3023#define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec 3024#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 3025#define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded 3026#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 3027#define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee 3028#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 3029#define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def 3030#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 3031#define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0 3032#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 3033#define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1 3034#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 3035#define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2 3036#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 3037#define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3 3038#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 3039#define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4 3040#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 3041#define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5 3042#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 3043#define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6 3044#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 3045#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7 3046#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 3047#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8 3048#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 3049#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9 3050#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 3051#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa 3052#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 3053#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb 3054#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 3055#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc 3056#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 3057#define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd 3058#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 3059#define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe 3060#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 3061#define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff 3062#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 3063#define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00 3064#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 3065#define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01 3066#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 3067#define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02 3068#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 3069#define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03 3070#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 3071#define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04 3072#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 3073#define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05 3074#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 3075#define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06 3076#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 3077#define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07 3078#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 3079#define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08 3080#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 3081#define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09 3082#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 3083#define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a 3084#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 3085#define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b 3086#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 3087#define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c 3088#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 3089#define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d 3090#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 3091#define mmCM0_CM_MEM_PWR_CTRL2 0x0e0e 3092#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 3093#define mmCM0_CM_MEM_PWR_STATUS2 0x0e0f 3094#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 3095#define mmCM0_CM_3DLUT_MODE 0x0e10 3096#define mmCM0_CM_3DLUT_MODE_BASE_IDX 2 3097#define mmCM0_CM_3DLUT_INDEX 0x0e11 3098#define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2 3099#define mmCM0_CM_3DLUT_DATA 0x0e12 3100#define mmCM0_CM_3DLUT_DATA_BASE_IDX 2 3101#define mmCM0_CM_3DLUT_DATA_30BIT 0x0e13 3102#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 3103#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14 3104#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 3105#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15 3106#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 3107#define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16 3108#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 3109#define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17 3110#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 3111#define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 3112#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 3113#define mmCM0_CM_TEST_DEBUG_INDEX 0x0e19 3114#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 3115#define mmCM0_CM_TEST_DEBUG_DATA 0x0e1a 3116#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 3117 3118 3119// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 3120// base address: 0x3890 3121#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0e24 3122#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 3123#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x0e25 3124#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 3125#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x0e26 3126#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 3127#define mmDC_PERFMON7_PERFMON_CNTL 0x0e27 3128#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 3129#define mmDC_PERFMON7_PERFMON_CNTL2 0x0e28 3130#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 3131#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0e29 3132#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3133#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0e2a 3134#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 3135#define mmDC_PERFMON7_PERFMON_HI 0x0e2b 3136#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2 3137#define mmDC_PERFMON7_PERFMON_LOW 0x0e2c 3138#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 3139 3140 3141// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 3142// base address: 0x5ac 3143#define mmDPP_TOP1_DPP_CONTROL 0x0e30 3144#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2 3145#define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31 3146#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 3147#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 3148#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 3149#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 3150#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 3151#define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34 3152#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 3153#define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35 3154#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 3155 3156 3157// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 3158// base address: 0x5ac 3159#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 3160#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3161#define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b 3162#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 3163#define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 3164#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 3165#define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 3166#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 3167#define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 3168#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 3169#define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 3170#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 3171#define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 3172#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 3173#define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 3174#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 3175#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 3176#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 3177#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 3178#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 3179#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44 3180#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 3181#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 3182#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 3183#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 3184#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 3185#define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 3186#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 3187#define mmCNVC_CFG1_PRE_DEALPHA 0x0e49 3188#define mmCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 3189#define mmCNVC_CFG1_PRE_CSC_MODE 0x0e4a 3190#define mmCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 3191#define mmCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 3192#define mmCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 3193#define mmCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 3194#define mmCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 3195#define mmCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 3196#define mmCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 3197#define mmCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 3198#define mmCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 3199#define mmCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 3200#define mmCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 3201#define mmCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 3202#define mmCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 3203#define mmCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 3204#define mmCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 3205#define mmCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 3206#define mmCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 3207#define mmCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 3208#define mmCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 3209#define mmCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 3210#define mmCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 3211#define mmCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 3212#define mmCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 3213#define mmCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 3214#define mmCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 3215#define mmCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 3216#define mmCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 3217#define mmCNVC_CFG1_PRE_DEGAM 0x0e58 3218#define mmCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 3219#define mmCNVC_CFG1_PRE_REALPHA 0x0e59 3220#define mmCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 3221 3222 3223// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 3224// base address: 0x5ac 3225#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e5c 3226#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 3227#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e5d 3228#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 3229#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e5e 3230#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 3231#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f 3232#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3233 3234 3235// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 3236// base address: 0x5ac 3237#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 3238#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3239#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 3240#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3241#define mmDSCL1_SCL_MODE 0x0e66 3242#define mmDSCL1_SCL_MODE_BASE_IDX 2 3243#define mmDSCL1_SCL_TAP_CONTROL 0x0e67 3244#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 3245#define mmDSCL1_DSCL_CONTROL 0x0e68 3246#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2 3247#define mmDSCL1_DSCL_2TAP_CONTROL 0x0e69 3248#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 3249#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a 3250#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3251#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b 3252#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3253#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c 3254#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3255#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d 3256#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3257#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e 3258#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3259#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f 3260#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3261#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e70 3262#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 3263#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 3264#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3265#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 3266#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3267#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 3268#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3269#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 3270#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3271#define mmDSCL1_SCL_BLACK_COLOR 0x0e75 3272#define mmDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 3273#define mmDSCL1_DSCL_UPDATE 0x0e76 3274#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2 3275#define mmDSCL1_DSCL_AUTOCAL 0x0e77 3276#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2 3277#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 3278#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3279#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 3280#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3281#define mmDSCL1_OTG_H_BLANK 0x0e7a 3282#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2 3283#define mmDSCL1_OTG_V_BLANK 0x0e7b 3284#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2 3285#define mmDSCL1_RECOUT_START 0x0e7c 3286#define mmDSCL1_RECOUT_START_BASE_IDX 2 3287#define mmDSCL1_RECOUT_SIZE 0x0e7d 3288#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2 3289#define mmDSCL1_MPC_SIZE 0x0e7e 3290#define mmDSCL1_MPC_SIZE_BASE_IDX 2 3291#define mmDSCL1_LB_DATA_FORMAT 0x0e7f 3292#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2 3293#define mmDSCL1_LB_MEMORY_CTRL 0x0e80 3294#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 3295#define mmDSCL1_LB_V_COUNTER 0x0e81 3296#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2 3297#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 3298#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 3299#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 3300#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 3301#define mmDSCL1_OBUF_CONTROL 0x0e84 3302#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2 3303#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 3304#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 3305 3306 3307// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 3308// base address: 0x5ac 3309#define mmCM1_CM_CONTROL 0x0e8b 3310#define mmCM1_CM_CONTROL_BASE_IDX 2 3311#define mmCM1_CM_POST_CSC_CONTROL 0x0e8c 3312#define mmCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 3313#define mmCM1_CM_POST_CSC_C11_C12 0x0e8d 3314#define mmCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 3315#define mmCM1_CM_POST_CSC_C13_C14 0x0e8e 3316#define mmCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 3317#define mmCM1_CM_POST_CSC_C21_C22 0x0e8f 3318#define mmCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 3319#define mmCM1_CM_POST_CSC_C23_C24 0x0e90 3320#define mmCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 3321#define mmCM1_CM_POST_CSC_C31_C32 0x0e91 3322#define mmCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 3323#define mmCM1_CM_POST_CSC_C33_C34 0x0e92 3324#define mmCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 3325#define mmCM1_CM_POST_CSC_B_C11_C12 0x0e93 3326#define mmCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 3327#define mmCM1_CM_POST_CSC_B_C13_C14 0x0e94 3328#define mmCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 3329#define mmCM1_CM_POST_CSC_B_C21_C22 0x0e95 3330#define mmCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 3331#define mmCM1_CM_POST_CSC_B_C23_C24 0x0e96 3332#define mmCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 3333#define mmCM1_CM_POST_CSC_B_C31_C32 0x0e97 3334#define mmCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 3335#define mmCM1_CM_POST_CSC_B_C33_C34 0x0e98 3336#define mmCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 3337#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 3338#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 3339#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a 3340#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 3341#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b 3342#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 3343#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c 3344#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 3345#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d 3346#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 3347#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e 3348#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 3349#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f 3350#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 3351#define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 3352#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 3353#define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 3354#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 3355#define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 3356#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 3357#define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 3358#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 3359#define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 3360#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 3361#define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 3362#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 3363#define mmCM1_CM_BIAS_CR_R 0x0ea6 3364#define mmCM1_CM_BIAS_CR_R_BASE_IDX 2 3365#define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea7 3366#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 3367#define mmCM1_CM_GAMCOR_CONTROL 0x0ea8 3368#define mmCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 3369#define mmCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 3370#define mmCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 3371#define mmCM1_CM_GAMCOR_LUT_DATA 0x0eaa 3372#define mmCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 3373#define mmCM1_CM_GAMCOR_LUT_CONTROL 0x0eab 3374#define mmCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 3375#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac 3376#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 3377#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead 3378#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 3379#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae 3380#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 3381#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf 3382#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 3383#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 3384#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 3385#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 3386#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 3387#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 3388#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 3389#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 3390#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 3391#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 3392#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 3393#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 3394#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 3395#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 3396#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 3397#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 3398#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 3399#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 3400#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 3401#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 3402#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 3403#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba 3404#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 3405#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb 3406#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 3407#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc 3408#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 3409#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd 3410#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 3411#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe 3412#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 3413#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf 3414#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 3415#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 3416#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 3417#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 3418#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 3419#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 3420#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 3421#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 3422#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 3423#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 3424#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 3425#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 3426#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 3427#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 3428#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 3429#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 3430#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 3431#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 3432#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 3433#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 3434#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 3435#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca 3436#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 3437#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb 3438#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 3439#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc 3440#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 3441#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd 3442#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 3443#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece 3444#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 3445#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf 3446#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 3447#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 3448#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 3449#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 3450#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 3451#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 3452#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 3453#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 3454#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 3455#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 3456#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 3457#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 3458#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 3459#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 3460#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 3461#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 3462#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 3463#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 3464#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 3465#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 3466#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 3467#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda 3468#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 3469#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb 3470#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 3471#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc 3472#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 3473#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd 3474#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 3475#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede 3476#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 3477#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf 3478#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 3479#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 3480#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 3481#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 3482#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 3483#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 3484#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 3485#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 3486#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 3487#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 3488#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 3489#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 3490#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 3491#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 3492#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 3493#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 3494#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 3495#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 3496#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 3497#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 3498#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 3499#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea 3500#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 3501#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb 3502#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 3503#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec 3504#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 3505#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed 3506#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 3507#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee 3508#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 3509#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef 3510#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 3511#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 3512#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 3513#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 3514#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 3515#define mmCM1_CM_BLNDGAM_CONTROL 0x0ef2 3516#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 3517#define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3 3518#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 3519#define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ef4 3520#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 3521#define mmCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5 3522#define mmCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 3523#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6 3524#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 3525#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7 3526#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 3527#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8 3528#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 3529#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9 3530#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 3531#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa 3532#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 3533#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb 3534#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 3535#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc 3536#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 3537#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd 3538#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 3539#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe 3540#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 3541#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff 3542#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 3543#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00 3544#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 3545#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01 3546#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 3547#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02 3548#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 3549#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03 3550#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 3551#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04 3552#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 3553#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05 3554#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 3555#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06 3556#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 3557#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07 3558#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 3559#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08 3560#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 3561#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09 3562#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 3563#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a 3564#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 3565#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b 3566#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 3567#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c 3568#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 3569#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d 3570#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 3571#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e 3572#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 3573#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f 3574#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 3575#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10 3576#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 3577#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11 3578#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 3579#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12 3580#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 3581#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13 3582#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 3583#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14 3584#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 3585#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15 3586#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 3587#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16 3588#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 3589#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17 3590#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 3591#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18 3592#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 3593#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19 3594#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 3595#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a 3596#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 3597#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b 3598#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 3599#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c 3600#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 3601#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d 3602#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 3603#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e 3604#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 3605#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f 3606#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 3607#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20 3608#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 3609#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21 3610#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 3611#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22 3612#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 3613#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23 3614#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 3615#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24 3616#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 3617#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25 3618#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 3619#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26 3620#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 3621#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27 3622#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 3623#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28 3624#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 3625#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29 3626#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 3627#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a 3628#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 3629#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b 3630#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 3631#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c 3632#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 3633#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d 3634#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 3635#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e 3636#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 3637#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f 3638#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 3639#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30 3640#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 3641#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31 3642#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 3643#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32 3644#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 3645#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33 3646#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 3647#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34 3648#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 3649#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35 3650#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 3651#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36 3652#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 3653#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37 3654#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 3655#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38 3656#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 3657#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39 3658#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 3659#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a 3660#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 3661#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b 3662#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 3663#define mmCM1_CM_HDR_MULT_COEF 0x0f3c 3664#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2 3665#define mmCM1_CM_MEM_PWR_CTRL 0x0f3d 3666#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 3667#define mmCM1_CM_MEM_PWR_STATUS 0x0f3e 3668#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 3669#define mmCM1_CM_DEALPHA 0x0f40 3670#define mmCM1_CM_DEALPHA_BASE_IDX 2 3671#define mmCM1_CM_COEF_FORMAT 0x0f41 3672#define mmCM1_CM_COEF_FORMAT_BASE_IDX 2 3673#define mmCM1_CM_SHAPER_CONTROL 0x0f42 3674#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2 3675#define mmCM1_CM_SHAPER_OFFSET_R 0x0f43 3676#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 3677#define mmCM1_CM_SHAPER_OFFSET_G 0x0f44 3678#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 3679#define mmCM1_CM_SHAPER_OFFSET_B 0x0f45 3680#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 3681#define mmCM1_CM_SHAPER_SCALE_R 0x0f46 3682#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 3683#define mmCM1_CM_SHAPER_SCALE_G_B 0x0f47 3684#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 3685#define mmCM1_CM_SHAPER_LUT_INDEX 0x0f48 3686#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 3687#define mmCM1_CM_SHAPER_LUT_DATA 0x0f49 3688#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 3689#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a 3690#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 3691#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b 3692#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 3693#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c 3694#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 3695#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d 3696#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 3697#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e 3698#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 3699#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f 3700#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 3701#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50 3702#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 3703#define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51 3704#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 3705#define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52 3706#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 3707#define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53 3708#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 3709#define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54 3710#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 3711#define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55 3712#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 3713#define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56 3714#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 3715#define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57 3716#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 3717#define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58 3718#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 3719#define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59 3720#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 3721#define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a 3722#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 3723#define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b 3724#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 3725#define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c 3726#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 3727#define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d 3728#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 3729#define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e 3730#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 3731#define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f 3732#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 3733#define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60 3734#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 3735#define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61 3736#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 3737#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62 3738#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 3739#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63 3740#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 3741#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64 3742#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 3743#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65 3744#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 3745#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66 3746#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 3747#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67 3748#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 3749#define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68 3750#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 3751#define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69 3752#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 3753#define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a 3754#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 3755#define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b 3756#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 3757#define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c 3758#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 3759#define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d 3760#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 3761#define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e 3762#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 3763#define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f 3764#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 3765#define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70 3766#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 3767#define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71 3768#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 3769#define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72 3770#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 3771#define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73 3772#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 3773#define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74 3774#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 3775#define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75 3776#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 3777#define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76 3778#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 3779#define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77 3780#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 3781#define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78 3782#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 3783#define mmCM1_CM_MEM_PWR_CTRL2 0x0f79 3784#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 3785#define mmCM1_CM_MEM_PWR_STATUS2 0x0f7a 3786#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 3787#define mmCM1_CM_3DLUT_MODE 0x0f7b 3788#define mmCM1_CM_3DLUT_MODE_BASE_IDX 2 3789#define mmCM1_CM_3DLUT_INDEX 0x0f7c 3790#define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2 3791#define mmCM1_CM_3DLUT_DATA 0x0f7d 3792#define mmCM1_CM_3DLUT_DATA_BASE_IDX 2 3793#define mmCM1_CM_3DLUT_DATA_30BIT 0x0f7e 3794#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 3795#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f 3796#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 3797#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80 3798#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 3799#define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81 3800#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 3801#define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82 3802#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 3803#define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 3804#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 3805#define mmCM1_CM_TEST_DEBUG_INDEX 0x0f84 3806#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 3807#define mmCM1_CM_TEST_DEBUG_DATA 0x0f85 3808#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 3809 3810 3811// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 3812// base address: 0x3e3c 3813#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0f8f 3814#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 3815#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0f90 3816#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 3817#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0f91 3818#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 3819#define mmDC_PERFMON8_PERFMON_CNTL 0x0f92 3820#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 3821#define mmDC_PERFMON8_PERFMON_CNTL2 0x0f93 3822#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 3823#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x0f94 3824#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3825#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x0f95 3826#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 3827#define mmDC_PERFMON8_PERFMON_HI 0x0f96 3828#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2 3829#define mmDC_PERFMON8_PERFMON_LOW 0x0f97 3830#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 3831 3832 3833// addressBlock: dce_dc_opp_fmt0_dispdec 3834// base address: 0x0 3835#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c 3836#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 3837#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d 3838#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 3839#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e 3840#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 3841#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 3842#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 3843#define mmFMT0_FMT_CONTROL 0x1840 3844#define mmFMT0_FMT_CONTROL_BASE_IDX 2 3845#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 3846#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 3847#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842 3848#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 3849#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843 3850#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 3851#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844 3852#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 3853#define mmFMT0_FMT_CLAMP_CNTL 0x1845 3854#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 3855#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 3856#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 3857#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 3858#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 3859#define mmFMT0_FMT_422_CONTROL 0x1849 3860#define mmFMT0_FMT_422_CONTROL_BASE_IDX 2 3861 3862 3863// addressBlock: dce_dc_opp_dpg0_dispdec 3864// base address: 0x0 3865#define mmDPG0_DPG_CONTROL 0x1854 3866#define mmDPG0_DPG_CONTROL_BASE_IDX 2 3867#define mmDPG0_DPG_RAMP_CONTROL 0x1855 3868#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 3869#define mmDPG0_DPG_DIMENSIONS 0x1856 3870#define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2 3871#define mmDPG0_DPG_COLOUR_R_CR 0x1857 3872#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 3873#define mmDPG0_DPG_COLOUR_G_Y 0x1858 3874#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 3875#define mmDPG0_DPG_COLOUR_B_CB 0x1859 3876#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 3877#define mmDPG0_DPG_OFFSET_SEGMENT 0x185a 3878#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 3879#define mmDPG0_DPG_STATUS 0x185b 3880#define mmDPG0_DPG_STATUS_BASE_IDX 2 3881 3882 3883// addressBlock: dce_dc_opp_oppbuf0_dispdec 3884// base address: 0x0 3885#define mmOPPBUF0_OPPBUF_CONTROL 0x1884 3886#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 3887#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 3888#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 3889#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 3890#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 3891#define mmOPPBUF0_OPPBUF_CONTROL1 0x1889 3892#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 3893 3894 3895// addressBlock: dce_dc_opp_opp_pipe0_dispdec 3896// base address: 0x0 3897#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 3898#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 3899 3900 3901// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 3902// base address: 0x0 3903#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 3904#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 3905#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 3906#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 3907#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 3908#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 3909#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 3910#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 3911#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 3912#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 3913 3914 3915// addressBlock: dce_dc_opp_fmt1_dispdec 3916// base address: 0x168 3917#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896 3918#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 3919#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897 3920#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 3921#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898 3922#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 3923#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 3924#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 3925#define mmFMT1_FMT_CONTROL 0x189a 3926#define mmFMT1_FMT_CONTROL_BASE_IDX 2 3927#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 3928#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 3929#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c 3930#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 3931#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d 3932#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 3933#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e 3934#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 3935#define mmFMT1_FMT_CLAMP_CNTL 0x189f 3936#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 3937#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 3938#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 3939#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 3940#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 3941#define mmFMT1_FMT_422_CONTROL 0x18a3 3942#define mmFMT1_FMT_422_CONTROL_BASE_IDX 2 3943 3944 3945// addressBlock: dce_dc_opp_dpg1_dispdec 3946// base address: 0x168 3947#define mmDPG1_DPG_CONTROL 0x18ae 3948#define mmDPG1_DPG_CONTROL_BASE_IDX 2 3949#define mmDPG1_DPG_RAMP_CONTROL 0x18af 3950#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 3951#define mmDPG1_DPG_DIMENSIONS 0x18b0 3952#define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2 3953#define mmDPG1_DPG_COLOUR_R_CR 0x18b1 3954#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 3955#define mmDPG1_DPG_COLOUR_G_Y 0x18b2 3956#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 3957#define mmDPG1_DPG_COLOUR_B_CB 0x18b3 3958#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 3959#define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4 3960#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 3961#define mmDPG1_DPG_STATUS 0x18b5 3962#define mmDPG1_DPG_STATUS_BASE_IDX 2 3963 3964 3965// addressBlock: dce_dc_opp_oppbuf1_dispdec 3966// base address: 0x168 3967#define mmOPPBUF1_OPPBUF_CONTROL 0x18de 3968#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 3969#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 3970#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 3971#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 3972#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 3973#define mmOPPBUF1_OPPBUF_CONTROL1 0x18e3 3974#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 3975 3976 3977// addressBlock: dce_dc_opp_opp_pipe1_dispdec 3978// base address: 0x168 3979#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 3980#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 3981 3982 3983// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 3984// base address: 0x168 3985#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 3986#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 3987#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 3988#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 3989#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 3990#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 3991#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 3992#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 3993#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 3994#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 3995 3996 3997// addressBlock: dce_dc_opp_opp_top_dispdec 3998// base address: 0x0 3999#define mmOPP_TOP_CLK_CONTROL 0x1a5e 4000#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2 4001#define mmOPP_ABM_CONTROL 0x1a60 4002#define mmOPP_ABM_CONTROL_BASE_IDX 2 4003 4004 4005// addressBlock: dce_dc_opp_dscrm0_dispdec 4006// base address: 0x0 4007#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 4008#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 4009 4010 4011// addressBlock: dce_dc_opp_dscrm1_dispdec 4012// base address: 0x4 4013#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 4014#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 4015 4016 4017// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec 4018// base address: 0x6af8 4019#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x1abe 4020#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 4021#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x1abf 4022#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 4023#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x1ac0 4024#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 4025#define mmDC_PERFMON9_PERFMON_CNTL 0x1ac1 4026#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 4027#define mmDC_PERFMON9_PERFMON_CNTL2 0x1ac2 4028#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 4029#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x1ac3 4030#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4031#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x1ac4 4032#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 4033#define mmDC_PERFMON9_PERFMON_HI 0x1ac5 4034#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2 4035#define mmDC_PERFMON9_PERFMON_LOW 0x1ac6 4036#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 4037 4038 4039// addressBlock: dce_dc_optc_odm0_dispdec 4040// base address: 0x0 4041#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 4042#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 4043#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 4044#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 4045#define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 4046#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 4047#define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd 4048#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 4049#define mmODM0_OPTC_WIDTH_CONTROL 0x1ace 4050#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 4051#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 4052#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 4053#define mmODM0_OPTC_MEMORY_CONFIG 0x1ad0 4054#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 4055#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 4056#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 4057 4058 4059// addressBlock: dce_dc_optc_odm1_dispdec 4060// base address: 0x40 4061#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 4062#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 4063#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 4064#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 4065#define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 4066#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 4067#define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add 4068#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 4069#define mmODM1_OPTC_WIDTH_CONTROL 0x1ade 4070#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 4071#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 4072#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 4073#define mmODM1_OPTC_MEMORY_CONFIG 0x1ae0 4074#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 4075#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 4076#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 4077 4078 4079// addressBlock: dce_dc_optc_otg0_dispdec 4080// base address: 0x0 4081#define mmOTG0_OTG_H_TOTAL 0x1b2a 4082#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2 4083#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b 4084#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 4085#define mmOTG0_OTG_H_SYNC_A 0x1b2c 4086#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2 4087#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 4088#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 4089#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e 4090#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 4091#define mmOTG0_OTG_V_TOTAL 0x1b2f 4092#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2 4093#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30 4094#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 4095#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31 4096#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 4097#define mmOTG0_OTG_V_TOTAL_MID 0x1b32 4098#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 4099#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33 4100#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 4101#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 4102#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 4103#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 4104#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 4105#define mmOTG0_OTG_V_BLANK_START_END 0x1b36 4106#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 4107#define mmOTG0_OTG_V_SYNC_A 0x1b37 4108#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2 4109#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38 4110#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 4111#define mmOTG0_OTG_TRIGA_CNTL 0x1b39 4112#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 4113#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a 4114#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 4115#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b 4116#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 4117#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c 4118#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 4119#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d 4120#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 4121#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e 4122#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 4123#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f 4124#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 4125#define mmOTG0_OTG_CONTROL 0x1b41 4126#define mmOTG0_OTG_CONTROL_BASE_IDX 2 4127#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44 4128#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 4129#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45 4130#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 4131#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 4132#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 4133#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 4134#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 4135#define mmOTG0_OTG_STATUS 0x1b49 4136#define mmOTG0_OTG_STATUS_BASE_IDX 2 4137#define mmOTG0_OTG_STATUS_POSITION 0x1b4a 4138#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2 4139#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b 4140#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 4141#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c 4142#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 4143#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d 4144#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 4145#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e 4146#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 4147#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f 4148#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 4149#define mmOTG0_OTG_COUNT_RESET 0x1b50 4150#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2 4151#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 4152#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 4153#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 4154#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 4155#define mmOTG0_OTG_STEREO_STATUS 0x1b53 4156#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2 4157#define mmOTG0_OTG_STEREO_CONTROL 0x1b54 4158#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 4159#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55 4160#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 4161#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 4162#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 4163#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57 4164#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 4165#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58 4166#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 4167#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59 4168#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 4169#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a 4170#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 4171#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b 4172#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 4173#define mmOTG0_OTG_MASTER_EN 0x1b5c 4174#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2 4175#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e 4176#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2 4177#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f 4178#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 4179#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 4180#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 4181#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 4182#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 4183#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 4184#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 4185#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 4186#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 4187#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 4188#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 4189#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 4190#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 4191#define mmOTG0_OTG_CRC_CNTL 0x1b68 4192#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2 4193#define mmOTG0_OTG_CRC_CNTL2 0x1b69 4194#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2 4195#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a 4196#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 4197#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b 4198#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 4199#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c 4200#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 4201#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d 4202#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 4203#define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e 4204#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 4205#define mmOTG0_OTG_CRC0_DATA_B 0x1b6f 4206#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 4207#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 4208#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 4209#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 4210#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 4211#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 4212#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 4213#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 4214#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 4215#define mmOTG0_OTG_CRC1_DATA_RG 0x1b74 4216#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 4217#define mmOTG0_OTG_CRC1_DATA_B 0x1b75 4218#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 4219#define mmOTG0_OTG_CRC2_DATA_RG 0x1b76 4220#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 4221#define mmOTG0_OTG_CRC2_DATA_B 0x1b77 4222#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 4223#define mmOTG0_OTG_CRC3_DATA_RG 0x1b78 4224#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 4225#define mmOTG0_OTG_CRC3_DATA_B 0x1b79 4226#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 4227#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a 4228#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 4229#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b 4230#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 4231#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 4232#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 4233#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 4234#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 4235#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84 4236#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 4237#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 4238#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 4239#define mmOTG0_OTG_CLOCK_CONTROL 0x1b86 4240#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 4241#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87 4242#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 4243#define mmOTG0_OTG_VUPDATE_PARAM 0x1b88 4244#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 4245#define mmOTG0_OTG_VREADY_PARAM 0x1b89 4246#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2 4247#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a 4248#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 4249#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b 4250#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 4251#define mmOTG0_OTG_GSL_CONTROL 0x1b8c 4252#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2 4253#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d 4254#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 4255#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e 4256#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 4257#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f 4258#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 4259#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90 4260#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 4261#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91 4262#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 4263#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92 4264#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 4265#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93 4266#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 4267#define mmOTG0_OTG_GLOBAL_CONTROL4 0x1b94 4268#define mmOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 4269#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95 4270#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 4271#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96 4272#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 4273#define mmOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97 4274#define mmOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 4275#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98 4276#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 4277#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99 4278#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 4279#define mmOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a 4280#define mmOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 4281#define mmOTG0_OTG_DRR_CONTROL 0x1b9b 4282#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2 4283#define mmOTG0_OTG_M_CONST_DTO0 0x1b9c 4284#define mmOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 4285#define mmOTG0_OTG_M_CONST_DTO1 0x1b9d 4286#define mmOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 4287#define mmOTG0_OTG_REQUEST_CONTROL 0x1b9e 4288#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 4289#define mmOTG0_OTG_DSC_START_POSITION 0x1b9f 4290#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 4291#define mmOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0 4292#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 4293#define mmOTG0_OTG_SPARE_REGISTER 0x1ba2 4294#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 4295 4296 4297// addressBlock: dce_dc_optc_otg1_dispdec 4298// base address: 0x200 4299#define mmOTG1_OTG_H_TOTAL 0x1baa 4300#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2 4301#define mmOTG1_OTG_H_BLANK_START_END 0x1bab 4302#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 4303#define mmOTG1_OTG_H_SYNC_A 0x1bac 4304#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2 4305#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad 4306#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 4307#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae 4308#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 4309#define mmOTG1_OTG_V_TOTAL 0x1baf 4310#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2 4311#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0 4312#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 4313#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1 4314#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 4315#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2 4316#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 4317#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 4318#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 4319#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 4320#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 4321#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 4322#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 4323#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6 4324#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 4325#define mmOTG1_OTG_V_SYNC_A 0x1bb7 4326#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2 4327#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 4328#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 4329#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9 4330#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 4331#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba 4332#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 4333#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb 4334#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 4335#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc 4336#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 4337#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd 4338#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 4339#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe 4340#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 4341#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf 4342#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 4343#define mmOTG1_OTG_CONTROL 0x1bc1 4344#define mmOTG1_OTG_CONTROL_BASE_IDX 2 4345#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 4346#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 4347#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 4348#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 4349#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 4350#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 4351#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 4352#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 4353#define mmOTG1_OTG_STATUS 0x1bc9 4354#define mmOTG1_OTG_STATUS_BASE_IDX 2 4355#define mmOTG1_OTG_STATUS_POSITION 0x1bca 4356#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2 4357#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb 4358#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 4359#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc 4360#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 4361#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd 4362#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 4363#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce 4364#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 4365#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf 4366#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 4367#define mmOTG1_OTG_COUNT_RESET 0x1bd0 4368#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2 4369#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 4370#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 4371#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 4372#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 4373#define mmOTG1_OTG_STEREO_STATUS 0x1bd3 4374#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2 4375#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4 4376#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 4377#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 4378#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 4379#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 4380#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 4381#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 4382#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 4383#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 4384#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 4385#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 4386#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 4387#define mmOTG1_OTG_UPDATE_LOCK 0x1bda 4388#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 4389#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb 4390#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 4391#define mmOTG1_OTG_MASTER_EN 0x1bdc 4392#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2 4393#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde 4394#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2 4395#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf 4396#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 4397#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 4398#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 4399#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 4400#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 4401#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 4402#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 4403#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 4404#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 4405#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 4406#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 4407#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 4408#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 4409#define mmOTG1_OTG_CRC_CNTL 0x1be8 4410#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2 4411#define mmOTG1_OTG_CRC_CNTL2 0x1be9 4412#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2 4413#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea 4414#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 4415#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb 4416#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 4417#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec 4418#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 4419#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed 4420#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 4421#define mmOTG1_OTG_CRC0_DATA_RG 0x1bee 4422#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 4423#define mmOTG1_OTG_CRC0_DATA_B 0x1bef 4424#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 4425#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 4426#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 4427#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 4428#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 4429#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 4430#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 4431#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 4432#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 4433#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4 4434#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 4435#define mmOTG1_OTG_CRC1_DATA_B 0x1bf5 4436#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 4437#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf6 4438#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 4439#define mmOTG1_OTG_CRC2_DATA_B 0x1bf7 4440#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 4441#define mmOTG1_OTG_CRC3_DATA_RG 0x1bf8 4442#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 4443#define mmOTG1_OTG_CRC3_DATA_B 0x1bf9 4444#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 4445#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa 4446#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 4447#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb 4448#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 4449#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 4450#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 4451#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 4452#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 4453#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04 4454#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 4455#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 4456#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 4457#define mmOTG1_OTG_CLOCK_CONTROL 0x1c06 4458#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 4459#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07 4460#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 4461#define mmOTG1_OTG_VUPDATE_PARAM 0x1c08 4462#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 4463#define mmOTG1_OTG_VREADY_PARAM 0x1c09 4464#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2 4465#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a 4466#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 4467#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b 4468#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 4469#define mmOTG1_OTG_GSL_CONTROL 0x1c0c 4470#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2 4471#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d 4472#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 4473#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e 4474#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 4475#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f 4476#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 4477#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10 4478#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 4479#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11 4480#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 4481#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12 4482#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 4483#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13 4484#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 4485#define mmOTG1_OTG_GLOBAL_CONTROL4 0x1c14 4486#define mmOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 4487#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15 4488#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 4489#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16 4490#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 4491#define mmOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17 4492#define mmOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 4493#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18 4494#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 4495#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19 4496#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 4497#define mmOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a 4498#define mmOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 4499#define mmOTG1_OTG_DRR_CONTROL 0x1c1b 4500#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2 4501#define mmOTG1_OTG_M_CONST_DTO0 0x1c1c 4502#define mmOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 4503#define mmOTG1_OTG_M_CONST_DTO1 0x1c1d 4504#define mmOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 4505#define mmOTG1_OTG_REQUEST_CONTROL 0x1c1e 4506#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 4507#define mmOTG1_OTG_DSC_START_POSITION 0x1c1f 4508#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 4509#define mmOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20 4510#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 4511#define mmOTG1_OTG_SPARE_REGISTER 0x1c22 4512#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 4513 4514 4515// addressBlock: dce_dc_optc_optc_misc_dispdec 4516// base address: 0x0 4517#define mmDWB_SOURCE_SELECT 0x1e2a 4518#define mmDWB_SOURCE_SELECT_BASE_IDX 2 4519#define mmGSL_SOURCE_SELECT 0x1e2b 4520#define mmGSL_SOURCE_SELECT_BASE_IDX 2 4521#define mmOPTC_CLOCK_CONTROL 0x1e2c 4522#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2 4523#define mmODM_MEM_PWR_CTRL 0x1e2d 4524#define mmODM_MEM_PWR_CTRL_BASE_IDX 2 4525#define mmODM_MEM_PWR_CTRL2 0x1e2e 4526#define mmODM_MEM_PWR_CTRL2_BASE_IDX 2 4527#define mmODM_MEM_PWR_CTRL3 0x1e2f 4528#define mmODM_MEM_PWR_CTRL3_BASE_IDX 2 4529#define mmODM_MEM_PWR_STATUS 0x1e30 4530#define mmODM_MEM_PWR_STATUS_BASE_IDX 2 4531#define mmOPTC_MISC_SPARE_REGISTER 0x1e31 4532#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 4533 4534 4535// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec 4536// base address: 0x79a8 4537#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x1e6a 4538#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 4539#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x1e6b 4540#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 4541#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x1e6c 4542#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 4543#define mmDC_PERFMON10_PERFMON_CNTL 0x1e6d 4544#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 4545#define mmDC_PERFMON10_PERFMON_CNTL2 0x1e6e 4546#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 4547#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x1e6f 4548#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4549#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x1e70 4550#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 4551#define mmDC_PERFMON10_PERFMON_HI 0x1e71 4552#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2 4553#define mmDC_PERFMON10_PERFMON_LOW 0x1e72 4554#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 4555 4556 4557// addressBlock: dce_dc_dio_dout_i2c_dispdec 4558// base address: 0x0 4559#define mmDC_I2C_CONTROL 0x1e98 4560#define mmDC_I2C_CONTROL_BASE_IDX 2 4561#define mmDC_I2C_ARBITRATION 0x1e99 4562#define mmDC_I2C_ARBITRATION_BASE_IDX 2 4563#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a 4564#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 4565#define mmDC_I2C_SW_STATUS 0x1e9b 4566#define mmDC_I2C_SW_STATUS_BASE_IDX 2 4567#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c 4568#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 4569#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d 4570#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 4571#define mmDC_I2C_DDC1_SPEED 0x1ea2 4572#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2 4573#define mmDC_I2C_DDC1_SETUP 0x1ea3 4574#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2 4575#define mmDC_I2C_DDC2_SPEED 0x1ea4 4576#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2 4577#define mmDC_I2C_DDC2_SETUP 0x1ea5 4578#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2 4579#define mmDC_I2C_TRANSACTION0 0x1eae 4580#define mmDC_I2C_TRANSACTION0_BASE_IDX 2 4581#define mmDC_I2C_TRANSACTION1 0x1eaf 4582#define mmDC_I2C_TRANSACTION1_BASE_IDX 2 4583#define mmDC_I2C_TRANSACTION2 0x1eb0 4584#define mmDC_I2C_TRANSACTION2_BASE_IDX 2 4585#define mmDC_I2C_TRANSACTION3 0x1eb1 4586#define mmDC_I2C_TRANSACTION3_BASE_IDX 2 4587#define mmDC_I2C_DATA 0x1eb2 4588#define mmDC_I2C_DATA_BASE_IDX 2 4589#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6 4590#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 4591#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 4592#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 4593 4594 4595// addressBlock: dce_dc_dio_dio_misc_dispdec 4596// base address: 0x0 4597#define mmDIO_SCRATCH0 0x1eca 4598#define mmDIO_SCRATCH0_BASE_IDX 2 4599#define mmDIO_SCRATCH1 0x1ecb 4600#define mmDIO_SCRATCH1_BASE_IDX 2 4601#define mmDIO_SCRATCH2 0x1ecc 4602#define mmDIO_SCRATCH2_BASE_IDX 2 4603#define mmDIO_SCRATCH3 0x1ecd 4604#define mmDIO_SCRATCH3_BASE_IDX 2 4605#define mmDIO_SCRATCH4 0x1ece 4606#define mmDIO_SCRATCH4_BASE_IDX 2 4607#define mmDIO_SCRATCH5 0x1ecf 4608#define mmDIO_SCRATCH5_BASE_IDX 2 4609#define mmDIO_SCRATCH6 0x1ed0 4610#define mmDIO_SCRATCH6_BASE_IDX 2 4611#define mmDIO_SCRATCH7 0x1ed1 4612#define mmDIO_SCRATCH7_BASE_IDX 2 4613#define mmDIO_MEM_PWR_STATUS 0x1edd 4614#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2 4615#define mmDIO_MEM_PWR_CTRL 0x1ede 4616#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2 4617#define mmDIO_MEM_PWR_CTRL2 0x1edf 4618#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2 4619#define mmDIO_CLK_CNTL 0x1ee0 4620#define mmDIO_CLK_CNTL_BASE_IDX 2 4621#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4 4622#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 4623#define mmDIG_SOFT_RESET 0x1eee 4624#define mmDIG_SOFT_RESET_BASE_IDX 2 4625#define mmDIO_CLK_CNTL2 0x1ef2 4626#define mmDIO_CLK_CNTL2_BASE_IDX 2 4627#define mmDIO_CLK_CNTL3 0x1ef3 4628#define mmDIO_CLK_CNTL3_BASE_IDX 2 4629#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 4630#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 4631#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 4632#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 4633#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 4634#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 4635 4636 4637// addressBlock: dce_dc_dio_hpd0_dispdec 4638// base address: 0x0 4639#define mmHPD0_DC_HPD_INT_STATUS 0x1f14 4640#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 4641#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15 4642#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 4643#define mmHPD0_DC_HPD_CONTROL 0x1f16 4644#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2 4645#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 4646#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 4647#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 4648#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 4649 4650 4651// addressBlock: dce_dc_dio_hpd1_dispdec 4652// base address: 0x20 4653#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c 4654#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 4655#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d 4656#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 4657#define mmHPD1_DC_HPD_CONTROL 0x1f1e 4658#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2 4659#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 4660#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 4661#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 4662#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 4663 4664 4665// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec 4666// base address: 0x7d10 4667#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x1f44 4668#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 4669#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x1f45 4670#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 4671#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x1f46 4672#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 4673#define mmDC_PERFMON11_PERFMON_CNTL 0x1f47 4674#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 4675#define mmDC_PERFMON11_PERFMON_CNTL2 0x1f48 4676#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 4677#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x1f49 4678#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4679#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x1f4a 4680#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 4681#define mmDC_PERFMON11_PERFMON_HI 0x1f4b 4682#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2 4683#define mmDC_PERFMON11_PERFMON_LOW 0x1f4c 4684#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 4685 4686 4687// addressBlock: dce_dc_dio_dp_aux0_dispdec 4688// base address: 0x0 4689#define mmDP_AUX0_AUX_CONTROL 0x1f50 4690#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2 4691#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51 4692#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 4693#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52 4694#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 4695#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 4696#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 4697#define mmDP_AUX0_AUX_SW_STATUS 0x1f54 4698#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 4699#define mmDP_AUX0_AUX_LS_STATUS 0x1f55 4700#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 4701#define mmDP_AUX0_AUX_SW_DATA 0x1f56 4702#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2 4703#define mmDP_AUX0_AUX_LS_DATA 0x1f57 4704#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2 4705#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 4706#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 4707#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 4708#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 4709#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 4710#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 4711#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 4712#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 4713#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 4714#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 4715#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 4716#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 4717#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e 4718#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 4719#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 4720#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 4721#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 4722#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 4723#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 4724#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 4725#define mmDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 4726#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 4727 4728 4729// addressBlock: dce_dc_dio_dp_aux1_dispdec 4730// base address: 0x70 4731#define mmDP_AUX1_AUX_CONTROL 0x1f6c 4732#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2 4733#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d 4734#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 4735#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e 4736#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 4737#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 4738#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 4739#define mmDP_AUX1_AUX_SW_STATUS 0x1f70 4740#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 4741#define mmDP_AUX1_AUX_LS_STATUS 0x1f71 4742#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 4743#define mmDP_AUX1_AUX_SW_DATA 0x1f72 4744#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2 4745#define mmDP_AUX1_AUX_LS_DATA 0x1f73 4746#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2 4747#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 4748#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 4749#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 4750#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 4751#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 4752#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 4753#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 4754#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 4755#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 4756#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 4757#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 4758#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 4759#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a 4760#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 4761#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 4762#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 4763#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 4764#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 4765#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 4766#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 4767#define mmDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 4768#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 4769 4770 4771// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec 4772// base address: 0x154a0 4773#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 4774#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 4775#define mmVPG0_VPG_GENERIC_PACKET_DATA 0x2069 4776#define mmVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 4777#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 4778#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 4779#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 4780#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 4781#define mmVPG0_VPG_GENERIC_STATUS 0x206c 4782#define mmVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 4783#define mmVPG0_VPG_MEM_PWR 0x206d 4784#define mmVPG0_VPG_MEM_PWR_BASE_IDX 2 4785#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 4786#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 4787#define mmVPG0_VPG_ISRC1_2_DATA 0x206f 4788#define mmVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 4789#define mmVPG0_VPG_MPEG_INFO0 0x2070 4790#define mmVPG0_VPG_MPEG_INFO0_BASE_IDX 2 4791#define mmVPG0_VPG_MPEG_INFO1 0x2071 4792#define mmVPG0_VPG_MPEG_INFO1_BASE_IDX 2 4793 4794 4795// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec 4796// base address: 0x154cc 4797#define mmAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 4798#define mmAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 4799#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 4800#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 4801#define mmAFMT0_AFMT_AUDIO_INFO0 0x2076 4802#define mmAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 4803#define mmAFMT0_AFMT_AUDIO_INFO1 0x2077 4804#define mmAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 4805#define mmAFMT0_AFMT_60958_0 0x2078 4806#define mmAFMT0_AFMT_60958_0_BASE_IDX 2 4807#define mmAFMT0_AFMT_60958_1 0x2079 4808#define mmAFMT0_AFMT_60958_1_BASE_IDX 2 4809#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 4810#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 4811#define mmAFMT0_AFMT_RAMP_CONTROL0 0x207b 4812#define mmAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 4813#define mmAFMT0_AFMT_RAMP_CONTROL1 0x207c 4814#define mmAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 4815#define mmAFMT0_AFMT_RAMP_CONTROL2 0x207d 4816#define mmAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 4817#define mmAFMT0_AFMT_RAMP_CONTROL3 0x207e 4818#define mmAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 4819#define mmAFMT0_AFMT_60958_2 0x207f 4820#define mmAFMT0_AFMT_60958_2_BASE_IDX 2 4821#define mmAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 4822#define mmAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 4823#define mmAFMT0_AFMT_STATUS 0x2081 4824#define mmAFMT0_AFMT_STATUS_BASE_IDX 2 4825#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 4826#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 4827#define mmAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 4828#define mmAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 4829#define mmAFMT0_AFMT_INTERRUPT_STATUS 0x2084 4830#define mmAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 4831#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 4832#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 4833#define mmAFMT0_AFMT_MEM_PWR 0x2087 4834#define mmAFMT0_AFMT_MEM_PWR_BASE_IDX 2 4835 4836 4837// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec 4838// base address: 0x15524 4839#define mmDME0_DME_CONTROL 0x2089 4840#define mmDME0_DME_CONTROL_BASE_IDX 2 4841#define mmDME0_DME_MEMORY_CONTROL 0x208a 4842#define mmDME0_DME_MEMORY_CONTROL_BASE_IDX 2 4843 4844 4845// addressBlock: dce_dc_dio_dig0_dispdec 4846// base address: 0x0 4847#define mmDIG0_DIG_FE_CNTL 0x208b 4848#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2 4849#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x208c 4850#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 4851#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x208d 4852#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 4853#define mmDIG0_DIG_CLOCK_PATTERN 0x208e 4854#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 4855#define mmDIG0_DIG_TEST_PATTERN 0x208f 4856#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2 4857#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 4858#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 4859#define mmDIG0_DIG_FIFO_STATUS 0x2091 4860#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2 4861#define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092 4862#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 4863#define mmDIG0_HDMI_CONTROL 0x2093 4864#define mmDIG0_HDMI_CONTROL_BASE_IDX 2 4865#define mmDIG0_HDMI_STATUS 0x2094 4866#define mmDIG0_HDMI_STATUS_BASE_IDX 2 4867#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095 4868#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 4869#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2096 4870#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 4871#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2097 4872#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 4873#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2098 4874#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 4875#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2099 4876#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 4877#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a 4878#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 4879#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b 4880#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 4881#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c 4882#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 4883#define mmDIG0_HDMI_GC 0x209d 4884#define mmDIG0_HDMI_GC_BASE_IDX 2 4885#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e 4886#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 4887#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f 4888#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 4889#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0 4890#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 4891#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1 4892#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 4893#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2 4894#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 4895#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3 4896#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 4897#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4 4898#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 4899#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5 4900#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 4901#define mmDIG0_HDMI_DB_CONTROL 0x20a6 4902#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2 4903#define mmDIG0_HDMI_ACR_32_0 0x20a7 4904#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2 4905#define mmDIG0_HDMI_ACR_32_1 0x20a8 4906#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2 4907#define mmDIG0_HDMI_ACR_44_0 0x20a9 4908#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2 4909#define mmDIG0_HDMI_ACR_44_1 0x20aa 4910#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2 4911#define mmDIG0_HDMI_ACR_48_0 0x20ab 4912#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2 4913#define mmDIG0_HDMI_ACR_48_1 0x20ac 4914#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2 4915#define mmDIG0_HDMI_ACR_STATUS_0 0x20ad 4916#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 4917#define mmDIG0_HDMI_ACR_STATUS_1 0x20ae 4918#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 4919#define mmDIG0_AFMT_CNTL 0x20af 4920#define mmDIG0_AFMT_CNTL_BASE_IDX 2 4921#define mmDIG0_DIG_BE_CNTL 0x20b0 4922#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2 4923#define mmDIG0_DIG_BE_EN_CNTL 0x20b1 4924#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 4925#define mmDIG0_TMDS_CNTL 0x20d7 4926#define mmDIG0_TMDS_CNTL_BASE_IDX 2 4927#define mmDIG0_TMDS_CONTROL_CHAR 0x20d8 4928#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 4929#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9 4930#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 4931#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da 4932#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 4933#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db 4934#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 4935#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc 4936#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 4937#define mmDIG0_TMDS_CTL_BITS 0x20de 4938#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2 4939#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20df 4940#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 4941#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0 4942#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 4943#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1 4944#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 4945#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2 4946#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 4947#define mmDIG0_DIG_VERSION 0x20e4 4948#define mmDIG0_DIG_VERSION_BASE_IDX 2 4949#define mmDIG0_DIG_LANE_ENABLE 0x20e5 4950#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2 4951#define mmDIG0_FORCE_DIG_DISABLE 0x20e6 4952#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 4953 4954// addressBlock: dce_dc_dio_dp0_dispdec 4955// base address: 0x0 4956#define mmDP0_DP_LINK_CNTL 0x2108 4957#define mmDP0_DP_LINK_CNTL_BASE_IDX 2 4958#define mmDP0_DP_PIXEL_FORMAT 0x2109 4959#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2 4960#define mmDP0_DP_MSA_COLORIMETRY 0x210a 4961#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 4962#define mmDP0_DP_CONFIG 0x210b 4963#define mmDP0_DP_CONFIG_BASE_IDX 2 4964#define mmDP0_DP_VID_STREAM_CNTL 0x210c 4965#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 4966#define mmDP0_DP_STEER_FIFO 0x210d 4967#define mmDP0_DP_STEER_FIFO_BASE_IDX 2 4968#define mmDP0_DP_MSA_MISC 0x210e 4969#define mmDP0_DP_MSA_MISC_BASE_IDX 2 4970#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 4971#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 4972#define mmDP0_DP_VID_TIMING 0x2110 4973#define mmDP0_DP_VID_TIMING_BASE_IDX 2 4974#define mmDP0_DP_VID_N 0x2111 4975#define mmDP0_DP_VID_N_BASE_IDX 2 4976#define mmDP0_DP_VID_M 0x2112 4977#define mmDP0_DP_VID_M_BASE_IDX 2 4978#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113 4979#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 4980#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114 4981#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 4982#define mmDP0_DP_VID_MSA_VBID 0x2115 4983#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2 4984#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116 4985#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 4986#define mmDP0_DP_DPHY_CNTL 0x2117 4987#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2 4988#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 4989#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 4990#define mmDP0_DP_DPHY_SYM0 0x2119 4991#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2 4992#define mmDP0_DP_DPHY_SYM1 0x211a 4993#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2 4994#define mmDP0_DP_DPHY_SYM2 0x211b 4995#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2 4996#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c 4997#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 4998#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d 4999#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 5000#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e 5001#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 5002#define mmDP0_DP_DPHY_CRC_EN 0x211f 5003#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2 5004#define mmDP0_DP_DPHY_CRC_CNTL 0x2120 5005#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 5006#define mmDP0_DP_DPHY_CRC_RESULT 0x2121 5007#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 5008#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122 5009#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 5010#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123 5011#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 5012#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124 5013#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 5014#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 5015#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 5016#define mmDP0_DP_SEC_CNTL 0x212b 5017#define mmDP0_DP_SEC_CNTL_BASE_IDX 2 5018#define mmDP0_DP_SEC_CNTL1 0x212c 5019#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2 5020#define mmDP0_DP_SEC_FRAMING1 0x212d 5021#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2 5022#define mmDP0_DP_SEC_FRAMING2 0x212e 5023#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2 5024#define mmDP0_DP_SEC_FRAMING3 0x212f 5025#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2 5026#define mmDP0_DP_SEC_FRAMING4 0x2130 5027#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2 5028#define mmDP0_DP_SEC_AUD_N 0x2131 5029#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2 5030#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132 5031#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 5032#define mmDP0_DP_SEC_AUD_M 0x2133 5033#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2 5034#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134 5035#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 5036#define mmDP0_DP_SEC_TIMESTAMP 0x2135 5037#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 5038#define mmDP0_DP_SEC_PACKET_CNTL 0x2136 5039#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 5040#define mmDP0_DP_MSE_RATE_CNTL 0x2137 5041#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 5042#define mmDP0_DP_MSE_RATE_UPDATE 0x2139 5043#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 5044#define mmDP0_DP_MSE_SAT0 0x213a 5045#define mmDP0_DP_MSE_SAT0_BASE_IDX 2 5046#define mmDP0_DP_MSE_SAT1 0x213b 5047#define mmDP0_DP_MSE_SAT1_BASE_IDX 2 5048#define mmDP0_DP_MSE_SAT2 0x213c 5049#define mmDP0_DP_MSE_SAT2_BASE_IDX 2 5050#define mmDP0_DP_MSE_SAT_UPDATE 0x213d 5051#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 5052#define mmDP0_DP_MSE_LINK_TIMING 0x213e 5053#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 5054#define mmDP0_DP_MSE_MISC_CNTL 0x213f 5055#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 5056#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 5057#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 5058#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 5059#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 5060#define mmDP0_DP_MSE_SAT0_STATUS 0x2147 5061#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 5062#define mmDP0_DP_MSE_SAT1_STATUS 0x2148 5063#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 5064#define mmDP0_DP_MSE_SAT2_STATUS 0x2149 5065#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 5066#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c 5067#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 5068#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d 5069#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 5070#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e 5071#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 5072#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f 5073#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 5074#define mmDP0_DP_MSO_CNTL 0x2150 5075#define mmDP0_DP_MSO_CNTL_BASE_IDX 2 5076#define mmDP0_DP_MSO_CNTL1 0x2151 5077#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2 5078#define mmDP0_DP_DSC_CNTL 0x2152 5079#define mmDP0_DP_DSC_CNTL_BASE_IDX 2 5080#define mmDP0_DP_SEC_CNTL2 0x2153 5081#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2 5082#define mmDP0_DP_SEC_CNTL3 0x2154 5083#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2 5084#define mmDP0_DP_SEC_CNTL4 0x2155 5085#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2 5086#define mmDP0_DP_SEC_CNTL5 0x2156 5087#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2 5088#define mmDP0_DP_SEC_CNTL6 0x2157 5089#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2 5090#define mmDP0_DP_SEC_CNTL7 0x2158 5091#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2 5092#define mmDP0_DP_DB_CNTL 0x2159 5093#define mmDP0_DP_DB_CNTL_BASE_IDX 2 5094#define mmDP0_DP_MSA_VBID_MISC 0x215a 5095#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2 5096#define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b 5097#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 5098#define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c 5099#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 5100#define mmDP0_DP_ALPM_CNTL 0x215d 5101#define mmDP0_DP_ALPM_CNTL_BASE_IDX 2 5102#define mmDP0_DP_GSP8_CNTL 0x215e 5103#define mmDP0_DP_GSP8_CNTL_BASE_IDX 2 5104#define mmDP0_DP_GSP9_CNTL 0x215f 5105#define mmDP0_DP_GSP9_CNTL_BASE_IDX 2 5106#define mmDP0_DP_GSP10_CNTL 0x2160 5107#define mmDP0_DP_GSP10_CNTL_BASE_IDX 2 5108#define mmDP0_DP_GSP11_CNTL 0x2161 5109#define mmDP0_DP_GSP11_CNTL_BASE_IDX 2 5110#define mmDP0_DP_GSP_EN_DB_STATUS 0x2162 5111#define mmDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 5112 5113 5114// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec 5115// base address: 0x158a0 5116#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 5117#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 5118#define mmVPG1_VPG_GENERIC_PACKET_DATA 0x2169 5119#define mmVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 5120#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a 5121#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 5122#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b 5123#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 5124#define mmVPG1_VPG_GENERIC_STATUS 0x216c 5125#define mmVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 5126#define mmVPG1_VPG_MEM_PWR 0x216d 5127#define mmVPG1_VPG_MEM_PWR_BASE_IDX 2 5128#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e 5129#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 5130#define mmVPG1_VPG_ISRC1_2_DATA 0x216f 5131#define mmVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 5132#define mmVPG1_VPG_MPEG_INFO0 0x2170 5133#define mmVPG1_VPG_MPEG_INFO0_BASE_IDX 2 5134#define mmVPG1_VPG_MPEG_INFO1 0x2171 5135#define mmVPG1_VPG_MPEG_INFO1_BASE_IDX 2 5136 5137 5138// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec 5139// base address: 0x158cc 5140#define mmAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 5141#define mmAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 5142#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 5143#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 5144#define mmAFMT1_AFMT_AUDIO_INFO0 0x2176 5145#define mmAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 5146#define mmAFMT1_AFMT_AUDIO_INFO1 0x2177 5147#define mmAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 5148#define mmAFMT1_AFMT_60958_0 0x2178 5149#define mmAFMT1_AFMT_60958_0_BASE_IDX 2 5150#define mmAFMT1_AFMT_60958_1 0x2179 5151#define mmAFMT1_AFMT_60958_1_BASE_IDX 2 5152#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a 5153#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 5154#define mmAFMT1_AFMT_RAMP_CONTROL0 0x217b 5155#define mmAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 5156#define mmAFMT1_AFMT_RAMP_CONTROL1 0x217c 5157#define mmAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 5158#define mmAFMT1_AFMT_RAMP_CONTROL2 0x217d 5159#define mmAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 5160#define mmAFMT1_AFMT_RAMP_CONTROL3 0x217e 5161#define mmAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 5162#define mmAFMT1_AFMT_60958_2 0x217f 5163#define mmAFMT1_AFMT_60958_2_BASE_IDX 2 5164#define mmAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 5165#define mmAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 5166#define mmAFMT1_AFMT_STATUS 0x2181 5167#define mmAFMT1_AFMT_STATUS_BASE_IDX 2 5168#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 5169#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 5170#define mmAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 5171#define mmAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 5172#define mmAFMT1_AFMT_INTERRUPT_STATUS 0x2184 5173#define mmAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 5174#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 5175#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 5176#define mmAFMT1_AFMT_MEM_PWR 0x2187 5177#define mmAFMT1_AFMT_MEM_PWR_BASE_IDX 2 5178 5179 5180// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec 5181// base address: 0x15924 5182#define mmDME1_DME_CONTROL 0x2189 5183#define mmDME1_DME_CONTROL_BASE_IDX 2 5184#define mmDME1_DME_MEMORY_CONTROL 0x218a 5185#define mmDME1_DME_MEMORY_CONTROL_BASE_IDX 2 5186 5187 5188// addressBlock: dce_dc_dio_dig1_dispdec 5189// base address: 0x400 5190#define mmDIG1_DIG_FE_CNTL 0x218b 5191#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2 5192#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x218c 5193#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 5194#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x218d 5195#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 5196#define mmDIG1_DIG_CLOCK_PATTERN 0x218e 5197#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 5198#define mmDIG1_DIG_TEST_PATTERN 0x218f 5199#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2 5200#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 5201#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 5202#define mmDIG1_DIG_FIFO_STATUS 0x2191 5203#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2 5204#define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192 5205#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 5206#define mmDIG1_HDMI_CONTROL 0x2193 5207#define mmDIG1_HDMI_CONTROL_BASE_IDX 2 5208#define mmDIG1_HDMI_STATUS 0x2194 5209#define mmDIG1_HDMI_STATUS_BASE_IDX 2 5210#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195 5211#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 5212#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2196 5213#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 5214#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2197 5215#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 5216#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2198 5217#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 5218#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2199 5219#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 5220#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a 5221#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 5222#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b 5223#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 5224#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c 5225#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 5226#define mmDIG1_HDMI_GC 0x219d 5227#define mmDIG1_HDMI_GC_BASE_IDX 2 5228#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e 5229#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 5230#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f 5231#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 5232#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0 5233#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 5234#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1 5235#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 5236#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2 5237#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 5238#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3 5239#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 5240#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4 5241#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 5242#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5 5243#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 5244#define mmDIG1_HDMI_DB_CONTROL 0x21a6 5245#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2 5246#define mmDIG1_HDMI_ACR_32_0 0x21a7 5247#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2 5248#define mmDIG1_HDMI_ACR_32_1 0x21a8 5249#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2 5250#define mmDIG1_HDMI_ACR_44_0 0x21a9 5251#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2 5252#define mmDIG1_HDMI_ACR_44_1 0x21aa 5253#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2 5254#define mmDIG1_HDMI_ACR_48_0 0x21ab 5255#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2 5256#define mmDIG1_HDMI_ACR_48_1 0x21ac 5257#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2 5258#define mmDIG1_HDMI_ACR_STATUS_0 0x21ad 5259#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 5260#define mmDIG1_HDMI_ACR_STATUS_1 0x21ae 5261#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 5262#define mmDIG1_AFMT_CNTL 0x21af 5263#define mmDIG1_AFMT_CNTL_BASE_IDX 2 5264#define mmDIG1_DIG_BE_CNTL 0x21b0 5265#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2 5266#define mmDIG1_DIG_BE_EN_CNTL 0x21b1 5267#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 5268#define mmDIG1_TMDS_CNTL 0x21d7 5269#define mmDIG1_TMDS_CNTL_BASE_IDX 2 5270#define mmDIG1_TMDS_CONTROL_CHAR 0x21d8 5271#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 5272#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9 5273#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 5274#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da 5275#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 5276#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db 5277#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 5278#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc 5279#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 5280#define mmDIG1_TMDS_CTL_BITS 0x21de 5281#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2 5282#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21df 5283#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 5284#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0 5285#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 5286#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1 5287#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 5288#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2 5289#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 5290#define mmDIG1_DIG_VERSION 0x21e4 5291#define mmDIG1_DIG_VERSION_BASE_IDX 2 5292#define mmDIG1_DIG_LANE_ENABLE 0x21e5 5293#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2 5294#define mmDIG1_FORCE_DIG_DISABLE 0x21e6 5295#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 5296 5297// addressBlock: dce_dc_dio_dp1_dispdec 5298// base address: 0x400 5299#define mmDP1_DP_LINK_CNTL 0x2208 5300#define mmDP1_DP_LINK_CNTL_BASE_IDX 2 5301#define mmDP1_DP_PIXEL_FORMAT 0x2209 5302#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2 5303#define mmDP1_DP_MSA_COLORIMETRY 0x220a 5304#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 5305#define mmDP1_DP_CONFIG 0x220b 5306#define mmDP1_DP_CONFIG_BASE_IDX 2 5307#define mmDP1_DP_VID_STREAM_CNTL 0x220c 5308#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 5309#define mmDP1_DP_STEER_FIFO 0x220d 5310#define mmDP1_DP_STEER_FIFO_BASE_IDX 2 5311#define mmDP1_DP_MSA_MISC 0x220e 5312#define mmDP1_DP_MSA_MISC_BASE_IDX 2 5313#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 5314#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 5315#define mmDP1_DP_VID_TIMING 0x2210 5316#define mmDP1_DP_VID_TIMING_BASE_IDX 2 5317#define mmDP1_DP_VID_N 0x2211 5318#define mmDP1_DP_VID_N_BASE_IDX 2 5319#define mmDP1_DP_VID_M 0x2212 5320#define mmDP1_DP_VID_M_BASE_IDX 2 5321#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213 5322#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 5323#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214 5324#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 5325#define mmDP1_DP_VID_MSA_VBID 0x2215 5326#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2 5327#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216 5328#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 5329#define mmDP1_DP_DPHY_CNTL 0x2217 5330#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2 5331#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 5332#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 5333#define mmDP1_DP_DPHY_SYM0 0x2219 5334#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2 5335#define mmDP1_DP_DPHY_SYM1 0x221a 5336#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2 5337#define mmDP1_DP_DPHY_SYM2 0x221b 5338#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2 5339#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c 5340#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 5341#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d 5342#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 5343#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e 5344#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 5345#define mmDP1_DP_DPHY_CRC_EN 0x221f 5346#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2 5347#define mmDP1_DP_DPHY_CRC_CNTL 0x2220 5348#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 5349#define mmDP1_DP_DPHY_CRC_RESULT 0x2221 5350#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 5351#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222 5352#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 5353#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223 5354#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 5355#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224 5356#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 5357#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 5358#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 5359#define mmDP1_DP_SEC_CNTL 0x222b 5360#define mmDP1_DP_SEC_CNTL_BASE_IDX 2 5361#define mmDP1_DP_SEC_CNTL1 0x222c 5362#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2 5363#define mmDP1_DP_SEC_FRAMING1 0x222d 5364#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2 5365#define mmDP1_DP_SEC_FRAMING2 0x222e 5366#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2 5367#define mmDP1_DP_SEC_FRAMING3 0x222f 5368#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2 5369#define mmDP1_DP_SEC_FRAMING4 0x2230 5370#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2 5371#define mmDP1_DP_SEC_AUD_N 0x2231 5372#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2 5373#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232 5374#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 5375#define mmDP1_DP_SEC_AUD_M 0x2233 5376#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2 5377#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234 5378#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 5379#define mmDP1_DP_SEC_TIMESTAMP 0x2235 5380#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 5381#define mmDP1_DP_SEC_PACKET_CNTL 0x2236 5382#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 5383#define mmDP1_DP_MSE_RATE_CNTL 0x2237 5384#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 5385#define mmDP1_DP_MSE_RATE_UPDATE 0x2239 5386#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 5387#define mmDP1_DP_MSE_SAT0 0x223a 5388#define mmDP1_DP_MSE_SAT0_BASE_IDX 2 5389#define mmDP1_DP_MSE_SAT1 0x223b 5390#define mmDP1_DP_MSE_SAT1_BASE_IDX 2 5391#define mmDP1_DP_MSE_SAT2 0x223c 5392#define mmDP1_DP_MSE_SAT2_BASE_IDX 2 5393#define mmDP1_DP_MSE_SAT_UPDATE 0x223d 5394#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 5395#define mmDP1_DP_MSE_LINK_TIMING 0x223e 5396#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 5397#define mmDP1_DP_MSE_MISC_CNTL 0x223f 5398#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 5399#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 5400#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 5401#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 5402#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 5403#define mmDP1_DP_MSE_SAT0_STATUS 0x2247 5404#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 5405#define mmDP1_DP_MSE_SAT1_STATUS 0x2248 5406#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 5407#define mmDP1_DP_MSE_SAT2_STATUS 0x2249 5408#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 5409#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c 5410#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 5411#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d 5412#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 5413#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e 5414#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 5415#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f 5416#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 5417#define mmDP1_DP_MSO_CNTL 0x2250 5418#define mmDP1_DP_MSO_CNTL_BASE_IDX 2 5419#define mmDP1_DP_MSO_CNTL1 0x2251 5420#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2 5421#define mmDP1_DP_DSC_CNTL 0x2252 5422#define mmDP1_DP_DSC_CNTL_BASE_IDX 2 5423#define mmDP1_DP_SEC_CNTL2 0x2253 5424#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2 5425#define mmDP1_DP_SEC_CNTL3 0x2254 5426#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2 5427#define mmDP1_DP_SEC_CNTL4 0x2255 5428#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2 5429#define mmDP1_DP_SEC_CNTL5 0x2256 5430#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2 5431#define mmDP1_DP_SEC_CNTL6 0x2257 5432#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2 5433#define mmDP1_DP_SEC_CNTL7 0x2258 5434#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2 5435#define mmDP1_DP_DB_CNTL 0x2259 5436#define mmDP1_DP_DB_CNTL_BASE_IDX 2 5437#define mmDP1_DP_MSA_VBID_MISC 0x225a 5438#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2 5439#define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b 5440#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 5441#define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c 5442#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 5443#define mmDP1_DP_ALPM_CNTL 0x225d 5444#define mmDP1_DP_ALPM_CNTL_BASE_IDX 2 5445#define mmDP1_DP_GSP8_CNTL 0x225e 5446#define mmDP1_DP_GSP8_CNTL_BASE_IDX 2 5447#define mmDP1_DP_GSP9_CNTL 0x225f 5448#define mmDP1_DP_GSP9_CNTL_BASE_IDX 2 5449#define mmDP1_DP_GSP10_CNTL 0x2260 5450#define mmDP1_DP_GSP10_CNTL_BASE_IDX 2 5451#define mmDP1_DP_GSP11_CNTL 0x2261 5452#define mmDP1_DP_GSP11_CNTL_BASE_IDX 2 5453#define mmDP1_DP_GSP_EN_DB_STATUS 0x2262 5454#define mmDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 5455 5456 5457// addressBlock: dce_dc_dcio_dcio_dispdec 5458// base address: 0x0 5459#define mmDC_GENERICA 0x2868 5460#define mmDC_GENERICA_BASE_IDX 2 5461#define mmDC_GENERICB 0x2869 5462#define mmDC_GENERICB_BASE_IDX 2 5463#define mmDCIO_CLOCK_CNTL 0x286a 5464#define mmDCIO_CLOCK_CNTL_BASE_IDX 2 5465#define mmDC_REF_CLK_CNTL 0x286b 5466#define mmDC_REF_CLK_CNTL_BASE_IDX 2 5467#define mmUNIPHYA_LINK_CNTL 0x286d 5468#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2 5469#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 5470#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 5471#define mmUNIPHYB_LINK_CNTL 0x286f 5472#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2 5473#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 5474#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 5475#define mmDCIO_WRCMD_DELAY 0x287e 5476#define mmDCIO_WRCMD_DELAY_BASE_IDX 2 5477#define mmDC_PINSTRAPS 0x2880 5478#define mmDC_PINSTRAPS_BASE_IDX 2 5479#define mmLVTMA_PWRSEQ_CNTL 0x2883 5480#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2 5481#define mmLVTMA_PWRSEQ_STATE 0x2884 5482#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2 5483#define mmLVTMA_PWRSEQ_REF_DIV 0x2885 5484#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2 5485#define mmLVTMA_PWRSEQ_DELAY1 0x2886 5486#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2 5487#define mmLVTMA_PWRSEQ_DELAY2 0x2887 5488#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2 5489#define mmBL_PWM_CNTL 0x2888 5490#define mmBL_PWM_CNTL_BASE_IDX 2 5491#define mmBL_PWM_CNTL2 0x2889 5492#define mmBL_PWM_CNTL2_BASE_IDX 2 5493#define mmBL_PWM_PERIOD_CNTL 0x288a 5494#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2 5495#define mmBL_PWM_GRP1_REG_LOCK 0x288b 5496#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 5497#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c 5498#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 5499#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 5500#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 5501#define mmDCIO_SOFT_RESET 0x289e 5502#define mmDCIO_SOFT_RESET_BASE_IDX 2 5503 5504 5505// addressBlock: dce_dc_dcio_dcio_chip_dispdec 5506// base address: 0x0 5507#define mmDC_GPIO_GENERIC_MASK 0x28c8 5508#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2 5509#define mmDC_GPIO_GENERIC_A 0x28c9 5510#define mmDC_GPIO_GENERIC_A_BASE_IDX 2 5511#define mmDC_GPIO_GENERIC_EN 0x28ca 5512#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2 5513#define mmDC_GPIO_GENERIC_Y 0x28cb 5514#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2 5515#define mmDC_GPIO_DDC1_MASK 0x28d0 5516#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2 5517#define mmDC_GPIO_DDC1_A 0x28d1 5518#define mmDC_GPIO_DDC1_A_BASE_IDX 2 5519#define mmDC_GPIO_DDC1_EN 0x28d2 5520#define mmDC_GPIO_DDC1_EN_BASE_IDX 2 5521#define mmDC_GPIO_DDC1_Y 0x28d3 5522#define mmDC_GPIO_DDC1_Y_BASE_IDX 2 5523#define mmDC_GPIO_DDC2_MASK 0x28d4 5524#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2 5525#define mmDC_GPIO_DDC2_A 0x28d5 5526#define mmDC_GPIO_DDC2_A_BASE_IDX 2 5527#define mmDC_GPIO_DDC2_EN 0x28d6 5528#define mmDC_GPIO_DDC2_EN_BASE_IDX 2 5529#define mmDC_GPIO_DDC2_Y 0x28d7 5530#define mmDC_GPIO_DDC2_Y_BASE_IDX 2 5531#define mmDC_GPIO_DDCVGA_MASK 0x28e8 5532#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2 5533#define mmDC_GPIO_DDCVGA_A 0x28e9 5534#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2 5535#define mmDC_GPIO_DDCVGA_EN 0x28ea 5536#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2 5537#define mmDC_GPIO_DDCVGA_Y 0x28eb 5538#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2 5539#define mmDC_GPIO_GENLK_MASK 0x28f0 5540#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2 5541#define mmDC_GPIO_GENLK_A 0x28f1 5542#define mmDC_GPIO_GENLK_A_BASE_IDX 2 5543#define mmDC_GPIO_GENLK_EN 0x28f2 5544#define mmDC_GPIO_GENLK_EN_BASE_IDX 2 5545#define mmDC_GPIO_GENLK_Y 0x28f3 5546#define mmDC_GPIO_GENLK_Y_BASE_IDX 2 5547#define mmDC_GPIO_HPD_MASK 0x28f4 5548#define mmDC_GPIO_HPD_MASK_BASE_IDX 2 5549#define mmDC_GPIO_HPD_A 0x28f5 5550#define mmDC_GPIO_HPD_A_BASE_IDX 2 5551#define mmDC_GPIO_HPD_EN 0x28f6 5552#define mmDC_GPIO_HPD_EN_BASE_IDX 2 5553#define mmDC_GPIO_HPD_Y 0x28f7 5554#define mmDC_GPIO_HPD_Y_BASE_IDX 2 5555#define mmDC_GPIO_PWRSEQ_MASK 0x28f8 5556#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 5557#define mmDC_GPIO_PWRSEQ_A 0x28f9 5558#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2 5559#define mmDC_GPIO_PWRSEQ_EN 0x28fa 5560#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2 5561#define mmDC_GPIO_PWRSEQ_Y 0x28fb 5562#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2 5563#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc 5564#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 5565#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd 5566#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 5567#define mmPHY_AUX_CNTL 0x28ff 5568#define mmPHY_AUX_CNTL_BASE_IDX 2 5569#define mmDC_GPIO_TX12_EN 0x2915 5570#define mmDC_GPIO_TX12_EN_BASE_IDX 2 5571#define mmDC_GPIO_AUX_CTRL_0 0x2916 5572#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2 5573#define mmDC_GPIO_AUX_CTRL_1 0x2917 5574#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2 5575#define mmDC_GPIO_AUX_CTRL_2 0x2918 5576#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 5577#define mmDC_GPIO_RXEN 0x2919 5578#define mmDC_GPIO_RXEN_BASE_IDX 2 5579#define mmDC_GPIO_PULLUPEN 0x291a 5580#define mmDC_GPIO_PULLUPEN_BASE_IDX 2 5581#define mmDC_GPIO_AUX_CTRL_3 0x291b 5582#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2 5583#define mmDC_GPIO_AUX_CTRL_4 0x291c 5584#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2 5585#define mmDC_GPIO_AUX_CTRL_5 0x291d 5586#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2 5587#define mmAUXI2C_PAD_ALL_PWR_OK 0x291e 5588#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 5589 5590 5591 5592// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec 5593// base address: 0x0 5594#define mmDSC_TOP0_DSC_TOP_CONTROL 0x3000 5595#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 5596#define mmDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 5597#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 5598 5599 5600// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec 5601// base address: 0x0 5602#define mmDSCCIF0_DSCCIF_CONFIG0 0x3005 5603#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 5604#define mmDSCCIF0_DSCCIF_CONFIG1 0x3006 5605#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 5606 5607 5608// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec 5609// base address: 0x0 5610#define mmDSCC0_DSCC_CONFIG0 0x300a 5611#define mmDSCC0_DSCC_CONFIG0_BASE_IDX 2 5612#define mmDSCC0_DSCC_CONFIG1 0x300b 5613#define mmDSCC0_DSCC_CONFIG1_BASE_IDX 2 5614#define mmDSCC0_DSCC_STATUS 0x300c 5615#define mmDSCC0_DSCC_STATUS_BASE_IDX 2 5616#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d 5617#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 5618#define mmDSCC0_DSCC_PPS_CONFIG0 0x300e 5619#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 5620#define mmDSCC0_DSCC_PPS_CONFIG1 0x300f 5621#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 5622#define mmDSCC0_DSCC_PPS_CONFIG2 0x3010 5623#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 5624#define mmDSCC0_DSCC_PPS_CONFIG3 0x3011 5625#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 5626#define mmDSCC0_DSCC_PPS_CONFIG4 0x3012 5627#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 5628#define mmDSCC0_DSCC_PPS_CONFIG5 0x3013 5629#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 5630#define mmDSCC0_DSCC_PPS_CONFIG6 0x3014 5631#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 5632#define mmDSCC0_DSCC_PPS_CONFIG7 0x3015 5633#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 5634#define mmDSCC0_DSCC_PPS_CONFIG8 0x3016 5635#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 5636#define mmDSCC0_DSCC_PPS_CONFIG9 0x3017 5637#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 5638#define mmDSCC0_DSCC_PPS_CONFIG10 0x3018 5639#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 5640#define mmDSCC0_DSCC_PPS_CONFIG11 0x3019 5641#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 5642#define mmDSCC0_DSCC_PPS_CONFIG12 0x301a 5643#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 5644#define mmDSCC0_DSCC_PPS_CONFIG13 0x301b 5645#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 5646#define mmDSCC0_DSCC_PPS_CONFIG14 0x301c 5647#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 5648#define mmDSCC0_DSCC_PPS_CONFIG15 0x301d 5649#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 5650#define mmDSCC0_DSCC_PPS_CONFIG16 0x301e 5651#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 5652#define mmDSCC0_DSCC_PPS_CONFIG17 0x301f 5653#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 5654#define mmDSCC0_DSCC_PPS_CONFIG18 0x3020 5655#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 5656#define mmDSCC0_DSCC_PPS_CONFIG19 0x3021 5657#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 5658#define mmDSCC0_DSCC_PPS_CONFIG20 0x3022 5659#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 5660#define mmDSCC0_DSCC_PPS_CONFIG21 0x3023 5661#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 5662#define mmDSCC0_DSCC_PPS_CONFIG22 0x3024 5663#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 5664#define mmDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 5665#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 5666#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 5667#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 5668#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 5669#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 5670#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 5671#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 5672#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 5673#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 5674#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a 5675#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 5676#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b 5677#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 5678#define mmDSCC0_DSCC_MAX_ABS_ERROR0 0x302c 5679#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 5680#define mmDSCC0_DSCC_MAX_ABS_ERROR1 0x302d 5681#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 5682#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e 5683#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 5684#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f 5685#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 5686#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 5687#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 5688#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 5689#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 5690#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 5691#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 5692#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 5693#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 5694#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 5695#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 5696#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 5697#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 5698#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0 0x3036 5699#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 5700#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1 0x3037 5701#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 5702#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2 0x3038 5703#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 5704#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3 0x3039 5705#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 5706#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a 5707#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 5708#define mmDSCC0_DSCC_TEST_DEBUG_DATA0 0x303b 5709#define mmDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 5710#define mmDSCC0_DSCC_TEST_DEBUG_DATA1 0x303c 5711#define mmDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 5712#define mmDSCC0_DSCC_TEST_DEBUG_DATA2 0x303d 5713#define mmDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 5714#define mmDSCC0_DSCC_TEST_DEBUG_DATA3 0x303e 5715#define mmDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 5716 5717 5718// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 5719// base address: 0xc140 5720#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x3050 5721#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 5722#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x3051 5723#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 5724#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x3052 5725#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 5726#define mmDC_PERFMON12_PERFMON_CNTL 0x3053 5727#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 5728#define mmDC_PERFMON12_PERFMON_CNTL2 0x3054 5729#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 5730#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x3055 5731#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5732#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x3056 5733#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 5734#define mmDC_PERFMON12_PERFMON_HI 0x3057 5735#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2 5736#define mmDC_PERFMON12_PERFMON_LOW 0x3058 5737#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 5738 5739 5740// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec 5741// base address: 0x170 5742#define mmDSC_TOP1_DSC_TOP_CONTROL 0x305c 5743#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 5744#define mmDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 5745#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 5746 5747 5748// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec 5749// base address: 0x170 5750#define mmDSCCIF1_DSCCIF_CONFIG0 0x3061 5751#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 5752#define mmDSCCIF1_DSCCIF_CONFIG1 0x3062 5753#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 5754 5755 5756// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec 5757// base address: 0x170 5758#define mmDSCC1_DSCC_CONFIG0 0x3066 5759#define mmDSCC1_DSCC_CONFIG0_BASE_IDX 2 5760#define mmDSCC1_DSCC_CONFIG1 0x3067 5761#define mmDSCC1_DSCC_CONFIG1_BASE_IDX 2 5762#define mmDSCC1_DSCC_STATUS 0x3068 5763#define mmDSCC1_DSCC_STATUS_BASE_IDX 2 5764#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 5765#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 5766#define mmDSCC1_DSCC_PPS_CONFIG0 0x306a 5767#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 5768#define mmDSCC1_DSCC_PPS_CONFIG1 0x306b 5769#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 5770#define mmDSCC1_DSCC_PPS_CONFIG2 0x306c 5771#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 5772#define mmDSCC1_DSCC_PPS_CONFIG3 0x306d 5773#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 5774#define mmDSCC1_DSCC_PPS_CONFIG4 0x306e 5775#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 5776#define mmDSCC1_DSCC_PPS_CONFIG5 0x306f 5777#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 5778#define mmDSCC1_DSCC_PPS_CONFIG6 0x3070 5779#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 5780#define mmDSCC1_DSCC_PPS_CONFIG7 0x3071 5781#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 5782#define mmDSCC1_DSCC_PPS_CONFIG8 0x3072 5783#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 5784#define mmDSCC1_DSCC_PPS_CONFIG9 0x3073 5785#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 5786#define mmDSCC1_DSCC_PPS_CONFIG10 0x3074 5787#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 5788#define mmDSCC1_DSCC_PPS_CONFIG11 0x3075 5789#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 5790#define mmDSCC1_DSCC_PPS_CONFIG12 0x3076 5791#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 5792#define mmDSCC1_DSCC_PPS_CONFIG13 0x3077 5793#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 5794#define mmDSCC1_DSCC_PPS_CONFIG14 0x3078 5795#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 5796#define mmDSCC1_DSCC_PPS_CONFIG15 0x3079 5797#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 5798#define mmDSCC1_DSCC_PPS_CONFIG16 0x307a 5799#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 5800#define mmDSCC1_DSCC_PPS_CONFIG17 0x307b 5801#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 5802#define mmDSCC1_DSCC_PPS_CONFIG18 0x307c 5803#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 5804#define mmDSCC1_DSCC_PPS_CONFIG19 0x307d 5805#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 5806#define mmDSCC1_DSCC_PPS_CONFIG20 0x307e 5807#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 5808#define mmDSCC1_DSCC_PPS_CONFIG21 0x307f 5809#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 5810#define mmDSCC1_DSCC_PPS_CONFIG22 0x3080 5811#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 5812#define mmDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 5813#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 5814#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 5815#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 5816#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 5817#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 5818#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 5819#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 5820#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 5821#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 5822#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 5823#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 5824#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 5825#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 5826#define mmDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 5827#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 5828#define mmDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 5829#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 5830#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a 5831#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 5832#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b 5833#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 5834#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c 5835#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 5836#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d 5837#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 5838#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e 5839#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 5840#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f 5841#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 5842#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 5843#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 5844#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 5845#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 5846#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0 0x3092 5847#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 5848#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1 0x3093 5849#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 5850#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2 0x3094 5851#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 5852#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3 0x3095 5853#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 5854#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 5855#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 5856#define mmDSCC1_DSCC_TEST_DEBUG_DATA0 0x3097 5857#define mmDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 5858#define mmDSCC1_DSCC_TEST_DEBUG_DATA1 0x3098 5859#define mmDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 5860#define mmDSCC1_DSCC_TEST_DEBUG_DATA2 0x3099 5861#define mmDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 5862#define mmDSCC1_DSCC_TEST_DEBUG_DATA3 0x309a 5863#define mmDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 5864 5865 5866// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 5867// base address: 0xc2b0 5868#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x30ac 5869#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 5870#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x30ad 5871#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 5872#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x30ae 5873#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 5874#define mmDC_PERFMON13_PERFMON_CNTL 0x30af 5875#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 5876#define mmDC_PERFMON13_PERFMON_CNTL2 0x30b0 5877#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 5878#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x30b1 5879#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5880#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x30b2 5881#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 5882#define mmDC_PERFMON13_PERFMON_HI 0x30b3 5883#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2 5884#define mmDC_PERFMON13_PERFMON_LOW 0x30b4 5885#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 5886 5887 5888// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec 5889// base address: 0x0 5890#define mmDWB_ENABLE_CLK_CTRL 0x3228 5891#define mmDWB_ENABLE_CLK_CTRL_BASE_IDX 2 5892#define mmDWB_MEM_PWR_CTRL 0x3229 5893#define mmDWB_MEM_PWR_CTRL_BASE_IDX 2 5894#define mmFC_MODE_CTRL 0x322a 5895#define mmFC_MODE_CTRL_BASE_IDX 2 5896#define mmFC_FLOW_CTRL 0x322b 5897#define mmFC_FLOW_CTRL_BASE_IDX 2 5898#define mmFC_WINDOW_START 0x322c 5899#define mmFC_WINDOW_START_BASE_IDX 2 5900#define mmFC_WINDOW_SIZE 0x322d 5901#define mmFC_WINDOW_SIZE_BASE_IDX 2 5902#define mmFC_SOURCE_SIZE 0x322e 5903#define mmFC_SOURCE_SIZE_BASE_IDX 2 5904#define mmDWB_UPDATE_CTRL 0x322f 5905#define mmDWB_UPDATE_CTRL_BASE_IDX 2 5906#define mmDWB_CRC_CTRL 0x3230 5907#define mmDWB_CRC_CTRL_BASE_IDX 2 5908#define mmDWB_CRC_MASK_R_G 0x3231 5909#define mmDWB_CRC_MASK_R_G_BASE_IDX 2 5910#define mmDWB_CRC_MASK_B_A 0x3232 5911#define mmDWB_CRC_MASK_B_A_BASE_IDX 2 5912#define mmDWB_CRC_VAL_R_G 0x3233 5913#define mmDWB_CRC_VAL_R_G_BASE_IDX 2 5914#define mmDWB_CRC_VAL_B_A 0x3234 5915#define mmDWB_CRC_VAL_B_A_BASE_IDX 2 5916#define mmDWB_OUT_CTRL 0x3235 5917#define mmDWB_OUT_CTRL_BASE_IDX 2 5918#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 5919#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 5920#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 5921#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 5922#define mmDWB_HOST_READ_CONTROL 0x3238 5923#define mmDWB_HOST_READ_CONTROL_BASE_IDX 2 5924#define mmDWB_OVERFLOW_STATUS 0x3239 5925#define mmDWB_OVERFLOW_STATUS_BASE_IDX 2 5926#define mmDWB_OVERFLOW_COUNTER 0x323a 5927#define mmDWB_OVERFLOW_COUNTER_BASE_IDX 2 5928#define mmDWB_SOFT_RESET 0x323b 5929#define mmDWB_SOFT_RESET_BASE_IDX 2 5930 5931 5932// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec 5933// base address: 0xca20 5934#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x3288 5935#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 5936#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x3289 5937#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 5938#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x328a 5939#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 5940#define mmDC_PERFMON14_PERFMON_CNTL 0x328b 5941#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 5942#define mmDC_PERFMON14_PERFMON_CNTL2 0x328c 5943#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 5944#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x328d 5945#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5946#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x328e 5947#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 5948#define mmDC_PERFMON14_PERFMON_HI 0x328f 5949#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2 5950#define mmDC_PERFMON14_PERFMON_LOW 0x3290 5951#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 5952 5953 5954// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec 5955// base address: 0x0 5956#define mmDWB_HDR_MULT_COEF 0x3294 5957#define mmDWB_HDR_MULT_COEF_BASE_IDX 2 5958#define mmDWB_GAMUT_REMAP_MODE 0x3295 5959#define mmDWB_GAMUT_REMAP_MODE_BASE_IDX 2 5960#define mmDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 5961#define mmDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 5962#define mmDWB_GAMUT_REMAPA_C11_C12 0x3297 5963#define mmDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 5964#define mmDWB_GAMUT_REMAPA_C13_C14 0x3298 5965#define mmDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 5966#define mmDWB_GAMUT_REMAPA_C21_C22 0x3299 5967#define mmDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 5968#define mmDWB_GAMUT_REMAPA_C23_C24 0x329a 5969#define mmDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 5970#define mmDWB_GAMUT_REMAPA_C31_C32 0x329b 5971#define mmDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 5972#define mmDWB_GAMUT_REMAPA_C33_C34 0x329c 5973#define mmDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 5974#define mmDWB_GAMUT_REMAPB_C11_C12 0x329d 5975#define mmDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 5976#define mmDWB_GAMUT_REMAPB_C13_C14 0x329e 5977#define mmDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 5978#define mmDWB_GAMUT_REMAPB_C21_C22 0x329f 5979#define mmDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 5980#define mmDWB_GAMUT_REMAPB_C23_C24 0x32a0 5981#define mmDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 5982#define mmDWB_GAMUT_REMAPB_C31_C32 0x32a1 5983#define mmDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 5984#define mmDWB_GAMUT_REMAPB_C33_C34 0x32a2 5985#define mmDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 5986#define mmDWB_OGAM_CONTROL 0x32a3 5987#define mmDWB_OGAM_CONTROL_BASE_IDX 2 5988#define mmDWB_OGAM_LUT_INDEX 0x32a4 5989#define mmDWB_OGAM_LUT_INDEX_BASE_IDX 2 5990#define mmDWB_OGAM_LUT_DATA 0x32a5 5991#define mmDWB_OGAM_LUT_DATA_BASE_IDX 2 5992#define mmDWB_OGAM_LUT_CONTROL 0x32a6 5993#define mmDWB_OGAM_LUT_CONTROL_BASE_IDX 2 5994#define mmDWB_OGAM_RAMA_START_CNTL_B 0x32a7 5995#define mmDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 5996#define mmDWB_OGAM_RAMA_START_CNTL_G 0x32a8 5997#define mmDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 5998#define mmDWB_OGAM_RAMA_START_CNTL_R 0x32a9 5999#define mmDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 6000#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 6001#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6002#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 6003#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6004#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 6005#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6006#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 6007#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6008#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 6009#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6010#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 6011#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6012#define mmDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 6013#define mmDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 6014#define mmDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 6015#define mmDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 6016#define mmDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 6017#define mmDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 6018#define mmDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 6019#define mmDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 6020#define mmDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 6021#define mmDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 6022#define mmDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 6023#define mmDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 6024#define mmDWB_OGAM_RAMA_OFFSET_B 0x32b6 6025#define mmDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 6026#define mmDWB_OGAM_RAMA_OFFSET_G 0x32b7 6027#define mmDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 6028#define mmDWB_OGAM_RAMA_OFFSET_R 0x32b8 6029#define mmDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 6030#define mmDWB_OGAM_RAMA_REGION_0_1 0x32b9 6031#define mmDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 6032#define mmDWB_OGAM_RAMA_REGION_2_3 0x32ba 6033#define mmDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 6034#define mmDWB_OGAM_RAMA_REGION_4_5 0x32bb 6035#define mmDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 6036#define mmDWB_OGAM_RAMA_REGION_6_7 0x32bc 6037#define mmDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 6038#define mmDWB_OGAM_RAMA_REGION_8_9 0x32bd 6039#define mmDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 6040#define mmDWB_OGAM_RAMA_REGION_10_11 0x32be 6041#define mmDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 6042#define mmDWB_OGAM_RAMA_REGION_12_13 0x32bf 6043#define mmDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 6044#define mmDWB_OGAM_RAMA_REGION_14_15 0x32c0 6045#define mmDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 6046#define mmDWB_OGAM_RAMA_REGION_16_17 0x32c1 6047#define mmDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 6048#define mmDWB_OGAM_RAMA_REGION_18_19 0x32c2 6049#define mmDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 6050#define mmDWB_OGAM_RAMA_REGION_20_21 0x32c3 6051#define mmDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 6052#define mmDWB_OGAM_RAMA_REGION_22_23 0x32c4 6053#define mmDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 6054#define mmDWB_OGAM_RAMA_REGION_24_25 0x32c5 6055#define mmDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 6056#define mmDWB_OGAM_RAMA_REGION_26_27 0x32c6 6057#define mmDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 6058#define mmDWB_OGAM_RAMA_REGION_28_29 0x32c7 6059#define mmDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 6060#define mmDWB_OGAM_RAMA_REGION_30_31 0x32c8 6061#define mmDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 6062#define mmDWB_OGAM_RAMA_REGION_32_33 0x32c9 6063#define mmDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 6064#define mmDWB_OGAM_RAMB_START_CNTL_B 0x32ca 6065#define mmDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 6066#define mmDWB_OGAM_RAMB_START_CNTL_G 0x32cb 6067#define mmDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 6068#define mmDWB_OGAM_RAMB_START_CNTL_R 0x32cc 6069#define mmDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 6070#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 6071#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6072#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 6073#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6074#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 6075#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6076#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 6077#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6078#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 6079#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6080#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 6081#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6082#define mmDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 6083#define mmDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 6084#define mmDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 6085#define mmDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 6086#define mmDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 6087#define mmDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 6088#define mmDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 6089#define mmDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 6090#define mmDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 6091#define mmDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 6092#define mmDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 6093#define mmDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 6094#define mmDWB_OGAM_RAMB_OFFSET_B 0x32d9 6095#define mmDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 6096#define mmDWB_OGAM_RAMB_OFFSET_G 0x32da 6097#define mmDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 6098#define mmDWB_OGAM_RAMB_OFFSET_R 0x32db 6099#define mmDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 6100#define mmDWB_OGAM_RAMB_REGION_0_1 0x32dc 6101#define mmDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 6102#define mmDWB_OGAM_RAMB_REGION_2_3 0x32dd 6103#define mmDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 6104#define mmDWB_OGAM_RAMB_REGION_4_5 0x32de 6105#define mmDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 6106#define mmDWB_OGAM_RAMB_REGION_6_7 0x32df 6107#define mmDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 6108#define mmDWB_OGAM_RAMB_REGION_8_9 0x32e0 6109#define mmDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 6110#define mmDWB_OGAM_RAMB_REGION_10_11 0x32e1 6111#define mmDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 6112#define mmDWB_OGAM_RAMB_REGION_12_13 0x32e2 6113#define mmDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 6114#define mmDWB_OGAM_RAMB_REGION_14_15 0x32e3 6115#define mmDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 6116#define mmDWB_OGAM_RAMB_REGION_16_17 0x32e4 6117#define mmDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 6118#define mmDWB_OGAM_RAMB_REGION_18_19 0x32e5 6119#define mmDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 6120#define mmDWB_OGAM_RAMB_REGION_20_21 0x32e6 6121#define mmDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 6122#define mmDWB_OGAM_RAMB_REGION_22_23 0x32e7 6123#define mmDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 6124#define mmDWB_OGAM_RAMB_REGION_24_25 0x32e8 6125#define mmDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 6126#define mmDWB_OGAM_RAMB_REGION_26_27 0x32e9 6127#define mmDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 6128#define mmDWB_OGAM_RAMB_REGION_28_29 0x32ea 6129#define mmDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 6130#define mmDWB_OGAM_RAMB_REGION_30_31 0x32eb 6131#define mmDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 6132#define mmDWB_OGAM_RAMB_REGION_32_33 0x32ec 6133#define mmDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 6134 6135 6136// addressBlock: dce_dc_mpc_mpcc0_dispdec 6137// base address: 0x0 6138#define mmMPCC0_MPCC_TOP_SEL 0x0000 6139#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 3 6140#define mmMPCC0_MPCC_BOT_SEL 0x0001 6141#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 3 6142#define mmMPCC0_MPCC_OPP_ID 0x0002 6143#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 3 6144#define mmMPCC0_MPCC_CONTROL 0x0003 6145#define mmMPCC0_MPCC_CONTROL_BASE_IDX 3 6146#define mmMPCC0_MPCC_SM_CONTROL 0x0004 6147#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 6148#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 6149#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6150#define mmMPCC0_MPCC_TOP_GAIN 0x0006 6151#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 6152#define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 6153#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6154#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 6155#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6156#define mmMPCC0_MPCC_BG_R_CR 0x0009 6157#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 3 6158#define mmMPCC0_MPCC_BG_G_Y 0x000a 6159#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 3 6160#define mmMPCC0_MPCC_BG_B_CB 0x000b 6161#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 3 6162#define mmMPCC0_MPCC_MEM_PWR_CTRL 0x000c 6163#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6164#define mmMPCC0_MPCC_STATUS 0x000d 6165#define mmMPCC0_MPCC_STATUS_BASE_IDX 3 6166 6167 6168// addressBlock: dce_dc_mpc_mpcc1_dispdec 6169// base address: 0x80 6170#define mmMPCC1_MPCC_TOP_SEL 0x0020 6171#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 3 6172#define mmMPCC1_MPCC_BOT_SEL 0x0021 6173#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 3 6174#define mmMPCC1_MPCC_OPP_ID 0x0022 6175#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 3 6176#define mmMPCC1_MPCC_CONTROL 0x0023 6177#define mmMPCC1_MPCC_CONTROL_BASE_IDX 3 6178#define mmMPCC1_MPCC_SM_CONTROL 0x0024 6179#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 6180#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025 6181#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6182#define mmMPCC1_MPCC_TOP_GAIN 0x0026 6183#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 6184#define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027 6185#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6186#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028 6187#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6188#define mmMPCC1_MPCC_BG_R_CR 0x0029 6189#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 3 6190#define mmMPCC1_MPCC_BG_G_Y 0x002a 6191#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 3 6192#define mmMPCC1_MPCC_BG_B_CB 0x002b 6193#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 3 6194#define mmMPCC1_MPCC_MEM_PWR_CTRL 0x002c 6195#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6196#define mmMPCC1_MPCC_STATUS 0x002d 6197#define mmMPCC1_MPCC_STATUS_BASE_IDX 3 6198 6199 6200// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec 6201// base address: 0x0 6202#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100 6203#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 6204#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101 6205#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6206#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102 6207#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6208#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103 6209#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6210#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104 6211#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6212#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105 6213#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6214#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106 6215#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6216#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107 6217#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6218#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108 6219#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6220#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109 6221#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6222#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a 6223#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6224#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b 6225#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6226#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c 6227#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6228#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d 6229#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6230#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e 6231#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6232#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f 6233#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6234#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110 6235#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6236#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111 6237#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6238#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112 6239#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6240#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113 6241#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6242#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114 6243#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6244#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115 6245#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6246#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116 6247#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6248#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117 6249#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6250#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118 6251#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6252#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119 6253#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6254#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a 6255#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6256#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b 6257#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6258#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c 6259#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6260#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d 6261#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6262#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e 6263#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6264#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f 6265#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6266#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120 6267#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6268#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121 6269#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6270#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122 6271#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6272#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123 6273#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6274#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124 6275#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6276#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125 6277#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6278#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126 6279#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6280#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127 6281#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6282#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128 6283#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6284#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129 6285#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6286#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a 6287#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6288#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b 6289#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6290#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c 6291#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6292#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d 6293#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6294#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e 6295#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6296#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f 6297#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6298#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130 6299#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6300#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131 6301#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6302#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132 6303#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6304#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133 6305#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6306#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134 6307#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 6308#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135 6309#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 6310#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136 6311#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 6312#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137 6313#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 6314#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138 6315#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 6316#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139 6317#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 6318#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a 6319#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 6320#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b 6321#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6322#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c 6323#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6324#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d 6325#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6326#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e 6327#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6328#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f 6329#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6330#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140 6331#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6332#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141 6333#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6334#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142 6335#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6336#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143 6337#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6338#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144 6339#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6340#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145 6341#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6342#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146 6343#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6344#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147 6345#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6346#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148 6347#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 6348#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149 6349#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 6350#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a 6351#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6352#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b 6353#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 6354#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c 6355#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6356#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d 6357#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6358#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e 6359#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6360#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f 6361#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6362#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150 6363#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6364#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151 6365#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6366#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152 6367#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6368#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153 6369#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6370#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154 6371#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6372#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155 6373#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6374#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156 6375#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6376#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157 6377#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6378 6379 6380// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec 6381// base address: 0x200 6382#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180 6383#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 6384#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181 6385#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6386#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182 6387#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6388#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183 6389#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6390#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184 6391#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6392#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185 6393#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6394#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186 6395#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6396#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187 6397#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6398#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188 6399#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6400#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189 6401#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6402#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a 6403#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6404#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b 6405#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6406#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c 6407#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6408#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d 6409#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6410#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e 6411#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6412#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f 6413#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6414#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190 6415#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6416#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191 6417#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6418#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192 6419#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6420#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193 6421#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6422#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194 6423#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6424#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195 6425#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6426#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196 6427#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6428#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197 6429#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6430#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198 6431#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6432#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199 6433#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6434#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a 6435#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6436#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b 6437#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6438#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c 6439#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6440#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d 6441#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6442#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e 6443#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6444#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f 6445#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6446#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0 6447#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6448#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1 6449#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6450#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2 6451#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6452#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3 6453#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6454#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4 6455#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6456#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5 6457#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6458#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6 6459#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6460#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7 6461#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6462#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8 6463#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6464#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9 6465#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6466#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa 6467#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6468#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab 6469#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6470#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac 6471#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6472#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad 6473#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6474#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae 6475#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6476#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af 6477#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6478#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0 6479#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6480#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1 6481#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6482#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2 6483#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6484#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3 6485#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6486#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4 6487#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 6488#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5 6489#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 6490#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6 6491#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 6492#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7 6493#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 6494#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8 6495#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 6496#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9 6497#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 6498#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba 6499#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 6500#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb 6501#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6502#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc 6503#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6504#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd 6505#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6506#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be 6507#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6508#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf 6509#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6510#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0 6511#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6512#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1 6513#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6514#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2 6515#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6516#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3 6517#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6518#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4 6519#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6520#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5 6521#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6522#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6 6523#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6524#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7 6525#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6526#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8 6527#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 6528#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9 6529#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 6530#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca 6531#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6532#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb 6533#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 6534#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc 6535#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6536#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd 6537#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6538#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce 6539#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6540#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf 6541#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6542#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0 6543#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6544#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1 6545#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6546#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2 6547#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6548#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3 6549#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6550#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4 6551#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6552#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5 6553#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6554#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6 6555#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6556#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7 6557#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6558 6559 6560// addressBlock: dce_dc_mpc_mpc_cfg_dispdec 6561// base address: 0x0 6562#define mmMPC_CLOCK_CONTROL 0x0500 6563#define mmMPC_CLOCK_CONTROL_BASE_IDX 3 6564#define mmMPC_SOFT_RESET 0x0501 6565#define mmMPC_SOFT_RESET_BASE_IDX 3 6566#define mmMPC_CRC_CTRL 0x0502 6567#define mmMPC_CRC_CTRL_BASE_IDX 3 6568#define mmMPC_CRC_SEL_CONTROL 0x0503 6569#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 3 6570#define mmMPC_CRC_RESULT_AR 0x0504 6571#define mmMPC_CRC_RESULT_AR_BASE_IDX 3 6572#define mmMPC_CRC_RESULT_GB 0x0505 6573#define mmMPC_CRC_RESULT_GB_BASE_IDX 3 6574#define mmMPC_CRC_RESULT_C 0x0506 6575#define mmMPC_CRC_RESULT_C_BASE_IDX 3 6576#define mmMPC_PERFMON_EVENT_CTRL 0x0509 6577#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 6578#define mmMPC_BYPASS_BG_AR 0x050a 6579#define mmMPC_BYPASS_BG_AR_BASE_IDX 3 6580#define mmMPC_BYPASS_BG_GB 0x050b 6581#define mmMPC_BYPASS_BG_GB_BASE_IDX 3 6582#define mmMPC_HOST_READ_CONTROL 0x050c 6583#define mmMPC_HOST_READ_CONTROL_BASE_IDX 3 6584#define mmMPC_DPP_PENDING_STATUS 0x050d 6585#define mmMPC_DPP_PENDING_STATUS_BASE_IDX 3 6586#define mmMPC_PENDING_STATUS_MISC 0x050e 6587#define mmMPC_PENDING_STATUS_MISC_BASE_IDX 3 6588#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f 6589#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 6590#define mmADR_CFG_VUPDATE_LOCK_SET0 0x0510 6591#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 6592#define mmADR_VUPDATE_LOCK_SET0 0x0511 6593#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 3 6594#define mmCFG_VUPDATE_LOCK_SET0 0x0512 6595#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 6596#define mmCUR_VUPDATE_LOCK_SET0 0x0513 6597#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 6598#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514 6599#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 6600#define mmADR_CFG_VUPDATE_LOCK_SET1 0x0515 6601#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 6602#define mmADR_VUPDATE_LOCK_SET1 0x0516 6603#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 3 6604#define mmCFG_VUPDATE_LOCK_SET1 0x0517 6605#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 6606#define mmCUR_VUPDATE_LOCK_SET1 0x0518 6607#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 6608#define mmMPC_DWB0_MUX 0x055c 6609#define mmMPC_DWB0_MUX_BASE_IDX 3 6610 6611 6612// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec 6613// base address: 0x0 6614#define mmMPC_OUT0_MUX 0x0580 6615#define mmMPC_OUT0_MUX_BASE_IDX 3 6616#define mmMPC_OUT0_DENORM_CONTROL 0x0581 6617#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 6618#define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x0582 6619#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 6620#define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x0583 6621#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 6622#define mmMPC_OUT1_MUX 0x0584 6623#define mmMPC_OUT1_MUX_BASE_IDX 3 6624#define mmMPC_OUT1_DENORM_CONTROL 0x0585 6625#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 6626#define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x0586 6627#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 6628#define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x0587 6629#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 6630#define mmMPC_OUT_CSC_COEF_FORMAT 0x0598 6631#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 6632#define mmMPC_OUT0_CSC_MODE 0x0599 6633#define mmMPC_OUT0_CSC_MODE_BASE_IDX 3 6634#define mmMPC_OUT0_CSC_C11_C12_A 0x059a 6635#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 6636#define mmMPC_OUT0_CSC_C13_C14_A 0x059b 6637#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 6638#define mmMPC_OUT0_CSC_C21_C22_A 0x059c 6639#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 6640#define mmMPC_OUT0_CSC_C23_C24_A 0x059d 6641#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 6642#define mmMPC_OUT0_CSC_C31_C32_A 0x059e 6643#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 6644#define mmMPC_OUT0_CSC_C33_C34_A 0x059f 6645#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 6646#define mmMPC_OUT0_CSC_C11_C12_B 0x05a0 6647#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 6648#define mmMPC_OUT0_CSC_C13_C14_B 0x05a1 6649#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 6650#define mmMPC_OUT0_CSC_C21_C22_B 0x05a2 6651#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 6652#define mmMPC_OUT0_CSC_C23_C24_B 0x05a3 6653#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 6654#define mmMPC_OUT0_CSC_C31_C32_B 0x05a4 6655#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 6656#define mmMPC_OUT0_CSC_C33_C34_B 0x05a5 6657#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 6658#define mmMPC_OUT1_CSC_MODE 0x05a6 6659#define mmMPC_OUT1_CSC_MODE_BASE_IDX 3 6660#define mmMPC_OUT1_CSC_C11_C12_A 0x05a7 6661#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 6662#define mmMPC_OUT1_CSC_C13_C14_A 0x05a8 6663#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 6664#define mmMPC_OUT1_CSC_C21_C22_A 0x05a9 6665#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 6666#define mmMPC_OUT1_CSC_C23_C24_A 0x05aa 6667#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 6668#define mmMPC_OUT1_CSC_C31_C32_A 0x05ab 6669#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 6670#define mmMPC_OUT1_CSC_C33_C34_A 0x05ac 6671#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 6672#define mmMPC_OUT1_CSC_C11_C12_B 0x05ad 6673#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 6674#define mmMPC_OUT1_CSC_C13_C14_B 0x05ae 6675#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 6676#define mmMPC_OUT1_CSC_C21_C22_B 0x05af 6677#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 6678#define mmMPC_OUT1_CSC_C23_C24_B 0x05b0 6679#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 6680#define mmMPC_OUT1_CSC_C31_C32_B 0x05b1 6681#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 6682#define mmMPC_OUT1_CSC_C33_C34_B 0x05b2 6683#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 6684 6685 6686// addressBlock: dce_dc_mpc_mpc_rmu_dispdec 6687// base address: 0x0 6688#define mmMPC_RMU_CONTROL 0x0680 6689#define mmMPC_RMU_CONTROL_BASE_IDX 3 6690#define mmMPC_RMU_MEM_PWR_CTRL 0x0681 6691#define mmMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3 6692#define mmMPC_RMU0_SHAPER_CONTROL 0x0682 6693#define mmMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3 6694#define mmMPC_RMU0_SHAPER_OFFSET_R 0x0683 6695#define mmMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3 6696#define mmMPC_RMU0_SHAPER_OFFSET_G 0x0684 6697#define mmMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3 6698#define mmMPC_RMU0_SHAPER_OFFSET_B 0x0685 6699#define mmMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3 6700#define mmMPC_RMU0_SHAPER_SCALE_R 0x0686 6701#define mmMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3 6702#define mmMPC_RMU0_SHAPER_SCALE_G_B 0x0687 6703#define mmMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3 6704#define mmMPC_RMU0_SHAPER_LUT_INDEX 0x0688 6705#define mmMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3 6706#define mmMPC_RMU0_SHAPER_LUT_DATA 0x0689 6707#define mmMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3 6708#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a 6709#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 6710#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b 6711#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 6712#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c 6713#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 6714#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d 6715#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 6716#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e 6717#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 6718#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f 6719#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 6720#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690 6721#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 6722#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691 6723#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 6724#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692 6725#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 6726#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693 6727#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 6728#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694 6729#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 6730#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695 6731#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 6732#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696 6733#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 6734#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697 6735#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 6736#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698 6737#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 6738#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699 6739#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 6740#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a 6741#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 6742#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b 6743#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 6744#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c 6745#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 6746#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d 6747#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 6748#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e 6749#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 6750#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f 6751#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 6752#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0 6753#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 6754#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1 6755#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 6756#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2 6757#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 6758#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3 6759#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 6760#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4 6761#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 6762#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5 6763#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 6764#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6 6765#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 6766#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7 6767#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 6768#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8 6769#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 6770#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9 6771#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 6772#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa 6773#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 6774#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab 6775#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 6776#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac 6777#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 6778#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad 6779#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 6780#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae 6781#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 6782#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af 6783#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 6784#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0 6785#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 6786#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1 6787#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 6788#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2 6789#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 6790#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3 6791#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 6792#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4 6793#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 6794#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5 6795#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 6796#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6 6797#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 6798#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7 6799#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 6800#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8 6801#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 6802#define mmMPC_RMU0_3DLUT_MODE 0x06b9 6803#define mmMPC_RMU0_3DLUT_MODE_BASE_IDX 3 6804#define mmMPC_RMU0_3DLUT_INDEX 0x06ba 6805#define mmMPC_RMU0_3DLUT_INDEX_BASE_IDX 3 6806#define mmMPC_RMU0_3DLUT_DATA 0x06bb 6807#define mmMPC_RMU0_3DLUT_DATA_BASE_IDX 3 6808#define mmMPC_RMU0_3DLUT_DATA_30BIT 0x06bc 6809#define mmMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3 6810#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd 6811#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 6812#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be 6813#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 6814#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf 6815#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3 6816#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0 6817#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3 6818#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1 6819#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3 6820// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec 6821// base address: 0x1901c 6822#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x08c7 6823#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 3 6824#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x08c8 6825#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 3 6826#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x08c9 6827#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 3 6828#define mmDC_PERFMON15_PERFMON_CNTL 0x08ca 6829#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 3 6830#define mmDC_PERFMON15_PERFMON_CNTL2 0x08cb 6831#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 3 6832#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x08cc 6833#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 6834#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x08cd 6835#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 3 6836#define mmDC_PERFMON15_PERFMON_HI 0x08ce 6837#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 3 6838#define mmDC_PERFMON15_PERFMON_LOW 0x08cf 6839#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 6840 6841 6842// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec 6843// base address: 0x2646c 6844#define mmAFMT2_AFMT_VBI_PACKET_CONTROL 0x091c 6845#define mmAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 6846#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x091d 6847#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 6848#define mmAFMT2_AFMT_60958_0 0x0920 6849#define mmAFMT2_AFMT_60958_0_BASE_IDX 3 6850#define mmAFMT2_AFMT_60958_1 0x0921 6851#define mmAFMT2_AFMT_60958_1_BASE_IDX 3 6852#define mmAFMT2_AFMT_60958_2 0x0927 6853#define mmAFMT2_AFMT_60958_2_BASE_IDX 3 6854#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x092a 6855#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 6856#define mmAFMT2_AFMT_INFOFRAME_CONTROL0 0x092b 6857#define mmAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 6858#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL 0x092d 6859#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 6860#define mmAFMT2_AFMT_MEM_PWR 0x092f 6861#define mmAFMT2_AFMT_MEM_PWR_BASE_IDX 3 6862 6863 6864// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec 6865// base address: 0x264c4 6866#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 6867#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 6868#define mmVPG2_VPG_GENERIC_PACKET_DATA 0x0932 6869#define mmVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 6870#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 6871#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 6872#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 6873#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 6874#define mmVPG2_VPG_GENERIC_STATUS 0x0935 6875#define mmVPG2_VPG_GENERIC_STATUS_BASE_IDX 3 6876 6877 6878// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec 6879// base address: 0x264f0 6880#define mmDME2_DME_CONTROL 0x093c 6881#define mmDME2_DME_CONTROL_BASE_IDX 3 6882#define mmDME2_DME_MEMORY_CONTROL 0x093d 6883#define mmDME2_DME_MEMORY_CONTROL_BASE_IDX 3 6884 6885 6886// addressBlock: dce_dc_hpo_hpo_top_dispdec 6887// base address: 0x0 6888#define mmHPO_TOP_CLOCK_CONTROL 0x0e43 6889#define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 6890 6891 6892// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec 6893// base address: 0x1a698 6894#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x0e66 6895#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 3 6896#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x0e67 6897#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 3 6898#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x0e68 6899#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 3 6900#define mmDC_PERFMON16_PERFMON_CNTL 0x0e69 6901#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 3 6902#define mmDC_PERFMON16_PERFMON_CNTL2 0x0e6a 6903#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 3 6904#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x0e6b 6905#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 6906#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x0e6c 6907#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 3 6908#define mmDC_PERFMON16_PERFMON_HI 0x0e6d 6909#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 3 6910#define mmDC_PERFMON16_PERFMON_LOW 0x0e6e 6911#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 3 6912 6913 6914// addressBlock: dce_dc_opp_abm0_dispdec 6915// base address: 0x0 6916#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 6917#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 6918#define mmABM0_BL1_PWM_USER_LEVEL 0x0e7b 6919#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 6920#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 6921#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 6922#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 6923#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 6924#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 6925#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 6926#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 6927#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 6928#define mmABM0_BL1_PWM_ABM_CNTL 0x0e80 6929#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 6930#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 6931#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 6932#define mmABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 6933#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 6934#define mmABM0_DC_ABM1_CNTL 0x0e83 6935#define mmABM0_DC_ABM1_CNTL_BASE_IDX 3 6936#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 6937#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 6938#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 6939#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 6940#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 6941#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 6942#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 6943#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 6944#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 6945#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 6946#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 6947#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 6948#define mmABM0_DC_ABM1_ACE_THRES_12 0x0e8a 6949#define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 6950#define mmABM0_DC_ABM1_ACE_THRES_34 0x0e8b 6951#define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 6952#define mmABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c 6953#define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 6954#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e 6955#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 6956#define mmABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f 6957#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 6958#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 6959#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 6960#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 6961#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 6962#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 6963#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 6964#define mmABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 6965#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 6966#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 6967#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 6968#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 6969#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 6970#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 6971#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 6972#define mmABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 6973#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 6974#define mmABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 6975#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 6976#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 6977#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 6978#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a 6979#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 6980#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b 6981#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 6982#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c 6983#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 6984#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d 6985#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 6986#define mmABM0_DC_ABM1_HG_RESULT_1 0x0e9e 6987#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 6988#define mmABM0_DC_ABM1_HG_RESULT_2 0x0e9f 6989#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 6990#define mmABM0_DC_ABM1_HG_RESULT_3 0x0ea0 6991#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 6992#define mmABM0_DC_ABM1_HG_RESULT_4 0x0ea1 6993#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 6994#define mmABM0_DC_ABM1_HG_RESULT_5 0x0ea2 6995#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 6996#define mmABM0_DC_ABM1_HG_RESULT_6 0x0ea3 6997#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 6998#define mmABM0_DC_ABM1_HG_RESULT_7 0x0ea4 6999#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7000#define mmABM0_DC_ABM1_HG_RESULT_8 0x0ea5 7001#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7002#define mmABM0_DC_ABM1_HG_RESULT_9 0x0ea6 7003#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7004#define mmABM0_DC_ABM1_HG_RESULT_10 0x0ea7 7005#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7006#define mmABM0_DC_ABM1_HG_RESULT_11 0x0ea8 7007#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7008#define mmABM0_DC_ABM1_HG_RESULT_12 0x0ea9 7009#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7010#define mmABM0_DC_ABM1_HG_RESULT_13 0x0eaa 7011#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7012#define mmABM0_DC_ABM1_HG_RESULT_14 0x0eab 7013#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7014#define mmABM0_DC_ABM1_HG_RESULT_15 0x0eac 7015#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7016#define mmABM0_DC_ABM1_HG_RESULT_16 0x0ead 7017#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7018#define mmABM0_DC_ABM1_HG_RESULT_17 0x0eae 7019#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7020#define mmABM0_DC_ABM1_HG_RESULT_18 0x0eaf 7021#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7022#define mmABM0_DC_ABM1_HG_RESULT_19 0x0eb0 7023#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7024#define mmABM0_DC_ABM1_HG_RESULT_20 0x0eb1 7025#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7026#define mmABM0_DC_ABM1_HG_RESULT_21 0x0eb2 7027#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7028#define mmABM0_DC_ABM1_HG_RESULT_22 0x0eb3 7029#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7030#define mmABM0_DC_ABM1_HG_RESULT_23 0x0eb4 7031#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7032#define mmABM0_DC_ABM1_HG_RESULT_24 0x0eb5 7033#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7034#define mmABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 7035#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7036 7037 7038// addressBlock: dce_dc_opp_abm1_dispdec 7039// base address: 0x104 7040#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 7041#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7042#define mmABM1_BL1_PWM_USER_LEVEL 0x0ebc 7043#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 7044#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 7045#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7046#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 7047#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7048#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 7049#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7050#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 7051#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7052#define mmABM1_BL1_PWM_ABM_CNTL 0x0ec1 7053#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 7054#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 7055#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7056#define mmABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 7057#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7058#define mmABM1_DC_ABM1_CNTL 0x0ec4 7059#define mmABM1_DC_ABM1_CNTL_BASE_IDX 3 7060#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 7061#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7062#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 7063#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7064#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 7065#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7066#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 7067#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7068#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 7069#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7070#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca 7071#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7072#define mmABM1_DC_ABM1_ACE_THRES_12 0x0ecb 7073#define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7074#define mmABM1_DC_ABM1_ACE_THRES_34 0x0ecc 7075#define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7076#define mmABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd 7077#define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7078#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf 7079#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7080#define mmABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 7081#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7082#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 7083#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7084#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 7085#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7086#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 7087#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7088#define mmABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 7089#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7090#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 7091#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7092#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 7093#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7094#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 7095#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7096#define mmABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 7097#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7098#define mmABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 7099#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7100#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda 7101#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7102#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb 7103#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7104#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc 7105#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7106#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd 7107#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7108#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede 7109#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7110#define mmABM1_DC_ABM1_HG_RESULT_1 0x0edf 7111#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7112#define mmABM1_DC_ABM1_HG_RESULT_2 0x0ee0 7113#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7114#define mmABM1_DC_ABM1_HG_RESULT_3 0x0ee1 7115#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7116#define mmABM1_DC_ABM1_HG_RESULT_4 0x0ee2 7117#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7118#define mmABM1_DC_ABM1_HG_RESULT_5 0x0ee3 7119#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7120#define mmABM1_DC_ABM1_HG_RESULT_6 0x0ee4 7121#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7122#define mmABM1_DC_ABM1_HG_RESULT_7 0x0ee5 7123#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7124#define mmABM1_DC_ABM1_HG_RESULT_8 0x0ee6 7125#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7126#define mmABM1_DC_ABM1_HG_RESULT_9 0x0ee7 7127#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7128#define mmABM1_DC_ABM1_HG_RESULT_10 0x0ee8 7129#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7130#define mmABM1_DC_ABM1_HG_RESULT_11 0x0ee9 7131#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7132#define mmABM1_DC_ABM1_HG_RESULT_12 0x0eea 7133#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7134#define mmABM1_DC_ABM1_HG_RESULT_13 0x0eeb 7135#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7136#define mmABM1_DC_ABM1_HG_RESULT_14 0x0eec 7137#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7138#define mmABM1_DC_ABM1_HG_RESULT_15 0x0eed 7139#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7140#define mmABM1_DC_ABM1_HG_RESULT_16 0x0eee 7141#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7142#define mmABM1_DC_ABM1_HG_RESULT_17 0x0eef 7143#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7144#define mmABM1_DC_ABM1_HG_RESULT_18 0x0ef0 7145#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7146#define mmABM1_DC_ABM1_HG_RESULT_19 0x0ef1 7147#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7148#define mmABM1_DC_ABM1_HG_RESULT_20 0x0ef2 7149#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7150#define mmABM1_DC_ABM1_HG_RESULT_21 0x0ef3 7151#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7152#define mmABM1_DC_ABM1_HG_RESULT_22 0x0ef4 7153#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7154#define mmABM1_DC_ABM1_HG_RESULT_23 0x0ef5 7155#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7156#define mmABM1_DC_ABM1_HG_RESULT_24 0x0ef6 7157#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7158#define mmABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 7159#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7160 7161 7162// addressBlock: dce_dc_hda_azcontroller_azdec 7163// base address: 0x0 7164#define mmCORB_WRITE_POINTER 0x0000 7165#define mmCORB_WRITE_POINTER_BASE_IDX 0 7166#define mmCORB_READ_POINTER 0x0000 7167#define mmCORB_READ_POINTER_BASE_IDX 0 7168#define mmCORB_CONTROL 0x0001 7169#define mmCORB_CONTROL_BASE_IDX 0 7170#define mmCORB_STATUS 0x0001 7171#define mmCORB_STATUS_BASE_IDX 0 7172#define mmCORB_SIZE 0x0001 7173#define mmCORB_SIZE_BASE_IDX 0 7174#define mmRIRB_LOWER_BASE_ADDRESS 0x0002 7175#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 7176#define mmRIRB_UPPER_BASE_ADDRESS 0x0003 7177#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 7178#define mmRIRB_WRITE_POINTER 0x0004 7179#define mmRIRB_WRITE_POINTER_BASE_IDX 0 7180#define mmRESPONSE_INTERRUPT_COUNT 0x0004 7181#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0 7182#define mmRIRB_CONTROL 0x0005 7183#define mmRIRB_CONTROL_BASE_IDX 0 7184#define mmRIRB_STATUS 0x0005 7185#define mmRIRB_STATUS_BASE_IDX 0 7186#define mmRIRB_SIZE 0x0005 7187#define mmRIRB_SIZE_BASE_IDX 0 7188#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 7189#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 7190#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 7191#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 7192#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 7193#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 7194#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 7195#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 7196#define mmIMMEDIATE_COMMAND_STATUS 0x0008 7197#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0 7198#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a 7199#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 7200#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b 7201#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 7202#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c 7203#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 7204 7205 7206// addressBlock: dce_dc_hda_azendpoint_azdec 7207// base address: 0x0 7208#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 7209#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 7210#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 7211#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 7212 7213 7214// addressBlock: dce_dc_hda_azinputendpoint_azdec 7215// base address: 0x0 7216#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 7217#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 7218#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 7219#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 7220 7221 7222 7223// addressBlock: vga_vgaseqind 7224// base address: 0x0 7225#define ixSEQ00 0x0000 7226#define ixSEQ01 0x0001 7227#define ixSEQ02 0x0002 7228#define ixSEQ03 0x0003 7229#define ixSEQ04 0x0004 7230 7231 7232// addressBlock: vga_vgacrtind 7233// base address: 0x0 7234#define ixCRT00 0x0000 7235#define ixCRT01 0x0001 7236#define ixCRT02 0x0002 7237#define ixCRT03 0x0003 7238#define ixCRT04 0x0004 7239#define ixCRT05 0x0005 7240#define ixCRT06 0x0006 7241#define ixCRT07 0x0007 7242#define ixCRT08 0x0008 7243#define ixCRT09 0x0009 7244#define ixCRT0A 0x000a 7245#define ixCRT0B 0x000b 7246#define ixCRT0C 0x000c 7247#define ixCRT0D 0x000d 7248#define ixCRT0E 0x000e 7249#define ixCRT0F 0x000f 7250#define ixCRT10 0x0010 7251#define ixCRT11 0x0011 7252#define ixCRT12 0x0012 7253#define ixCRT13 0x0013 7254#define ixCRT14 0x0014 7255#define ixCRT15 0x0015 7256#define ixCRT16 0x0016 7257#define ixCRT17 0x0017 7258#define ixCRT18 0x0018 7259#define ixCRT1E 0x001e 7260#define ixCRT1F 0x001f 7261#define ixCRT22 0x0022 7262 7263 7264// addressBlock: vga_vgagrphind 7265// base address: 0x0 7266#define ixGRA00 0x0000 7267#define ixGRA01 0x0001 7268#define ixGRA02 0x0002 7269#define ixGRA03 0x0003 7270#define ixGRA04 0x0004 7271#define ixGRA05 0x0005 7272#define ixGRA06 0x0006 7273#define ixGRA07 0x0007 7274#define ixGRA08 0x0008 7275 7276 7277// addressBlock: vga_vgaattrind 7278// base address: 0x0 7279#define ixATTR00 0x0000 7280#define ixATTR01 0x0001 7281#define ixATTR02 0x0002 7282#define ixATTR03 0x0003 7283#define ixATTR04 0x0004 7284#define ixATTR05 0x0005 7285#define ixATTR06 0x0006 7286#define ixATTR07 0x0007 7287#define ixATTR08 0x0008 7288#define ixATTR09 0x0009 7289#define ixATTR0A 0x000a 7290#define ixATTR0B 0x000b 7291#define ixATTR0C 0x000c 7292#define ixATTR0D 0x000d 7293#define ixATTR0E 0x000e 7294#define ixATTR0F 0x000f 7295#define ixATTR10 0x0010 7296#define ixATTR11 0x0011 7297#define ixATTR12 0x0012 7298#define ixATTR13 0x0013 7299#define ixATTR14 0x0014 7300 7301 7302// addressBlock: azendpoint_f2codecind 7303// base address: 0x0 7304#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 7305#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 7306#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 7307#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 7308#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 7309#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 7310#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 7311#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 7312#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 7313#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 7314#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 7315#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 7316#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 7317#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 7318#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 7319#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 7320#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 7321#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 7322#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 7323#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 7324#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 7325#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 7326#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 7327#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 7328#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 7329#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 7330#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 7331#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 7332#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 7333#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 7334#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 7335#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 7336#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 7337#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 7338#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 7339#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 7340#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 7341#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 7342#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 7343#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 7344#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 7345#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 7346#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 7347#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 7348#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 7349#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 7350#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 7351#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 7352#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 7353#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 7354#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 7355#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 7356#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 7357#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 7358#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 7359#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 7360#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 7361#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 7362 7363 7364// addressBlock: azendpoint_descriptorind 7365// base address: 0x0 7366#define ixAUDIO_DESCRIPTOR0 0x0001 7367#define ixAUDIO_DESCRIPTOR1 0x0002 7368#define ixAUDIO_DESCRIPTOR2 0x0003 7369#define ixAUDIO_DESCRIPTOR3 0x0004 7370#define ixAUDIO_DESCRIPTOR4 0x0005 7371#define ixAUDIO_DESCRIPTOR5 0x0006 7372#define ixAUDIO_DESCRIPTOR6 0x0007 7373#define ixAUDIO_DESCRIPTOR7 0x0008 7374#define ixAUDIO_DESCRIPTOR8 0x0009 7375#define ixAUDIO_DESCRIPTOR9 0x000a 7376#define ixAUDIO_DESCRIPTOR10 0x000b 7377#define ixAUDIO_DESCRIPTOR11 0x000c 7378#define ixAUDIO_DESCRIPTOR12 0x000d 7379#define ixAUDIO_DESCRIPTOR13 0x000e 7380 7381 7382// addressBlock: azendpoint_sinkinfoind 7383// base address: 0x0 7384#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 7385#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 7386#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 7387#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 7388#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 7389#define ixSINK_DESCRIPTION0 0x0005 7390#define ixSINK_DESCRIPTION1 0x0006 7391#define ixSINK_DESCRIPTION2 0x0007 7392#define ixSINK_DESCRIPTION3 0x0008 7393#define ixSINK_DESCRIPTION4 0x0009 7394#define ixSINK_DESCRIPTION5 0x000a 7395#define ixSINK_DESCRIPTION6 0x000b 7396#define ixSINK_DESCRIPTION7 0x000c 7397#define ixSINK_DESCRIPTION8 0x000d 7398#define ixSINK_DESCRIPTION9 0x000e 7399#define ixSINK_DESCRIPTION10 0x000f 7400#define ixSINK_DESCRIPTION11 0x0010 7401#define ixSINK_DESCRIPTION12 0x0011 7402#define ixSINK_DESCRIPTION13 0x0012 7403#define ixSINK_DESCRIPTION14 0x0013 7404#define ixSINK_DESCRIPTION15 0x0014 7405#define ixSINK_DESCRIPTION16 0x0015 7406#define ixSINK_DESCRIPTION17 0x0016 7407 7408 7409// addressBlock: azf0controller_azinputcrc0resultind 7410// base address: 0x0 7411#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 7412#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 7413#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 7414#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 7415#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 7416#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 7417#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 7418#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 7419 7420 7421// addressBlock: azf0controller_azinputcrc1resultind 7422// base address: 0x0 7423#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 7424#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 7425#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 7426#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 7427#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 7428#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 7429#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 7430#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 7431 7432 7433// addressBlock: azf0controller_azcrc0resultind 7434// base address: 0x0 7435#define ixAZALIA_CRC0_CHANNEL0 0x0000 7436#define ixAZALIA_CRC0_CHANNEL1 0x0001 7437#define ixAZALIA_CRC0_CHANNEL2 0x0002 7438#define ixAZALIA_CRC0_CHANNEL3 0x0003 7439#define ixAZALIA_CRC0_CHANNEL4 0x0004 7440#define ixAZALIA_CRC0_CHANNEL5 0x0005 7441#define ixAZALIA_CRC0_CHANNEL6 0x0006 7442#define ixAZALIA_CRC0_CHANNEL7 0x0007 7443 7444 7445// addressBlock: azf0controller_azcrc1resultind 7446// base address: 0x0 7447#define ixAZALIA_CRC1_CHANNEL0 0x0000 7448#define ixAZALIA_CRC1_CHANNEL1 0x0001 7449#define ixAZALIA_CRC1_CHANNEL2 0x0002 7450#define ixAZALIA_CRC1_CHANNEL3 0x0003 7451#define ixAZALIA_CRC1_CHANNEL4 0x0004 7452#define ixAZALIA_CRC1_CHANNEL5 0x0005 7453#define ixAZALIA_CRC1_CHANNEL6 0x0006 7454#define ixAZALIA_CRC1_CHANNEL7 0x0007 7455 7456 7457// addressBlock: azinputendpoint_f2codecind 7458// base address: 0x0 7459#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 7460#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 7461#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 7462#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 7463#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 7464#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 7465#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 7466#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 7467#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 7468#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 7469#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 7470#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 7471#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 7472#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 7473#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 7474#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 7475#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 7476#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 7477#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 7478#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 7479#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 7480#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 7481#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 7482#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 7483#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 7484#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 7485#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 7486#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 7487#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 7488#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 7489#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 7490#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 7491 7492 7493// addressBlock: azroot_f2codecind 7494// base address: 0x0 7495#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 7496#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 7497#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 7498#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 7499#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 7500#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 7501#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 7502#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 7503#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 7504#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 7505#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 7506#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 7507#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 7508#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 7509#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 7510 7511 7512// addressBlock: azf0stream0_streamind 7513// base address: 0x0 7514#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 7515#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7516#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7517#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7518#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7519 7520 7521// addressBlock: azf0stream1_streamind 7522// base address: 0x0 7523#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 7524#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7525#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7526#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7527#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7528 7529 7530// addressBlock: azf0stream2_streamind 7531// base address: 0x0 7532#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 7533#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7534#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7535#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7536#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7537 7538 7539// addressBlock: azf0stream3_streamind 7540// base address: 0x0 7541#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 7542#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7543#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7544#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7545#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7546 7547 7548// addressBlock: azf0stream4_streamind 7549// base address: 0x0 7550#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 7551#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7552#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7553#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7554#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7555 7556 7557// addressBlock: azf0stream5_streamind 7558// base address: 0x0 7559#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 7560#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7561#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7562#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7563#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7564 7565 7566// addressBlock: azf0stream6_streamind 7567// base address: 0x0 7568#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 7569#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7570#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7571#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7572#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7573 7574 7575// addressBlock: azf0stream7_streamind 7576// base address: 0x0 7577#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 7578#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7579#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7580#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7581#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7582 7583 7584// addressBlock: azf0stream8_streamind 7585// base address: 0x0 7586#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 7587#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7588#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7589#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7590#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7591 7592 7593// addressBlock: azf0stream9_streamind 7594// base address: 0x0 7595#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 7596#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7597#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7598#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7599#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7600 7601 7602// addressBlock: azf0stream10_streamind 7603// base address: 0x0 7604#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 7605#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7606#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7607#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7608#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7609 7610 7611// addressBlock: azf0stream11_streamind 7612// base address: 0x0 7613#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 7614#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7615#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7616#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7617#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7618 7619 7620// addressBlock: azf0stream12_streamind 7621// base address: 0x0 7622#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 7623#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7624#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7625#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7626#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7627 7628 7629// addressBlock: azf0stream13_streamind 7630// base address: 0x0 7631#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 7632#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7633#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7634#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7635#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7636 7637 7638// addressBlock: azf0stream14_streamind 7639// base address: 0x0 7640#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 7641#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7642#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7643#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7644#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7645 7646 7647// addressBlock: azf0stream15_streamind 7648// base address: 0x0 7649#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 7650#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 7651#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 7652#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 7653#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 7654 7655 7656// addressBlock: azf0endpoint0_endpointind 7657// base address: 0x0 7658#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 7659#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 7660#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 7661#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 7662#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 7663#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 7664#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 7665#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 7666#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 7667#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 7668#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 7669#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 7670#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 7671#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 7672#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 7673#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 7674#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 7675#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 7676#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 7677#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 7678#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 7679#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 7680#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 7681#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 7682#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 7683#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 7684#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 7685#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 7686#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 7687#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 7688#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 7689#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 7690#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 7691#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 7692#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 7693#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 7694#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 7695#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 7696#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 7697#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 7698#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 7699#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 7700#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 7701#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 7702#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 7703#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 7704#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 7705#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 7706#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 7707#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 7708#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 7709#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 7710#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 7711#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 7712#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 7713#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 7714#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 7715#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 7716#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 7717#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 7718#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 7719#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 7720#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 7721#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 7722#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 7723#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 7724#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 7725#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 7726#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 7727#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 7728#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 7729 7730 7731// addressBlock: azf0endpoint1_endpointind 7732// base address: 0x0 7733#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 7734#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 7735#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 7736#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 7737#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 7738#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 7739#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 7740#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 7741#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 7742#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 7743#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 7744#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 7745#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 7746#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 7747#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 7748#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 7749#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 7750#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 7751#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 7752#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 7753#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 7754#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 7755#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 7756#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 7757#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 7758#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 7759#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 7760#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 7761#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 7762#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 7763#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 7764#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 7765#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 7766#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 7767#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 7768#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 7769#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 7770#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 7771#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 7772#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 7773#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 7774#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 7775#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 7776#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 7777#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 7778#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 7779#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 7780#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 7781#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 7782#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 7783#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 7784#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 7785#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 7786#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 7787#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 7788#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 7789#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 7790#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 7791#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 7792#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 7793#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 7794#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 7795#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 7796#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 7797#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 7798#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 7799#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 7800#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 7801#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 7802#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 7803#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 7804 7805 7806// addressBlock: azf0endpoint2_endpointind 7807// base address: 0x0 7808#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 7809#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 7810#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 7811#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 7812#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 7813#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 7814#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 7815#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 7816#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 7817#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 7818#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 7819#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 7820#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 7821#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 7822#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 7823#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 7824#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 7825#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 7826#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 7827#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 7828#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 7829#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 7830#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 7831#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 7832#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 7833#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 7834#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 7835#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 7836#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 7837#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 7838#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 7839#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 7840#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 7841#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 7842#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 7843#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 7844#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 7845#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 7846#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 7847#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 7848#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 7849#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 7850#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 7851#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 7852#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 7853#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 7854#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 7855#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 7856#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 7857#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 7858#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 7859#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 7860#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 7861#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 7862#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 7863#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 7864#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 7865#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 7866#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 7867#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 7868#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 7869#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 7870#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 7871#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 7872#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 7873#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 7874#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 7875#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 7876#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 7877#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 7878#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 7879 7880 7881// addressBlock: azf0endpoint3_endpointind 7882// base address: 0x0 7883#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 7884#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 7885#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 7886#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 7887#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 7888#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 7889#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 7890#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 7891#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 7892#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 7893#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 7894#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 7895#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 7896#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 7897#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 7898#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 7899#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 7900#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 7901#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 7902#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 7903#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 7904#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 7905#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 7906#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 7907#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 7908#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 7909#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 7910#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 7911#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 7912#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 7913#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 7914#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 7915#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 7916#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 7917#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 7918#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 7919#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 7920#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 7921#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 7922#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 7923#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 7924#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 7925#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 7926#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 7927#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 7928#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 7929#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 7930#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 7931#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 7932#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 7933#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 7934#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 7935#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 7936#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 7937#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 7938#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 7939#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 7940#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 7941#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 7942#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 7943#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 7944#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 7945#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 7946#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 7947#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 7948#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 7949#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 7950#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 7951#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 7952#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 7953#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 7954 7955 7956// addressBlock: azf0endpoint4_endpointind 7957// base address: 0x0 7958#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 7959#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 7960#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 7961#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 7962#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 7963#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 7964#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 7965#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 7966#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 7967#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 7968#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 7969#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 7970#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 7971#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 7972#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 7973#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 7974#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 7975#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 7976#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 7977#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 7978#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 7979#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 7980#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 7981#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 7982#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 7983#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 7984#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 7985#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 7986#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 7987#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 7988#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 7989#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 7990#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 7991#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 7992#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 7993#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 7994#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 7995#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 7996#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 7997#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 7998#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 7999#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 8000#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 8001#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 8002#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8003#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8004#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8005#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 8006#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 8007#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 8008#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 8009#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 8010#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 8011#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 8012#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 8013#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 8014#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 8015#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 8016#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 8017#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 8018#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8019#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 8020#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8021#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 8022#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 8023#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 8024#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 8025#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 8026#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 8027#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 8028#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 8029 8030 8031// addressBlock: azf0endpoint5_endpointind 8032// base address: 0x0 8033#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 8034#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 8035#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 8036#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 8037#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 8038#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 8039#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 8040#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 8041#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 8042#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 8043#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 8044#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 8045#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 8046#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 8047#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 8048#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 8049#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 8050#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 8051#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 8052#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 8053#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 8054#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 8055#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 8056#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 8057#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 8058#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 8059#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 8060#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 8061#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 8062#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 8063#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 8064#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 8065#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 8066#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 8067#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 8068#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 8069#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 8070#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 8071#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 8072#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 8073#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 8074#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 8075#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 8076#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 8077#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8078#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8079#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8080#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 8081#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 8082#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 8083#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 8084#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 8085#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 8086#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 8087#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 8088#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 8089#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 8090#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 8091#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 8092#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 8093#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8094#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 8095#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8096#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 8097#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 8098#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 8099#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 8100#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 8101#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 8102#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 8103#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 8104 8105 8106// addressBlock: azf0endpoint6_endpointind 8107// base address: 0x0 8108#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 8109#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 8110#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 8111#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 8112#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 8113#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 8114#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 8115#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 8116#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 8117#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 8118#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 8119#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 8120#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 8121#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 8122#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 8123#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 8124#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 8125#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 8126#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 8127#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 8128#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 8129#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 8130#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 8131#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 8132#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 8133#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 8134#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 8135#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 8136#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 8137#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 8138#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 8139#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 8140#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 8141#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 8142#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 8143#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 8144#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 8145#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 8146#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 8147#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 8148#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 8149#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 8150#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 8151#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 8152#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8153#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8154#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8155#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 8156#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 8157#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 8158#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 8159#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 8160#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 8161#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 8162#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 8163#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 8164#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 8165#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 8166#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 8167#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 8168#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8169#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 8170#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8171#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 8172#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 8173#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 8174#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 8175#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 8176#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 8177#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 8178#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 8179 8180 8181// addressBlock: azf0endpoint7_endpointind 8182// base address: 0x0 8183#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 8184#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 8185#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 8186#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 8187#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 8188#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 8189#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 8190#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 8191#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 8192#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 8193#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 8194#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 8195#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 8196#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 8197#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 8198#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 8199#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 8200#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 8201#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 8202#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 8203#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 8204#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 8205#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 8206#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 8207#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 8208#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 8209#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 8210#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 8211#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 8212#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 8213#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 8214#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 8215#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 8216#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 8217#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 8218#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 8219#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 8220#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 8221#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 8222#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 8223#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 8224#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 8225#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 8226#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 8227#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8228#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8229#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8230#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 8231#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 8232#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 8233#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 8234#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 8235#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 8236#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 8237#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 8238#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 8239#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 8240#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 8241#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 8242#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 8243#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8244#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 8245#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8246#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 8247#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 8248#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 8249#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 8250#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 8251#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 8252#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 8253#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 8254 8255 8256// addressBlock: azf0inputendpoint0_inputendpointind 8257// base address: 0x0 8258#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 8259#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 8260#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 8261#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 8262#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 8263#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 8264#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 8265#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 8266#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 8267#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 8268#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 8269#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 8270#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 8271#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 8272#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 8273#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8274#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8275#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8276#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8277#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 8278#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8279#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 8280#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 8281 8282 8283// addressBlock: azf0inputendpoint1_inputendpointind 8284// base address: 0x0 8285#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 8286#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 8287#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 8288#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 8289#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 8290#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 8291#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 8292#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 8293#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 8294#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 8295#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 8296#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 8297#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 8298#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 8299#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 8300#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8301#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8302#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8303#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8304#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 8305#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8306#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 8307#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 8308 8309 8310// addressBlock: azf0inputendpoint2_inputendpointind 8311// base address: 0x0 8312#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 8313#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 8314#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 8315#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 8316#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 8317#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 8318#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 8319#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 8320#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 8321#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 8322#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 8323#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 8324#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 8325#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 8326#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 8327#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8328#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8329#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8330#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8331#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 8332#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8333#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 8334#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 8335 8336 8337// addressBlock: azf0inputendpoint3_inputendpointind 8338// base address: 0x0 8339#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 8340#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 8341#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 8342#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 8343#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 8344#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 8345#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 8346#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 8347#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 8348#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 8349#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 8350#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 8351#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 8352#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 8353#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 8354#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8355#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8356#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8357#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8358#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 8359#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8360#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 8361#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 8362 8363 8364// addressBlock: azf0inputendpoint4_inputendpointind 8365// base address: 0x0 8366#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 8367#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 8368#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 8369#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 8370#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 8371#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 8372#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 8373#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 8374#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 8375#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 8376#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 8377#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 8378#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 8379#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 8380#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 8381#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8382#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8383#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8384#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8385#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 8386#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8387#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 8388#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 8389 8390 8391// addressBlock: azf0inputendpoint5_inputendpointind 8392// base address: 0x0 8393#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 8394#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 8395#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 8396#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 8397#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 8398#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 8399#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 8400#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 8401#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 8402#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 8403#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 8404#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 8405#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 8406#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 8407#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 8408#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8409#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8410#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8411#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8412#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 8413#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8414#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 8415#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 8416 8417 8418// addressBlock: azf0inputendpoint6_inputendpointind 8419// base address: 0x0 8420#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 8421#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 8422#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 8423#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 8424#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 8425#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 8426#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 8427#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 8428#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 8429#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 8430#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 8431#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 8432#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 8433#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 8434#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 8435#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8436#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8437#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8438#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8439#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 8440#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8441#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 8442#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 8443 8444 8445// addressBlock: azf0inputendpoint7_inputendpointind 8446// base address: 0x0 8447#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 8448#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 8449#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 8450#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 8451#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 8452#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 8453#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 8454#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 8455#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 8456#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 8457#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 8458#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 8459#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 8460#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 8461#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 8462#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 8463#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 8464#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 8465#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 8466#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 8467#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 8468#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 8469#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 8470 8471#endif
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