amd_cper.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright 2025 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 */
 24#ifndef __AMD_CPER_H__
 25#define __AMD_CPER_H__
 26
 27#include <linux/uuid.h>
 28
 29#define CPER_HDR_REV_1          (0x100)
 30#define CPER_SEC_MINOR_REV_1    (0x01)
 31#define CPER_SEC_MAJOR_REV_22   (0x22)
 32#define CPER_MAX_OAM_COUNT      (8)
 33
 34#define CPER_CTX_TYPE_CRASH     (1)
 35#define CPER_CTX_TYPE_BOOT      (9)
 36
 37#define CPER_CREATOR_ID_AMDGPU	"amdgpu"
 38
 39#define CPER_NOTIFY_MCE                                               \
 40	GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \
 41		  0xE1, 0x49, 0x13, 0xBB)
 42#define CPER_NOTIFY_CMC                                               \
 43	GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
 44		  0xEB, 0xD4, 0xF8, 0x90)
 45#define BOOT_TYPE                                                     \
 46	GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \
 47		  0xD4, 0x64, 0xB3, 0x8F)
 48
 49#define AMD_CRASHDUMP                                                 \
 50	GUID_INIT(0x32AC0C78, 0x2623, 0x48F6, 0xB0, 0xD0, 0x73, 0x65, \
 51		  0x72, 0x5F, 0xD6, 0xAE)
 52#define AMD_GPU_NONSTANDARD_ERROR                                     \
 53	GUID_INIT(0x32AC0C78, 0x2623, 0x48F6, 0x81, 0xA2, 0xAC, 0x69, \
 54		  0x17, 0x80, 0x55, 0x1D)
 55#define PROC_ERR_SECTION_TYPE                                         \
 56	GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \
 57		  0x24, 0x2B, 0x6E, 0x1D)
 58
 59enum cper_error_severity {
 60	CPER_SEV_NON_FATAL_UNCORRECTED = 0,
 61	CPER_SEV_FATAL                 = 1,
 62	CPER_SEV_NON_FATAL_CORRECTED   = 2,
 63	CPER_SEV_NUM                   = 3,
 64
 65	CPER_SEV_UNUSED = 10,
 66};
 67
 68enum cper_aca_reg {
 69	CPER_ACA_REG_CTL_LO    = 0,
 70	CPER_ACA_REG_CTL_HI    = 1,
 71	CPER_ACA_REG_STATUS_LO = 2,
 72	CPER_ACA_REG_STATUS_HI = 3,
 73	CPER_ACA_REG_ADDR_LO   = 4,
 74	CPER_ACA_REG_ADDR_HI   = 5,
 75	CPER_ACA_REG_MISC0_LO  = 6,
 76	CPER_ACA_REG_MISC0_HI  = 7,
 77	CPER_ACA_REG_CONFIG_LO = 8,
 78	CPER_ACA_REG_CONFIG_HI = 9,
 79	CPER_ACA_REG_IPID_LO   = 10,
 80	CPER_ACA_REG_IPID_HI   = 11,
 81	CPER_ACA_REG_SYND_LO   = 12,
 82	CPER_ACA_REG_SYND_HI   = 13,
 83
 84	CPER_ACA_REG_COUNT     = 32,
 85};
 86
 87#pragma pack(push, 1)
 88
 89struct cper_timestamp {
 90	uint8_t seconds;
 91	uint8_t minutes;
 92	uint8_t hours;
 93	uint8_t flag;
 94	uint8_t day;
 95	uint8_t month;
 96	uint8_t year;
 97	uint8_t century;
 98};
 99
100struct cper_hdr {
101	char                     signature[4];  /* "CPER"  */
102	uint16_t                 revision;
103	uint32_t                 signature_end; /* 0xFFFFFFFF */
104	uint16_t                 sec_cnt;
105	enum cper_error_severity error_severity;
106	union {
107		struct {
108			uint32_t platform_id	: 1;
109			uint32_t timestamp	: 1;
110			uint32_t partition_id	: 1;
111			uint32_t reserved	: 29;
112		} valid_bits;
113		uint32_t valid_mask;
114	};
115	uint32_t		record_length;    /* Total size of CPER Entry */
116	struct cper_timestamp	timestamp;
117	char			platform_id[16];
118	guid_t			partition_id;     /* Reserved */
119	char			creator_id[16];
120	guid_t			notify_type;      /* CMC, MCE */
121	char			record_id[8];     /* Unique CPER Entry ID */
122	uint32_t		flags;            /* Reserved */
123	uint64_t		persistence_info; /* Reserved */
124	uint8_t			reserved[12];     /* Reserved */
125};
126
127struct cper_sec_desc {
128	uint32_t sec_offset;     /* Offset from the start of CPER entry */
129	uint32_t sec_length;
130	uint8_t  revision_minor; /* CPER_SEC_MINOR_REV_1 */
131	uint8_t  revision_major; /* CPER_SEC_MAJOR_REV_22 */
132	union {
133		struct {
134			uint8_t fru_id		: 1;
135			uint8_t fru_text	: 1;
136			uint8_t reserved	: 6;
137		} valid_bits;
138		uint8_t valid_mask;
139	};
140	uint8_t reserved;
141	union {
142		struct {
143			uint32_t primary		: 1;
144			uint32_t reserved1		: 2;
145			uint32_t exceed_err_threshold	: 1;
146			uint32_t latent_err		: 1;
147			uint32_t reserved2		: 27;
148		} flag_bits;
149		uint32_t flag_mask;
150	};
151	guid_t				sec_type;
152	char				fru_id[16];
153	enum cper_error_severity	severity;
154	char				fru_text[20];
155};
156
157struct cper_sec_nonstd_err_hdr {
158	union {
159		struct {
160			uint64_t apic_id		: 1;
161			uint64_t fw_id			: 1;
162			uint64_t err_info_cnt		: 6;
163			uint64_t err_context_cnt	: 6;
164		} valid_bits;
165		uint64_t valid_mask;
166	};
167	uint64_t apic_id;
168	char     fw_id[48];
169};
170
171struct cper_sec_nonstd_err_info {
172	guid_t error_type;
173	union {
174		struct {
175			uint64_t ms_chk			: 1;
176			uint64_t target_addr_id		: 1;
177			uint64_t req_id			: 1;
178			uint64_t resp_id		: 1;
179			uint64_t instr_ptr		: 1;
180			uint64_t reserved		: 59;
181		} valid_bits;
182		uint64_t        valid_mask;
183	};
184	union {
185		struct {
186			uint64_t err_type_valid		: 1;
187			uint64_t pcc_valid		: 1;
188			uint64_t uncorr_valid		: 1;
189			uint64_t precise_ip_valid	: 1;
190			uint64_t restartable_ip_valid	: 1;
191			uint64_t overflow_valid		: 1;
192			uint64_t reserved1		: 10;
193			uint64_t err_type		: 2;
194			uint64_t pcc			: 1;
195			uint64_t uncorr			: 1;
196			uint64_t precised_ip		: 1;
197			uint64_t restartable_ip		: 1;
198			uint64_t overflow		: 1;
199			uint64_t reserved2		: 41;
200		} ms_chk_bits;
201		uint64_t ms_chk_mask;
202	};
203	uint64_t target_addr_id;
204	uint64_t req_id;
205	uint64_t resp_id;
206	uint64_t instr_ptr;
207};
208
209struct cper_sec_nonstd_err_ctx {
210	uint16_t reg_ctx_type;
211	uint16_t reg_arr_size;
212	uint32_t msr_addr;
213	uint64_t mm_reg_addr;
214	uint32_t reg_dump[CPER_ACA_REG_COUNT];
215};
216
217struct cper_sec_nonstd_err {
218	struct cper_sec_nonstd_err_hdr  hdr;
219	struct cper_sec_nonstd_err_info info;
220	struct cper_sec_nonstd_err_ctx  ctx;
221};
222
223struct cper_sec_crashdump_hdr {
224	uint64_t reserved1;
225	uint64_t reserved2;
226	char     fw_id[48];
227	uint64_t reserved3[8];
228};
229
230struct cper_sec_crashdump_reg_data {
231	uint32_t status_lo;
232	uint32_t status_hi;
233	uint32_t addr_lo;
234	uint32_t addr_hi;
235	uint32_t ipid_lo;
236	uint32_t ipid_hi;
237	uint32_t synd_lo;
238	uint32_t synd_hi;
239};
240
241struct cper_sec_crashdump_body_fatal {
242	uint16_t                           reg_ctx_type;
243	uint16_t                           reg_arr_size;
244	uint32_t                           reserved1;
245	uint64_t                           reserved2;
246	struct cper_sec_crashdump_reg_data data;
247};
248
249struct cper_sec_crashdump_body_boot {
250	uint16_t reg_ctx_type;
251	uint16_t reg_arr_size;
252	uint32_t reserved1;
253	uint64_t reserved2;
254	uint64_t msg[CPER_MAX_OAM_COUNT];
255};
256
257struct cper_sec_crashdump_fatal {
258	struct cper_sec_crashdump_hdr        hdr;
259	struct cper_sec_crashdump_body_fatal body;
260};
261
262struct cper_sec_crashdump_boot {
263	struct cper_sec_crashdump_hdr       hdr;
264	struct cper_sec_crashdump_body_boot body;
265};
266
267#pragma pack(pop)
268
269#endif