freesync.c

   1/*
   2 * Copyright 2016-2023 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "dm_services.h"
  27#include "dc.h"
  28#include "mod_freesync.h"
  29#include "core_types.h"
  30
  31#define MOD_FREESYNC_MAX_CONCURRENT_STREAMS  32
  32
  33#define MIN_REFRESH_RANGE 10
  34/* Refresh rate ramp at a fixed rate of 65 Hz/second */
  35#define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
  36/* Number of elements in the render times cache array */
  37#define RENDER_TIMES_MAX_COUNT 10
  38/* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
  39#define BTR_MAX_MARGIN 2500
  40/* Threshold to change BTR multiplier (to avoid frequent changes) */
  41#define BTR_DRIFT_MARGIN 2000
  42/* Threshold to exit fixed refresh rate */
  43#define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 1
  44/* Number of consecutive frames to check before entering/exiting fixed refresh */
  45#define FIXED_REFRESH_ENTER_FRAME_COUNT 5
  46#define FIXED_REFRESH_EXIT_FRAME_COUNT 10
  47/* Flip interval workaround constants */
  48#define VSYNCS_BETWEEN_FLIP_THRESHOLD 2
  49#define FREESYNC_CONSEC_FLIP_AFTER_VSYNC 5
  50#define FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US 500
  51#define MICRO_HZ_TO_HZ(x) (x / 1000000)
  52
  53struct core_freesync {
  54	struct mod_freesync public;
  55	struct dc *dc;
  56};
  57
  58#define MOD_FREESYNC_TO_CORE(mod_freesync)\
  59		container_of(mod_freesync, struct core_freesync, public)
  60
  61struct mod_freesync *mod_freesync_create(struct dc *dc)
  62{
  63	struct core_freesync *core_freesync =
  64			kzalloc(sizeof(struct core_freesync), GFP_KERNEL);
  65
  66	if (core_freesync == NULL)
  67		goto fail_alloc_context;
  68
  69	if (dc == NULL)
  70		goto fail_construct;
  71
  72	core_freesync->dc = dc;
  73	return &core_freesync->public;
  74
  75fail_construct:
  76	kfree(core_freesync);
  77
  78fail_alloc_context:
  79	return NULL;
  80}
  81
  82void mod_freesync_destroy(struct mod_freesync *mod_freesync)
  83{
  84	struct core_freesync *core_freesync = NULL;
  85
  86	if (mod_freesync == NULL)
  87		return;
  88	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
  89	kfree(core_freesync);
  90}
  91
  92#if 0 /* Unused currently */
  93static unsigned int calc_refresh_in_uhz_from_duration(
  94		unsigned int duration_in_ns)
  95{
  96	unsigned int refresh_in_uhz =
  97			((unsigned int)(div64_u64((1000000000ULL * 1000000),
  98					duration_in_ns)));
  99	return refresh_in_uhz;
 100}
 101#endif
 102
 103static unsigned int calc_duration_in_us_from_refresh_in_uhz(
 104		unsigned int refresh_in_uhz)
 105{
 106	unsigned int duration_in_us =
 107			((unsigned int)(div64_u64((1000000000ULL * 1000),
 108					refresh_in_uhz)));
 109	return duration_in_us;
 110}
 111
 112static unsigned int calc_duration_in_us_from_v_total(
 113		const struct dc_stream_state *stream,
 114		const struct mod_vrr_params *in_vrr,
 115		unsigned int v_total)
 116{
 117	unsigned int duration_in_us =
 118			(unsigned int)(div64_u64(((unsigned long long)(v_total)
 119				* 10000) * stream->timing.h_total,
 120					stream->timing.pix_clk_100hz));
 121
 122	return duration_in_us;
 123}
 124
 125static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)
 126{
 127	unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;
 128
 129	if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {
 130		max_hw_v_total -= stream->timing.v_front_porch + 1;
 131	}
 132
 133	return max_hw_v_total;
 134}
 135
 136unsigned int mod_freesync_calc_v_total_from_refresh(
 137		const struct dc_stream_state *stream,
 138		unsigned int refresh_in_uhz)
 139{
 140	unsigned int v_total;
 141	unsigned int frame_duration_in_ns;
 142
 143	if (refresh_in_uhz == 0)
 144		return stream->timing.v_total;
 145
 146	frame_duration_in_ns =
 147			((unsigned int)(div64_u64((1000000000ULL * 1000000),
 148					refresh_in_uhz)));
 149
 150	if (refresh_in_uhz <= stream->timing.min_refresh_in_uhz) {
 151		/* When the target refresh rate is the minimum panel refresh rate,
 152		 * round down the vtotal value to avoid stretching vblank over
 153		 * panel's vtotal boundary.
 154		 */
 155		v_total = div64_u64(div64_u64(((unsigned long long)(
 156				frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
 157				stream->timing.h_total), 1000000);
 158	} else if (refresh_in_uhz >= stream->timing.max_refresh_in_uhz) {
 159		/* When the target refresh rate is the maximum panel refresh rate
 160		 * round up the vtotal value to prevent off-by-one error causing
 161		 * v_total_min to be below the panel's lower bound
 162		 */
 163		v_total = div64_u64(div64_u64(((unsigned long long)(
 164				frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
 165				stream->timing.h_total) + (1000000 - 1), 1000000);
 166	} else {
 167		v_total = div64_u64(div64_u64(((unsigned long long)(
 168				frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
 169				stream->timing.h_total) + 500000, 1000000);
 170	}
 171
 172	/* v_total cannot be less than nominal */
 173	if (v_total < stream->timing.v_total) {
 174		ASSERT(v_total < stream->timing.v_total);
 175		v_total = stream->timing.v_total;
 176	}
 177
 178	return v_total;
 179}
 180
 181static unsigned int calc_v_total_from_duration(
 182		const struct dc_stream_state *stream,
 183		const struct mod_vrr_params *vrr,
 184		unsigned int duration_in_us)
 185{
 186	unsigned int v_total = 0;
 187
 188	if (duration_in_us < vrr->min_duration_in_us)
 189		duration_in_us = vrr->min_duration_in_us;
 190
 191	if (duration_in_us > vrr->max_duration_in_us)
 192		duration_in_us = vrr->max_duration_in_us;
 193
 194	if (dc_is_hdmi_signal(stream->signal)) { // change for HDMI to comply with spec
 195		uint32_t h_total_up_scaled;
 196
 197		h_total_up_scaled = stream->timing.h_total * 10000;
 198		v_total = div_u64((unsigned long long)duration_in_us
 199					* stream->timing.pix_clk_100hz + (h_total_up_scaled - 1),
 200					h_total_up_scaled); //ceiling for MMax and MMin for MVRR
 201	} else {
 202		v_total = div64_u64(div64_u64(((unsigned long long)(
 203					duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
 204					stream->timing.h_total), 1000);
 205	}
 206
 207	/* v_total cannot be less than nominal */
 208	if (v_total < stream->timing.v_total) {
 209		ASSERT(v_total < stream->timing.v_total);
 210		v_total = stream->timing.v_total;
 211	}
 212
 213	return v_total;
 214}
 215
 216static void update_v_total_for_static_ramp(
 217		struct core_freesync *core_freesync,
 218		const struct dc_stream_state *stream,
 219		struct mod_vrr_params *in_out_vrr)
 220{
 221	unsigned int v_total = 0;
 222	unsigned int current_duration_in_us =
 223			calc_duration_in_us_from_v_total(
 224				stream, in_out_vrr,
 225				in_out_vrr->adjust.v_total_max);
 226	unsigned int target_duration_in_us =
 227			calc_duration_in_us_from_refresh_in_uhz(
 228				in_out_vrr->fixed.target_refresh_in_uhz);
 229	bool ramp_direction_is_up = current_duration_in_us >
 230				target_duration_in_us;
 231
 232	/* Calculate ratio between new and current frame duration with 3 digit */
 233	unsigned int frame_duration_ratio = div64_u64(1000000,
 234		(1000 +  div64_u64(((unsigned long long)(
 235		STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) *
 236		current_duration_in_us),
 237		1000000)));
 238
 239	/* Calculate delta between new and current frame duration in us */
 240	unsigned int frame_duration_delta = div64_u64(((unsigned long long)(
 241		current_duration_in_us) *
 242		(1000 - frame_duration_ratio)), 1000);
 243
 244	/* Adjust frame duration delta based on ratio between current and
 245	 * standard frame duration (frame duration at 60 Hz refresh rate).
 246	 */
 247	unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)(
 248		frame_duration_delta) * current_duration_in_us), 16666);
 249
 250	/* Going to a higher refresh rate (lower frame duration) */
 251	if (ramp_direction_is_up) {
 252		/* Reduce frame duration */
 253		current_duration_in_us -= ramp_rate_interpolated;
 254
 255		/* Adjust for frame duration below min */
 256		if (current_duration_in_us <= target_duration_in_us) {
 257			in_out_vrr->fixed.ramping_active = false;
 258			in_out_vrr->fixed.ramping_done = true;
 259			current_duration_in_us =
 260				calc_duration_in_us_from_refresh_in_uhz(
 261				in_out_vrr->fixed.target_refresh_in_uhz);
 262		}
 263	/* Going to a lower refresh rate (larger frame duration) */
 264	} else {
 265		/* Increase frame duration */
 266		current_duration_in_us += ramp_rate_interpolated;
 267
 268		/* Adjust for frame duration above max */
 269		if (current_duration_in_us >= target_duration_in_us) {
 270			in_out_vrr->fixed.ramping_active = false;
 271			in_out_vrr->fixed.ramping_done = true;
 272			current_duration_in_us =
 273				calc_duration_in_us_from_refresh_in_uhz(
 274				in_out_vrr->fixed.target_refresh_in_uhz);
 275		}
 276	}
 277
 278	v_total = div64_u64(div64_u64(((unsigned long long)(
 279			current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
 280				stream->timing.h_total), 1000);
 281
 282	/* v_total cannot be less than nominal */
 283	if (v_total < stream->timing.v_total)
 284		v_total = stream->timing.v_total;
 285
 286	in_out_vrr->adjust.v_total_min = v_total;
 287	in_out_vrr->adjust.v_total_max = v_total;
 288}
 289
 290static void apply_below_the_range(struct core_freesync *core_freesync,
 291		const struct dc_stream_state *stream,
 292		unsigned int last_render_time_in_us,
 293		struct mod_vrr_params *in_out_vrr)
 294{
 295	unsigned int inserted_frame_duration_in_us = 0;
 296	unsigned int mid_point_frames_ceil = 0;
 297	unsigned int mid_point_frames_floor = 0;
 298	unsigned int frame_time_in_us = 0;
 299	unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
 300	unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
 301	unsigned int frames_to_insert = 0;
 302	unsigned int delta_from_mid_point_delta_in_us;
 303	unsigned int max_render_time_in_us =
 304			in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us;
 305
 306	/* Program BTR */
 307	if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) {
 308		/* Exit Below the Range */
 309		if (in_out_vrr->btr.btr_active) {
 310			in_out_vrr->btr.frame_counter = 0;
 311			in_out_vrr->btr.btr_active = false;
 312		}
 313	} else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) {
 314		/* Enter Below the Range */
 315		if (!in_out_vrr->btr.btr_active)
 316			in_out_vrr->btr.btr_active = true;
 317	}
 318
 319	/* BTR set to "not active" so disengage */
 320	if (!in_out_vrr->btr.btr_active) {
 321		in_out_vrr->btr.inserted_duration_in_us = 0;
 322		in_out_vrr->btr.frames_to_insert = 0;
 323		in_out_vrr->btr.frame_counter = 0;
 324
 325		/* Restore FreeSync */
 326		in_out_vrr->adjust.v_total_min =
 327			mod_freesync_calc_v_total_from_refresh(stream,
 328				in_out_vrr->max_refresh_in_uhz);
 329		in_out_vrr->adjust.v_total_max =
 330			mod_freesync_calc_v_total_from_refresh(stream,
 331				in_out_vrr->min_refresh_in_uhz);
 332	/* BTR set to "active" so engage */
 333	} else {
 334
 335		/* Calculate number of midPoint frames that could fit within
 336		 * the render time interval - take ceil of this value
 337		 */
 338		mid_point_frames_ceil = (last_render_time_in_us +
 339				in_out_vrr->btr.mid_point_in_us - 1) /
 340					in_out_vrr->btr.mid_point_in_us;
 341
 342		if (mid_point_frames_ceil > 0) {
 343			frame_time_in_us = last_render_time_in_us /
 344				mid_point_frames_ceil;
 345			delta_from_mid_point_in_us_1 =
 346				(in_out_vrr->btr.mid_point_in_us >
 347				frame_time_in_us) ?
 348				(in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
 349				(frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
 350		}
 351
 352		/* Calculate number of midPoint frames that could fit within
 353		 * the render time interval - take floor of this value
 354		 */
 355		mid_point_frames_floor = last_render_time_in_us /
 356				in_out_vrr->btr.mid_point_in_us;
 357
 358		if (mid_point_frames_floor > 0) {
 359
 360			frame_time_in_us = last_render_time_in_us /
 361				mid_point_frames_floor;
 362			delta_from_mid_point_in_us_2 =
 363				(in_out_vrr->btr.mid_point_in_us >
 364				frame_time_in_us) ?
 365				(in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
 366				(frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
 367		}
 368
 369		/* Choose number of frames to insert based on how close it
 370		 * can get to the mid point of the variable range.
 371		 *  - Delta for CEIL: delta_from_mid_point_in_us_1
 372		 *  - Delta for FLOOR: delta_from_mid_point_in_us_2
 373		 */
 374		if (mid_point_frames_ceil &&
 375		    (last_render_time_in_us / mid_point_frames_ceil) <
 376		    in_out_vrr->min_duration_in_us) {
 377			/* Check for out of range.
 378			 * If using CEIL produces a value that is out of range,
 379			 * then we are forced to use FLOOR.
 380			 */
 381			frames_to_insert = mid_point_frames_floor;
 382		} else if (mid_point_frames_floor < 2) {
 383			/* Check if FLOOR would result in non-LFC. In this case
 384			 * choose to use CEIL
 385			 */
 386			frames_to_insert = mid_point_frames_ceil;
 387		} else if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
 388			/* If choosing CEIL results in a frame duration that is
 389			 * closer to the mid point of the range.
 390			 * Choose CEIL
 391			 */
 392			frames_to_insert = mid_point_frames_ceil;
 393		} else {
 394			/* If choosing FLOOR results in a frame duration that is
 395			 * closer to the mid point of the range.
 396			 * Choose FLOOR
 397			 */
 398			frames_to_insert = mid_point_frames_floor;
 399		}
 400
 401		/* Prefer current frame multiplier when BTR is enabled unless it drifts
 402		 * too far from the midpoint
 403		 */
 404		if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
 405			delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
 406					delta_from_mid_point_in_us_1;
 407		} else {
 408			delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 -
 409					delta_from_mid_point_in_us_2;
 410		}
 411		if (in_out_vrr->btr.frames_to_insert != 0 &&
 412				delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {
 413			if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <
 414					max_render_time_in_us) &&
 415				((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) >
 416					in_out_vrr->min_duration_in_us))
 417				frames_to_insert = in_out_vrr->btr.frames_to_insert;
 418		}
 419
 420		/* Either we've calculated the number of frames to insert,
 421		 * or we need to insert min duration frames
 422		 */
 423		if (frames_to_insert &&
 424		    (last_render_time_in_us / frames_to_insert) <
 425		    in_out_vrr->min_duration_in_us){
 426			frames_to_insert -= (frames_to_insert > 1) ?
 427					1 : 0;
 428		}
 429
 430		if (frames_to_insert > 0)
 431			inserted_frame_duration_in_us = last_render_time_in_us /
 432							frames_to_insert;
 433
 434		if (inserted_frame_duration_in_us < in_out_vrr->min_duration_in_us)
 435			inserted_frame_duration_in_us = in_out_vrr->min_duration_in_us;
 436
 437		/* Cache the calculated variables */
 438		in_out_vrr->btr.inserted_duration_in_us =
 439			inserted_frame_duration_in_us;
 440		in_out_vrr->btr.frames_to_insert = frames_to_insert;
 441		in_out_vrr->btr.frame_counter = frames_to_insert;
 442	}
 443}
 444
 445static void apply_fixed_refresh(struct core_freesync *core_freesync,
 446		const struct dc_stream_state *stream,
 447		unsigned int last_render_time_in_us,
 448		struct mod_vrr_params *in_out_vrr)
 449{
 450	bool update = false;
 451	unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
 452
 453	/* Compute the exit refresh rate and exit frame duration */
 454	unsigned int exit_refresh_rate_in_milli_hz = ((1000000000/max_render_time_in_us)
 455			+ (1000*FIXED_REFRESH_EXIT_MARGIN_IN_HZ));
 456	unsigned int exit_frame_duration_in_us = 1000000000/exit_refresh_rate_in_milli_hz;
 457
 458	if (last_render_time_in_us < exit_frame_duration_in_us) {
 459		/* Exit Fixed Refresh mode */
 460		if (in_out_vrr->fixed.fixed_active) {
 461			in_out_vrr->fixed.frame_counter++;
 462
 463			if (in_out_vrr->fixed.frame_counter >
 464					FIXED_REFRESH_EXIT_FRAME_COUNT) {
 465				in_out_vrr->fixed.frame_counter = 0;
 466				in_out_vrr->fixed.fixed_active = false;
 467				in_out_vrr->fixed.target_refresh_in_uhz = 0;
 468				update = true;
 469			}
 470		} else
 471			in_out_vrr->fixed.frame_counter = 0;
 472	} else if (last_render_time_in_us > max_render_time_in_us) {
 473		/* Enter Fixed Refresh mode */
 474		if (!in_out_vrr->fixed.fixed_active) {
 475			in_out_vrr->fixed.frame_counter++;
 476
 477			if (in_out_vrr->fixed.frame_counter >
 478					FIXED_REFRESH_ENTER_FRAME_COUNT) {
 479				in_out_vrr->fixed.frame_counter = 0;
 480				in_out_vrr->fixed.fixed_active = true;
 481				in_out_vrr->fixed.target_refresh_in_uhz =
 482						in_out_vrr->max_refresh_in_uhz;
 483				update = true;
 484			}
 485		} else
 486			in_out_vrr->fixed.frame_counter = 0;
 487	}
 488
 489	if (update) {
 490		if (in_out_vrr->fixed.fixed_active) {
 491			in_out_vrr->adjust.v_total_min =
 492				mod_freesync_calc_v_total_from_refresh(
 493				stream, in_out_vrr->max_refresh_in_uhz);
 494			in_out_vrr->adjust.v_total_max =
 495					in_out_vrr->adjust.v_total_min;
 496		} else {
 497			in_out_vrr->adjust.v_total_min =
 498				mod_freesync_calc_v_total_from_refresh(stream,
 499					in_out_vrr->max_refresh_in_uhz);
 500			in_out_vrr->adjust.v_total_max =
 501				mod_freesync_calc_v_total_from_refresh(stream,
 502					in_out_vrr->min_refresh_in_uhz);
 503		}
 504	}
 505}
 506
 507static void determine_flip_interval_workaround_req(struct mod_vrr_params *in_vrr,
 508		unsigned int curr_time_stamp_in_us)
 509{
 510	in_vrr->flip_interval.vsync_to_flip_in_us = curr_time_stamp_in_us -
 511			in_vrr->flip_interval.v_update_timestamp_in_us;
 512
 513	/* Determine conditions for stopping workaround */
 514	if (in_vrr->flip_interval.flip_interval_workaround_active &&
 515			in_vrr->flip_interval.vsyncs_between_flip < VSYNCS_BETWEEN_FLIP_THRESHOLD &&
 516			in_vrr->flip_interval.vsync_to_flip_in_us > FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
 517		in_vrr->flip_interval.flip_interval_detect_counter = 0;
 518		in_vrr->flip_interval.program_flip_interval_workaround = true;
 519		in_vrr->flip_interval.flip_interval_workaround_active = false;
 520	} else {
 521		/* Determine conditions for starting workaround */
 522		if (in_vrr->flip_interval.vsyncs_between_flip >= VSYNCS_BETWEEN_FLIP_THRESHOLD &&
 523				in_vrr->flip_interval.vsync_to_flip_in_us < FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
 524			/* Increase flip interval counter we have 2 vsyncs between flips and
 525			 * vsync to flip interval is less than 500us
 526			 */
 527			in_vrr->flip_interval.flip_interval_detect_counter++;
 528			if (in_vrr->flip_interval.flip_interval_detect_counter > FREESYNC_CONSEC_FLIP_AFTER_VSYNC) {
 529				/* Start workaround if we detect 5 consecutive instances of the above case */
 530				in_vrr->flip_interval.program_flip_interval_workaround = true;
 531				in_vrr->flip_interval.flip_interval_workaround_active = true;
 532			}
 533		} else {
 534			/* Reset the flip interval counter if we condition is no longer met */
 535			in_vrr->flip_interval.flip_interval_detect_counter = 0;
 536		}
 537	}
 538
 539	in_vrr->flip_interval.vsyncs_between_flip = 0;
 540}
 541
 542static bool vrr_settings_require_update(struct core_freesync *core_freesync,
 543		struct mod_freesync_config *in_config,
 544		unsigned int min_refresh_in_uhz,
 545		unsigned int max_refresh_in_uhz,
 546		struct mod_vrr_params *in_vrr)
 547{
 548	if (in_vrr->state != in_config->state) {
 549		return true;
 550	} else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED &&
 551			in_vrr->fixed.target_refresh_in_uhz !=
 552					in_config->fixed_refresh_in_uhz) {
 553		return true;
 554	} else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) {
 555		return true;
 556	} else if (in_vrr->max_refresh_in_uhz != max_refresh_in_uhz) {
 557		return true;
 558	}
 559
 560	return false;
 561}
 562
 563static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
 564		struct dc_info_packet *infopacket,
 565		bool freesync_on_desktop)
 566{
 567	/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
 568	infopacket->sb[1] = 0x1A;
 569
 570	/* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
 571	infopacket->sb[2] = 0x00;
 572
 573	/* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
 574	infopacket->sb[3] = 0x00;
 575
 576	/* PB4 = Reserved */
 577
 578	/* PB5 = Reserved */
 579
 580	/* PB6 = [Bits 7:3 = Reserved] */
 581
 582	/* PB6 = [Bit 0 = FreeSync Supported] */
 583	if (vrr->state != VRR_STATE_UNSUPPORTED)
 584		infopacket->sb[6] |= 0x01;
 585
 586	/* PB6 = [Bit 1 = FreeSync Enabled] */
 587	if (vrr->state != VRR_STATE_DISABLED &&
 588			vrr->state != VRR_STATE_UNSUPPORTED)
 589		infopacket->sb[6] |= 0x02;
 590
 591	if (freesync_on_desktop) {
 592		/* PB6 = [Bit 2 = FreeSync Active] */
 593		if (vrr->state != VRR_STATE_DISABLED &&
 594			vrr->state != VRR_STATE_UNSUPPORTED)
 595			infopacket->sb[6] |= 0x04;
 596	} else {
 597		if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
 598			vrr->state == VRR_STATE_ACTIVE_FIXED)
 599			infopacket->sb[6] |= 0x04;
 600	}
 601
 602	// For v1 & 2 infoframes program nominal if non-fs mode, otherwise full range
 603	/* PB7 = FreeSync Minimum refresh rate (Hz) */
 604	if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
 605			vrr->state == VRR_STATE_ACTIVE_FIXED) {
 606		infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 500000) / 1000000);
 607	} else {
 608		infopacket->sb[7] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
 609	}
 610
 611	/* PB8 = FreeSync Maximum refresh rate (Hz)
 612	 * Note: We should never go above the field rate of the mode timing set.
 613	 */
 614	infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
 615}
 616
 617static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
 618		struct dc_info_packet *infopacket,
 619		bool freesync_on_desktop)
 620{
 621	unsigned int min_refresh;
 622	unsigned int max_refresh;
 623	unsigned int fixed_refresh;
 624	unsigned int min_programmed;
 625
 626	/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
 627	infopacket->sb[1] = 0x1A;
 628
 629	/* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
 630	infopacket->sb[2] = 0x00;
 631
 632	/* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
 633	infopacket->sb[3] = 0x00;
 634
 635	/* PB4 = Reserved */
 636
 637	/* PB5 = Reserved */
 638
 639	/* PB6 = [Bits 7:3 = Reserved] */
 640
 641	/* PB6 = [Bit 0 = FreeSync Supported] */
 642	if (vrr->state != VRR_STATE_UNSUPPORTED)
 643		infopacket->sb[6] |= 0x01;
 644
 645	/* PB6 = [Bit 1 = FreeSync Enabled] */
 646	if (vrr->state != VRR_STATE_DISABLED &&
 647			vrr->state != VRR_STATE_UNSUPPORTED)
 648		infopacket->sb[6] |= 0x02;
 649
 650	/* PB6 = [Bit 2 = FreeSync Active] */
 651	if (freesync_on_desktop) {
 652		if (vrr->state != VRR_STATE_DISABLED &&
 653			vrr->state != VRR_STATE_UNSUPPORTED)
 654			infopacket->sb[6] |= 0x04;
 655	} else {
 656		if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
 657			vrr->state == VRR_STATE_ACTIVE_FIXED)
 658			infopacket->sb[6] |= 0x04;
 659	}
 660
 661	min_refresh = (vrr->min_refresh_in_uhz + 500000) / 1000000;
 662	max_refresh = (vrr->max_refresh_in_uhz + 500000) / 1000000;
 663	fixed_refresh = (vrr->fixed_refresh_in_uhz + 500000) / 1000000;
 664
 665	min_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh :
 666			(vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? min_refresh :
 667			(vrr->state == VRR_STATE_INACTIVE) ? min_refresh :
 668			max_refresh; // Non-fs case, program nominal range
 669
 670	/* PB7 = FreeSync Minimum refresh rate (Hz) */
 671	infopacket->sb[7] = min_programmed & 0xFF;
 672
 673	/* PB8 = FreeSync Maximum refresh rate (Hz) */
 674	infopacket->sb[8] = max_refresh & 0xFF;
 675
 676	/* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */
 677	infopacket->sb[11] = (min_programmed >> 8) & 0x03;
 678
 679	/* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */
 680	infopacket->sb[12] = (max_refresh >> 8) & 0x03;
 681
 682	/* PB16 : Reserved bits 7:1, FixedRate bit 0 */
 683	infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;
 684}
 685
 686static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
 687		struct dc_info_packet *infopacket)
 688{
 689	if (app_tf != TRANSFER_FUNC_UNKNOWN) {
 690		infopacket->valid = true;
 691
 692		if (app_tf == TRANSFER_FUNC_PQ2084)
 693			infopacket->sb[9] |= 0x20; // PB9 = [Bit 5 = PQ EOTF Active]
 694		else {
 695			infopacket->sb[6] |= 0x08;  // PB6 = [Bit 3 = Native Color Active]
 696			if (app_tf == TRANSFER_FUNC_GAMMA_22)
 697				infopacket->sb[9] |= 0x04;  // PB9 = [Bit 2 = Gamma 2.2 EOTF Active]
 698		}
 699	}
 700}
 701
 702static void build_vrr_infopacket_header_v1(enum signal_type signal,
 703		struct dc_info_packet *infopacket,
 704		unsigned int *payload_size)
 705{
 706	if (dc_is_hdmi_signal(signal)) {
 707
 708		/* HEADER */
 709
 710		/* HB0  = Packet Type = 0x83 (Source Product
 711		 *	  Descriptor InfoFrame)
 712		 */
 713		infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
 714
 715		/* HB1  = Version = 0x01 */
 716		infopacket->hb1 = 0x01;
 717
 718		/* HB2  = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
 719		infopacket->hb2 = 0x08;
 720
 721		*payload_size = 0x08;
 722
 723	} else if (dc_is_dp_signal(signal)) {
 724
 725		/* HEADER */
 726
 727		/* HB0  = Secondary-data Packet ID = 0 - Only non-zero
 728		 *	  when used to associate audio related info packets
 729		 */
 730		infopacket->hb0 = 0x00;
 731
 732		/* HB1  = Packet Type = 0x83 (Source Product
 733		 *	  Descriptor InfoFrame)
 734		 */
 735		infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
 736
 737		/* HB2  = [Bits 7:0 = Least significant eight bits -
 738		 *	  For INFOFRAME, the value must be 1Bh]
 739		 */
 740		infopacket->hb2 = 0x1B;
 741
 742		/* HB3  = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
 743		 *	  [Bits 1:0 = Most significant two bits = 0x00]
 744		 */
 745		infopacket->hb3 = 0x04;
 746
 747		*payload_size = 0x1B;
 748	}
 749}
 750
 751static void build_vrr_infopacket_header_v2(enum signal_type signal,
 752		struct dc_info_packet *infopacket,
 753		unsigned int *payload_size)
 754{
 755	if (dc_is_hdmi_signal(signal)) {
 756
 757		/* HEADER */
 758
 759		/* HB0  = Packet Type = 0x83 (Source Product
 760		 *	  Descriptor InfoFrame)
 761		 */
 762		infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
 763
 764		/* HB1  = Version = 0x02 */
 765		infopacket->hb1 = 0x02;
 766
 767		/* HB2  = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */
 768		infopacket->hb2 = 0x09;
 769
 770		*payload_size = 0x09;
 771	} else if (dc_is_dp_signal(signal)) {
 772
 773		/* HEADER */
 774
 775		/* HB0  = Secondary-data Packet ID = 0 - Only non-zero
 776		 *	  when used to associate audio related info packets
 777		 */
 778		infopacket->hb0 = 0x00;
 779
 780		/* HB1  = Packet Type = 0x83 (Source Product
 781		 *	  Descriptor InfoFrame)
 782		 */
 783		infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
 784
 785		/* HB2  = [Bits 7:0 = Least significant eight bits -
 786		 *	  For INFOFRAME, the value must be 1Bh]
 787		 */
 788		infopacket->hb2 = 0x1B;
 789
 790		/* HB3  = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
 791		 *	  [Bits 1:0 = Most significant two bits = 0x00]
 792		 */
 793		infopacket->hb3 = 0x08;
 794
 795		*payload_size = 0x1B;
 796	}
 797}
 798
 799static void build_vrr_infopacket_header_v3(enum signal_type signal,
 800		struct dc_info_packet *infopacket,
 801		unsigned int *payload_size)
 802{
 803	unsigned char version;
 804
 805	version = 3;
 806	if (dc_is_hdmi_signal(signal)) {
 807
 808		/* HEADER */
 809
 810		/* HB0  = Packet Type = 0x83 (Source Product
 811		 *	  Descriptor InfoFrame)
 812		 */
 813		infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
 814
 815		/* HB1  = Version = 0x03 */
 816		infopacket->hb1 = version;
 817
 818		/* HB2  = [Bits 7:5 = 0] [Bits 4:0 = Length] */
 819		infopacket->hb2 = 0x10;
 820
 821		*payload_size = 0x10;
 822	} else if (dc_is_dp_signal(signal)) {
 823
 824		/* HEADER */
 825
 826		/* HB0  = Secondary-data Packet ID = 0 - Only non-zero
 827		 *	  when used to associate audio related info packets
 828		 */
 829		infopacket->hb0 = 0x00;
 830
 831		/* HB1  = Packet Type = 0x83 (Source Product
 832		 *	  Descriptor InfoFrame)
 833		 */
 834		infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
 835
 836		/* HB2  = [Bits 7:0 = Least significant eight bits -
 837		 *	  For INFOFRAME, the value must be 1Bh]
 838		 */
 839		infopacket->hb2 = 0x1B;
 840
 841		/* HB3  = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
 842		 *	  [Bits 1:0 = Most significant two bits = 0x00]
 843		 */
 844
 845		infopacket->hb3 = (version & 0x3F) << 2;
 846
 847		*payload_size = 0x1B;
 848	}
 849}
 850
 851static void build_vrr_infopacket_checksum(unsigned int *payload_size,
 852		struct dc_info_packet *infopacket)
 853{
 854	/* Calculate checksum */
 855	unsigned int idx = 0;
 856	unsigned char checksum = 0;
 857
 858	checksum += infopacket->hb0;
 859	checksum += infopacket->hb1;
 860	checksum += infopacket->hb2;
 861	checksum += infopacket->hb3;
 862
 863	for (idx = 1; idx <= *payload_size; idx++)
 864		checksum += infopacket->sb[idx];
 865
 866	/* PB0 = Checksum (one byte complement) */
 867	infopacket->sb[0] = (unsigned char)(0x100 - checksum);
 868
 869	infopacket->valid = true;
 870}
 871
 872static void build_vrr_infopacket_v1(enum signal_type signal,
 873		const struct mod_vrr_params *vrr,
 874		struct dc_info_packet *infopacket,
 875		bool freesync_on_desktop)
 876{
 877	/* SPD info packet for FreeSync */
 878	unsigned int payload_size = 0;
 879
 880	build_vrr_infopacket_header_v1(signal, infopacket, &payload_size);
 881	build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
 882	build_vrr_infopacket_checksum(&payload_size, infopacket);
 883
 884	infopacket->valid = true;
 885}
 886
 887static void build_vrr_infopacket_v2(enum signal_type signal,
 888		const struct mod_vrr_params *vrr,
 889		enum color_transfer_func app_tf,
 890		struct dc_info_packet *infopacket,
 891		bool freesync_on_desktop)
 892{
 893	unsigned int payload_size = 0;
 894
 895	build_vrr_infopacket_header_v2(signal, infopacket, &payload_size);
 896	build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
 897
 898	build_vrr_infopacket_fs2_data(app_tf, infopacket);
 899
 900	build_vrr_infopacket_checksum(&payload_size, infopacket);
 901
 902	infopacket->valid = true;
 903}
 904
 905static void build_vrr_infopacket_v3(enum signal_type signal,
 906		const struct mod_vrr_params *vrr,
 907		enum color_transfer_func app_tf,
 908		struct dc_info_packet *infopacket,
 909		bool freesync_on_desktop)
 910{
 911	unsigned int payload_size = 0;
 912
 913	build_vrr_infopacket_header_v3(signal, infopacket, &payload_size);
 914	build_vrr_infopacket_data_v3(vrr, infopacket, freesync_on_desktop);
 915
 916	build_vrr_infopacket_fs2_data(app_tf, infopacket);
 917
 918	build_vrr_infopacket_checksum(&payload_size, infopacket);
 919
 920	infopacket->valid = true;
 921}
 922
 923static void build_vrr_infopacket_sdp_v1_3(enum vrr_packet_type packet_type,
 924										struct dc_info_packet *infopacket)
 925{
 926	uint8_t idx = 0, size = 0;
 927
 928	size = ((packet_type == PACKET_TYPE_FS_V1) ? 0x08 :
 929			(packet_type == PACKET_TYPE_FS_V3) ? 0x10 :
 930												0x09);
 931
 932	for (idx = infopacket->hb2; idx > 1; idx--) // Data Byte Count: 0x1B
 933		infopacket->sb[idx] = infopacket->sb[idx-1];
 934
 935	infopacket->sb[1] = size;                         // Length
 936	infopacket->sb[0] = (infopacket->hb3 >> 2) & 0x3F;//Version
 937	infopacket->hb3   = (0x13 << 2);                  // Header,SDP 1.3
 938	infopacket->hb2   = 0x1D;
 939}
 940
 941void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
 942		const struct dc_stream_state *stream,
 943		const struct mod_vrr_params *vrr,
 944		enum vrr_packet_type packet_type,
 945		enum color_transfer_func app_tf,
 946		struct dc_info_packet *infopacket,
 947		bool pack_sdp_v1_3)
 948{
 949	/* SPD info packet for FreeSync
 950	 * VTEM info packet for HdmiVRR
 951	 * Check if Freesync is supported. Return if false. If true,
 952	 * set the corresponding bit in the info packet
 953	 */
 954	if (!vrr->send_info_frame)
 955		return;
 956
 957	switch (packet_type) {
 958	case PACKET_TYPE_FS_V3:
 959		build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
 960		break;
 961	case PACKET_TYPE_FS_V2:
 962		build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
 963		break;
 964	case PACKET_TYPE_VRR:
 965	case PACKET_TYPE_FS_V1:
 966	default:
 967		build_vrr_infopacket_v1(stream->signal, vrr, infopacket, stream->freesync_on_desktop);
 968	}
 969
 970	if (true == pack_sdp_v1_3 &&
 971		true == dc_is_dp_signal(stream->signal) &&
 972		packet_type != PACKET_TYPE_VRR &&
 973		packet_type != PACKET_TYPE_VTEM)
 974		build_vrr_infopacket_sdp_v1_3(packet_type, infopacket);
 975}
 976
 977void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
 978		const struct dc_stream_state *stream,
 979		struct mod_freesync_config *in_config,
 980		struct mod_vrr_params *in_out_vrr)
 981{
 982	struct core_freesync *core_freesync = NULL;
 983	unsigned long long nominal_field_rate_in_uhz = 0;
 984	unsigned long long rounded_nominal_in_uhz = 0;
 985	unsigned int refresh_range = 0;
 986	unsigned long long min_refresh_in_uhz = 0;
 987	unsigned long long max_refresh_in_uhz = 0;
 988	unsigned long long min_hardware_refresh_in_uhz = 0;
 989
 990	if (mod_freesync == NULL)
 991		return;
 992
 993	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
 994
 995	/* Calculate nominal field rate for stream */
 996	nominal_field_rate_in_uhz =
 997			mod_freesync_calc_nominal_field_rate(stream);
 998
 999	if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
1000		min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
1001			(stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));
1002	}
1003	/* Limit minimum refresh rate to what can be supported by hardware */
1004	min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ?
1005		min_hardware_refresh_in_uhz : in_config->min_refresh_in_uhz;
1006	max_refresh_in_uhz = in_config->max_refresh_in_uhz;
1007
1008	/* Full range may be larger than current video timing, so cap at nominal */
1009	if (max_refresh_in_uhz > nominal_field_rate_in_uhz)
1010		max_refresh_in_uhz = nominal_field_rate_in_uhz;
1011
1012	/* Full range may be larger than current video timing, so cap at nominal */
1013	if (min_refresh_in_uhz > max_refresh_in_uhz)
1014		min_refresh_in_uhz = max_refresh_in_uhz;
1015
1016	/* If a monitor reports exactly max refresh of 2x of min, enforce it on nominal */
1017	rounded_nominal_in_uhz =
1018			div_u64(nominal_field_rate_in_uhz + 50000, 100000) * 100000;
1019	if (in_config->max_refresh_in_uhz == (2 * in_config->min_refresh_in_uhz) &&
1020		in_config->max_refresh_in_uhz == rounded_nominal_in_uhz)
1021		min_refresh_in_uhz = div_u64(nominal_field_rate_in_uhz, 2);
1022
1023	if (!vrr_settings_require_update(core_freesync,
1024			in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz,
1025			in_out_vrr))
1026		return;
1027
1028	in_out_vrr->state = in_config->state;
1029	in_out_vrr->send_info_frame = in_config->vsif_supported;
1030
1031	if (in_config->state == VRR_STATE_UNSUPPORTED) {
1032		in_out_vrr->state = VRR_STATE_UNSUPPORTED;
1033		in_out_vrr->supported = false;
1034		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1035		in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1036
1037		return;
1038
1039	} else {
1040		in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz;
1041		in_out_vrr->max_duration_in_us =
1042				calc_duration_in_us_from_refresh_in_uhz(
1043						(unsigned int)min_refresh_in_uhz);
1044
1045		in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz;
1046		in_out_vrr->min_duration_in_us =
1047				calc_duration_in_us_from_refresh_in_uhz(
1048						(unsigned int)max_refresh_in_uhz);
1049
1050		if (in_config->state == VRR_STATE_ACTIVE_FIXED)
1051			in_out_vrr->fixed_refresh_in_uhz = in_config->fixed_refresh_in_uhz;
1052		else
1053			in_out_vrr->fixed_refresh_in_uhz = 0;
1054
1055		refresh_range = div_u64(in_out_vrr->max_refresh_in_uhz + 500000, 1000000) -
1056				div_u64(in_out_vrr->min_refresh_in_uhz + 500000, 1000000);
1057
1058		in_out_vrr->supported = true;
1059	}
1060
1061	in_out_vrr->fixed.ramping_active = in_config->ramping;
1062
1063	in_out_vrr->btr.btr_enabled = in_config->btr;
1064
1065	if (in_out_vrr->max_refresh_in_uhz < (2 * in_out_vrr->min_refresh_in_uhz))
1066		in_out_vrr->btr.btr_enabled = false;
1067	else {
1068		in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
1069				2 * in_out_vrr->min_duration_in_us;
1070		if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)
1071			in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;
1072	}
1073
1074	in_out_vrr->btr.btr_active = false;
1075	in_out_vrr->btr.inserted_duration_in_us = 0;
1076	in_out_vrr->btr.frames_to_insert = 0;
1077	in_out_vrr->btr.frame_counter = 0;
1078	in_out_vrr->fixed.fixed_active = false;
1079	in_out_vrr->fixed.target_refresh_in_uhz = 0;
1080
1081	in_out_vrr->btr.mid_point_in_us =
1082				(in_out_vrr->min_duration_in_us +
1083				 in_out_vrr->max_duration_in_us) / 2;
1084
1085	if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
1086		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1087		in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1088	} else if (in_out_vrr->state == VRR_STATE_DISABLED) {
1089		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1090		in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1091	} else if (in_out_vrr->state == VRR_STATE_INACTIVE) {
1092		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1093		in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1094	} else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1095			refresh_range >= MIN_REFRESH_RANGE) {
1096
1097		in_out_vrr->adjust.v_total_min =
1098			mod_freesync_calc_v_total_from_refresh(stream,
1099				in_out_vrr->max_refresh_in_uhz);
1100		in_out_vrr->adjust.v_total_max =
1101			mod_freesync_calc_v_total_from_refresh(stream,
1102				in_out_vrr->min_refresh_in_uhz);
1103	} else if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED) {
1104		in_out_vrr->fixed.target_refresh_in_uhz =
1105				in_out_vrr->fixed_refresh_in_uhz;
1106		if (in_out_vrr->fixed.ramping_active &&
1107				in_out_vrr->fixed.fixed_active) {
1108			/* Do not update vtotals if ramping is already active
1109			 * in order to continue ramp from current refresh.
1110			 */
1111			in_out_vrr->fixed.fixed_active = true;
1112		} else {
1113			in_out_vrr->fixed.fixed_active = true;
1114			in_out_vrr->adjust.v_total_min =
1115				mod_freesync_calc_v_total_from_refresh(stream,
1116					in_out_vrr->fixed.target_refresh_in_uhz);
1117			in_out_vrr->adjust.v_total_max =
1118				in_out_vrr->adjust.v_total_min;
1119		}
1120	} else {
1121		in_out_vrr->state = VRR_STATE_INACTIVE;
1122		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1123		in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1124	}
1125
1126	in_out_vrr->adjust.allow_otg_v_count_halt = (in_config->state == VRR_STATE_ACTIVE_FIXED) ? true : false;
1127}
1128
1129void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
1130		const struct dc_plane_state *plane,
1131		const struct dc_stream_state *stream,
1132		unsigned int curr_time_stamp_in_us,
1133		struct mod_vrr_params *in_out_vrr)
1134{
1135	struct core_freesync *core_freesync = NULL;
1136	unsigned int last_render_time_in_us = 0;
1137
1138	if (mod_freesync == NULL)
1139		return;
1140
1141	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1142
1143	if (in_out_vrr->supported &&
1144			in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
1145
1146		last_render_time_in_us = curr_time_stamp_in_us -
1147				plane->time.prev_update_time_in_us;
1148
1149		if (in_out_vrr->btr.btr_enabled) {
1150			apply_below_the_range(core_freesync,
1151					stream,
1152					last_render_time_in_us,
1153					in_out_vrr);
1154		} else {
1155			apply_fixed_refresh(core_freesync,
1156				stream,
1157				last_render_time_in_us,
1158				in_out_vrr);
1159		}
1160
1161		determine_flip_interval_workaround_req(in_out_vrr,
1162				curr_time_stamp_in_us);
1163
1164	}
1165}
1166
1167void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
1168		const struct dc_stream_state *stream,
1169		struct mod_vrr_params *in_out_vrr)
1170{
1171	struct core_freesync *core_freesync = NULL;
1172	unsigned int cur_timestamp_in_us;
1173	unsigned long long cur_tick;
1174
1175	if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
1176		return;
1177
1178	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1179
1180	if (in_out_vrr->supported == false)
1181		return;
1182
1183	cur_tick = dm_get_timestamp(core_freesync->dc->ctx);
1184	cur_timestamp_in_us = (unsigned int)
1185			div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);
1186
1187	in_out_vrr->flip_interval.vsyncs_between_flip++;
1188	in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
1189
1190	if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1191			(in_out_vrr->flip_interval.flip_interval_workaround_active ||
1192			(!in_out_vrr->flip_interval.flip_interval_workaround_active &&
1193			in_out_vrr->flip_interval.program_flip_interval_workaround))) {
1194		// set freesync vmin vmax to nominal for workaround
1195		in_out_vrr->adjust.v_total_min =
1196			mod_freesync_calc_v_total_from_refresh(
1197			stream, in_out_vrr->max_refresh_in_uhz);
1198		in_out_vrr->adjust.v_total_max =
1199				in_out_vrr->adjust.v_total_min;
1200		in_out_vrr->flip_interval.program_flip_interval_workaround = false;
1201		in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = true;
1202		return;
1203	}
1204
1205	if (in_out_vrr->state != VRR_STATE_ACTIVE_VARIABLE &&
1206			in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup) {
1207		in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = false;
1208		in_out_vrr->flip_interval.flip_interval_detect_counter = 0;
1209		in_out_vrr->flip_interval.vsyncs_between_flip = 0;
1210		in_out_vrr->flip_interval.vsync_to_flip_in_us = 0;
1211	}
1212
1213	/* Below the Range Logic */
1214
1215	/* Only execute if in fullscreen mode */
1216	if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1217					in_out_vrr->btr.btr_active) {
1218		/* TODO: pass in flag for Pre-DCE12 ASIC
1219		 * in order for frame variable duration to take affect,
1220		 * it needs to be done one VSYNC early, which is at
1221		 * frameCounter == 1.
1222		 * For DCE12 and newer updates to V_TOTAL_MIN/MAX
1223		 * will take affect on current frame
1224		 */
1225		if (in_out_vrr->btr.frames_to_insert ==
1226				in_out_vrr->btr.frame_counter) {
1227			in_out_vrr->adjust.v_total_min =
1228				calc_v_total_from_duration(stream,
1229				in_out_vrr,
1230				in_out_vrr->btr.inserted_duration_in_us);
1231			in_out_vrr->adjust.v_total_max =
1232				in_out_vrr->adjust.v_total_min;
1233		}
1234
1235		if (in_out_vrr->btr.frame_counter > 0)
1236			in_out_vrr->btr.frame_counter--;
1237
1238		/* Restore FreeSync */
1239		if (in_out_vrr->btr.frame_counter == 0) {
1240			in_out_vrr->adjust.v_total_min =
1241				mod_freesync_calc_v_total_from_refresh(stream,
1242				in_out_vrr->max_refresh_in_uhz);
1243			in_out_vrr->adjust.v_total_max =
1244				mod_freesync_calc_v_total_from_refresh(stream,
1245				in_out_vrr->min_refresh_in_uhz);
1246		}
1247	}
1248
1249	/* If in fullscreen freesync mode or in video, do not program
1250	 * static screen ramp values
1251	 */
1252	if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE)
1253		in_out_vrr->fixed.ramping_active = false;
1254
1255	/* Gradual Static Screen Ramping Logic
1256	 * Execute if ramp is active and user enabled freesync static screen
1257	 */
1258	if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED &&
1259				in_out_vrr->fixed.ramping_active) {
1260		update_v_total_for_static_ramp(
1261				core_freesync, stream, in_out_vrr);
1262	}
1263
1264	/*
1265	 * If VRR is inactive, set vtotal min and max to nominal vtotal
1266	 */
1267	 if (in_out_vrr->state == VRR_STATE_INACTIVE) {
1268		in_out_vrr->adjust.v_total_min =
1269			mod_freesync_calc_v_total_from_refresh(stream,
1270				in_out_vrr->max_refresh_in_uhz);
1271		in_out_vrr->adjust.v_total_max = in_out_vrr->adjust.v_total_min;
1272		return;
1273	}
1274}
1275
1276unsigned long long mod_freesync_calc_nominal_field_rate(
1277			const struct dc_stream_state *stream)
1278{
1279	unsigned long long nominal_field_rate_in_uhz = 0;
1280	unsigned int total = stream->timing.h_total * stream->timing.v_total;
1281
1282	/* Calculate nominal field rate for stream, rounded up to nearest integer */
1283	nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz;
1284	nominal_field_rate_in_uhz *= 100000000ULL;
1285
1286	nominal_field_rate_in_uhz =	div_u64(nominal_field_rate_in_uhz, total);
1287
1288	return nominal_field_rate_in_uhz;
1289}
1290
1291bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr)
1292{
1293	return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED);
1294}