dpcd_defs.h

  1/*
  2 * Copyright 2012-15 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DAL_DPCD_DEFS_H__
 27#define __DAL_DPCD_DEFS_H__
 28
 29#include <drm/display/drm_dp_helper.h>
 30#ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h
 31#define DP_SINK_HW_REVISION_START 0x409
 32#endif
 33/* Panel Replay*/
 34#ifndef DP_PANEL_REPLAY_CAPABILITY_SUPPORT // can remove this once the define gets into linux drm_dp_helper.h
 35#define DP_PANEL_REPLAY_CAPABILITY_SUPPORT 0x0b0
 36#endif /* DP_PANEL_REPLAY_CAPABILITY_SUPPORT */
 37#ifndef DP_PANEL_REPLAY_CAPABILITY // can remove this once the define gets into linux drm_dp_helper.h
 38#define DP_PANEL_REPLAY_CAPABILITY 0x0b1
 39#endif /* DP_PANEL_REPLAY_CAPABILITY */
 40#ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1  // can remove this once the define gets into linux drm_dp_helper.h
 41#define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1  0x1b0
 42#endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 */
 43#ifndef DP_PANEL_REPLAY_ENABLE // can remove this once the define gets into linux drm_dp_helper.h
 44#define DP_PANEL_REPLAY_ENABLE (1 << 0)
 45#endif /* DP_PANEL_REPLAY_ENABLE */
 46#ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 // can remove this once the define gets into linux drm_dp_helper.h
 47#define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 0x1b1
 48#endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 */
 49
 50enum dpcd_revision {
 51	DPCD_REV_10 = 0x10,
 52	DPCD_REV_11 = 0x11,
 53	DPCD_REV_12 = 0x12,
 54	DPCD_REV_13 = 0x13,
 55	DPCD_REV_14 = 0x14
 56};
 57
 58/* these are the types stored at DOWNSTREAMPORT_PRESENT */
 59enum dpcd_downstream_port_type {
 60	DOWNSTREAM_DP = 0,
 61	DOWNSTREAM_VGA,
 62	DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */
 63	DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */
 64};
 65
 66enum dpcd_link_test_patterns {
 67	LINK_TEST_PATTERN_NONE = 0,
 68	LINK_TEST_PATTERN_COLOR_RAMP,
 69	LINK_TEST_PATTERN_VERTICAL_BARS,
 70	LINK_TEST_PATTERN_COLOR_SQUARES
 71};
 72
 73enum dpcd_test_color_format {
 74	TEST_COLOR_FORMAT_RGB = 0,
 75	TEST_COLOR_FORMAT_YCBCR422,
 76	TEST_COLOR_FORMAT_YCBCR444
 77};
 78
 79enum dpcd_test_bit_depth {
 80	TEST_BIT_DEPTH_6 = 0,
 81	TEST_BIT_DEPTH_8,
 82	TEST_BIT_DEPTH_10,
 83	TEST_BIT_DEPTH_12,
 84	TEST_BIT_DEPTH_16
 85};
 86
 87/* PHY (encoder) test patterns
 88The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248)
 89*/
 90enum dpcd_phy_test_patterns {
 91	PHY_TEST_PATTERN_NONE = 0,
 92	PHY_TEST_PATTERN_D10_2,
 93	PHY_TEST_PATTERN_SYMBOL_ERROR,
 94	PHY_TEST_PATTERN_PRBS7,
 95	PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */
 96	PHY_TEST_PATTERN_CP2520_1,
 97	PHY_TEST_PATTERN_CP2520_2,
 98	PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */
 99	PHY_TEST_PATTERN_128b_132b_TPS1 = 0x8,
100	PHY_TEST_PATTERN_128b_132b_TPS2 = 0x10,
101	PHY_TEST_PATTERN_PRBS9 = 0x18,
102	PHY_TEST_PATTERN_PRBS11 = 0x20,
103	PHY_TEST_PATTERN_PRBS15 = 0x28,
104	PHY_TEST_PATTERN_PRBS23 = 0x30,
105	PHY_TEST_PATTERN_PRBS31 = 0x38,
106	PHY_TEST_PATTERN_264BIT_CUSTOM = 0x40,
107	PHY_TEST_PATTERN_SQUARE = 0x48,
108	PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED = 0x49,
109	PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED = 0x4A,
110	PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED = 0x4B,
111};
112
113enum dpcd_test_dyn_range {
114	TEST_DYN_RANGE_VESA = 0,
115	TEST_DYN_RANGE_CEA
116};
117
118enum dpcd_audio_test_pattern {
119	AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */
120	AUDIO_TEST_PATTERN_SAWTOOTH
121};
122
123enum dpcd_audio_sampling_rate {
124	AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */
125	AUDIO_SAMPLING_RATE_44_1KHZ,
126	AUDIO_SAMPLING_RATE_48KHZ,
127	AUDIO_SAMPLING_RATE_88_2KHZ,
128	AUDIO_SAMPLING_RATE_96KHZ,
129	AUDIO_SAMPLING_RATE_176_4KHZ,
130	AUDIO_SAMPLING_RATE_192KHZ
131};
132
133enum dpcd_audio_channels {
134	AUDIO_CHANNELS_1 = 0,/* direct HW translation */
135	AUDIO_CHANNELS_2,
136	AUDIO_CHANNELS_3,
137	AUDIO_CHANNELS_4,
138	AUDIO_CHANNELS_5,
139	AUDIO_CHANNELS_6,
140	AUDIO_CHANNELS_7,
141	AUDIO_CHANNELS_8,
142
143	AUDIO_CHANNELS_COUNT
144};
145
146enum dpcd_audio_test_pattern_periods {
147	DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */
148	DPCD_AUDIO_TEST_PATTERN_PERIOD_3,
149	DPCD_AUDIO_TEST_PATTERN_PERIOD_6,
150	DPCD_AUDIO_TEST_PATTERN_PERIOD_12,
151	DPCD_AUDIO_TEST_PATTERN_PERIOD_24,
152	DPCD_AUDIO_TEST_PATTERN_PERIOD_48,
153	DPCD_AUDIO_TEST_PATTERN_PERIOD_96,
154	DPCD_AUDIO_TEST_PATTERN_PERIOD_192,
155	DPCD_AUDIO_TEST_PATTERN_PERIOD_384,
156	DPCD_AUDIO_TEST_PATTERN_PERIOD_768,
157	DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
158};
159
160/* This enum is for programming DPCD TRAINING_PATTERN_SET */
161enum dpcd_training_patterns {
162	DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */
163	DPCD_TRAINING_PATTERN_1,
164	DPCD_TRAINING_PATTERN_2,
165	DPCD_TRAINING_PATTERN_3,
166	DPCD_TRAINING_PATTERN_4 = 7,
167	DPCD_128b_132b_TPS1 = 1,
168	DPCD_128b_132b_TPS2 = 2,
169	DPCD_128b_132b_TPS2_CDS = 3,
170};
171
172/* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
173It defines the possible PSR states. */
174enum dpcd_psr_sink_states {
175	PSR_SINK_STATE_INACTIVE = 0,
176	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1,
177	PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2,
178	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3,
179	PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4,
180	PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
181};
182
183#define DP_SOURCE_SEQUENCE                      0x30C
184#define DP_SOURCE_TABLE_REVISION                0x310
185#define DP_SOURCE_PAYLOAD_SIZE                  0x311
186#define DP_SOURCE_SINK_CAP                      0x317
187#define DP_SOURCE_BACKLIGHT_LEVEL               0x320
188#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK        0x326
189#define DP_SOURCE_BACKLIGHT_CONTROL             0x32E
190#define DP_SOURCE_BACKLIGHT_ENABLE              0x32F
191#define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED      0x340
192#define DP_SINK_PR_REPLAY_STATUS                0x378
193#define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE     0x379
194#define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A
195#define DP_SINK_EMISSION_RATE                   0x37E
196
197/* Remove once drm_dp_helper.h is updated upstream */
198#ifndef DP_TOTAL_LTTPR_CNT
199#define DP_TOTAL_LTTPR_CNT                                  0xF000A /* 2.1 */
200#endif
201
202#endif /* __DAL_DPCD_DEFS_H__ */