FILE
dmub_dcn401.h

File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h C
  1// SPDX-License-Identifier: MIT
  2//
  3// Copyright 2024 Advanced Micro Devices, Inc.
  4
  5#ifndef _DMUB_DCN401_H_
  6#define _DMUB_DCN401_H_
  7
  8#include "dmub_dcn31.h"
  9
 10struct dmub_srv;
 11
 12/* DCN401 register definitions. */
 13
 14#define DMUB_DCN401_REGS() \
 15	DMUB_SR(DMCUB_CNTL) \
 16	DMUB_SR(DMCUB_CNTL2) \
 17	DMUB_SR(DMCUB_SEC_CNTL) \
 18	DMUB_SR(DMCUB_INBOX0_SIZE) \
 19	DMUB_SR(DMCUB_INBOX0_RPTR) \
 20	DMUB_SR(DMCUB_INBOX0_WPTR) \
 21	DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
 22	DMUB_SR(DMCUB_INBOX1_SIZE) \
 23	DMUB_SR(DMCUB_INBOX1_RPTR) \
 24	DMUB_SR(DMCUB_INBOX1_WPTR) \
 25	DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
 26	DMUB_SR(DMCUB_OUTBOX0_SIZE) \
 27	DMUB_SR(DMCUB_OUTBOX0_RPTR) \
 28	DMUB_SR(DMCUB_OUTBOX0_WPTR) \
 29	DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
 30	DMUB_SR(DMCUB_OUTBOX1_SIZE) \
 31	DMUB_SR(DMCUB_OUTBOX1_RPTR) \
 32	DMUB_SR(DMCUB_OUTBOX1_WPTR) \
 33	DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
 34	DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
 35	DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
 36	DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
 37	DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
 38	DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
 39	DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
 40	DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
 41	DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
 42	DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
 43	DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
 44	DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
 45	DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
 46	DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
 47	DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
 48	DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
 49	DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
 50	DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
 51	DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
 52	DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
 53	DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
 54	DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
 55	DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
 56	DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
 57	DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
 58	DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
 59	DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
 60	DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
 61	DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
 62	DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
 63	DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
 64	DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
 65	DMUB_SR(DMCUB_REGION4_OFFSET) \
 66	DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
 67	DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
 68	DMUB_SR(DMCUB_REGION5_OFFSET) \
 69	DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
 70	DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
 71	DMUB_SR(DMCUB_REGION6_OFFSET) \
 72	DMUB_SR(DMCUB_REGION6_OFFSET_HIGH) \
 73	DMUB_SR(DMCUB_REGION6_TOP_ADDRESS) \
 74	DMUB_SR(DMCUB_SCRATCH0) \
 75	DMUB_SR(DMCUB_SCRATCH1) \
 76	DMUB_SR(DMCUB_SCRATCH2) \
 77	DMUB_SR(DMCUB_SCRATCH3) \
 78	DMUB_SR(DMCUB_SCRATCH4) \
 79	DMUB_SR(DMCUB_SCRATCH5) \
 80	DMUB_SR(DMCUB_SCRATCH6) \
 81	DMUB_SR(DMCUB_SCRATCH7) \
 82	DMUB_SR(DMCUB_SCRATCH8) \
 83	DMUB_SR(DMCUB_SCRATCH9) \
 84	DMUB_SR(DMCUB_SCRATCH10) \
 85	DMUB_SR(DMCUB_SCRATCH11) \
 86	DMUB_SR(DMCUB_SCRATCH12) \
 87	DMUB_SR(DMCUB_SCRATCH13) \
 88	DMUB_SR(DMCUB_SCRATCH14) \
 89	DMUB_SR(DMCUB_SCRATCH15) \
 90	DMUB_SR(DMCUB_SCRATCH16) \
 91	DMUB_SR(DMCUB_SCRATCH17) \
 92	DMUB_SR(DMCUB_GPINT_DATAIN0) \
 93	DMUB_SR(DMCUB_GPINT_DATAIN1) \
 94	DMUB_SR(DMCUB_GPINT_DATAOUT) \
 95	DMUB_SR(CC_DC_PIPE_DIS) \
 96	DMUB_SR(MMHUBBUB_SOFT_RESET) \
 97	DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
 98	DMUB_SR(DCN_VM_FB_OFFSET) \
 99	DMUB_SR(DMCUB_TIMER_CURRENT) \
100	DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
101	DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
102	DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
103	DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \
104	DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
105	DMUB_SR(DMCUB_INTERRUPT_ACK) \
106	DMUB_SR(DMCUB_INTERRUPT_STATUS) \
107	DMUB_SR(DMCUB_REG_INBOX0_RDY) \
108	DMUB_SR(DMCUB_REG_INBOX0_MSG0) \
109	DMUB_SR(DMCUB_REG_INBOX0_MSG1) \
110	DMUB_SR(DMCUB_REG_INBOX0_MSG2) \
111	DMUB_SR(DMCUB_REG_INBOX0_MSG3) \
112	DMUB_SR(DMCUB_REG_INBOX0_MSG4) \
113	DMUB_SR(DMCUB_REG_INBOX0_MSG5) \
114	DMUB_SR(DMCUB_REG_INBOX0_MSG6) \
115	DMUB_SR(DMCUB_REG_INBOX0_MSG7) \
116	DMUB_SR(DMCUB_REG_INBOX0_MSG8) \
117	DMUB_SR(DMCUB_REG_INBOX0_MSG9) \
118	DMUB_SR(DMCUB_REG_INBOX0_MSG10) \
119	DMUB_SR(DMCUB_REG_INBOX0_MSG11) \
120	DMUB_SR(DMCUB_REG_INBOX0_MSG12) \
121	DMUB_SR(DMCUB_REG_INBOX0_MSG13) \
122	DMUB_SR(DMCUB_REG_INBOX0_MSG14) \
123	DMUB_SR(DMCUB_REG_INBOX0_RSP) \
124	DMUB_SR(DMCUB_REG_OUTBOX0_RDY) \
125	DMUB_SR(DMCUB_REG_OUTBOX0_MSG0) \
126	DMUB_SR(DMCUB_REG_OUTBOX0_RSP) \
127	DMUB_SR(HOST_INTERRUPT_CSR)
128
129#define DMUB_DCN401_FIELDS() \
130	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
131	DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
132	DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
133	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
134	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
135	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
136	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
137	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
138	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
139	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
140	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
141	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
142	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
143	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
144	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
145	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
146	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
147	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
148	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
149	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
150	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
151	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
152	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
153	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
154	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
155	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
156	DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_TOP_ADDRESS) \
157	DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_ENABLE) \
158	DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
159	DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
160	DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
161	DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
162	DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \
163	DMUB_SF(DMCUB_REGION3_TMR_AXI_SPACE, DMCUB_REGION3_TMR_AXI_SPACE) \
164	DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \
165	DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) \
166	DMUB_SF(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT) \
167	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK) \
168	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT) \
169	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN) \
170	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK) \
171	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT) \
172	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN) \
173	DMUB_SF(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS)
174
175struct dmub_srv_dcn401_reg_offset {
176#define DMUB_SR(reg) uint32_t reg;
177	DMUB_DCN401_REGS()
178	DMCUB_INTERNAL_REGS()
179#undef DMUB_SR
180};
181
182struct dmub_srv_dcn401_reg_shift {
183#define DMUB_SF(reg, field) uint8_t reg##__##field;
184	DMUB_DCN401_FIELDS()
185#undef DMUB_SF
186};
187
188struct dmub_srv_dcn401_reg_mask {
189#define DMUB_SF(reg, field) uint32_t reg##__##field;
190	DMUB_DCN401_FIELDS()
191#undef DMUB_SF
192};
193
194struct dmub_srv_dcn401_regs {
195	const struct dmub_srv_dcn401_reg_offset offset;
196	const struct dmub_srv_dcn401_reg_mask mask;
197	const struct dmub_srv_dcn401_reg_shift shift;
198};
199
200extern const struct dmub_srv_dcn401_regs dmub_srv_dcn401_regs;
201
202void dmub_dcn401_reset(struct dmub_srv *dmub);
203
204void dmub_dcn401_reset_release(struct dmub_srv *dmub);
205
206void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,
207			      const struct dmub_window *cw0,
208			      const struct dmub_window *cw1);
209
210void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,
211		      const struct dmub_window *cw0,
212		      const struct dmub_window *cw1);
213
214void dmub_dcn401_setup_windows(struct dmub_srv *dmub,
215			      const struct dmub_window *cw2,
216			      const struct dmub_window *cw3,
217			      const struct dmub_window *cw4,
218			      const struct dmub_window *cw5,
219			      const struct dmub_window *cw6,
220			      const struct dmub_window *region6);
221
222void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,
223			      const struct dmub_region *inbox1);
224
225uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub);
226
227uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub);
228
229void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
230
231void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,
232			      const struct dmub_region *outbox1);
233
234uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub);
235
236void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
237
238bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub);
239
240bool dmub_dcn401_is_supported(struct dmub_srv *dmub);
241
242void dmub_dcn401_set_gpint(struct dmub_srv *dmub,
243			  union dmub_gpint_data_register reg);
244
245bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,
246			       union dmub_gpint_data_register reg);
247
248uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub);
249
250uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub);
251
252void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
253
254void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
255
256union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub);
257
258void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,
259			      const struct dmub_region *outbox0);
260
261uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub);
262
263void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
264
265uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub);
266
267void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub);
268
269void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub);
270void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
271void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub);
272uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub);
273
274void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,
275		union dmub_rb_cmd *cmd);
276uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub);
277void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,
278		union dmub_rb_cmd *cmd);
279void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);
280void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);
281void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable);
282
283void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub);
284void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg);
285void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *msg);
286uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub);
287void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable);
288uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub);
289
290#endif /* _DMUB_DCN401_H_ */
~/ Read-only file preview.