dmub_dcn35.c

  1/*
  2 * Copyright 2022 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "../dmub_srv.h"
 27#include "dc_types.h"
 28#include "dmub_reg.h"
 29#include "dmub_dcn35.h"
 30#include "dc/dc_types.h"
 31
 32#include "dcn/dcn_3_5_0_offset.h"
 33#include "dcn/dcn_3_5_0_sh_mask.h"
 34
 35#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
 36#define CTX dmub
 37#define REGS dmub->regs_dcn35
 38#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 39
 40void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) {
 41	struct dmub_srv_dcn35_regs *regs = dmub->regs_dcn35;
 42#define REG_STRUCT regs
 43
 44#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
 45	DMUB_DCN35_REGS()
 46	DMCUB_INTERNAL_REGS()
 47#undef DMUB_SR
 48
 49#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
 50	DMUB_DCN35_FIELDS()
 51#undef DMUB_SF
 52
 53#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
 54	DMUB_DCN35_FIELDS()
 55#undef DMUB_SF
 56#undef REG_STRUCT
 57}
 58
 59static void dmub_dcn35_get_fb_base_offset(struct dmub_srv *dmub,
 60					  uint64_t *fb_base,
 61					  uint64_t *fb_offset)
 62{
 63	uint32_t tmp;
 64
 65	/*
 66	if (dmub->fb_base || dmub->fb_offset) {
 67		*fb_base = dmub->fb_base;
 68		*fb_offset = dmub->fb_offset;
 69		return;
 70	}
 71	*/
 72
 73	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
 74	*fb_base = (uint64_t)tmp << 24;
 75
 76	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
 77	*fb_offset = (uint64_t)tmp << 24;
 78}
 79
 80static inline void dmub_dcn35_translate_addr(const union dmub_addr *addr_in,
 81					     uint64_t fb_base,
 82					     uint64_t fb_offset,
 83					     union dmub_addr *addr_out)
 84{
 85	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
 86}
 87
 88void dmub_dcn35_reset(struct dmub_srv *dmub)
 89{
 90	union dmub_gpint_data_register cmd;
 91	const uint32_t timeout = 100000;
 92	uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
 93
 94	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
 95	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled);
 96
 97	if (in_reset == 0 && is_enabled != 0) {
 98		cmd.bits.status = 1;
 99		cmd.bits.command_code = DMUB_GPINT__STOP_FW;
100		cmd.bits.param = 0;
101
102		dmub->hw_funcs.set_gpint(dmub, cmd);
103
104		for (i = 0; i < timeout; ++i) {
105			if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
106				break;
107
108			udelay(1);
109		}
110
111		for (i = 0; i < timeout; ++i) {
112			scratch = REG_READ(DMCUB_SCRATCH7);
113			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
114				break;
115
116			udelay(1);
117		}
118
119		for (i = 0; i < timeout; ++i) {
120			REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
121			if (pwait_mode & (1 << 0))
122				break;
123
124			udelay(1);
125		}
126		/* Force reset in case we timed out, DMCUB is likely hung. */
127	}
128
129	if (is_enabled) {
130		REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
131		udelay(1);
132		REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
133	}
134
135	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
136	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
137	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
138	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
139	REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
140	REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
141	REG_WRITE(DMCUB_SCRATCH0, 0);
142
143	/* Clear the GPINT command manually so we don't send anything during boot. */
144	cmd.all = 0;
145	dmub->hw_funcs.set_gpint(dmub, cmd);
146}
147
148void dmub_dcn35_reset_release(struct dmub_srv *dmub)
149{
150	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
151
152	REG_UPDATE_3(DMU_CLK_CNTL,
153		     LONO_DISPCLK_GATE_DISABLE, 1,
154		     LONO_SOCCLK_GATE_DISABLE, 1,
155		     LONO_DMCUBCLK_GATE_DISABLE, 1);
156
157	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
158	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
159	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
160}
161
162void dmub_dcn35_backdoor_load(struct dmub_srv *dmub,
163			      const struct dmub_window *cw0,
164			      const struct dmub_window *cw1)
165{
166	union dmub_addr offset;
167	uint64_t fb_base, fb_offset;
168
169	dmub_dcn35_get_fb_base_offset(dmub, &fb_base, &fb_offset);
170
171	dmub_dcn35_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
172
173	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
174	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
175	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
176	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
177		  DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
178		  DMCUB_REGION3_CW0_ENABLE, 1);
179
180	dmub_dcn35_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
181
182	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
183	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
184	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
185	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
186		  DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
187		  DMCUB_REGION3_CW1_ENABLE, 1);
188
189	/* TODO: Do we need to set DMCUB_MEM_UNIT_ID? */
190	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0);
191}
192
193void dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub,
194		      const struct dmub_window *cw0,
195		      const struct dmub_window *cw1)
196{
197	union dmub_addr offset;
198
199	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
200	offset = cw0->offset;
201	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
202	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
203	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
204	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
205			DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
206			DMCUB_REGION3_CW0_ENABLE, 1);
207	offset = cw1->offset;
208	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
209	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
210	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
211	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
212			DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
213			DMCUB_REGION3_CW1_ENABLE, 1);
214	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
215			0x20);
216}
217void dmub_dcn35_setup_windows(struct dmub_srv *dmub,
218			      const struct dmub_window *cw2,
219			      const struct dmub_window *cw3,
220			      const struct dmub_window *cw4,
221			      const struct dmub_window *cw5,
222			      const struct dmub_window *cw6,
223			      const struct dmub_window *region6)
224{
225	union dmub_addr offset;
226
227	offset = cw3->offset;
228
229	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
230	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
231	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
232	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
233		  DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
234		  DMCUB_REGION3_CW3_ENABLE, 1);
235
236	offset = cw4->offset;
237
238	REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
239	REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
240	REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
241	REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
242		  DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
243		  DMCUB_REGION3_CW4_ENABLE, 1);
244
245	offset = cw5->offset;
246
247	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
248	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
249	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
250	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
251		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
252		  DMCUB_REGION3_CW5_ENABLE, 1);
253
254	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
255	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
256	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
257		  DMCUB_REGION5_TOP_ADDRESS,
258		  cw5->region.top - cw5->region.base - 1,
259		  DMCUB_REGION5_ENABLE, 1);
260
261	offset = cw6->offset;
262
263	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
264	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
265	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
266	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
267		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
268		  DMCUB_REGION3_CW6_ENABLE, 1);
269
270	offset = region6->offset;
271
272	REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part);
273	REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);
274	REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0,
275		  DMCUB_REGION6_TOP_ADDRESS,
276		  region6->region.top - region6->region.base - 1,
277		  DMCUB_REGION6_ENABLE, 1);
278}
279
280void dmub_dcn35_setup_mailbox(struct dmub_srv *dmub,
281			      const struct dmub_region *inbox1)
282{
283	REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
284	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
285}
286
287uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub)
288{
289	return REG_READ(DMCUB_INBOX1_WPTR);
290}
291
292uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub)
293{
294	return REG_READ(DMCUB_INBOX1_RPTR);
295}
296
297void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
298{
299	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
300}
301
302void dmub_dcn35_setup_out_mailbox(struct dmub_srv *dmub,
303			      const struct dmub_region *outbox1)
304{
305	REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
306	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
307}
308
309uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub)
310{
311	/**
312	 * outbox1 wptr register is accessed without locks (dal & dc)
313	 * and to be called only by dmub_srv_stat_get_notification()
314	 */
315	return REG_READ(DMCUB_OUTBOX1_WPTR);
316}
317
318void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
319{
320	/**
321	 * outbox1 rptr register is accessed without locks (dal & dc)
322	 * and to be called only by dmub_srv_stat_get_notification()
323	 */
324	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
325}
326
327bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub)
328{
329	union dmub_fw_boot_status status;
330	uint32_t is_enable;
331
332	status.all = REG_READ(DMCUB_SCRATCH0);
333	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
334
335	return is_enable != 0 && status.bits.dal_fw;
336}
337
338bool dmub_dcn35_is_supported(struct dmub_srv *dmub)
339{
340	uint32_t supported = 0;
341
342	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
343
344	return supported;
345}
346
347void dmub_dcn35_set_gpint(struct dmub_srv *dmub,
348			  union dmub_gpint_data_register reg)
349{
350	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
351}
352
353bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub,
354			       union dmub_gpint_data_register reg)
355{
356	union dmub_gpint_data_register test;
357
358	reg.bits.status = 0;
359	test.all = REG_READ(DMCUB_GPINT_DATAIN1);
360
361	return test.all == reg.all;
362}
363
364uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub)
365{
366	return REG_READ(DMCUB_SCRATCH7);
367}
368
369uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub)
370{
371	uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
372
373	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
374
375	REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
376	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
377	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
378
379	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
380
381	return dataout;
382}
383
384union dmub_fw_boot_status dmub_dcn35_get_fw_boot_status(struct dmub_srv *dmub)
385{
386	union dmub_fw_boot_status status;
387
388	status.all = REG_READ(DMCUB_SCRATCH0);
389	return status;
390}
391
392union dmub_fw_boot_options dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub)
393{
394	union dmub_fw_boot_options option;
395
396	option.all = REG_READ(DMCUB_SCRATCH14);
397	return option;
398}
399
400void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
401{
402	union dmub_fw_boot_options boot_options = {0};
403
404	if (!dmub->dpia_supported) {
405		dmub->dpia_supported = dmub_dcn35_get_fw_boot_option(dmub).bits.enable_dpia;
406	}
407
408	boot_options.bits.z10_disable = params->disable_z10;
409	boot_options.bits.dpia_supported = params->dpia_supported;
410	boot_options.bits.enable_dpia = dmub->dpia_supported && !params->disable_dpia;
411	boot_options.bits.usb4_cm_version = params->usb4_cm_version;
412	boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported;
413	boot_options.bits.power_optimization = params->power_optimization;
414	boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds;
415	boot_options.bits.disable_clk_gate = params->disable_clock_gate;
416	boot_options.bits.ips_disable = params->disable_ips;
417	boot_options.bits.ips_sequential_ono = params->ips_sequential_ono;
418	boot_options.bits.disable_sldo_opt = params->disable_sldo_opt;
419	boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig;
420	boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc;
421	boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation;
422
423	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
424}
425
426void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
427{
428	union dmub_fw_boot_options boot_options;
429	boot_options.all = REG_READ(DMCUB_SCRATCH14);
430	boot_options.bits.skip_phy_init_panel_sequence = skip;
431	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
432}
433
434void dmub_dcn35_setup_outbox0(struct dmub_srv *dmub,
435			      const struct dmub_region *outbox0)
436{
437	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
438
439	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
440}
441
442uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub)
443{
444	return REG_READ(DMCUB_OUTBOX0_WPTR);
445}
446
447void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
448{
449	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
450}
451
452uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub)
453{
454	return REG_READ(DMCUB_TIMER_CURRENT);
455}
456
457void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub)
458{
459	uint32_t is_dmub_enabled, is_soft_reset, is_pwait;
460	uint32_t is_traceport_enabled, is_cw6_enabled;
461	struct dmub_timeout_info timeout = {0};
462
463	if (!dmub)
464		return;
465
466	/* timeout data filled externally, cache before resetting memory */
467	timeout = dmub->debug.timeout_info;
468	memset(&dmub->debug, 0, sizeof(dmub->debug));
469	dmub->debug.timeout_info = timeout;
470
471	dmub->debug.dmcub_version = dmub->fw_version;
472
473	dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
474	dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
475	dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
476	dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
477	dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
478	dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
479	dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
480	dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
481	dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
482	dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
483	dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
484	dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
485	dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
486	dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
487	dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
488	dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
489	dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
490
491	dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
492	dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
493	dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
494
495	dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
496	dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
497	dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
498
499	dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
500	dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
501	dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
502
503	dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
504	dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
505	dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
506
507	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
508	dmub->debug.is_dmcub_enabled = is_dmub_enabled;
509
510	REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
511	dmub->debug.is_pwait = is_pwait;
512
513	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
514	dmub->debug.is_dmcub_soft_reset = is_soft_reset;
515
516	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
517	dmub->debug.is_traceport_en  = is_traceport_enabled;
518
519	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
520	dmub->debug.is_cw6_enabled = is_cw6_enabled;
521
522	dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
523}
524
525bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub)
526{
527	uint64_t region3_cw5_offset;
528	uint32_t top_addr, top_addr_enable, offset_low;
529	uint32_t offset_high, base_addr, fw_version;
530	bool is_vbios_fw = false;
531
532	memset(&dmub->preos_info, 0, sizeof(dmub->preos_info));
533
534	fw_version = REG_READ(DMCUB_SCRATCH1);
535	is_vbios_fw = ((fw_version >> 6) & 0x01) ? true : false;
536	if (!is_vbios_fw)
537		return false;
538
539	dmub->preos_info.boot_status = REG_READ(DMCUB_SCRATCH0);
540	dmub->preos_info.fw_version = REG_READ(DMCUB_SCRATCH1);
541	dmub->preos_info.boot_options = REG_READ(DMCUB_SCRATCH14);
542	REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS,
543		DMCUB_REGION3_CW5_ENABLE, &top_addr_enable);
544	if (top_addr_enable) {
545		dmub_dcn35_get_fb_base_offset(dmub,
546			&dmub->preos_info.fb_base, &dmub->preos_info.fb_offset);
547		offset_low = REG_READ(DMCUB_REGION3_CW5_OFFSET);
548		offset_high = REG_READ(DMCUB_REGION3_CW5_OFFSET_HIGH);
549		region3_cw5_offset = ((uint64_t)offset_high << 32) | offset_low;
550		dmub->preos_info.trace_buffer_phy_addr = region3_cw5_offset
551			- dmub->preos_info.fb_base + dmub->preos_info.fb_offset;
552
553		REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS,
554			DMCUB_REGION3_CW5_TOP_ADDRESS, &top_addr);
555		base_addr = REG_READ(DMCUB_REGION3_CW5_BASE_ADDRESS) & 0x1FFFFFFF;
556		dmub->preos_info.trace_buffer_size =
557			(top_addr > base_addr) ? (top_addr - base_addr + 1) : 0;
558	}
559
560	return true;
561}
562
563void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub)
564{
565	/* DMCUB_REGION3_TMR_AXI_SPACE values:
566	 * 0b011 (0x3) - FB physical address
567	 * 0b100 (0x4) - GPU virtual address
568	 *
569	 * Default value is 0x3 (FB Physical address for TMR). When programming
570	 * DMUB to be in system memory, change to 0x4. The system memory allocated
571	 * is accessible by both GPU and CPU, so we use GPU virtual address.
572	 */
573	REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
574}
575
576bool dmub_dcn35_should_detect(struct dmub_srv *dmub)
577{
578	uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);
579	bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0;
580	return should_detect;
581}
582
583void dmub_dcn35_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
584{
585	REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
586}
587
588void dmub_dcn35_clear_inbox0_ack_register(struct dmub_srv *dmub)
589{
590	REG_WRITE(DMCUB_SCRATCH17, 0);
591}
592
593uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub)
594{
595	return REG_READ(DMCUB_SCRATCH17);
596}
597
598bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub)
599{
600	union dmub_fw_boot_status status;
601	uint32_t is_enable;
602
603	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
604	if (is_enable == 0)
605		return false;
606
607	status.all = REG_READ(DMCUB_SCRATCH0);
608
609	return (status.bits.dal_fw && status.bits.hw_power_init_done && status.bits.mailbox_rdy) ||
610	       (!status.bits.dal_fw && status.bits.mailbox_rdy);
611}