dmub_dcn32.c

  1/*
  2 * Copyright 2022 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "../dmub_srv.h"
 27#include "dmub_reg.h"
 28#include "dmub_dcn32.h"
 29#include "dc/dc_types.h"
 30#include "dc_hw_types.h"
 31
 32#include "dcn/dcn_3_2_0_offset.h"
 33#include "dcn/dcn_3_2_0_sh_mask.h"
 34
 35#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
 36#define CTX dmub
 37#define REGS dmub->regs_dcn32
 38#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 39
 40void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub,  struct dc_context *ctx)
 41{
 42	struct dmub_srv_dcn32_regs *regs = dmub->regs_dcn32;
 43
 44#define REG_STRUCT regs
 45
 46#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
 47	DMUB_DCN32_REGS()
 48	DMCUB_INTERNAL_REGS()
 49#undef DMUB_SR
 50
 51#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
 52	DMUB_DCN32_FIELDS()
 53#undef DMUB_SF
 54
 55#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
 56	DMUB_DCN32_FIELDS()
 57#undef DMUB_SF
 58
 59#undef REG_STRUCT
 60}
 61
 62static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,
 63		uint64_t *fb_base,
 64		uint64_t *fb_offset)
 65{
 66	uint32_t tmp;
 67
 68	if (dmub->fb_base || dmub->fb_offset) {
 69		*fb_base = dmub->fb_base;
 70		*fb_offset = dmub->fb_offset;
 71		return;
 72	}
 73
 74	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
 75	*fb_base = (uint64_t)tmp << 24;
 76
 77	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
 78	*fb_offset = (uint64_t)tmp << 24;
 79}
 80
 81static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in,
 82		uint64_t fb_base,
 83		uint64_t fb_offset,
 84		union dmub_addr *addr_out)
 85{
 86	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
 87}
 88
 89void dmub_dcn32_reset(struct dmub_srv *dmub)
 90{
 91	union dmub_gpint_data_register cmd;
 92	const uint32_t timeout_us = 1 * 1000 * 1000; //1s
 93	const uint32_t poll_delay_us = 1; //1us
 94	uint32_t i = 0;
 95	uint32_t enabled, in_reset, scratch, pwait_mode;
 96
 97	REG_GET(DMCUB_CNTL,
 98			DMCUB_ENABLE, &enabled);
 99	REG_GET(DMCUB_CNTL2,
100			DMCUB_SOFT_RESET, &in_reset);
101
102	if (enabled && in_reset == 0) {
103		cmd.bits.status = 1;
104		cmd.bits.command_code = DMUB_GPINT__STOP_FW;
105		cmd.bits.param = 0;
106
107		dmub->hw_funcs.set_gpint(dmub, cmd);
108
109		for (; i < timeout_us; i++) {
110			scratch = REG_READ(DMCUB_SCRATCH7);
111			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
112				break;
113
114			udelay(poll_delay_us);
115		}
116
117		for (; i < timeout_us; i++) {
118			REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
119			if (pwait_mode & (1 << 0))
120				break;
121
122			udelay(poll_delay_us);
123		}
124	}
125
126	if (enabled) {
127		REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
128		udelay(1);
129		REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
130	}
131
132	if (i >= timeout_us) {
133		/* timeout should never occur */
134		BREAK_TO_DEBUGGER();
135	}
136
137	REG_UPDATE(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE, 0);
138	REG_UPDATE(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE, 0);
139	REG_UPDATE(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE, 0);
140	REG_UPDATE(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE, 0);
141	REG_UPDATE(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, 0);
142	REG_UPDATE(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE, 0);
143
144	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
145	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
146	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
147	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
148	REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
149	REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
150	REG_WRITE(DMCUB_SCRATCH0, 0);
151
152	/* Clear the GPINT command manually so we don't reset again. */
153	cmd.all = 0;
154	dmub->hw_funcs.set_gpint(dmub, cmd);
155}
156
157void dmub_dcn32_reset_release(struct dmub_srv *dmub)
158{
159	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
160	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
161	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
162	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
163}
164
165void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,
166		const struct dmub_window *cw0,
167		const struct dmub_window *cw1)
168{
169	union dmub_addr offset;
170	uint64_t fb_base, fb_offset;
171
172	dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset);
173
174	/* reset and disable DMCUB and MMHUBBUB DMUIF */
175	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
176	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
177
178	dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
179
180	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
181	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
182	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
183	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
184			DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
185			DMCUB_REGION3_CW0_ENABLE, 1);
186
187	dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
188
189	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
190	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
191	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
192	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
193			DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
194			DMCUB_REGION3_CW1_ENABLE, 1);
195
196	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
197			0x20);
198}
199
200void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,
201		      const struct dmub_window *cw0,
202		      const struct dmub_window *cw1)
203{
204	union dmub_addr offset;
205
206	/* reset and disable DMCUB and MMHUBBUB DMUIF */
207	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
208	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
209
210	offset = cw0->offset;
211
212	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
213	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
214	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
215	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
216			DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
217			DMCUB_REGION3_CW0_ENABLE, 1);
218
219	offset = cw1->offset;
220
221	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
222	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
223	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
224	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
225			DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
226			DMCUB_REGION3_CW1_ENABLE, 1);
227
228	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
229			0x20);
230}
231
232void dmub_dcn32_setup_windows(struct dmub_srv *dmub,
233		const struct dmub_window *cw2,
234		const struct dmub_window *cw3,
235		const struct dmub_window *cw4,
236		const struct dmub_window *cw5,
237		const struct dmub_window *cw6,
238		const struct dmub_window *region6)
239{
240	union dmub_addr offset;
241
242	offset = cw3->offset;
243
244	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
245	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
246	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
247	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
248			DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
249			DMCUB_REGION3_CW3_ENABLE, 1);
250
251	offset = cw4->offset;
252
253	REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
254	REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
255	REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
256	REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
257			DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
258			DMCUB_REGION3_CW4_ENABLE, 1);
259
260	offset = cw5->offset;
261
262	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
263	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
264	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
265	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
266			DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
267			DMCUB_REGION3_CW5_ENABLE, 1);
268
269	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
270	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
271	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
272			DMCUB_REGION5_TOP_ADDRESS,
273			cw5->region.top - cw5->region.base - 1,
274			DMCUB_REGION5_ENABLE, 1);
275
276	offset = cw6->offset;
277
278	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
279	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
280	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
281	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
282			DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
283			DMCUB_REGION3_CW6_ENABLE, 1);
284}
285
286void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,
287		const struct dmub_region *inbox1)
288{
289	REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
290	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
291}
292
293uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub)
294{
295	return REG_READ(DMCUB_INBOX1_WPTR);
296}
297
298uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub)
299{
300	return REG_READ(DMCUB_INBOX1_RPTR);
301}
302
303void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
304{
305	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
306}
307
308void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,
309		const struct dmub_region *outbox1)
310{
311	REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
312	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
313}
314
315uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub)
316{
317	/**
318	 * outbox1 wptr register is accessed without locks (dal & dc)
319	 * and to be called only by dmub_srv_stat_get_notification()
320	 */
321	return REG_READ(DMCUB_OUTBOX1_WPTR);
322}
323
324void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
325{
326	/**
327	 * outbox1 rptr register is accessed without locks (dal & dc)
328	 * and to be called only by dmub_srv_stat_get_notification()
329	 */
330	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
331}
332
333bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub)
334{
335	union dmub_fw_boot_status status;
336	uint32_t is_hw_init;
337
338	status.all = REG_READ(DMCUB_SCRATCH0);
339	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
340
341	return is_hw_init != 0 && status.bits.dal_fw;
342}
343
344bool dmub_dcn32_is_supported(struct dmub_srv *dmub)
345{
346	uint32_t supported = 0;
347
348	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
349
350	return supported;
351}
352
353void dmub_dcn32_set_gpint(struct dmub_srv *dmub,
354		union dmub_gpint_data_register reg)
355{
356	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
357}
358
359bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,
360		union dmub_gpint_data_register reg)
361{
362	union dmub_gpint_data_register test;
363
364	reg.bits.status = 0;
365	test.all = REG_READ(DMCUB_GPINT_DATAIN1);
366
367	return test.all == reg.all;
368}
369
370uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub)
371{
372	return REG_READ(DMCUB_SCRATCH7);
373}
374
375uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub)
376{
377	uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
378
379	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
380
381	REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
382	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
383	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
384
385	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
386
387	return dataout;
388}
389
390union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub)
391{
392	union dmub_fw_boot_status status;
393
394	status.all = REG_READ(DMCUB_SCRATCH0);
395	return status;
396}
397
398void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
399{
400	union dmub_fw_boot_options boot_options = {0};
401
402	boot_options.bits.z10_disable = params->disable_z10;
403
404	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
405}
406
407void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
408{
409	union dmub_fw_boot_options boot_options;
410	boot_options.all = REG_READ(DMCUB_SCRATCH14);
411	boot_options.bits.skip_phy_init_panel_sequence = skip;
412	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
413}
414
415void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,
416		const struct dmub_region *outbox0)
417{
418	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
419
420	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
421}
422
423uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub)
424{
425	return REG_READ(DMCUB_OUTBOX0_WPTR);
426}
427
428void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
429{
430	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
431}
432
433uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub)
434{
435	return REG_READ(DMCUB_TIMER_CURRENT);
436}
437
438void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub)
439{
440	uint32_t is_dmub_enabled, is_soft_reset, is_pwait;
441	uint32_t is_traceport_enabled, is_cw6_enabled;
442	struct dmub_timeout_info timeout = {0};
443
444	if (!dmub)
445		return;
446
447	/* timeout data filled externally, cache before resetting memory */
448	timeout = dmub->debug.timeout_info;
449	memset(&dmub->debug, 0, sizeof(dmub->debug));
450	dmub->debug.timeout_info = timeout;
451
452	dmub->debug.dmcub_version = dmub->fw_version;
453
454	dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
455	dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
456	dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
457	dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
458	dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
459	dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
460	dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
461	dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
462	dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
463	dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
464	dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
465	dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
466	dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
467	dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
468	dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
469	dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
470	dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
471
472	dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
473	dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
474	dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
475
476	dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
477	dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
478	dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
479
480	dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
481	dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
482	dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
483
484	dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
485	dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
486	dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
487
488	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
489	dmub->debug.is_dmcub_enabled = is_dmub_enabled;
490
491	REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
492	dmub->debug.is_pwait = is_pwait;
493
494	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
495	dmub->debug.is_dmcub_soft_reset = is_soft_reset;
496
497	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
498	dmub->debug.is_traceport_en  = is_traceport_enabled;
499
500	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
501	dmub->debug.is_cw6_enabled = is_cw6_enabled;
502
503	dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
504}
505void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub)
506{
507	/* DMCUB_REGION3_TMR_AXI_SPACE values:
508	 * 0b011 (0x3) - FB physical address
509	 * 0b100 (0x4) - GPU virtual address
510	 *
511	 * Default value is 0x3 (FB Physical address for TMR). When programming
512	 * DMUB to be in system memory, change to 0x4. The system memory allocated
513	 * is accessible by both GPU and CPU, so we use GPU virtual address.
514	 */
515	REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
516}
517
518void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
519{
520	REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
521}
522
523void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub)
524{
525	REG_WRITE(DMCUB_SCRATCH17, 0);
526}
527
528uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub)
529{
530	return REG_READ(DMCUB_SCRATCH17);
531}
532
533void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index)
534{
535	uint32_t index = 0;
536
537	if (subvp_index == 0) {
538		index = REG_READ(DMCUB_SCRATCH15);
539		if (index) {
540			REG_WRITE(DMCUB_SCRATCH9, addr->grph.addr.low_part);
541			REG_WRITE(DMCUB_SCRATCH11, addr->grph.meta_addr.low_part);
542		} else {
543			REG_WRITE(DMCUB_SCRATCH12,  addr->grph.addr.low_part);
544			REG_WRITE(DMCUB_SCRATCH13, addr->grph.meta_addr.low_part);
545		}
546		REG_WRITE(DMCUB_SCRATCH15, !index);
547	} else if (subvp_index == 1) {
548		index = REG_READ(DMCUB_SCRATCH23);
549		if (index) {
550			REG_WRITE(DMCUB_SCRATCH18, addr->grph.addr.low_part);
551			REG_WRITE(DMCUB_SCRATCH19, addr->grph.meta_addr.low_part);
552		} else {
553			REG_WRITE(DMCUB_SCRATCH20,  addr->grph.addr.low_part);
554			REG_WRITE(DMCUB_SCRATCH22, addr->grph.meta_addr.low_part);
555		}
556		REG_WRITE(DMCUB_SCRATCH23, !index);
557	} else {
558		return;
559	}
560}