dmub_dcn31.c

  1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "../dmub_srv.h"
 27#include "dmub_reg.h"
 28#include "dmub_dcn31.h"
 29
 30#include "yellow_carp_offset.h"
 31#include "dcn/dcn_3_1_2_offset.h"
 32#include "dcn/dcn_3_1_2_sh_mask.h"
 33
 34#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
 35#define CTX dmub
 36#define REGS dmub->regs_dcn31
 37#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
 38
 39const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs = {
 40#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
 41	{
 42		DMUB_DCN31_REGS()
 43		DMCUB_INTERNAL_REGS()
 44	},
 45#undef DMUB_SR
 46
 47#define DMUB_SF(reg, field) FD_MASK(reg, field),
 48	{ DMUB_DCN31_FIELDS() },
 49#undef DMUB_SF
 50
 51#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
 52	{ DMUB_DCN31_FIELDS() },
 53#undef DMUB_SF
 54};
 55
 56static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub,
 57					  uint64_t *fb_base,
 58					  uint64_t *fb_offset)
 59{
 60	uint32_t tmp;
 61
 62	if (dmub->fb_base || dmub->fb_offset) {
 63		*fb_base = dmub->fb_base;
 64		*fb_offset = dmub->fb_offset;
 65		return;
 66	}
 67
 68	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
 69	*fb_base = (uint64_t)tmp << 24;
 70
 71	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
 72	*fb_offset = (uint64_t)tmp << 24;
 73}
 74
 75static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in,
 76					     uint64_t fb_base,
 77					     uint64_t fb_offset,
 78					     union dmub_addr *addr_out)
 79{
 80	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
 81}
 82
 83void dmub_dcn31_reset(struct dmub_srv *dmub)
 84{
 85	union dmub_gpint_data_register cmd;
 86	const uint32_t timeout = 100000;
 87	uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
 88
 89	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
 90
 91	if (in_reset == 0) {
 92		cmd.bits.status = 1;
 93		cmd.bits.command_code = DMUB_GPINT__STOP_FW;
 94		cmd.bits.param = 0;
 95
 96		dmub->hw_funcs.set_gpint(dmub, cmd);
 97
 98		/**
 99		 * Timeout covers both the ACK and the wait
100		 * for remaining work to finish.
101		 */
102
103		for (i = 0; i < timeout; ++i) {
104			if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
105				break;
106
107			udelay(1);
108		}
109
110		for (i = 0; i < timeout; ++i) {
111			scratch = REG_READ(DMCUB_SCRATCH7);
112			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
113				break;
114
115			udelay(1);
116		}
117
118		for (i = 0; i < timeout; ++i) {
119			REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
120			if (pwait_mode & (1 << 0))
121				break;
122
123			udelay(1);
124		}
125		/* Force reset in case we timed out, DMCUB is likely hung. */
126	}
127
128	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled);
129
130	if (is_enabled) {
131		REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
132		REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
133		REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
134	}
135
136	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
137	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
138	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
139	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
140	REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
141	REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
142	REG_WRITE(DMCUB_SCRATCH0, 0);
143
144	/* Clear the GPINT command manually so we don't send anything during boot. */
145	cmd.all = 0;
146	dmub->hw_funcs.set_gpint(dmub, cmd);
147}
148
149void dmub_dcn31_reset_release(struct dmub_srv *dmub)
150{
151	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
152	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
153	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
154	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
155}
156
157void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,
158			      const struct dmub_window *cw0,
159			      const struct dmub_window *cw1)
160{
161	union dmub_addr offset;
162	uint64_t fb_base, fb_offset;
163
164	dmub_dcn31_get_fb_base_offset(dmub, &fb_base, &fb_offset);
165
166	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
167
168	dmub_dcn31_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
169
170	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
171	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
172	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
173	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
174		  DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
175		  DMCUB_REGION3_CW0_ENABLE, 1);
176
177	dmub_dcn31_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
178
179	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
180	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
181	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
182	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
183		  DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
184		  DMCUB_REGION3_CW1_ENABLE, 1);
185
186	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
187		     0x20);
188}
189
190void dmub_dcn31_setup_windows(struct dmub_srv *dmub,
191			      const struct dmub_window *cw2,
192			      const struct dmub_window *cw3,
193			      const struct dmub_window *cw4,
194			      const struct dmub_window *cw5,
195			      const struct dmub_window *cw6,
196			      const struct dmub_window *region6)
197{
198	union dmub_addr offset;
199
200	offset = cw3->offset;
201
202	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
203	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
204	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
205	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
206		  DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
207		  DMCUB_REGION3_CW3_ENABLE, 1);
208
209	offset = cw4->offset;
210
211	REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
212	REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
213	REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
214	REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
215		  DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
216		  DMCUB_REGION3_CW4_ENABLE, 1);
217
218	offset = cw5->offset;
219
220	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
221	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
222	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
223	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
224		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
225		  DMCUB_REGION3_CW5_ENABLE, 1);
226
227	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
228	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
229	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
230		  DMCUB_REGION5_TOP_ADDRESS,
231		  cw5->region.top - cw5->region.base - 1,
232		  DMCUB_REGION5_ENABLE, 1);
233
234	offset = cw6->offset;
235
236	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
237	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
238	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
239	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
240		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
241		  DMCUB_REGION3_CW6_ENABLE, 1);
242}
243
244void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,
245			      const struct dmub_region *inbox1)
246{
247	REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
248	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
249}
250
251uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub)
252{
253	return REG_READ(DMCUB_INBOX1_WPTR);
254}
255
256uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub)
257{
258	return REG_READ(DMCUB_INBOX1_RPTR);
259}
260
261void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
262{
263	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
264}
265
266void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,
267			      const struct dmub_region *outbox1)
268{
269	REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
270	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
271}
272
273uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub)
274{
275	/**
276	 * outbox1 wptr register is accessed without locks (dal & dc)
277	 * and to be called only by dmub_srv_stat_get_notification()
278	 */
279	return REG_READ(DMCUB_OUTBOX1_WPTR);
280}
281
282void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
283{
284	/**
285	 * outbox1 rptr register is accessed without locks (dal & dc)
286	 * and to be called only by dmub_srv_stat_get_notification()
287	 */
288	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
289}
290
291bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub)
292{
293	union dmub_fw_boot_status status;
294	uint32_t is_enable;
295
296	status.all = REG_READ(DMCUB_SCRATCH0);
297	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
298
299	return is_enable != 0 && status.bits.dal_fw;
300}
301
302bool dmub_dcn31_is_supported(struct dmub_srv *dmub)
303{
304	uint32_t supported = 0;
305
306	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
307
308	return supported;
309}
310
311bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub)
312{
313	return dmub->fw_version >= DMUB_FW_VERSION(4, 0, 59);
314}
315
316void dmub_dcn31_set_gpint(struct dmub_srv *dmub,
317			  union dmub_gpint_data_register reg)
318{
319	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
320}
321
322bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
323			       union dmub_gpint_data_register reg)
324{
325	union dmub_gpint_data_register test;
326
327	reg.bits.status = 0;
328	test.all = REG_READ(DMCUB_GPINT_DATAIN1);
329
330	return test.all == reg.all;
331}
332
333uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub)
334{
335	return REG_READ(DMCUB_SCRATCH7);
336}
337
338uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub)
339{
340	uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
341
342	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
343
344	REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
345	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
346	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
347
348	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
349
350	return dataout;
351}
352
353union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub)
354{
355	union dmub_fw_boot_status status;
356
357	status.all = REG_READ(DMCUB_SCRATCH0);
358	return status;
359}
360
361union dmub_fw_boot_options dmub_dcn31_get_fw_boot_option(struct dmub_srv *dmub)
362{
363	union dmub_fw_boot_options option;
364
365	option.all = REG_READ(DMCUB_SCRATCH14);
366	return option;
367}
368
369void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
370{
371	union dmub_fw_boot_options boot_options = {0};
372
373	boot_options.bits.z10_disable = params->disable_z10;
374	boot_options.bits.dpia_supported = params->dpia_supported;
375	boot_options.bits.enable_dpia = params->disable_dpia ? 0 : 1;
376	boot_options.bits.usb4_cm_version = params->usb4_cm_version;
377	boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported;
378	boot_options.bits.power_optimization = params->power_optimization;
379	boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc;
380	boot_options.bits.override_hbr3_pll_vco = params->override_hbr3_pll_vco;
381
382	boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0;
383	boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation;
384
385	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
386}
387
388void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
389{
390	union dmub_fw_boot_options boot_options;
391	boot_options.all = REG_READ(DMCUB_SCRATCH14);
392	boot_options.bits.skip_phy_init_panel_sequence = skip;
393	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
394}
395
396void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,
397			      const struct dmub_region *outbox0)
398{
399	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
400
401	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
402}
403
404uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub)
405{
406	return REG_READ(DMCUB_OUTBOX0_WPTR);
407}
408
409void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
410{
411	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
412}
413
414uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub)
415{
416	return REG_READ(DMCUB_TIMER_CURRENT);
417}
418
419void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub)
420{
421	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait;
422	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
423	struct dmub_timeout_info timeout = {0};
424
425	if (!dmub)
426		return;
427
428	/* timeout data filled externally, cache before resetting memory */
429	timeout = dmub->debug.timeout_info;
430	memset(&dmub->debug, 0, sizeof(dmub->debug));
431	dmub->debug.timeout_info = timeout;
432
433	dmub->debug.dmcub_version = dmub->fw_version;
434
435	dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
436	dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
437	dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
438	dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
439	dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
440	dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
441	dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
442	dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
443	dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
444	dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
445	dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
446	dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
447	dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
448	dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
449	dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
450	dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
451
452	dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
453	dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
454	dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
455
456	dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
457	dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
458	dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
459
460	dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
461	dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
462	dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
463
464	dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
465	dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
466	dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
467
468	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
469	dmub->debug.is_dmcub_enabled = is_dmub_enabled;
470
471	REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
472	dmub->debug.is_pwait = is_pwait;
473
474	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
475	dmub->debug.is_dmcub_soft_reset = is_soft_reset;
476
477	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
478	dmub->debug.is_dmcub_secure_reset = is_sec_reset;
479
480	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
481	dmub->debug.is_traceport_en  = is_traceport_enabled;
482
483	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
484	dmub->debug.is_cw0_enabled = is_cw0_enabled;
485
486	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
487	dmub->debug.is_cw6_enabled = is_cw6_enabled;
488}
489
490bool dmub_dcn31_should_detect(struct dmub_srv *dmub)
491{
492	uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);
493	bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0;
494	return should_detect;
495}
496