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dmub_cmd.h
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linux-6.19.14/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef DMUB_CMD_H 27#define DMUB_CMD_H 28 29#include <asm/byteorder.h> 30#include <linux/types.h> 31#include <linux/string.h> 32#include <linux/delay.h> 33 34#include "atomfirmware.h" 35 36//<DMUB_TYPES>================================================================== 37/* Basic type definitions. */ 38 39#ifdef __forceinline 40#undef __forceinline 41#endif 42#define __forceinline inline 43 44/** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48#define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50/** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54#define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56/** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60#define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62/** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65#define SET_ABM_PIPE_NORMAL 1 66 67/** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70#define NUM_AMBI_LEVEL 5 71 72/** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75#define NUM_AGGR_LEVEL 4 76 77/** 78 * Number of segments in the gamma curve. 79 */ 80#define NUM_POWER_FN_SEGS 8 81 82/** 83 * Number of segments in the backlight curve. 84 */ 85#define NUM_BL_CURVE_SEGS 16 86 87/** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90#define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92/** 93 * Maximum number of bins in ABM histogram. 94 */ 95#define ABM_MAX_NUM_OF_HG_BINS 64 96 97/* Maximum number of SubVP streams */ 98#define DMUB_MAX_SUBVP_STREAMS 2 99 100/* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105#define DMUB_MAX_FPO_STREAMS 4 106 107/* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110#define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115/* Maximum number of streams on any ASIC. */ 116#define DMUB_MAX_STREAMS 6 117 118/* Maximum number of planes on any ASIC. */ 119#define DMUB_MAX_PLANES 6 120 121/* Maximum number of phantom planes on any ASIC */ 122#define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124/* Trace buffer offset for entry */ 125#define TRACE_BUFFER_ENTRY_OFFSET 16 126 127/** 128 * Maximum number of dirty rects supported by FW. 129 */ 130#define DMUB_MAX_DIRTY_RECTS 3 131 132/** 133 * 134 * PSR control version legacy 135 */ 136#define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137/** 138 * PSR control version with multi edp support 139 */ 140#define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143/** 144 * ABM control version legacy 145 */ 146#define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148/** 149 * ABM control version with multi edp support 150 */ 151#define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153/** 154 * Physical framebuffer address location, 64-bit. 155 */ 156#ifndef PHYSICAL_ADDRESS_LOC 157#define PHYSICAL_ADDRESS_LOC union large_integer 158#endif 159 160/** 161 * OS/FW agnostic memcpy 162 */ 163#ifndef dmub_memcpy 164#define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165#endif 166 167/** 168 * OS/FW agnostic memset 169 */ 170#ifndef dmub_memset 171#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172#endif 173 174/** 175 * OS/FW agnostic memcmp 176 */ 177#ifndef dmub_memcmp 178#define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179#endif 180 181/** 182 * OS/FW agnostic udelay 183 */ 184#ifndef dmub_udelay 185#define dmub_udelay(microseconds) udelay(microseconds) 186#endif 187 188#pragma pack(push, 1) 189#define ABM_NUM_OF_ACE_SEGMENTS 5 190 191/** 192 * Debug FW state offset 193 */ 194#define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242}; 243 244struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290}; 291 292/** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301}; 302 303/* Flattened structure containing SOC BB parameters stored in the VBIOS 304 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 305 * This also prevents alighment issues when new parameters are added to the SoC BB. 306 * The following parameters should be added since these values can't be obtained elsewhere: 307 * -dml2_soc_power_management_parameters 308 * -dml2_soc_vmin_clock_limits 309 */ 310struct dmub_soc_bb_params { 311 uint32_t dram_clk_change_blackout_ns; 312 uint32_t dram_clk_change_read_only_ns; 313 uint32_t dram_clk_change_write_only_ns; 314 uint32_t fclk_change_blackout_ns; 315 uint32_t g7_ppt_blackout_ns; 316 uint32_t stutter_enter_plus_exit_latency_ns; 317 uint32_t stutter_exit_latency_ns; 318 uint32_t z8_stutter_enter_plus_exit_latency_ns; 319 uint32_t z8_stutter_exit_latency_ns; 320 uint32_t z8_min_idle_time_ns; 321 uint32_t type_b_dram_clk_change_blackout_ns; 322 uint32_t type_b_ppt_blackout_ns; 323 uint32_t vmin_limit_dispclk_khz; 324 uint32_t vmin_limit_dcfclk_khz; 325 uint32_t g7_temperature_read_blackout_ns; 326}; 327#pragma pack(pop) 328 329/** 330 * Dirty rect definition. 331 */ 332struct dmub_rect { 333 /** 334 * Dirty rect x offset. 335 */ 336 uint32_t x; 337 338 /** 339 * Dirty rect y offset. 340 */ 341 uint32_t y; 342 343 /** 344 * Dirty rect width. 345 */ 346 uint32_t width; 347 348 /** 349 * Dirty rect height. 350 */ 351 uint32_t height; 352}; 353 354/** 355 * Flags that can be set by driver to change some PSR behaviour. 356 */ 357union dmub_psr_debug_flags { 358 /** 359 * Debug flags. 360 */ 361 struct { 362 /** 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * Force all selective updates to bw full frame updates. 369 */ 370 uint32_t force_full_frame_update : 1; 371 372 /** 373 * Use HW Lock Mgr object to do HW locking in FW. 374 */ 375 uint32_t use_hw_lock_mgr : 1; 376 377 /** 378 * Use TPS3 signal when restore main link. 379 */ 380 uint32_t force_wakeup_by_tps3 : 1; 381 382 /** 383 * Back to back flip, therefore cannot power down PHY 384 */ 385 uint32_t back_to_back_flip : 1; 386 387 /** 388 * Enable visual confirm for IPS 389 */ 390 uint32_t enable_ips_visual_confirm : 1; 391 } bitfields; 392 393 /** 394 * Union for debug flags. 395 */ 396 uint32_t u32All; 397}; 398 399/** 400 * Flags that can be set by driver to change some Replay behaviour. 401 */ 402union replay_debug_flags { 403 struct { 404 /** 405 * 0x1 (bit 0) 406 * Enable visual confirm in FW. 407 */ 408 uint32_t visual_confirm : 1; 409 410 /** 411 * 0x2 (bit 1) 412 * @skip_crc: Set if need to skip CRC. 413 */ 414 uint32_t skip_crc : 1; 415 416 /** 417 * 0x4 (bit 2) 418 * @force_link_power_on: Force disable ALPM control 419 */ 420 uint32_t force_link_power_on : 1; 421 422 /** 423 * 0x8 (bit 3) 424 * @force_phy_power_on: Force phy power on 425 */ 426 uint32_t force_phy_power_on : 1; 427 428 /** 429 * 0x10 (bit 4) 430 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 431 */ 432 uint32_t timing_resync_disabled : 1; 433 434 /** 435 * 0x20 (bit 5) 436 * @skip_crtc_disabled: CRTC disable skipped 437 */ 438 uint32_t skip_crtc_disabled : 1; 439 440 /** 441 * 0x40 (bit 6) 442 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 443 */ 444 uint32_t force_defer_one_frame_update : 1; 445 446 /** 447 * 0x80 (bit 7) 448 * @disable_delay_alpm_on: Force disable delay alpm on 449 */ 450 uint32_t disable_delay_alpm_on : 1; 451 452 /** 453 * 0x100 (bit 8) 454 * @disable_desync_error_check: Force disable desync error check 455 */ 456 uint32_t disable_desync_error_check : 1; 457 458 /** 459 * 0x200 (bit 9) 460 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 461 */ 462 uint32_t force_self_update_when_abm_non_steady : 1; 463 464 /** 465 * 0x400 (bit 10) 466 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 467 * If we enter IPS2, the Visual confirm bar will change to yellow 468 */ 469 uint32_t enable_ips_visual_confirm : 1; 470 471 /** 472 * 0x800 (bit 11) 473 * @enable_ips_residency_profiling: Enable IPS residency profiling 474 */ 475 uint32_t enable_ips_residency_profiling : 1; 476 477 /** 478 * 0x1000 (bit 12) 479 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 480 */ 481 uint32_t enable_coasting_vtotal_check : 1; 482 /** 483 * 0x2000 (bit 13) 484 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 485 */ 486 uint32_t enable_visual_confirm_debug : 1; 487 488 /** 489 * 0x4000 (bit 14) 490 * @debug_log_enabled: Debug Log Enabled 491 */ 492 uint32_t debug_log_enabled : 1; 493 494 /** 495 * 0x8000 (bit 15) 496 * @enable_sub_feature_visual_confirm: Enable Sub Feature Visual Confirm 497 */ 498 uint32_t enable_sub_feature_visual_confirm : 1; 499 500 uint32_t reserved : 16; 501 } bitfields; 502 503 uint32_t u32All; 504}; 505 506/** 507 * Flags record error state. 508 */ 509union replay_visual_confirm_error_state_flags { 510 struct { 511 /** 512 * 0x1 (bit 0) - Desync Error flag. 513 */ 514 uint32_t desync_error : 1; 515 516 /** 517 * 0x2 (bit 1) - State Transition Error flag. 518 */ 519 uint32_t state_transition_error : 1; 520 521 /** 522 * 0x4 (bit 2) - Crc Error flag 523 */ 524 uint32_t crc_error : 1; 525 526 /** 527 * 0x8 (bit 3) - Reserved 528 */ 529 uint32_t reserved_3 : 1; 530 531 /** 532 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 533 * Added new debug flag to control DPCD. 534 */ 535 uint32_t incorrect_vtotal_in_static_screen : 1; 536 537 /** 538 * 0x20 (bit 5) - No doubled Refresh Rate. 539 */ 540 uint32_t no_double_rr : 1; 541 542 /** 543 * Reserved bit 6-7 544 */ 545 uint32_t reserved_6_7 : 2; 546 547 /** 548 * Reserved bit 9-31 549 */ 550 uint32_t reserved_9_31 : 24; 551 } bitfields; 552 553 uint32_t u32All; 554}; 555 556union replay_hw_flags { 557 struct { 558 /** 559 * @allow_alpm_fw_standby_mode: To indicate whether the 560 * ALPM FW standby mode is allowed 561 */ 562 uint32_t allow_alpm_fw_standby_mode : 1; 563 564 /* 565 * @dsc_enable_status: DSC enable status in driver 566 */ 567 uint32_t dsc_enable_status : 1; 568 569 /** 570 * @fec_enable_status: receive fec enable/disable status from driver 571 */ 572 uint32_t fec_enable_status : 1; 573 574 /* 575 * @smu_optimizations_en: SMU power optimization. 576 * Only when active display is Replay capable and display enters Replay. 577 * Trigger interrupt to SMU to powerup/down. 578 */ 579 uint32_t smu_optimizations_en : 1; 580 581 /** 582 * @phy_power_state: Indicates current phy power state 583 */ 584 uint32_t phy_power_state : 1; 585 586 /** 587 * @link_power_state: Indicates current link power state 588 */ 589 uint32_t link_power_state : 1; 590 /** 591 * Use TPS3 signal when restore main link. 592 */ 593 uint32_t force_wakeup_by_tps3 : 1; 594 /** 595 * @is_alpm_initialized: Indicates whether ALPM is initialized 596 */ 597 uint32_t is_alpm_initialized : 1; 598 599 /** 600 * @alpm_mode: Indicates ALPM mode selected 601 */ 602 uint32_t alpm_mode : 2; 603 } bitfields; 604 605 uint32_t u32All; 606}; 607 608/** 609 * Flags that can be set by driver to change some Panel Replay behaviour. 610 */ 611union pr_debug_flags { 612 struct { 613 /** 614 * 0x1 (bit 0) 615 * Enable visual confirm in FW. 616 */ 617 uint32_t visual_confirm : 1; 618 619 /** 620 * 0x2 (bit 1) 621 * @skip_crc: Set if need to skip CRC. 622 */ 623 uint32_t skip_crc : 1; 624 625 /** 626 * 0x4 (bit 2) 627 * @force_link_power_on: Force disable ALPM control 628 */ 629 uint32_t force_link_power_on : 1; 630 631 /** 632 * 0x8 (bit 3) 633 * @force_phy_power_on: Force phy power on 634 */ 635 uint32_t force_phy_power_on : 1; 636 637 /** 638 * 0x10 (bit 4) 639 * @skip_crtc_disabled: CRTC disable skipped 640 */ 641 uint32_t skip_crtc_disabled : 1; 642 643 /* 644 * 0x20 (bit 5) 645 * @visual_confirm_rate_control: Enable Visual Confirm rate control detection 646 */ 647 uint32_t visual_confirm_rate_control : 1; 648 649 uint32_t reserved : 26; 650 } bitfields; 651 652 uint32_t u32All; 653}; 654 655union pr_hw_flags { 656 struct { 657 /** 658 * @allow_alpm_fw_standby_mode: To indicate whether the 659 * ALPM FW standby mode is allowed 660 */ 661 uint32_t allow_alpm_fw_standby_mode : 1; 662 663 /* 664 * @dsc_enable_status: DSC enable status in driver 665 */ 666 uint32_t dsc_enable_status : 1; 667 668 /** 669 * @fec_enable_status: receive fec enable/disable status from driver 670 */ 671 uint32_t fec_enable_status : 1; 672 673 /* 674 * @smu_optimizations_en: SMU power optimization. 675 * Only when active display is Replay capable and display enters Replay. 676 * Trigger interrupt to SMU to powerup/down. 677 */ 678 uint32_t smu_optimizations_en : 1; 679 680 /** 681 * @phy_power_state: Indicates current phy power state 682 */ 683 uint32_t phy_power_state : 1; 684 685 /** 686 * @link_power_state: Indicates current link power state 687 */ 688 uint32_t link_power_state : 1; 689 /** 690 * Use TPS3 signal when restore main link. 691 */ 692 uint32_t force_wakeup_by_tps3 : 1; 693 /** 694 * @is_alpm_initialized: Indicates whether ALPM is initialized 695 */ 696 uint32_t is_alpm_initialized : 1; 697 /** 698 * @alpm_mode: Indicates ALPM mode selected 699 */ 700 uint32_t alpm_mode : 2; 701 } bitfields; 702 703 uint32_t u32All; 704}; 705 706union fw_assisted_mclk_switch_version { 707 struct { 708 uint8_t minor : 5; 709 uint8_t major : 3; 710 }; 711 uint8_t ver; 712}; 713 714/** 715 * DMUB feature capabilities. 716 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 717 */ 718struct dmub_feature_caps { 719 /** 720 * Max PSR version supported by FW. 721 */ 722 uint8_t psr; 723 uint8_t fw_assisted_mclk_switch_ver; 724 uint8_t reserved[4]; 725 uint8_t subvp_psr_support; 726 uint8_t gecc_enable; 727 uint8_t replay_supported; 728 uint8_t replay_reserved[3]; 729 uint8_t abm_aux_backlight_support; 730 uint8_t lsdma_support_in_dmu; 731}; 732 733struct dmub_visual_confirm_color { 734 /** 735 * Maximum 10 bits color value 736 */ 737 uint16_t color_r_cr; 738 uint16_t color_g_y; 739 uint16_t color_b_cb; 740 uint16_t panel_inst; 741}; 742 743/** 744 * struct dmub_cursor_offload_pipe_data_dcn30_v1 - DCN30+ per pipe data. 745 */ 746struct dmub_cursor_offload_pipe_data_dcn30_v1 { 747 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 748 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 749 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 750 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 751 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 752 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 753 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 754 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 755 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 756 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 757 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 758 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 759 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 760 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 761 uint32_t reserved0[4]; 762 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 763 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 764 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 765 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 766 uint32_t CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 767 uint32_t CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 768 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS : 16; 769 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE, : 16; 770 uint32_t reserved1[5]; 771 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 772 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 773 uint32_t reserved2[3]; 774}; 775 776/** 777 * struct dmub_cursor_offload_pipe_data_dcn401_v1 - DCN401 per pipe data. 778 */ 779struct dmub_cursor_offload_pipe_data_dcn401_v1 { 780 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 781 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 782 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 783 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 784 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 785 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 786 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 787 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 788 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 789 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 790 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 791 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 792 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 793 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 794 uint32_t reserved0[4]; 795 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 796 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 797 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 798 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 799 uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 800 uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 801 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16; 802 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16; 803 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB : 16; 804 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16; 805 uint32_t reserved1[4]; 806 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 807 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 808 uint32_t HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR : 1; 809 uint32_t reserved2[3]; 810}; 811 812/** 813 * struct dmub_cursor_offload_pipe_data_v1 - Per pipe data for cursor offload. 814 */ 815struct dmub_cursor_offload_pipe_data_v1 { 816 union { 817 struct dmub_cursor_offload_pipe_data_dcn30_v1 dcn30; /**< DCN30 cursor data. */ 818 struct dmub_cursor_offload_pipe_data_dcn401_v1 dcn401; /**< DCN401 cursor data. */ 819 uint8_t payload[96]; /**< Guarantees the cursor pipe data size per-pipe. */ 820 }; 821}; 822 823/** 824 * struct dmub_cursor_offload_payload_data_v1 - A payload of stream data. 825 */ 826struct dmub_cursor_offload_payload_data_v1 { 827 uint32_t write_idx_start; /**< Write index, updated before pipe_data is written. */ 828 uint32_t write_idx_finish; /**< Write index, updated after pipe_data is written. */ 829 uint32_t pipe_mask; /**< Mask of pipes to update. */ 830 uint32_t reserved; /**< Reserved for future use. */ 831 struct dmub_cursor_offload_pipe_data_v1 pipe_data[6]; /**< Per-pipe cursor data. */ 832}; 833 834/** 835 * struct dmub_cursor_offload_stream_v1 - Per-stream data for cursor offload. 836 */ 837struct dmub_cursor_offload_stream_v1 { 838 struct dmub_cursor_offload_payload_data_v1 payloads[4]; /**< A small buffer of cursor payloads. */ 839 uint32_t write_idx; /**< The index of the last written payload. */ 840}; 841 842/** 843 * struct dmub_cursor_offload_v1 - Cursor offload feature state. 844 */ 845struct dmub_cursor_offload_v1 { 846 struct dmub_cursor_offload_stream_v1 offload_streams[6]; /**< Per-stream cursor offload data */ 847}; 848 849//============================================================================== 850//</DMUB_TYPES>================================================================= 851//============================================================================== 852//< DMUB_META>================================================================== 853//============================================================================== 854#pragma pack(push, 1) 855 856/* Magic value for identifying dmub_fw_meta_info */ 857#define DMUB_FW_META_MAGIC 0x444D5542 858 859/* Offset from the end of the file to the dmub_fw_meta_info */ 860#define DMUB_FW_META_OFFSET 0x24 861 862/** 863 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 864 */ 865union dmub_fw_meta_feature_bits { 866 struct { 867 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 868 uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */ 869 uint32_t reserved : 30; 870 } bits; /**< status bits */ 871 uint32_t all; /**< 32-bit access to status bits */ 872}; 873 874/** 875 * struct dmub_fw_meta_info - metadata associated with fw binary 876 * 877 * NOTE: This should be considered a stable API. Fields should 878 * not be repurposed or reordered. New fields should be 879 * added instead to extend the structure. 880 * 881 * @magic_value: magic value identifying DMUB firmware meta info 882 * @fw_region_size: size of the firmware state region 883 * @trace_buffer_size: size of the tracebuffer region 884 * @fw_version: the firmware version information 885 * @dal_fw: 1 if the firmware is DAL 886 * @shared_state_size: size of the shared state region in bytes 887 * @shared_state_features: number of shared state features 888 */ 889struct dmub_fw_meta_info { 890 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 891 uint32_t fw_region_size; /**< size of the firmware state region */ 892 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 893 uint32_t fw_version; /**< the firmware version information */ 894 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 895 uint8_t reserved[3]; /**< padding bits */ 896 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 897 uint16_t shared_state_features; /**< number of shared state features */ 898 uint16_t reserved2; /**< padding bytes */ 899 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 900}; 901 902/** 903 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 904 */ 905union dmub_fw_meta { 906 struct dmub_fw_meta_info info; /**< metadata info */ 907 uint8_t reserved[64]; /**< padding bits */ 908}; 909 910#pragma pack(pop) 911 912//============================================================================== 913//< DMUB Trace Buffer>================================================================ 914//============================================================================== 915#if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 916/** 917 * dmub_trace_code_t - firmware trace code, 32-bits 918 */ 919typedef uint32_t dmub_trace_code_t; 920 921/** 922 * struct dmcub_trace_buf_entry - Firmware trace entry 923 */ 924struct dmcub_trace_buf_entry { 925 dmub_trace_code_t trace_code; /**< trace code for the event */ 926 uint32_t tick_count; /**< the tick count at time of trace */ 927 uint32_t param0; /**< trace defined parameter 0 */ 928 uint32_t param1; /**< trace defined parameter 1 */ 929}; 930#endif 931 932//============================================================================== 933//< DMUB_STATUS>================================================================ 934//============================================================================== 935 936/** 937 * DMCUB scratch registers can be used to determine firmware status. 938 * Current scratch register usage is as follows: 939 * 940 * SCRATCH0: FW Boot Status register 941 * SCRATCH5: LVTMA Status Register 942 * SCRATCH15: FW Boot Options register 943 */ 944 945/** 946 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 947 */ 948union dmub_fw_boot_status { 949 struct { 950 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 951 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 952 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 953 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 954 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 955 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 956 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 957 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 958 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 959 } bits; /**< status bits */ 960 uint32_t all; /**< 32-bit access to status bits */ 961}; 962 963/** 964 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 965 */ 966enum dmub_fw_boot_status_bit { 967 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 968 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 969 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 970 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 971 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 972 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 973 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 974 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 975 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 976}; 977 978/* Register bit definition for SCRATCH5 */ 979union dmub_lvtma_status { 980 struct { 981 uint32_t psp_ok : 1; 982 uint32_t edp_on : 1; 983 uint32_t reserved : 30; 984 } bits; 985 uint32_t all; 986}; 987 988enum dmub_lvtma_status_bit { 989 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 990 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 991}; 992 993enum dmub_ips_disable_type { 994 DMUB_IPS_ENABLE = 0, 995 DMUB_IPS_DISABLE_ALL = 1, 996 DMUB_IPS_DISABLE_IPS1 = 2, 997 DMUB_IPS_DISABLE_IPS2 = 3, 998 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 999 DMUB_IPS_DISABLE_DYNAMIC = 5, 1000 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 1001 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 1002}; 1003 1004enum dmub_ips_rcg_disable_type { 1005 DMUB_IPS_RCG_ENABLE = 0, 1006 DMUB_IPS0_RCG_DISABLE = 1, 1007 DMUB_IPS1_RCG_DISABLE = 2, 1008 DMUB_IPS_RCG_DISABLE = 3 1009}; 1010 1011enum dmub_ips_in_vpb_disable_type { 1012 DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour 1013 DMUB_IPS_VPB_DISABLE_ALL = 1, 1014 DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2, 1015 DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG 1016}; 1017 1018#define DMUB_IPS1_ALLOW_MASK 0x00000001 1019#define DMUB_IPS2_ALLOW_MASK 0x00000002 1020#define DMUB_IPS1_COMMIT_MASK 0x00000004 1021#define DMUB_IPS2_COMMIT_MASK 0x00000008 1022 1023enum dmub_ips_comand_type { 1024 /** 1025 * Start/stop IPS residency measurements for a given IPS mode 1026 */ 1027 DMUB_CMD__IPS_RESIDENCY_CNTL = 0, 1028 /** 1029 * Query IPS residency information for a given IPS mode 1030 */ 1031 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, 1032}; 1033 1034/** 1035 * enum dmub_cursor_offload_comand_type - Cursor offload subcommands. 1036 */ 1037enum dmub_cursor_offload_comand_type { 1038 /** 1039 * Initializes the cursor offload feature. 1040 */ 1041 DMUB_CMD__CURSOR_OFFLOAD_INIT = 0, 1042 /** 1043 * Enables cursor offloading for a stream and updates the timing parameters. 1044 */ 1045 DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE = 1, 1046 /** 1047 * Disables cursor offloading for a given stream. 1048 */ 1049 DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE = 2, 1050 /** 1051 * Programs the latest data for a given stream. 1052 */ 1053 DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM = 3, 1054}; 1055 1056/** 1057 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 1058 */ 1059union dmub_fw_boot_options { 1060 struct { 1061 uint32_t pemu_env : 1; /**< 1 if PEMU */ 1062 uint32_t fpga_env : 1; /**< 1 if FPGA */ 1063 uint32_t optimized_init : 1; /**< 1 if optimized init */ 1064 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 1065 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 1066 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 1067 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 1068 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 1069 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 1070 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 1071 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 1072 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 1073 uint32_t power_optimization: 1; 1074 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 1075 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 1076 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 1077 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 1078 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 1079 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 1080 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 1081 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 1082 uint32_t ips_disable: 3; /* options to disable ips support*/ 1083 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 1084 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 1085 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 1086 uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ 1087 uint32_t disable_dpia_bw_allocation: 1; /**< 1 to disable the USB4 DPIA BW allocation */ 1088 uint32_t reserved : 4; /**< reserved */ 1089 } bits; /**< boot bits */ 1090 uint32_t all; /**< 32-bit access to bits */ 1091}; 1092 1093enum dmub_fw_boot_options_bit { 1094 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 1095 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 1096 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 1097}; 1098 1099//============================================================================== 1100//< DMUB_SHARED_STATE>========================================================== 1101//============================================================================== 1102 1103/** 1104 * Shared firmware state between driver and firmware for lockless communication 1105 * in situations where the inbox/outbox may be unavailable. 1106 * 1107 * Each structure *must* be at most 256-bytes in size. The layout allocation is 1108 * described below: 1109 * 1110 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 1111 */ 1112 1113/** 1114 * enum dmub_shared_state_feature_id - List of shared state features. 1115 */ 1116enum dmub_shared_state_feature_id { 1117 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 1118 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 1119 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 1120 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 1121 DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1 = 4, 1122 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 1123}; 1124 1125/** 1126 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 1127 */ 1128union dmub_shared_state_ips_fw_signals { 1129 struct { 1130 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 1131 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 1132 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 1133 uint32_t detection_required : 1; /**< 1 if detection is required */ 1134 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 1135 uint32_t reserved_bits : 27; /**< Reversed */ 1136 } bits; 1137 uint32_t all; 1138}; 1139 1140/** 1141 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 1142 */ 1143union dmub_shared_state_ips_driver_signals { 1144 struct { 1145 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 1146 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 1147 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 1148 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 1149 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 1150 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 1151 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 1152 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 1153 uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */ 1154 uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */ 1155 uint32_t reserved_bits : 22; /**< Reversed bits */ 1156 } bits; 1157 uint32_t all; 1158}; 1159 1160/** 1161 * IPS FW Version 1162 */ 1163#define DMUB_SHARED_STATE__IPS_FW_VERSION 1 1164 1165struct dmub_shared_state_debug_setup { 1166 union { 1167 struct { 1168 uint32_t exclude_points[62]; 1169 } profile_mode; 1170 }; 1171}; 1172 1173/** 1174 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 1175 */ 1176struct dmub_shared_state_ips_fw { 1177 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 1178 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 1179 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 1180 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 1181 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 1182 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 1183 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 1184 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 1185 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 1186 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 1187}; /* 248-bytes, fixed */ 1188 1189/** 1190 * IPS Driver Version 1191 */ 1192#define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 1193 1194/** 1195 * struct dmub_shared_state_ips_driver - Driver state for IPS. 1196 */ 1197struct dmub_shared_state_ips_driver { 1198 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 1199 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 1200}; /* 248-bytes, fixed */ 1201 1202/** 1203 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1204 */ 1205struct dmub_shared_state_cursor_offload_stream_v1 { 1206 uint32_t last_write_idx; /**< Last write index */ 1207 uint8_t reserved[28]; /**< Reserved bytes. */ 1208}; /* 32-bytes, fixed */ 1209 1210/** 1211 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1212 */ 1213struct dmub_shared_state_cursor_offload_v1 { 1214 struct dmub_shared_state_cursor_offload_stream_v1 offload_streams[6]; /**< stream state, 32-bytes each */ 1215 uint8_t reserved[56]; /**< reserved for future use */ 1216}; /* 248-bytes, fixed */ 1217 1218/** 1219 * enum dmub_shared_state_feature_common - Generic payload. 1220 */ 1221struct dmub_shared_state_feature_common { 1222 uint32_t padding[62]; 1223}; /* 248-bytes, fixed */ 1224 1225/** 1226 * enum dmub_shared_state_feature_header - Feature description. 1227 */ 1228struct dmub_shared_state_feature_header { 1229 uint16_t id; /**< Feature ID */ 1230 uint16_t version; /**< Feature version */ 1231 uint32_t reserved; /**< Reserved bytes. */ 1232}; /* 8 bytes, fixed */ 1233 1234/** 1235 * struct dmub_shared_state_feature_block - Feature block. 1236 */ 1237struct dmub_shared_state_feature_block { 1238 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 1239 union dmub_shared_feature_state_union { 1240 struct dmub_shared_state_feature_common common; /**< Generic data */ 1241 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 1242 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 1243 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 1244 struct dmub_shared_state_cursor_offload_v1 cursor_offload_v1; /**< Cursor offload */ 1245 } data; /**< Shared state data. */ 1246}; /* 256-bytes, fixed */ 1247 1248/** 1249 * Shared state size in bytes. 1250 */ 1251#define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 1252 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 1253 1254//============================================================================== 1255//</DMUB_STATUS>================================================================ 1256//============================================================================== 1257//< DMUB_VBIOS>================================================================= 1258//============================================================================== 1259 1260/* 1261 * enum dmub_cmd_vbios_type - VBIOS commands. 1262 * 1263 * Command IDs should be treated as stable ABI. 1264 * Do not reuse or modify IDs. 1265 */ 1266enum dmub_cmd_vbios_type { 1267 /** 1268 * Configures the DIG encoder. 1269 */ 1270 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 1271 /** 1272 * Controls the PHY. 1273 */ 1274 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 1275 /** 1276 * Sets the pixel clock/symbol clock. 1277 */ 1278 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 1279 /** 1280 * Enables or disables power gating. 1281 */ 1282 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1283 /** 1284 * Controls embedded panels. 1285 */ 1286 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1287 /** 1288 * Query DP alt status on a transmitter. 1289 */ 1290 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1291 /** 1292 * Control PHY FSM 1293 */ 1294 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1295 /** 1296 * Controls domain power gating 1297 */ 1298 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1299}; 1300 1301//============================================================================== 1302//</DMUB_VBIOS>================================================================= 1303//============================================================================== 1304//< DMUB_GPINT>================================================================= 1305//============================================================================== 1306 1307/** 1308 * The shifts and masks below may alternatively be used to format and read 1309 * the command register bits. 1310 */ 1311 1312#define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1313#define DMUB_GPINT_DATA_PARAM_SHIFT 0 1314 1315#define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1316#define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1317 1318#define DMUB_GPINT_DATA_STATUS_MASK 0xF 1319#define DMUB_GPINT_DATA_STATUS_SHIFT 28 1320 1321/** 1322 * Command responses. 1323 */ 1324 1325/** 1326 * Return response for DMUB_GPINT__STOP_FW command. 1327 */ 1328#define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1329 1330/** 1331 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1332 */ 1333union dmub_gpint_data_register { 1334 struct { 1335 uint32_t param : 16; /**< 16-bit parameter */ 1336 uint32_t command_code : 12; /**< GPINT command */ 1337 uint32_t status : 4; /**< Command status bit */ 1338 } bits; /**< GPINT bit access */ 1339 uint32_t all; /**< GPINT 32-bit access */ 1340}; 1341 1342/* 1343 * enum dmub_gpint_command - GPINT command to DMCUB FW 1344 * 1345 * Command IDs should be treated as stable ABI. 1346 * Do not reuse or modify IDs. 1347 */ 1348enum dmub_gpint_command { 1349 /** 1350 * Invalid command, ignored. 1351 */ 1352 DMUB_GPINT__INVALID_COMMAND = 0, 1353 /** 1354 * DESC: Queries the firmware version. 1355 * RETURN: Firmware version. 1356 */ 1357 DMUB_GPINT__GET_FW_VERSION = 1, 1358 /** 1359 * DESC: Halts the firmware. 1360 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1361 */ 1362 DMUB_GPINT__STOP_FW = 2, 1363 /** 1364 * DESC: Get PSR state from FW. 1365 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1366 */ 1367 DMUB_GPINT__GET_PSR_STATE = 7, 1368 /** 1369 * DESC: Notifies DMCUB of the currently active streams. 1370 * ARGS: Stream mask, 1 bit per active stream index. 1371 */ 1372 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1373 /** 1374 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1375 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1376 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1377 * RETURN: PSR residency in milli-percent. 1378 */ 1379 DMUB_GPINT__PSR_RESIDENCY = 9, 1380 1381 /** 1382 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1383 */ 1384 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1385 1386 /** 1387 * DESC: Get REPLAY state from FW. 1388 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1389 */ 1390 DMUB_GPINT__GET_REPLAY_STATE = 13, 1391 1392 /** 1393 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1394 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1395 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1396 * RETURN: REPLAY residency in milli-percent. 1397 */ 1398 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1399 1400 /** 1401 * DESC: Copy bounding box to the host. 1402 * ARGS: Version of bounding box to copy 1403 * RETURN: Result of copying bounding box 1404 */ 1405 DMUB_GPINT__BB_COPY = 96, 1406 1407 /** 1408 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1409 * ARGS: The word3 for the 64 bit address 1410 */ 1411 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1412 1413 /** 1414 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1415 * ARGS: The word2 for the 64 bit address 1416 */ 1417 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1418 1419 /** 1420 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1421 * ARGS: The word1 for the 64 bit address 1422 */ 1423 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1424 1425 /** 1426 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1427 * ARGS: The word0 for the 64 bit address 1428 */ 1429 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1430 1431 /** 1432 * DESC: Updates the trace buffer lower 32-bit mask. 1433 * ARGS: The new mask 1434 * RETURN: Lower 32-bit mask. 1435 */ 1436 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1437 1438 /** 1439 * DESC: Updates the trace buffer mask bit0~bit15. 1440 * ARGS: The new mask 1441 * RETURN: Lower 32-bit mask. 1442 */ 1443 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1444 1445 /** 1446 * DESC: Updates the trace buffer mask bit16~bit31. 1447 * ARGS: The new mask 1448 * RETURN: Lower 32-bit mask. 1449 */ 1450 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1451 1452 /** 1453 * DESC: Updates the trace buffer mask bit32~bit47. 1454 * ARGS: The new mask 1455 * RETURN: Lower 32-bit mask. 1456 */ 1457 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1458 1459 /** 1460 * DESC: Updates the trace buffer mask bit48~bit63. 1461 * ARGS: The new mask 1462 * RETURN: Lower 32-bit mask. 1463 */ 1464 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1465 1466 /** 1467 * DESC: Read the trace buffer mask bi0~bit15. 1468 */ 1469 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1470 1471 /** 1472 * DESC: Read the trace buffer mask bit16~bit31. 1473 */ 1474 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1475 1476 /** 1477 * DESC: Read the trace buffer mask bi32~bit47. 1478 */ 1479 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1480 1481 /** 1482 * DESC: Updates the trace buffer mask bit32~bit63. 1483 */ 1484 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1485 1486 /** 1487 * DESC: Set IPS residency measurement 1488 * ARGS: 0 - Disable ips measurement 1489 * 1 - Enable ips measurement 1490 */ 1491 DMUB_GPINT__IPS_RESIDENCY = 121, 1492 1493 /** 1494 * DESC: Enable measurements for various task duration 1495 * ARGS: 0 - Disable measurement 1496 * 1 - Enable measurement 1497 */ 1498 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1499 1500 /** 1501 * DESC: Gets IPS residency in microseconds 1502 * ARGS: 0 - Return IPS1 residency 1503 * 1 - Return IPS2 residency 1504 * 2 - Return IPS1_RCG residency 1505 * 3 - Return IPS1_ONO2_ON residency 1506 * RETURN: Total residency in microseconds - lower 32 bits 1507 */ 1508 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1509 1510 /** 1511 * DESC: Gets IPS1 histogram counts 1512 * ARGS: Bucket index 1513 * RETURN: Total count for the bucket 1514 */ 1515 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1516 1517 /** 1518 * DESC: Gets IPS2 histogram counts 1519 * ARGS: Bucket index 1520 * RETURN: Total count for the bucket 1521 */ 1522 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1523 1524 /** 1525 * DESC: Gets IPS residency 1526 * ARGS: 0 - Return IPS1 residency 1527 * 1 - Return IPS2 residency 1528 * 2 - Return IPS1_RCG residency 1529 * 3 - Return IPS1_ONO2_ON residency 1530 * RETURN: Total residency in milli-percent. 1531 */ 1532 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1533 1534 /** 1535 * DESC: Gets IPS1_RCG histogram counts 1536 * ARGS: Bucket index 1537 * RETURN: Total count for the bucket 1538 */ 1539 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1540 1541 /** 1542 * DESC: Gets IPS1_ONO2_ON histogram counts 1543 * ARGS: Bucket index 1544 * RETURN: Total count for the bucket 1545 */ 1546 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1547 1548 /** 1549 * DESC: Gets IPS entry counter during residency measurement 1550 * ARGS: 0 - Return IPS1 entry counts 1551 * 1 - Return IPS2 entry counts 1552 * 2 - Return IPS1_RCG entry counts 1553 * 3 - Return IPS2_ONO2_ON entry counts 1554 * RETURN: Entry counter for selected IPS mode 1555 */ 1556 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1557 1558 /** 1559 * DESC: Gets IPS inactive residency in microseconds 1560 * ARGS: 0 - Return IPS1_MAX residency 1561 * 1 - Return IPS2 residency 1562 * 2 - Return IPS1_RCG residency 1563 * 3 - Return IPS1_ONO2_ON residency 1564 * RETURN: Total inactive residency in microseconds - lower 32 bits 1565 */ 1566 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1567 1568 /** 1569 * DESC: Gets IPS inactive residency in microseconds 1570 * ARGS: 0 - Return IPS1_MAX residency 1571 * 1 - Return IPS2 residency 1572 * 2 - Return IPS1_RCG residency 1573 * 3 - Return IPS1_ONO2_ON residency 1574 * RETURN: Total inactive residency in microseconds - upper 32 bits 1575 */ 1576 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1577 1578 /** 1579 * DESC: Gets IPS residency in microseconds 1580 * ARGS: 0 - Return IPS1 residency 1581 * 1 - Return IPS2 residency 1582 * 2 - Return IPS1_RCG residency 1583 * 3 - Return IPS1_ONO2_ON residency 1584 * RETURN: Total residency in microseconds - upper 32 bits 1585 */ 1586 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1587 /** 1588 * DESC: Setup debug configs. 1589 */ 1590 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1591 /** 1592 * DESC: Initiates IPS wake sequence. 1593 */ 1594 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1595}; 1596 1597/** 1598 * INBOX0 generic command definition 1599 */ 1600union dmub_inbox0_cmd_common { 1601 struct { 1602 uint32_t command_code: 8; /**< INBOX0 command code */ 1603 uint32_t param: 24; /**< 24-bit parameter */ 1604 } bits; 1605 uint32_t all; 1606}; 1607 1608/** 1609 * INBOX0 hw_lock command definition 1610 */ 1611union dmub_inbox0_cmd_lock_hw { 1612 struct { 1613 uint32_t command_code: 8; 1614 1615 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1616 uint32_t hw_lock_client: 2; 1617 1618 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1619 uint32_t otg_inst: 3; 1620 uint32_t opp_inst: 3; 1621 uint32_t dig_inst: 3; 1622 1623 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1624 uint32_t lock_pipe: 1; 1625 uint32_t lock_cursor: 1; 1626 uint32_t lock_dig: 1; 1627 uint32_t triple_buffer_lock: 1; 1628 1629 uint32_t lock: 1; /**< Lock */ 1630 uint32_t should_release: 1; /**< Release */ 1631 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1632 } bits; 1633 uint32_t all; 1634}; 1635 1636union dmub_inbox0_data_register { 1637 union dmub_inbox0_cmd_common inbox0_cmd_common; 1638 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1639}; 1640 1641enum dmub_inbox0_command { 1642 /** 1643 * DESC: Invalid command, ignored. 1644 */ 1645 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1646 /** 1647 * DESC: Notification to acquire/release HW lock 1648 * ARGS: 1649 */ 1650 DMUB_INBOX0_CMD__HW_LOCK = 1, 1651}; 1652//============================================================================== 1653//</DMUB_GPINT>================================================================= 1654//============================================================================== 1655//< DMUB_CMD>=================================================================== 1656//============================================================================== 1657 1658/** 1659 * Size in bytes of each DMUB command. 1660 */ 1661#define DMUB_RB_CMD_SIZE 64 1662 1663/** 1664 * Maximum number of items in the DMUB ringbuffer. 1665 */ 1666#define DMUB_RB_MAX_ENTRY 128 1667 1668/** 1669 * Ringbuffer size in bytes. 1670 */ 1671#define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1672 1673/** 1674 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1675 */ 1676#define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1677 1678/** 1679 * Ringbuffer size in bytes. 1680 */ 1681#define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1682 1683/** 1684 * REG_SET mask for reg offload. 1685 */ 1686#define REG_SET_MASK 0xFFFF 1687 1688/* 1689 * enum dmub_cmd_type - DMUB inbox command. 1690 * 1691 * Command IDs should be treated as stable ABI. 1692 * Do not reuse or modify IDs. 1693 */ 1694enum dmub_cmd_type { 1695 /** 1696 * Invalid command. 1697 */ 1698 DMUB_CMD__NULL = 0, 1699 /** 1700 * Read modify write register sequence offload. 1701 */ 1702 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1703 /** 1704 * Field update register sequence offload. 1705 */ 1706 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1707 /** 1708 * Burst write sequence offload. 1709 */ 1710 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1711 /** 1712 * Reg wait sequence offload. 1713 */ 1714 DMUB_CMD__REG_REG_WAIT = 4, 1715 /** 1716 * Workaround to avoid HUBP underflow during NV12 playback. 1717 */ 1718 DMUB_CMD__PLAT_54186_WA = 5, 1719 /** 1720 * Command type used to query FW feature caps. 1721 */ 1722 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1723 /** 1724 * Command type used to get visual confirm color. 1725 */ 1726 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1727 /** 1728 * Command type used for all PSR commands. 1729 */ 1730 DMUB_CMD__PSR = 64, 1731 /** 1732 * Command type used for all MALL commands. 1733 */ 1734 DMUB_CMD__MALL = 65, 1735 /** 1736 * Command type used for all ABM commands. 1737 */ 1738 DMUB_CMD__ABM = 66, 1739 /** 1740 * Command type used to update dirty rects in FW. 1741 */ 1742 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1743 /** 1744 * Command type used to update cursor info in FW. 1745 */ 1746 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1747 /** 1748 * Command type used for HW locking in FW. 1749 */ 1750 DMUB_CMD__HW_LOCK = 69, 1751 /** 1752 * Command type used to access DP AUX. 1753 */ 1754 DMUB_CMD__DP_AUX_ACCESS = 70, 1755 /** 1756 * Command type used for OUTBOX1 notification enable 1757 */ 1758 DMUB_CMD__OUTBOX1_ENABLE = 71, 1759 1760 /** 1761 * Command type used for all idle optimization commands. 1762 */ 1763 DMUB_CMD__IDLE_OPT = 72, 1764 /** 1765 * Command type used for all clock manager commands. 1766 */ 1767 DMUB_CMD__CLK_MGR = 73, 1768 /** 1769 * Command type used for all panel control commands. 1770 */ 1771 DMUB_CMD__PANEL_CNTL = 74, 1772 1773 /** 1774 * Command type used for all CAB commands. 1775 */ 1776 DMUB_CMD__CAB_FOR_SS = 75, 1777 1778 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1779 1780 /** 1781 * Command type used for interfacing with DPIA. 1782 */ 1783 DMUB_CMD__DPIA = 77, 1784 /** 1785 * Command type used for EDID CEA parsing 1786 */ 1787 DMUB_CMD__EDID_CEA = 79, 1788 /** 1789 * Command type used for getting usbc cable ID 1790 */ 1791 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1792 /** 1793 * Command type used to query HPD state. 1794 */ 1795 DMUB_CMD__QUERY_HPD_STATE = 82, 1796 /** 1797 * Command type used for all VBIOS interface commands. 1798 */ 1799 /** 1800 * Command type used for all REPLAY commands. 1801 */ 1802 DMUB_CMD__REPLAY = 83, 1803 1804 /** 1805 * Command type used for all SECURE_DISPLAY commands. 1806 */ 1807 DMUB_CMD__SECURE_DISPLAY = 85, 1808 1809 /** 1810 * Command type used to set DPIA HPD interrupt state 1811 */ 1812 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1813 1814 /** 1815 * Command type used for all PSP commands. 1816 */ 1817 DMUB_CMD__PSP = 88, 1818 1819 /** 1820 * Command type used for all Fused IO commands. 1821 */ 1822 DMUB_CMD__FUSED_IO = 89, 1823 1824 /** 1825 * Command type used for all LSDMA commands. 1826 */ 1827 DMUB_CMD__LSDMA = 90, 1828 1829 /** 1830 * Command type use for all IPS commands. 1831 */ 1832 DMUB_CMD__IPS = 91, 1833 1834 /** 1835 * Command type use for Cursor offload. 1836 */ 1837 DMUB_CMD__CURSOR_OFFLOAD = 92, 1838 1839 /** 1840 * Command type used for all SMART_POWER_OLED commands. 1841 */ 1842 DMUB_CMD__SMART_POWER_OLED = 93, 1843 1844 /** 1845 * Command type use for all Panel Replay commands. 1846 */ 1847 DMUB_CMD__PR = 94, 1848 1849 1850 /** 1851 * Command type use for VBIOS shared commands. 1852 */ 1853 DMUB_CMD__VBIOS = 128, 1854}; 1855 1856/** 1857 * enum dmub_out_cmd_type - DMUB outbox commands. 1858 */ 1859enum dmub_out_cmd_type { 1860 /** 1861 * Invalid outbox command, ignored. 1862 */ 1863 DMUB_OUT_CMD__NULL = 0, 1864 /** 1865 * Command type used for DP AUX Reply data notification 1866 */ 1867 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1868 /** 1869 * Command type used for DP HPD event notification 1870 */ 1871 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1872 /** 1873 * Command type used for SET_CONFIG Reply notification 1874 */ 1875 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1876 /** 1877 * Command type used for USB4 DPIA notification 1878 */ 1879 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1880 /** 1881 * Command type used for HPD redetect notification 1882 */ 1883 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1884 /** 1885 * Command type used for Fused IO notification 1886 */ 1887 DMUB_OUT_CMD__FUSED_IO = 7, 1888}; 1889 1890/* DMUB_CMD__DPIA command sub-types. */ 1891enum dmub_cmd_dpia_type { 1892 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1893 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1894 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1895 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1896 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1897}; 1898 1899/* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1900enum dmub_cmd_dpia_notification_type { 1901 DPIA_NOTIFY__BW_ALLOCATION = 0, 1902}; 1903 1904#pragma pack(push, 1) 1905 1906/** 1907 * struct dmub_cmd_header - Common command header fields. 1908 */ 1909struct dmub_cmd_header { 1910 unsigned int type : 8; /**< command type */ 1911 unsigned int sub_type : 8; /**< command sub type */ 1912 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1913 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1914 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1915 unsigned int reserved0 : 5; /**< reserved bits */ 1916 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1917 unsigned int reserved1 : 2; /**< reserved bits */ 1918}; 1919 1920/* 1921 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1922 * 1923 * 60 payload bytes can hold up to 5 sets of read modify writes, 1924 * each take 3 dwords. 1925 * 1926 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1927 * 1928 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1929 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1930 */ 1931struct dmub_cmd_read_modify_write_sequence { 1932 uint32_t addr; /**< register address */ 1933 uint32_t modify_mask; /**< modify mask */ 1934 uint32_t modify_value; /**< modify value */ 1935}; 1936 1937/** 1938 * Maximum number of ops in read modify write sequence. 1939 */ 1940#define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1941 1942/** 1943 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1944 */ 1945struct dmub_rb_cmd_read_modify_write { 1946 struct dmub_cmd_header header; /**< command header */ 1947 /** 1948 * Read modify write sequence. 1949 */ 1950 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1951}; 1952 1953/* 1954 * Update a register with specified masks and values sequeunce 1955 * 1956 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1957 * 1958 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1959 * 1960 * 1961 * USE CASE: 1962 * 1. auto-increment register where additional read would update pointer and produce wrong result 1963 * 2. toggle a bit without read in the middle 1964 */ 1965 1966struct dmub_cmd_reg_field_update_sequence { 1967 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1968 uint32_t modify_value; /**< value to update with */ 1969}; 1970 1971/** 1972 * Maximum number of ops in field update sequence. 1973 */ 1974#define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1975 1976/** 1977 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1978 */ 1979struct dmub_rb_cmd_reg_field_update_sequence { 1980 struct dmub_cmd_header header; /**< command header */ 1981 uint32_t addr; /**< register address */ 1982 /** 1983 * Field update sequence. 1984 */ 1985 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1986}; 1987 1988 1989/** 1990 * Maximum number of burst write values. 1991 */ 1992#define DMUB_BURST_WRITE_VALUES__MAX 14 1993 1994/* 1995 * struct dmub_rb_cmd_burst_write - Burst write 1996 * 1997 * support use case such as writing out LUTs. 1998 * 1999 * 60 payload bytes can hold up to 14 values to write to given address 2000 * 2001 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 2002 */ 2003struct dmub_rb_cmd_burst_write { 2004 struct dmub_cmd_header header; /**< command header */ 2005 uint32_t addr; /**< register start address */ 2006 /** 2007 * Burst write register values. 2008 */ 2009 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 2010}; 2011 2012/** 2013 * struct dmub_rb_cmd_common - Common command header 2014 */ 2015struct dmub_rb_cmd_common { 2016 struct dmub_cmd_header header; /**< command header */ 2017 /** 2018 * Padding to RB_CMD_SIZE 2019 */ 2020 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 2021}; 2022 2023/** 2024 * struct dmub_cmd_reg_wait_data - Register wait data 2025 */ 2026struct dmub_cmd_reg_wait_data { 2027 uint32_t addr; /**< Register address */ 2028 uint32_t mask; /**< Mask for register bits */ 2029 uint32_t condition_field_value; /**< Value to wait for */ 2030 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 2031}; 2032 2033/** 2034 * struct dmub_rb_cmd_reg_wait - Register wait command 2035 */ 2036struct dmub_rb_cmd_reg_wait { 2037 struct dmub_cmd_header header; /**< Command header */ 2038 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 2039}; 2040 2041/** 2042 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 2043 * 2044 * Reprograms surface parameters to avoid underflow. 2045 */ 2046struct dmub_cmd_PLAT_54186_wa { 2047 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 2048 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 2049 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 2050 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 2051 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 2052 struct { 2053 uint32_t hubp_inst : 4; /**< HUBP instance */ 2054 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 2055 uint32_t immediate :1; /**< Immediate flip */ 2056 uint32_t vmid : 4; /**< VMID */ 2057 uint32_t grph_stereo : 1; /**< 1 if stereo */ 2058 uint32_t reserved : 21; /**< Reserved */ 2059 } flip_params; /**< Pageflip parameters */ 2060 uint32_t reserved[9]; /**< Reserved bits */ 2061}; 2062 2063/** 2064 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 2065 */ 2066struct dmub_rb_cmd_PLAT_54186_wa { 2067 struct dmub_cmd_header header; /**< Command header */ 2068 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 2069}; 2070 2071/** 2072 * enum dmub_cmd_mall_type - MALL commands 2073 */ 2074enum dmub_cmd_mall_type { 2075 /** 2076 * Allows display refresh from MALL. 2077 */ 2078 DMUB_CMD__MALL_ACTION_ALLOW = 0, 2079 /** 2080 * Disallows display refresh from MALL. 2081 */ 2082 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 2083 /** 2084 * Cursor copy for MALL. 2085 */ 2086 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 2087 /** 2088 * Controls DF requests. 2089 */ 2090 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 2091}; 2092 2093/** 2094 * struct dmub_rb_cmd_mall - MALL command data. 2095 */ 2096struct dmub_rb_cmd_mall { 2097 struct dmub_cmd_header header; /**< Common command header */ 2098 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 2099 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 2100 uint32_t tmr_delay; /**< Timer delay */ 2101 uint32_t tmr_scale; /**< Timer scale */ 2102 uint16_t cursor_width; /**< Cursor width in pixels */ 2103 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 2104 uint16_t cursor_height; /**< Cursor height in pixels */ 2105 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 2106 uint8_t debug_bits; /**< Debug bits */ 2107 2108 uint8_t reserved1; /**< Reserved bits */ 2109 uint8_t reserved2; /**< Reserved bits */ 2110}; 2111 2112/** 2113 * enum dmub_cmd_cab_type - CAB command data. 2114 */ 2115enum dmub_cmd_cab_type { 2116 /** 2117 * No idle optimizations (i.e. no CAB) 2118 */ 2119 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 2120 /** 2121 * No DCN requests for memory 2122 */ 2123 DMUB_CMD__CAB_NO_DCN_REQ = 1, 2124 /** 2125 * Fit surfaces in CAB (i.e. CAB enable) 2126 */ 2127 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 2128 /** 2129 * Do not fit surfaces in CAB (i.e. no CAB) 2130 */ 2131 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 2132}; 2133 2134/** 2135 * struct dmub_rb_cmd_cab - CAB command data. 2136 */ 2137struct dmub_rb_cmd_cab_for_ss { 2138 struct dmub_cmd_header header; 2139 uint8_t cab_alloc_ways; /* total number of ways */ 2140 uint8_t debug_bits; /* debug bits */ 2141}; 2142 2143/** 2144 * Enum for indicating which MCLK switch mode per pipe 2145 */ 2146enum mclk_switch_mode { 2147 NONE = 0, 2148 FPO = 1, 2149 SUBVP = 2, 2150 VBLANK = 3, 2151}; 2152 2153/* Per pipe struct which stores the MCLK switch mode 2154 * data to be sent to DMUB. 2155 * Named "v2" for now -- once FPO and SUBVP are fully merged 2156 * the type name can be updated 2157 */ 2158struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 2159 union { 2160 struct { 2161 uint32_t pix_clk_100hz; 2162 uint16_t main_vblank_start; 2163 uint16_t main_vblank_end; 2164 uint16_t mall_region_lines; 2165 uint16_t prefetch_lines; 2166 uint16_t prefetch_to_mall_start_lines; 2167 uint16_t processing_delay_lines; 2168 uint16_t htotal; // required to calculate line time for multi-display cases 2169 uint16_t vtotal; 2170 uint8_t main_pipe_index; 2171 uint8_t phantom_pipe_index; 2172 /* Since the microschedule is calculated in terms of OTG lines, 2173 * include any scaling factors to make sure when we get accurate 2174 * conversion when programming MALL_START_LINE (which is in terms 2175 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 2176 * is 1/2 (numerator = 1, denominator = 2). 2177 */ 2178 uint8_t scale_factor_numerator; 2179 uint8_t scale_factor_denominator; 2180 uint8_t is_drr; 2181 uint8_t main_split_pipe_index; 2182 uint8_t phantom_split_pipe_index; 2183 } subvp_data; 2184 2185 struct { 2186 uint32_t pix_clk_100hz; 2187 uint16_t vblank_start; 2188 uint16_t vblank_end; 2189 uint16_t vstartup_start; 2190 uint16_t vtotal; 2191 uint16_t htotal; 2192 uint8_t vblank_pipe_index; 2193 uint8_t padding[1]; 2194 struct { 2195 uint8_t drr_in_use; 2196 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 2197 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 2198 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 2199 uint8_t use_ramping; // Use ramping or not 2200 uint8_t drr_vblank_start_margin; 2201 } drr_info; // DRR considered as part of SubVP + VBLANK case 2202 } vblank_data; 2203 } pipe_config; 2204 2205 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 2206 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 2207 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 2208 */ 2209 uint8_t mode; // enum mclk_switch_mode 2210}; 2211 2212/** 2213 * Config data for Sub-VP and FPO 2214 * Named "v2" for now -- once FPO and SUBVP are fully merged 2215 * the type name can be updated 2216 */ 2217struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 2218 uint16_t watermark_a_cache; 2219 uint8_t vertical_int_margin_us; 2220 uint8_t pstate_allow_width_us; 2221 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 2222}; 2223 2224/** 2225 * DMUB rb command definition for Sub-VP and FPO 2226 * Named "v2" for now -- once FPO and SUBVP are fully merged 2227 * the type name can be updated 2228 */ 2229struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 2230 struct dmub_cmd_header header; 2231 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 2232}; 2233 2234struct dmub_flip_addr_info { 2235 uint32_t surf_addr_lo; 2236 uint32_t surf_addr_c_lo; 2237 uint32_t meta_addr_lo; 2238 uint32_t meta_addr_c_lo; 2239 uint16_t surf_addr_hi; 2240 uint16_t surf_addr_c_hi; 2241 uint16_t meta_addr_hi; 2242 uint16_t meta_addr_c_hi; 2243}; 2244 2245struct dmub_fams2_flip_info { 2246 union { 2247 struct { 2248 uint8_t is_immediate: 1; 2249 } bits; 2250 uint8_t all; 2251 } config; 2252 uint8_t otg_inst; 2253 uint8_t pipe_mask; 2254 uint8_t pad; 2255 struct dmub_flip_addr_info addr_info; 2256}; 2257 2258struct dmub_rb_cmd_fams2_flip { 2259 struct dmub_cmd_header header; 2260 struct dmub_fams2_flip_info flip_info; 2261}; 2262 2263struct dmub_cmd_lsdma_data { 2264 union { 2265 struct lsdma_init_data { 2266 union dmub_addr gpu_addr_base; 2267 uint32_t ring_size; 2268 } init_data; 2269 struct lsdma_tiled_copy_data { 2270 uint32_t src_addr_lo; 2271 uint32_t src_addr_hi; 2272 2273 uint32_t dst_addr_lo; 2274 uint32_t dst_addr_hi; 2275 2276 uint32_t src_x : 16; 2277 uint32_t src_y : 16; 2278 2279 uint32_t dst_x : 16; 2280 uint32_t dst_y : 16; 2281 2282 uint32_t src_width : 16; 2283 uint32_t src_height : 16; 2284 2285 uint32_t dst_width : 16; 2286 uint32_t dst_height : 16; 2287 2288 uint32_t rect_x : 16; 2289 uint32_t rect_y : 16; 2290 2291 uint32_t src_swizzle_mode : 5; 2292 uint32_t src_mip_max : 5; 2293 uint32_t src_mip_id : 5; 2294 uint32_t dst_mip_max : 5; 2295 uint32_t dst_swizzle_mode : 5; 2296 uint32_t dst_mip_id : 5; 2297 uint32_t tmz : 1; 2298 uint32_t dcc : 1; 2299 2300 uint32_t data_format : 6; 2301 uint32_t padding1 : 4; 2302 uint32_t dst_element_size : 3; 2303 uint32_t num_type : 3; 2304 uint32_t src_element_size : 3; 2305 uint32_t write_compress : 2; 2306 uint32_t cache_policy_dst : 2; 2307 uint32_t cache_policy_src : 2; 2308 uint32_t read_compress : 2; 2309 uint32_t src_dim : 2; 2310 uint32_t dst_dim : 2; 2311 uint32_t max_uncom : 1; 2312 2313 uint32_t max_com : 2; 2314 uint32_t padding : 30; 2315 } tiled_copy_data; 2316 struct lsdma_linear_copy_data { 2317 uint32_t src_lo; 2318 uint32_t src_hi; 2319 2320 uint32_t dst_lo; 2321 uint32_t dst_hi; 2322 2323 uint32_t count : 30; 2324 uint32_t cache_policy_dst : 2; 2325 2326 uint32_t tmz : 1; 2327 uint32_t cache_policy_src : 2; 2328 uint32_t padding : 29; 2329 } linear_copy_data; 2330 struct lsdma_linear_sub_window_copy_data { 2331 uint32_t src_lo; 2332 uint32_t src_hi; 2333 2334 uint32_t dst_lo; 2335 uint32_t dst_hi; 2336 2337 uint32_t src_x : 16; 2338 uint32_t src_y : 16; 2339 2340 uint32_t dst_x : 16; 2341 uint32_t dst_y : 16; 2342 2343 uint32_t rect_x : 16; 2344 uint32_t rect_y : 16; 2345 2346 uint32_t src_pitch : 16; 2347 uint32_t dst_pitch : 16; 2348 2349 uint32_t src_slice_pitch; 2350 uint32_t dst_slice_pitch; 2351 2352 uint32_t tmz : 1; 2353 uint32_t element_size : 3; 2354 uint32_t src_cache_policy : 3; 2355 uint32_t dst_cache_policy : 3; 2356 uint32_t reserved0 : 22; 2357 } linear_sub_window_copy_data; 2358 struct lsdma_reg_write_data { 2359 uint32_t reg_addr; 2360 uint32_t reg_data; 2361 } reg_write_data; 2362 struct lsdma_pio_copy_data { 2363 uint32_t src_lo; 2364 uint32_t src_hi; 2365 2366 uint32_t dst_lo; 2367 uint32_t dst_hi; 2368 2369 union { 2370 struct { 2371 uint32_t byte_count : 26; 2372 uint32_t src_loc : 1; 2373 uint32_t dst_loc : 1; 2374 uint32_t src_addr_inc : 1; 2375 uint32_t dst_addr_inc : 1; 2376 uint32_t overlap_disable : 1; 2377 uint32_t constant_fill : 1; 2378 } fields; 2379 uint32_t raw; 2380 } packet; 2381 } pio_copy_data; 2382 struct lsdma_pio_constfill_data { 2383 uint32_t dst_lo; 2384 uint32_t dst_hi; 2385 2386 union { 2387 struct { 2388 uint32_t byte_count : 26; 2389 uint32_t src_loc : 1; 2390 uint32_t dst_loc : 1; 2391 uint32_t src_addr_inc : 1; 2392 uint32_t dst_addr_inc : 1; 2393 uint32_t overlap_disable : 1; 2394 uint32_t constant_fill : 1; 2395 } fields; 2396 uint32_t raw; 2397 } packet; 2398 2399 uint32_t data; 2400 } pio_constfill_data; 2401 2402 uint32_t all[14]; 2403 } u; 2404}; 2405 2406struct dmub_rb_cmd_lsdma { 2407 struct dmub_cmd_header header; 2408 struct dmub_cmd_lsdma_data lsdma_data; 2409}; 2410 2411struct dmub_optc_state_v2 { 2412 uint32_t v_total_min; 2413 uint32_t v_total_max; 2414 uint32_t v_total_mid; 2415 uint32_t v_total_mid_frame_num; 2416 uint8_t program_manual_trigger; 2417 uint8_t tg_inst; 2418 uint8_t pad[2]; 2419}; 2420 2421struct dmub_optc_position { 2422 uint32_t vpos; 2423 uint32_t hpos; 2424 uint32_t frame; 2425}; 2426 2427struct dmub_rb_cmd_fams2_drr_update { 2428 struct dmub_cmd_header header; 2429 struct dmub_optc_state_v2 dmub_optc_state_req; 2430}; 2431 2432/* HW and FW global configuration data for FAMS2 */ 2433/* FAMS2 types and structs */ 2434enum fams2_stream_type { 2435 FAMS2_STREAM_TYPE_NONE = 0, 2436 FAMS2_STREAM_TYPE_VBLANK = 1, 2437 FAMS2_STREAM_TYPE_VACTIVE = 2, 2438 FAMS2_STREAM_TYPE_DRR = 3, 2439 FAMS2_STREAM_TYPE_SUBVP = 4, 2440}; 2441 2442struct dmub_rect16 { 2443 /** 2444 * Dirty rect x offset. 2445 */ 2446 uint16_t x; 2447 2448 /** 2449 * Dirty rect y offset. 2450 */ 2451 uint16_t y; 2452 2453 /** 2454 * Dirty rect width. 2455 */ 2456 uint16_t width; 2457 2458 /** 2459 * Dirty rect height. 2460 */ 2461 uint16_t height; 2462}; 2463 2464/* static stream state */ 2465struct dmub_fams2_legacy_stream_static_state { 2466 uint8_t vactive_det_fill_delay_otg_vlines; 2467 uint8_t programming_delay_otg_vlines; 2468}; //v0 2469 2470struct dmub_fams2_subvp_stream_static_state { 2471 uint16_t vratio_numerator; 2472 uint16_t vratio_denominator; 2473 uint16_t phantom_vtotal; 2474 uint16_t phantom_vactive; 2475 union { 2476 struct { 2477 uint8_t is_multi_planar : 1; 2478 uint8_t is_yuv420 : 1; 2479 } bits; 2480 uint8_t all; 2481 } config; 2482 uint8_t programming_delay_otg_vlines; 2483 uint8_t prefetch_to_mall_otg_vlines; 2484 uint8_t phantom_otg_inst; 2485 uint8_t phantom_pipe_mask; 2486 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2487}; //v0 2488 2489struct dmub_fams2_drr_stream_static_state { 2490 uint16_t nom_stretched_vtotal; 2491 uint8_t programming_delay_otg_vlines; 2492 uint8_t only_stretch_if_required; 2493 uint8_t pad[2]; 2494}; //v0 2495 2496struct dmub_fams2_cmd_legacy_stream_static_state { 2497 uint16_t vactive_det_fill_delay_otg_vlines; 2498 uint16_t programming_delay_otg_vlines; 2499}; //v1 2500 2501struct dmub_fams2_cmd_subvp_stream_static_state { 2502 uint16_t vratio_numerator; 2503 uint16_t vratio_denominator; 2504 uint16_t phantom_vtotal; 2505 uint16_t phantom_vactive; 2506 uint16_t programming_delay_otg_vlines; 2507 uint16_t prefetch_to_mall_otg_vlines; 2508 union { 2509 struct { 2510 uint8_t is_multi_planar : 1; 2511 uint8_t is_yuv420 : 1; 2512 } bits; 2513 uint8_t all; 2514 } config; 2515 uint8_t phantom_otg_inst; 2516 uint8_t phantom_pipe_mask; 2517 uint8_t pad0; 2518 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2519 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2520}; //v1 2521 2522struct dmub_fams2_cmd_drr_stream_static_state { 2523 uint16_t nom_stretched_vtotal; 2524 uint16_t programming_delay_otg_vlines; 2525 uint8_t only_stretch_if_required; 2526 uint8_t pad[3]; 2527}; //v1 2528 2529union dmub_fams2_stream_static_sub_state { 2530 struct dmub_fams2_legacy_stream_static_state legacy; 2531 struct dmub_fams2_subvp_stream_static_state subvp; 2532 struct dmub_fams2_drr_stream_static_state drr; 2533}; //v0 2534 2535union dmub_fams2_cmd_stream_static_sub_state { 2536 COMMON_STREAM_STATIC_SUB_STATE 2537}; //v1 2538 2539union dmub_fams2_stream_static_sub_state_v2 { 2540 COMMON_STREAM_STATIC_SUB_STATE 2541}; //v2 2542 2543struct dmub_fams2_stream_static_state { 2544 enum fams2_stream_type type; 2545 uint32_t otg_vline_time_ns; 2546 uint32_t otg_vline_time_ticks; 2547 uint16_t htotal; 2548 uint16_t vtotal; // nominal vtotal 2549 uint16_t vblank_start; 2550 uint16_t vblank_end; 2551 uint16_t max_vtotal; 2552 uint16_t allow_start_otg_vline; 2553 uint16_t allow_end_otg_vline; 2554 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2555 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2556 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2557 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2558 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2559 union { 2560 struct { 2561 uint8_t is_drr: 1; // stream is DRR enabled 2562 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2563 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2564 } bits; 2565 uint8_t all; 2566 } config; 2567 uint8_t otg_inst; 2568 uint8_t pipe_mask; // pipe mask for the whole config 2569 uint8_t num_planes; 2570 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2571 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2572 union dmub_fams2_stream_static_sub_state sub_state; 2573}; //v0 2574 2575struct dmub_fams2_cmd_stream_static_base_state { 2576 enum fams2_stream_type type; 2577 uint32_t otg_vline_time_ns; 2578 uint32_t otg_vline_time_ticks; 2579 uint16_t htotal; 2580 uint16_t vtotal; // nominal vtotal 2581 uint16_t vblank_start; 2582 uint16_t vblank_end; 2583 uint16_t max_vtotal; 2584 uint16_t allow_start_otg_vline; 2585 uint16_t allow_end_otg_vline; 2586 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2587 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2588 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2589 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2590 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2591 union { 2592 struct { 2593 uint8_t is_drr : 1; // stream is DRR enabled 2594 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2595 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2596 } bits; 2597 uint8_t all; 2598 } config; 2599 uint8_t otg_inst; 2600 uint8_t pipe_mask; // pipe mask for the whole config 2601 uint8_t num_planes; 2602 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2603 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2604}; //v1 2605 2606struct dmub_fams2_stream_static_state_v1 { 2607 struct dmub_fams2_cmd_stream_static_base_state base; 2608 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2609}; //v1 2610 2611/** 2612 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2613 * p-state request to allow latency 2614 */ 2615enum dmub_fams2_allow_delay_check_mode { 2616 /* No check for request to allow delay */ 2617 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2618 /* Check for request to allow delay */ 2619 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2620 /* Check for prepare to allow delay */ 2621 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2622}; 2623 2624union dmub_fams2_global_feature_config { 2625 struct { 2626 uint32_t enable: 1; 2627 uint32_t enable_ppt_check: 1; 2628 uint32_t enable_stall_recovery: 1; 2629 uint32_t enable_debug: 1; 2630 uint32_t enable_offload_flip: 1; 2631 uint32_t enable_visual_confirm: 1; 2632 uint32_t allow_delay_check_mode: 2; 2633 uint32_t reserved: 24; 2634 } bits; 2635 uint32_t all; 2636}; 2637 2638struct dmub_cmd_fams2_global_config { 2639 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2640 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2641 uint32_t num_streams; 2642 union dmub_fams2_global_feature_config features; 2643 uint32_t recovery_timeout_us; 2644 uint32_t hwfq_flip_programming_delay_us; 2645 uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target 2646}; 2647 2648union dmub_cmd_fams2_config { 2649 struct dmub_cmd_fams2_global_config global; 2650// coverity[cert_dcl37_c_violation:FALSE] errno.h, stddef.h, stdint.h not included in atombios.h 2651 struct dmub_fams2_stream_static_state stream; //v0 2652 union { 2653 struct dmub_fams2_cmd_stream_static_base_state base; 2654 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2655 } stream_v1; //v1 2656}; 2657 2658struct dmub_fams2_config_v2 { 2659 struct dmub_cmd_fams2_global_config global; 2660 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2661}; 2662 2663/** 2664 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2665 */ 2666struct dmub_rb_cmd_fams2 { 2667 struct dmub_cmd_header header; 2668 union dmub_cmd_fams2_config config; 2669}; 2670 2671/** 2672 * Indirect buffer descriptor 2673 */ 2674struct dmub_ib_data { 2675 union dmub_addr src; // location of indirect buffer in memory 2676 uint16_t size; // indirect buffer size in bytes 2677}; 2678 2679/** 2680 * DMUB rb command definition for commands passed over indirect buffer 2681 */ 2682struct dmub_rb_cmd_ib { 2683 struct dmub_cmd_header header; 2684 struct dmub_ib_data ib_data; 2685}; 2686 2687/** 2688 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2689 */ 2690enum dmub_cmd_idle_opt_type { 2691 /** 2692 * DCN hardware restore. 2693 */ 2694 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2695 2696 /** 2697 * DCN hardware save. 2698 */ 2699 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2700 2701 /** 2702 * DCN hardware notify idle. 2703 */ 2704 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2705 2706 /** 2707 * DCN hardware notify power state. 2708 */ 2709 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2710 2711 /** 2712 * DCN notify to release HW. 2713 */ 2714 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2715}; 2716 2717/** 2718 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2719 */ 2720struct dmub_rb_cmd_idle_opt_dcn_restore { 2721 struct dmub_cmd_header header; /**< header */ 2722}; 2723 2724/** 2725 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2726 */ 2727struct dmub_dcn_notify_idle_cntl_data { 2728 uint8_t driver_idle; 2729 uint8_t skip_otg_disable; 2730 uint8_t reserved[58]; 2731}; 2732 2733/** 2734 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2735 */ 2736struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2737 struct dmub_cmd_header header; /**< header */ 2738 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2739}; 2740 2741/** 2742 * enum dmub_idle_opt_dc_power_state - DC power states. 2743 */ 2744enum dmub_idle_opt_dc_power_state { 2745 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2746 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2747 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2748 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2749 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2750}; 2751 2752/** 2753 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2754 */ 2755struct dmub_idle_opt_set_dc_power_state_data { 2756 uint8_t power_state; /**< power state */ 2757 uint8_t pad[3]; /**< padding */ 2758}; 2759 2760/** 2761 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2762 */ 2763struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2764 struct dmub_cmd_header header; /**< header */ 2765 struct dmub_idle_opt_set_dc_power_state_data data; 2766}; 2767 2768/** 2769 * struct dmub_clocks - Clock update notification. 2770 */ 2771struct dmub_clocks { 2772 uint32_t dispclk_khz; /**< dispclk kHz */ 2773 uint32_t dppclk_khz; /**< dppclk kHz */ 2774 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2775 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2776}; 2777 2778/** 2779 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2780 */ 2781enum dmub_cmd_clk_mgr_type { 2782 /** 2783 * Notify DMCUB of clock update. 2784 */ 2785 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2786}; 2787 2788/** 2789 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2790 */ 2791struct dmub_rb_cmd_clk_mgr_notify_clocks { 2792 struct dmub_cmd_header header; /**< header */ 2793 struct dmub_clocks clocks; /**< clock data */ 2794}; 2795 2796/** 2797 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2798 */ 2799struct dmub_cmd_digx_encoder_control_data { 2800 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2801}; 2802 2803/** 2804 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2805 */ 2806struct dmub_rb_cmd_digx_encoder_control { 2807 struct dmub_cmd_header header; /**< header */ 2808 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2809}; 2810 2811/** 2812 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2813 */ 2814struct dmub_cmd_set_pixel_clock_data { 2815 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2816}; 2817 2818/** 2819 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2820 */ 2821struct dmub_rb_cmd_set_pixel_clock { 2822 struct dmub_cmd_header header; /**< header */ 2823 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2824}; 2825 2826/** 2827 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2828 */ 2829struct dmub_cmd_enable_disp_power_gating_data { 2830 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2831}; 2832 2833/** 2834 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2835 */ 2836struct dmub_rb_cmd_enable_disp_power_gating { 2837 struct dmub_cmd_header header; /**< header */ 2838 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2839}; 2840 2841/** 2842 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2843 */ 2844struct dmub_dig_transmitter_control_data_v1_7 { 2845 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2846 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2847 union { 2848 uint8_t digmode; /**< enum atom_encode_mode_def */ 2849 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2850 } mode_laneset; 2851 uint8_t lanenum; /**< Number of lanes */ 2852 union { 2853 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2854 } symclk_units; 2855 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2856 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2857 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2858 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2859 uint8_t reserved1; /**< For future use */ 2860 uint8_t skip_phy_ssc_reduction; 2861 uint8_t reserved2[2]; /**< For future use */ 2862 uint32_t reserved3[11]; /**< For future use */ 2863}; 2864 2865/** 2866 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2867 */ 2868union dmub_cmd_dig1_transmitter_control_data { 2869 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2870 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2871}; 2872 2873/** 2874 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2875 */ 2876struct dmub_rb_cmd_dig1_transmitter_control { 2877 struct dmub_cmd_header header; /**< header */ 2878 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2879}; 2880 2881/** 2882 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2883 */ 2884struct dmub_rb_cmd_domain_control_data { 2885 uint8_t inst : 6; /**< DOMAIN instance to control */ 2886 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2887 uint8_t reserved[3]; /**< Reserved for future use */ 2888}; 2889 2890/** 2891 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2892 */ 2893struct dmub_rb_cmd_domain_control { 2894 struct dmub_cmd_header header; /**< header */ 2895 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2896}; 2897 2898/** 2899 * DPIA tunnel command parameters. 2900 */ 2901struct dmub_cmd_dig_dpia_control_data { 2902 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2903 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2904 union { 2905 uint8_t digmode; /** enum atom_encode_mode_def */ 2906 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2907 } mode_laneset; 2908 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2909 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2910 uint8_t hpdsel; /** =0: HPD is not assigned */ 2911 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2912 uint8_t dpia_id; /** Index of DPIA */ 2913 uint8_t fec_rdy : 1; 2914 uint8_t reserved : 7; 2915 uint32_t reserved1; 2916}; 2917 2918/** 2919 * DMUB command for DPIA tunnel control. 2920 */ 2921struct dmub_rb_cmd_dig1_dpia_control { 2922 struct dmub_cmd_header header; 2923 struct dmub_cmd_dig_dpia_control_data dpia_control; 2924}; 2925 2926/** 2927 * SET_CONFIG Command Payload (deprecated) 2928 */ 2929struct set_config_cmd_payload { 2930 uint8_t msg_type; /* set config message type */ 2931 uint8_t msg_data; /* set config message data */ 2932}; 2933 2934/** 2935 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2936 */ 2937struct dmub_cmd_set_config_control_data { 2938 struct set_config_cmd_payload cmd_pkt; 2939 uint8_t instance; /* DPIA instance */ 2940 uint8_t immed_status; /* Immediate status returned in case of error */ 2941}; 2942 2943/** 2944 * SET_CONFIG Request Command Payload 2945 */ 2946struct set_config_request_cmd_payload { 2947 uint8_t instance; /* DPIA instance */ 2948 uint8_t immed_status; /* Immediate status returned in case of error */ 2949 uint8_t msg_type; /* set config message type */ 2950 uint8_t reserved; 2951 uint32_t msg_data; /* set config message data */ 2952}; 2953 2954/** 2955 * DMUB command structure for SET_CONFIG command. 2956 */ 2957struct dmub_rb_cmd_set_config_access { 2958 struct dmub_cmd_header header; /* header */ 2959 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2960}; 2961 2962/** 2963 * DMUB command structure for SET_CONFIG request command. 2964 */ 2965struct dmub_rb_cmd_set_config_request { 2966 struct dmub_cmd_header header; /* header */ 2967 struct set_config_request_cmd_payload payload; /* set config request payload */ 2968}; 2969 2970/** 2971 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2972 */ 2973struct dmub_cmd_mst_alloc_slots_control_data { 2974 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2975 uint8_t instance; /* DPIA instance */ 2976 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2977 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2978}; 2979 2980/** 2981 * DMUB command structure for SET_ command. 2982 */ 2983struct dmub_rb_cmd_set_mst_alloc_slots { 2984 struct dmub_cmd_header header; /* header */ 2985 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2986}; 2987 2988/** 2989 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2990 */ 2991struct dmub_cmd_tps_notification_data { 2992 uint8_t instance; /* DPIA instance */ 2993 uint8_t tps; /* requested training pattern */ 2994 uint8_t reserved1; 2995 uint8_t reserved2; 2996}; 2997 2998/** 2999 * DMUB command structure for SET_TPS_NOTIFICATION command. 3000 */ 3001struct dmub_rb_cmd_set_tps_notification { 3002 struct dmub_cmd_header header; /* header */ 3003 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 3004}; 3005 3006/** 3007 * DMUB command structure for DPIA HPD int enable control. 3008 */ 3009struct dmub_rb_cmd_dpia_hpd_int_enable { 3010 struct dmub_cmd_header header; /* header */ 3011 uint32_t enable; /* dpia hpd interrupt enable */ 3012}; 3013 3014/** 3015 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 3016 */ 3017struct dmub_rb_cmd_dpphy_init { 3018 struct dmub_cmd_header header; /**< header */ 3019 uint8_t reserved[60]; /**< reserved bits */ 3020}; 3021 3022/** 3023 * enum dp_aux_request_action - DP AUX request command listing. 3024 * 3025 * 4 AUX request command bits are shifted to high nibble. 3026 */ 3027enum dp_aux_request_action { 3028 /** I2C-over-AUX write request */ 3029 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 3030 /** I2C-over-AUX read request */ 3031 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 3032 /** I2C-over-AUX write status request */ 3033 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 3034 /** I2C-over-AUX write request with MOT=1 */ 3035 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 3036 /** I2C-over-AUX read request with MOT=1 */ 3037 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 3038 /** I2C-over-AUX write status request with MOT=1 */ 3039 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 3040 /** Native AUX write request */ 3041 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 3042 /** Native AUX read request */ 3043 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 3044}; 3045 3046/** 3047 * enum aux_return_code_type - DP AUX process return code listing. 3048 */ 3049enum aux_return_code_type { 3050 /** AUX process succeeded */ 3051 AUX_RET_SUCCESS = 0, 3052 /** AUX process failed with unknown reason */ 3053 AUX_RET_ERROR_UNKNOWN, 3054 /** AUX process completed with invalid reply */ 3055 AUX_RET_ERROR_INVALID_REPLY, 3056 /** AUX process timed out */ 3057 AUX_RET_ERROR_TIMEOUT, 3058 /** HPD was low during AUX process */ 3059 AUX_RET_ERROR_HPD_DISCON, 3060 /** Failed to acquire AUX engine */ 3061 AUX_RET_ERROR_ENGINE_ACQUIRE, 3062 /** AUX request not supported */ 3063 AUX_RET_ERROR_INVALID_OPERATION, 3064 /** AUX process not available */ 3065 AUX_RET_ERROR_PROTOCOL_ERROR, 3066}; 3067 3068/** 3069 * enum aux_channel_type - DP AUX channel type listing. 3070 */ 3071enum aux_channel_type { 3072 /** AUX thru Legacy DP AUX */ 3073 AUX_CHANNEL_LEGACY_DDC, 3074 /** AUX thru DPIA DP tunneling */ 3075 AUX_CHANNEL_DPIA 3076}; 3077 3078/** 3079 * struct aux_transaction_parameters - DP AUX request transaction data 3080 */ 3081struct aux_transaction_parameters { 3082 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 3083 uint8_t action; /**< enum dp_aux_request_action */ 3084 uint8_t length; /**< DP AUX request data length */ 3085 uint8_t reserved; /**< For future use */ 3086 uint32_t address; /**< DP AUX address */ 3087 uint8_t data[16]; /**< DP AUX write data */ 3088}; 3089 3090/** 3091 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 3092 */ 3093struct dmub_cmd_dp_aux_control_data { 3094 uint8_t instance; /**< AUX instance or DPIA instance */ 3095 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 3096 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 3097 uint8_t reserved0; /**< For future use */ 3098 uint16_t timeout; /**< timeout time in us */ 3099 uint16_t reserved1; /**< For future use */ 3100 enum aux_channel_type type; /**< enum aux_channel_type */ 3101 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 3102}; 3103 3104/** 3105 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3106 */ 3107struct dmub_rb_cmd_dp_aux_access { 3108 /** 3109 * Command header. 3110 */ 3111 struct dmub_cmd_header header; 3112 /** 3113 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 3114 */ 3115 struct dmub_cmd_dp_aux_control_data aux_control; 3116}; 3117 3118/** 3119 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3120 */ 3121struct dmub_rb_cmd_outbox1_enable { 3122 /** 3123 * Command header. 3124 */ 3125 struct dmub_cmd_header header; 3126 /** 3127 * enable: 0x0 -> disable outbox1 notification (default value) 3128 * 0x1 -> enable outbox1 notification 3129 */ 3130 uint32_t enable; 3131}; 3132 3133/* DP AUX Reply command - OutBox Cmd */ 3134/** 3135 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3136 */ 3137struct aux_reply_data { 3138 /** 3139 * Aux cmd 3140 */ 3141 uint8_t command; 3142 /** 3143 * Aux reply data length (max: 16 bytes) 3144 */ 3145 uint8_t length; 3146 /** 3147 * Alignment only 3148 */ 3149 uint8_t pad[2]; 3150 /** 3151 * Aux reply data 3152 */ 3153 uint8_t data[16]; 3154}; 3155 3156/** 3157 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3158 */ 3159struct aux_reply_control_data { 3160 /** 3161 * Reserved for future use 3162 */ 3163 uint32_t handle; 3164 /** 3165 * Aux Instance 3166 */ 3167 uint8_t instance; 3168 /** 3169 * Aux transaction result: definition in enum aux_return_code_type 3170 */ 3171 uint8_t result; 3172 /** 3173 * Alignment only 3174 */ 3175 uint16_t pad; 3176}; 3177 3178/** 3179 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 3180 */ 3181struct dmub_rb_cmd_dp_aux_reply { 3182 /** 3183 * Command header. 3184 */ 3185 struct dmub_cmd_header header; 3186 /** 3187 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3188 */ 3189 struct aux_reply_control_data control; 3190 /** 3191 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3192 */ 3193 struct aux_reply_data reply_data; 3194}; 3195 3196/* DP HPD Notify command - OutBox Cmd */ 3197/** 3198 * DP HPD Type 3199 */ 3200enum dp_hpd_type { 3201 /** 3202 * Normal DP HPD 3203 */ 3204 DP_HPD = 0, 3205 /** 3206 * DP HPD short pulse 3207 */ 3208 DP_IRQ = 1, 3209 /** 3210 * Failure to acquire DP HPD state 3211 */ 3212 DP_NONE_HPD = 2 3213}; 3214 3215/** 3216 * DP HPD Status 3217 */ 3218enum dp_hpd_status { 3219 /** 3220 * DP_HPD status low 3221 */ 3222 DP_HPD_UNPLUG = 0, 3223 /** 3224 * DP_HPD status high 3225 */ 3226 DP_HPD_PLUG 3227}; 3228 3229/** 3230 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3231 */ 3232struct dp_hpd_data { 3233 /** 3234 * DP HPD instance 3235 */ 3236 uint8_t instance; 3237 /** 3238 * HPD type 3239 */ 3240 uint8_t hpd_type; 3241 /** 3242 * HPD status: only for type: DP_HPD to indicate status 3243 */ 3244 uint8_t hpd_status; 3245 /** 3246 * Alignment only 3247 */ 3248 uint8_t pad; 3249}; 3250 3251/** 3252 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3253 */ 3254struct dmub_rb_cmd_dp_hpd_notify { 3255 /** 3256 * Command header. 3257 */ 3258 struct dmub_cmd_header header; 3259 /** 3260 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3261 */ 3262 struct dp_hpd_data hpd_data; 3263}; 3264 3265/** 3266 * Definition of a SET_CONFIG reply from DPOA. 3267 */ 3268enum set_config_status { 3269 SET_CONFIG_PENDING = 0, 3270 SET_CONFIG_ACK_RECEIVED, 3271 SET_CONFIG_RX_TIMEOUT, 3272 SET_CONFIG_UNKNOWN_ERROR, 3273}; 3274 3275/** 3276 * Definition of a set_config reply 3277 */ 3278struct set_config_reply_control_data { 3279 uint8_t instance; /* DPIA Instance */ 3280 uint8_t status; /* Set Config reply */ 3281 uint16_t pad; /* Alignment */ 3282}; 3283 3284/** 3285 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 3286 */ 3287struct dmub_rb_cmd_dp_set_config_reply { 3288 struct dmub_cmd_header header; 3289 struct set_config_reply_control_data set_config_reply_control; 3290}; 3291 3292/** 3293 * Definition of a DPIA notification header 3294 */ 3295struct dpia_notification_header { 3296 uint8_t instance; /**< DPIA Instance */ 3297 uint8_t reserved[3]; 3298 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 3299}; 3300 3301/** 3302 * Definition of the common data struct of DPIA notification 3303 */ 3304struct dpia_notification_common { 3305 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 3306 - sizeof(struct dpia_notification_header)]; 3307}; 3308 3309/** 3310 * Definition of a DPIA notification data 3311 */ 3312struct dpia_bw_allocation_notify_data { 3313 union { 3314 struct { 3315 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 3316 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 3317 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 3318 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 3319 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 3320 uint16_t reserved: 11; /**< Reserved */ 3321 } bits; 3322 3323 uint16_t flags; 3324 }; 3325 3326 uint8_t cm_id; /**< CM ID */ 3327 uint8_t group_id; /**< Group ID */ 3328 uint8_t granularity; /**< BW Allocation Granularity */ 3329 uint8_t estimated_bw; /**< Estimated_BW */ 3330 uint8_t allocated_bw; /**< Allocated_BW */ 3331 uint8_t reserved; 3332}; 3333 3334/** 3335 * union dpia_notify_data_type - DPIA Notification in Outbox command 3336 */ 3337union dpia_notification_data { 3338 /** 3339 * DPIA Notification for common data struct 3340 */ 3341 struct dpia_notification_common common_data; 3342 3343 /** 3344 * DPIA Notification for DP BW Allocation support 3345 */ 3346 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3347}; 3348 3349/** 3350 * Definition of a DPIA notification payload 3351 */ 3352struct dpia_notification_payload { 3353 struct dpia_notification_header header; 3354 union dpia_notification_data data; /**< DPIA notification payload data */ 3355}; 3356 3357/** 3358 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3359 */ 3360struct dmub_rb_cmd_dpia_notification { 3361 struct dmub_cmd_header header; /**< DPIA notification header */ 3362 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3363}; 3364 3365/** 3366 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3367 */ 3368struct dmub_cmd_hpd_state_query_data { 3369 uint8_t instance; /**< HPD instance or DPIA instance */ 3370 uint8_t result; /**< For returning HPD state */ 3371 uint16_t pad; /** < Alignment */ 3372 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3373 enum aux_return_code_type status; /**< for returning the status of command */ 3374}; 3375 3376/** 3377 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3378 */ 3379struct dmub_rb_cmd_query_hpd_state { 3380 /** 3381 * Command header. 3382 */ 3383 struct dmub_cmd_header header; 3384 /** 3385 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3386 */ 3387 struct dmub_cmd_hpd_state_query_data data; 3388}; 3389 3390/** 3391 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3392 */ 3393struct dmub_rb_cmd_hpd_sense_notify_data { 3394 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3395 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3396}; 3397 3398/** 3399 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3400 */ 3401struct dmub_rb_cmd_hpd_sense_notify { 3402 struct dmub_cmd_header header; /**< header */ 3403 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3404}; 3405 3406/* 3407 * Command IDs should be treated as stable ABI. 3408 * Do not reuse or modify IDs. 3409 */ 3410 3411/** 3412 * PSR command sub-types. 3413 */ 3414enum dmub_cmd_psr_type { 3415 /** 3416 * Set PSR version support. 3417 */ 3418 DMUB_CMD__PSR_SET_VERSION = 0, 3419 /** 3420 * Copy driver-calculated parameters to PSR state. 3421 */ 3422 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3423 /** 3424 * Enable PSR. 3425 */ 3426 DMUB_CMD__PSR_ENABLE = 2, 3427 3428 /** 3429 * Disable PSR. 3430 */ 3431 DMUB_CMD__PSR_DISABLE = 3, 3432 3433 /** 3434 * Set PSR level. 3435 * PSR level is a 16-bit value dicated by driver that 3436 * will enable/disable different functionality. 3437 */ 3438 DMUB_CMD__PSR_SET_LEVEL = 4, 3439 3440 /** 3441 * Forces PSR enabled until an explicit PSR disable call. 3442 */ 3443 DMUB_CMD__PSR_FORCE_STATIC = 5, 3444 /** 3445 * Set vtotal in psr active for FreeSync PSR. 3446 */ 3447 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3448 /** 3449 * Set PSR power option 3450 */ 3451 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3452}; 3453 3454/** 3455 * Different PSR residency modes. 3456 * Different modes change the definition of PSR residency. 3457 */ 3458enum psr_residency_mode { 3459 PSR_RESIDENCY_MODE_PHY = 0, 3460 PSR_RESIDENCY_MODE_ALPM, 3461 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3462 /* Do not add below. */ 3463 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3464}; 3465 3466enum dmub_cmd_fams_type { 3467 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3468 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3469 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3470 /** 3471 * For SubVP set manual trigger in FW because it 3472 * triggers DRR_UPDATE_PENDING which SubVP relies 3473 * on (for any SubVP cases that use a DRR display) 3474 */ 3475 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3476 DMUB_CMD__FAMS2_CONFIG = 4, 3477 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3478 DMUB_CMD__FAMS2_FLIP = 6, 3479 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3480}; 3481 3482/** 3483 * PSR versions. 3484 */ 3485enum psr_version { 3486 /** 3487 * PSR version 1. 3488 */ 3489 PSR_VERSION_1 = 0, 3490 /** 3491 * Freesync PSR SU. 3492 */ 3493 PSR_VERSION_SU_1 = 1, 3494 /** 3495 * PSR not supported. 3496 */ 3497 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3498}; 3499 3500/** 3501 * PHY Link rate for DP. 3502 */ 3503enum phy_link_rate { 3504 /** 3505 * not supported. 3506 */ 3507 PHY_RATE_UNKNOWN = 0, 3508 /** 3509 * Rate_1 (RBR) - 1.62 Gbps/Lane 3510 */ 3511 PHY_RATE_162 = 1, 3512 /** 3513 * Rate_2 - 2.16 Gbps/Lane 3514 */ 3515 PHY_RATE_216 = 2, 3516 /** 3517 * Rate_3 - 2.43 Gbps/Lane 3518 */ 3519 PHY_RATE_243 = 3, 3520 /** 3521 * Rate_4 (HBR) - 2.70 Gbps/Lane 3522 */ 3523 PHY_RATE_270 = 4, 3524 /** 3525 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3526 */ 3527 PHY_RATE_324 = 5, 3528 /** 3529 * Rate_6 - 4.32 Gbps/Lane 3530 */ 3531 PHY_RATE_432 = 6, 3532 /** 3533 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3534 */ 3535 PHY_RATE_540 = 7, 3536 /** 3537 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3538 */ 3539 PHY_RATE_810 = 8, 3540 /** 3541 * UHBR10 - 10.0 Gbps/Lane 3542 */ 3543 PHY_RATE_1000 = 9, 3544 /** 3545 * UHBR13.5 - 13.5 Gbps/Lane 3546 */ 3547 PHY_RATE_1350 = 10, 3548 /** 3549 * UHBR10 - 20.0 Gbps/Lane 3550 */ 3551 PHY_RATE_2000 = 11, 3552 3553 PHY_RATE_675 = 12, 3554 /** 3555 * Rate 12 - 6.75 Gbps/Lane 3556 */ 3557}; 3558 3559/** 3560 * enum dmub_phy_fsm_state - PHY FSM states. 3561 * PHY FSM state to transit to during PSR enable/disable. 3562 */ 3563enum dmub_phy_fsm_state { 3564 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3565 DMUB_PHY_FSM_RESET, 3566 DMUB_PHY_FSM_RESET_RELEASED, 3567 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3568 DMUB_PHY_FSM_INITIALIZED, 3569 DMUB_PHY_FSM_CALIBRATED, 3570 DMUB_PHY_FSM_CALIBRATED_LP, 3571 DMUB_PHY_FSM_CALIBRATED_PG, 3572 DMUB_PHY_FSM_POWER_DOWN, 3573 DMUB_PHY_FSM_PLL_EN, 3574 DMUB_PHY_FSM_TX_EN, 3575 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3576 DMUB_PHY_FSM_FAST_LP, 3577 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3578 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3579 DMUB_PHY_FSM_P2_PLL_OFF, 3580 DMUB_PHY_FSM_P2_PLL_ON, 3581}; 3582 3583/** 3584 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3585 */ 3586struct dmub_cmd_psr_copy_settings_data { 3587 /** 3588 * Flags that can be set by driver to change some PSR behaviour. 3589 */ 3590 union dmub_psr_debug_flags debug; 3591 /** 3592 * 16-bit value dicated by driver that will enable/disable different functionality. 3593 */ 3594 uint16_t psr_level; 3595 /** 3596 * DPP HW instance. 3597 */ 3598 uint8_t dpp_inst; 3599 /** 3600 * MPCC HW instance. 3601 * Not used in dmub fw, 3602 * dmub fw will get active opp by reading odm registers. 3603 */ 3604 uint8_t mpcc_inst; 3605 /** 3606 * OPP HW instance. 3607 * Not used in dmub fw, 3608 * dmub fw will get active opp by reading odm registers. 3609 */ 3610 uint8_t opp_inst; 3611 /** 3612 * OTG HW instance. 3613 */ 3614 uint8_t otg_inst; 3615 /** 3616 * DIG FE HW instance. 3617 */ 3618 uint8_t digfe_inst; 3619 /** 3620 * DIG BE HW instance. 3621 */ 3622 uint8_t digbe_inst; 3623 /** 3624 * DP PHY HW instance. 3625 */ 3626 uint8_t dpphy_inst; 3627 /** 3628 * AUX HW instance. 3629 */ 3630 uint8_t aux_inst; 3631 /** 3632 * Determines if SMU optimzations are enabled/disabled. 3633 */ 3634 uint8_t smu_optimizations_en; 3635 /** 3636 * Unused. 3637 * TODO: Remove. 3638 */ 3639 uint8_t frame_delay; 3640 /** 3641 * If RFB setup time is greater than the total VBLANK time, 3642 * it is not possible for the sink to capture the video frame 3643 * in the same frame the SDP is sent. In this case, 3644 * the frame capture indication bit should be set and an extra 3645 * static frame should be transmitted to the sink. 3646 */ 3647 uint8_t frame_cap_ind; 3648 /** 3649 * Granularity of Y offset supported by sink. 3650 */ 3651 uint8_t su_y_granularity; 3652 /** 3653 * Indicates whether sink should start capturing 3654 * immediately following active scan line, 3655 * or starting with the 2nd active scan line. 3656 */ 3657 uint8_t line_capture_indication; 3658 /** 3659 * Multi-display optimizations are implemented on certain ASICs. 3660 */ 3661 uint8_t multi_disp_optimizations_en; 3662 /** 3663 * The last possible line SDP may be transmitted without violating 3664 * the RFB setup time or entering the active video frame. 3665 */ 3666 uint16_t init_sdp_deadline; 3667 /** 3668 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3669 */ 3670 uint8_t rate_control_caps ; 3671 /* 3672 * Force PSRSU always doing full frame update 3673 */ 3674 uint8_t force_ffu_mode; 3675 /** 3676 * Length of each horizontal line in us. 3677 */ 3678 uint32_t line_time_in_us; 3679 /** 3680 * FEC enable status in driver 3681 */ 3682 uint8_t fec_enable_status; 3683 /** 3684 * FEC re-enable delay when PSR exit. 3685 * unit is 100us, range form 0~255(0xFF). 3686 */ 3687 uint8_t fec_enable_delay_in100us; 3688 /** 3689 * PSR control version. 3690 */ 3691 uint8_t cmd_version; 3692 /** 3693 * Panel Instance. 3694 * Panel instance to identify which psr_state to use 3695 * Currently the support is only for 0 or 1 3696 */ 3697 uint8_t panel_inst; 3698 /* 3699 * DSC enable status in driver 3700 */ 3701 uint8_t dsc_enable_status; 3702 /* 3703 * Use FSM state for PSR power up/down 3704 */ 3705 uint8_t use_phy_fsm; 3706 /** 3707 * frame delay for frame re-lock 3708 */ 3709 uint8_t relock_delay_frame_cnt; 3710 /** 3711 * esd recovery indicate. 3712 */ 3713 uint8_t esd_recovery; 3714 /** 3715 * DSC Slice height. 3716 */ 3717 uint16_t dsc_slice_height; 3718 /** 3719 * Some panels request main link off before xth vertical line 3720 */ 3721 uint16_t poweroff_before_vertical_line; 3722 /** 3723 * Some panels cannot handle idle pattern during PSR entry. 3724 * To power down phy before disable stream to avoid sending 3725 * idle pattern. 3726 */ 3727 uint8_t power_down_phy_before_disable_stream; 3728}; 3729 3730/** 3731 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3732 */ 3733struct dmub_rb_cmd_psr_copy_settings { 3734 /** 3735 * Command header. 3736 */ 3737 struct dmub_cmd_header header; 3738 /** 3739 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3740 */ 3741 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3742}; 3743 3744/** 3745 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3746 */ 3747struct dmub_cmd_psr_set_level_data { 3748 /** 3749 * 16-bit value dicated by driver that will enable/disable different functionality. 3750 */ 3751 uint16_t psr_level; 3752 /** 3753 * PSR control version. 3754 */ 3755 uint8_t cmd_version; 3756 /** 3757 * Panel Instance. 3758 * Panel instance to identify which psr_state to use 3759 * Currently the support is only for 0 or 1 3760 */ 3761 uint8_t panel_inst; 3762}; 3763 3764/** 3765 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3766 */ 3767struct dmub_rb_cmd_psr_set_level { 3768 /** 3769 * Command header. 3770 */ 3771 struct dmub_cmd_header header; 3772 /** 3773 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3774 */ 3775 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3776}; 3777 3778struct dmub_rb_cmd_psr_enable_data { 3779 /** 3780 * PSR control version. 3781 */ 3782 uint8_t cmd_version; 3783 /** 3784 * Panel Instance. 3785 * Panel instance to identify which psr_state to use 3786 * Currently the support is only for 0 or 1 3787 */ 3788 uint8_t panel_inst; 3789 /** 3790 * Phy state to enter. 3791 * Values to use are defined in dmub_phy_fsm_state 3792 */ 3793 uint8_t phy_fsm_state; 3794 /** 3795 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3796 * Set this using enum phy_link_rate. 3797 * This does not support HDMI/DP2 for now. 3798 */ 3799 uint8_t phy_rate; 3800}; 3801 3802/** 3803 * Definition of a DMUB_CMD__PSR_ENABLE command. 3804 * PSR enable/disable is controlled using the sub_type. 3805 */ 3806struct dmub_rb_cmd_psr_enable { 3807 /** 3808 * Command header. 3809 */ 3810 struct dmub_cmd_header header; 3811 3812 struct dmub_rb_cmd_psr_enable_data data; 3813}; 3814 3815/** 3816 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3817 */ 3818struct dmub_cmd_psr_set_version_data { 3819 /** 3820 * PSR version that FW should implement. 3821 */ 3822 enum psr_version version; 3823 /** 3824 * PSR control version. 3825 */ 3826 uint8_t cmd_version; 3827 /** 3828 * Panel Instance. 3829 * Panel instance to identify which psr_state to use 3830 * Currently the support is only for 0 or 1 3831 */ 3832 uint8_t panel_inst; 3833 /** 3834 * Explicit padding to 4 byte boundary. 3835 */ 3836 uint8_t pad[2]; 3837}; 3838 3839/** 3840 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3841 */ 3842struct dmub_rb_cmd_psr_set_version { 3843 /** 3844 * Command header. 3845 */ 3846 struct dmub_cmd_header header; 3847 /** 3848 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3849 */ 3850 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3851}; 3852 3853struct dmub_cmd_psr_force_static_data { 3854 /** 3855 * PSR control version. 3856 */ 3857 uint8_t cmd_version; 3858 /** 3859 * Panel Instance. 3860 * Panel instance to identify which psr_state to use 3861 * Currently the support is only for 0 or 1 3862 */ 3863 uint8_t panel_inst; 3864 /** 3865 * Explicit padding to 4 byte boundary. 3866 */ 3867 uint8_t pad[2]; 3868}; 3869 3870/** 3871 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3872 */ 3873struct dmub_rb_cmd_psr_force_static { 3874 /** 3875 * Command header. 3876 */ 3877 struct dmub_cmd_header header; 3878 /** 3879 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3880 */ 3881 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3882}; 3883 3884/** 3885 * PSR SU debug flags. 3886 */ 3887union dmub_psr_su_debug_flags { 3888 /** 3889 * PSR SU debug flags. 3890 */ 3891 struct { 3892 /** 3893 * Update dirty rect in SW only. 3894 */ 3895 uint8_t update_dirty_rect_only : 1; 3896 /** 3897 * Reset the cursor/plane state before processing the call. 3898 */ 3899 uint8_t reset_state : 1; 3900 } bitfields; 3901 3902 /** 3903 * Union for debug flags. 3904 */ 3905 uint32_t u32All; 3906}; 3907 3908/** 3909 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3910 * This triggers a selective update for PSR SU. 3911 */ 3912struct dmub_cmd_update_dirty_rect_data { 3913 /** 3914 * Dirty rects from OS. 3915 */ 3916 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3917 /** 3918 * PSR SU debug flags. 3919 */ 3920 union dmub_psr_su_debug_flags debug_flags; 3921 /** 3922 * OTG HW instance. 3923 */ 3924 uint8_t pipe_idx; 3925 /** 3926 * Number of dirty rects. 3927 */ 3928 uint8_t dirty_rect_count; 3929 /** 3930 * PSR control version. 3931 */ 3932 uint8_t cmd_version; 3933 /** 3934 * Panel Instance. 3935 * Panel instance to identify which psr_state to use 3936 * Currently the support is only for 0 or 1 3937 */ 3938 uint8_t panel_inst; 3939}; 3940 3941/** 3942 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3943 */ 3944struct dmub_rb_cmd_update_dirty_rect { 3945 /** 3946 * Command header. 3947 */ 3948 struct dmub_cmd_header header; 3949 /** 3950 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3951 */ 3952 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3953}; 3954 3955/** 3956 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3957 */ 3958union dmub_reg_cursor_control_cfg { 3959 struct { 3960 uint32_t cur_enable: 1; 3961 uint32_t reser0: 3; 3962 uint32_t cur_2x_magnify: 1; 3963 uint32_t reser1: 3; 3964 uint32_t mode: 3; 3965 uint32_t reser2: 5; 3966 uint32_t pitch: 2; 3967 uint32_t reser3: 6; 3968 uint32_t line_per_chunk: 5; 3969 uint32_t reser4: 3; 3970 } bits; 3971 uint32_t raw; 3972}; 3973struct dmub_cursor_position_cache_hubp { 3974 union dmub_reg_cursor_control_cfg cur_ctl; 3975 union dmub_reg_position_cfg { 3976 struct { 3977 uint32_t cur_x_pos: 16; 3978 uint32_t cur_y_pos: 16; 3979 } bits; 3980 uint32_t raw; 3981 } position; 3982 union dmub_reg_hot_spot_cfg { 3983 struct { 3984 uint32_t hot_x: 16; 3985 uint32_t hot_y: 16; 3986 } bits; 3987 uint32_t raw; 3988 } hot_spot; 3989 union dmub_reg_dst_offset_cfg { 3990 struct { 3991 uint32_t dst_x_offset: 13; 3992 uint32_t reserved: 19; 3993 } bits; 3994 uint32_t raw; 3995 } dst_offset; 3996}; 3997 3998union dmub_reg_cur0_control_cfg { 3999 struct { 4000 uint32_t cur0_enable: 1; 4001 uint32_t expansion_mode: 1; 4002 uint32_t reser0: 1; 4003 uint32_t cur0_rom_en: 1; 4004 uint32_t mode: 3; 4005 uint32_t reserved: 25; 4006 } bits; 4007 uint32_t raw; 4008}; 4009struct dmub_cursor_position_cache_dpp { 4010 union dmub_reg_cur0_control_cfg cur0_ctl; 4011}; 4012struct dmub_cursor_position_cfg { 4013 struct dmub_cursor_position_cache_hubp pHubp; 4014 struct dmub_cursor_position_cache_dpp pDpp; 4015 uint8_t pipe_idx; 4016 /* 4017 * Padding is required. To be 4 Bytes Aligned. 4018 */ 4019 uint8_t padding[3]; 4020}; 4021 4022struct dmub_cursor_attribute_cache_hubp { 4023 uint32_t SURFACE_ADDR_HIGH; 4024 uint32_t SURFACE_ADDR; 4025 union dmub_reg_cursor_control_cfg cur_ctl; 4026 union dmub_reg_cursor_size_cfg { 4027 struct { 4028 uint32_t width: 16; 4029 uint32_t height: 16; 4030 } bits; 4031 uint32_t raw; 4032 } size; 4033 union dmub_reg_cursor_settings_cfg { 4034 struct { 4035 uint32_t dst_y_offset: 8; 4036 uint32_t chunk_hdl_adjust: 2; 4037 uint32_t reserved: 22; 4038 } bits; 4039 uint32_t raw; 4040 } settings; 4041}; 4042struct dmub_cursor_attribute_cache_dpp { 4043 union dmub_reg_cur0_control_cfg cur0_ctl; 4044}; 4045struct dmub_cursor_attributes_cfg { 4046 struct dmub_cursor_attribute_cache_hubp aHubp; 4047 struct dmub_cursor_attribute_cache_dpp aDpp; 4048}; 4049 4050struct dmub_cmd_update_cursor_payload0 { 4051 /** 4052 * Cursor dirty rects. 4053 */ 4054 struct dmub_rect cursor_rect; 4055 /** 4056 * PSR SU debug flags. 4057 */ 4058 union dmub_psr_su_debug_flags debug_flags; 4059 /** 4060 * Cursor enable/disable. 4061 */ 4062 uint8_t enable; 4063 /** 4064 * OTG HW instance. 4065 */ 4066 uint8_t pipe_idx; 4067 /** 4068 * PSR control version. 4069 */ 4070 uint8_t cmd_version; 4071 /** 4072 * Panel Instance. 4073 * Panel instance to identify which psr_state to use 4074 * Currently the support is only for 0 or 1 4075 */ 4076 uint8_t panel_inst; 4077 /** 4078 * Cursor Position Register. 4079 * Registers contains Hubp & Dpp modules 4080 */ 4081 struct dmub_cursor_position_cfg position_cfg; 4082}; 4083 4084struct dmub_cmd_update_cursor_payload1 { 4085 struct dmub_cursor_attributes_cfg attribute_cfg; 4086}; 4087 4088union dmub_cmd_update_cursor_info_data { 4089 struct dmub_cmd_update_cursor_payload0 payload0; 4090 struct dmub_cmd_update_cursor_payload1 payload1; 4091}; 4092/** 4093 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 4094 */ 4095struct dmub_rb_cmd_update_cursor_info { 4096 /** 4097 * Command header. 4098 */ 4099 struct dmub_cmd_header header; 4100 /** 4101 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 4102 */ 4103 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 4104}; 4105 4106/** 4107 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4108 */ 4109struct dmub_cmd_psr_set_vtotal_data { 4110 /** 4111 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 4112 */ 4113 uint16_t psr_vtotal_idle; 4114 /** 4115 * PSR control version. 4116 */ 4117 uint8_t cmd_version; 4118 /** 4119 * Panel Instance. 4120 * Panel instance to identify which psr_state to use 4121 * Currently the support is only for 0 or 1 4122 */ 4123 uint8_t panel_inst; 4124 /* 4125 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 4126 */ 4127 uint16_t psr_vtotal_su; 4128 /** 4129 * Explicit padding to 4 byte boundary. 4130 */ 4131 uint8_t pad2[2]; 4132}; 4133 4134/** 4135 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4136 */ 4137struct dmub_rb_cmd_psr_set_vtotal { 4138 /** 4139 * Command header. 4140 */ 4141 struct dmub_cmd_header header; 4142 /** 4143 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4144 */ 4145 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 4146}; 4147 4148/** 4149 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 4150 */ 4151struct dmub_cmd_psr_set_power_opt_data { 4152 /** 4153 * PSR control version. 4154 */ 4155 uint8_t cmd_version; 4156 /** 4157 * Panel Instance. 4158 * Panel instance to identify which psr_state to use 4159 * Currently the support is only for 0 or 1 4160 */ 4161 uint8_t panel_inst; 4162 /** 4163 * Explicit padding to 4 byte boundary. 4164 */ 4165 uint8_t pad[2]; 4166 /** 4167 * PSR power option 4168 */ 4169 uint32_t power_opt; 4170}; 4171 4172/** 4173 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4174 */ 4175struct dmub_rb_cmd_psr_set_power_opt { 4176 /** 4177 * Command header. 4178 */ 4179 struct dmub_cmd_header header; 4180 /** 4181 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4182 */ 4183 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 4184}; 4185 4186enum dmub_alpm_mode { 4187 ALPM_AUXWAKE = 0, 4188 ALPM_AUXLESS = 1, 4189 ALPM_UNSUPPORTED = 2, 4190}; 4191 4192/** 4193 * Definition of Replay Residency GPINT command. 4194 * Bit[0] - Residency mode for Revision 0 4195 * Bit[1] - Enable/Disable state 4196 * Bit[2-3] - Revision number 4197 * Bit[4-7] - Residency mode for Revision 1 4198 * Bit[8] - Panel instance 4199 * Bit[9-15] - Reserved 4200 */ 4201 4202enum pr_residency_mode { 4203 PR_RESIDENCY_MODE_PHY = 0x0, 4204 PR_RESIDENCY_MODE_ALPM, 4205 PR_RESIDENCY_MODE_IPS2, 4206 PR_RESIDENCY_MODE_FRAME_CNT, 4207 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 4208}; 4209 4210#define REPLAY_RESIDENCY_MODE_SHIFT (0) 4211#define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 4212#define REPLAY_RESIDENCY_REVISION_SHIFT (2) 4213#define REPLAY_RESIDENCY_MODE2_SHIFT (4) 4214 4215#define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4216# define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 4217# define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4218 4219#define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 4220# define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 4221# define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 4222# define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 4223 4224#define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4225# define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4226# define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4227 4228#define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 4229# define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 4230# define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 4231 4232/** 4233 * Definition of a replay_state. 4234 */ 4235enum replay_state { 4236 REPLAY_STATE_0 = 0x0, 4237 REPLAY_STATE_1 = 0x10, 4238 REPLAY_STATE_1A = 0x11, 4239 REPLAY_STATE_2 = 0x20, 4240 REPLAY_STATE_2A = 0x21, 4241 REPLAY_STATE_3 = 0x30, 4242 REPLAY_STATE_3INIT = 0x31, 4243 REPLAY_STATE_4 = 0x40, 4244 REPLAY_STATE_4A = 0x41, 4245 REPLAY_STATE_4B = 0x42, 4246 REPLAY_STATE_4C = 0x43, 4247 REPLAY_STATE_4D = 0x44, 4248 REPLAY_STATE_4E = 0x45, 4249 REPLAY_STATE_4B_LOCKED = 0x4A, 4250 REPLAY_STATE_4C_UNLOCKED = 0x4B, 4251 REPLAY_STATE_5 = 0x50, 4252 REPLAY_STATE_5A = 0x51, 4253 REPLAY_STATE_5B = 0x52, 4254 REPLAY_STATE_5A_LOCKED = 0x5A, 4255 REPLAY_STATE_5B_UNLOCKED = 0x5B, 4256 REPLAY_STATE_6 = 0x60, 4257 REPLAY_STATE_6A = 0x61, 4258 REPLAY_STATE_6B = 0x62, 4259 REPLAY_STATE_INVALID = 0xFF, 4260}; 4261 4262/** 4263 * Definition of a panel replay state 4264 */ 4265enum pr_state { 4266 PR_STATE_0 = 0x00, // State 0 steady state 4267 // Pending SDP and Unlock before back to State 0 4268 PR_STATE_0_PENDING_SDP_AND_UNLOCK = 0x01, 4269 PR_STATE_1 = 0x10, // State 1 4270 PR_STATE_2 = 0x20, // State 2 steady state 4271 // Pending frame transmission before transition to State 2 4272 PR_STATE_2_PENDING_FRAME_TRANSMISSION = 0x30, 4273 // Active and Powered Up 4274 PR_STATE_2_POWERED = 0x31, 4275 // Active and Powered Down, but need to blank HUBP after DPG_EN latch 4276 PR_STATE_2_PENDING_HUBP_BLANK = 0x32, 4277 // Active and Pending Power Up 4278 PR_STATE_2_PENDING_POWER_UP = 0x33, 4279 // Active and Powered Up, Pending DPG latch 4280 PR_STATE_2_PENDING_LOCK_FOR_DPG_POWER_ON = 0x34, 4281 // Active and Powered Up, Pending SDP and Unlock 4282 PR_STATE_2_PENDING_SDP_AND_UNLOCK = 0x35, 4283 // Pending transmission of AS SDP for timing sync, but no rfb update 4284 PR_STATE_2_PENDING_AS_SDP = 0x36, 4285 // Invalid 4286 PR_STATE_INVALID = 0xFF, 4287}; 4288 4289/** 4290 * Replay command sub-types. 4291 */ 4292enum dmub_cmd_replay_type { 4293 /** 4294 * Copy driver-calculated parameters to REPLAY state. 4295 */ 4296 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 4297 /** 4298 * Enable REPLAY. 4299 */ 4300 DMUB_CMD__REPLAY_ENABLE = 1, 4301 /** 4302 * Set Replay power option. 4303 */ 4304 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 4305 /** 4306 * Set coasting vtotal. 4307 */ 4308 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 4309 /** 4310 * Set power opt and coasting vtotal. 4311 */ 4312 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 4313 /** 4314 * Set disabled iiming sync. 4315 */ 4316 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 4317 /** 4318 * Set Residency Frameupdate Timer. 4319 */ 4320 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 4321 /** 4322 * Set pseudo vtotal 4323 */ 4324 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 4325 /** 4326 * Set adaptive sync sdp enabled 4327 */ 4328 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 4329 /** 4330 * Set version 4331 */ 4332 DMUB_CMD__REPLAY_SET_VERSION = 9, 4333 /** 4334 * Set Replay General command. 4335 */ 4336 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 4337}; 4338 4339/* 4340 * Panel Replay sub-types 4341 */ 4342enum dmub_cmd_panel_replay_type { 4343 DMUB_CMD__PR_ENABLE = 0, 4344 DMUB_CMD__PR_COPY_SETTINGS = 1, 4345 DMUB_CMD__PR_UPDATE_STATE = 2, 4346 DMUB_CMD__PR_GENERAL_CMD = 3, 4347}; 4348 4349enum dmub_cmd_panel_replay_state_update_subtype { 4350 PR_STATE_UPDATE_COASTING_VTOTAL = 0x1, 4351 PR_STATE_UPDATE_SYNC_MODE = 0x2, 4352}; 4353 4354enum dmub_cmd_panel_replay_general_subtype { 4355 PR_GENERAL_CMD_DEBUG_OPTION = 0x1, 4356}; 4357 4358/** 4359 * Replay general command sub-types. 4360 */ 4361enum dmub_cmd_replay_general_subtype { 4362 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 4363 /** 4364 * TODO: For backward compatible, allow new command only. 4365 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 4366 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 4367 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 4368 */ 4369 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 4370 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 4371 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 4372 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4373 REPLAY_GENERAL_CMD_VIDEO_CONFERENCING, 4374}; 4375 4376struct dmub_alpm_auxless_data { 4377 uint16_t lfps_setup_ns; 4378 uint16_t lfps_period_ns; 4379 uint16_t lfps_silence_ns; 4380 uint16_t lfps_t1_t2_override_us; 4381 short lfps_t1_t2_offset_us; 4382 uint8_t lttpr_count; 4383 /* 4384 * Padding to align structure to 4 byte boundary. 4385 */ 4386 uint8_t pad[1]; 4387}; 4388 4389/** 4390 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4391 */ 4392struct dmub_cmd_replay_copy_settings_data { 4393 /** 4394 * Flags that can be set by driver to change some replay behaviour. 4395 */ 4396 union replay_debug_flags debug; 4397 4398 /** 4399 * @flags: Flags used to determine feature functionality. 4400 */ 4401 union replay_hw_flags flags; 4402 4403 /** 4404 * DPP HW instance. 4405 */ 4406 uint8_t dpp_inst; 4407 /** 4408 * OTG HW instance. 4409 */ 4410 uint8_t otg_inst; 4411 /** 4412 * DIG FE HW instance. 4413 */ 4414 uint8_t digfe_inst; 4415 /** 4416 * DIG BE HW instance. 4417 */ 4418 uint8_t digbe_inst; 4419 /** 4420 * AUX HW instance. 4421 */ 4422 uint8_t aux_inst; 4423 /** 4424 * Panel Instance. 4425 * Panel isntance to identify which psr_state to use 4426 * Currently the support is only for 0 or 1 4427 */ 4428 uint8_t panel_inst; 4429 /** 4430 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4431 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4432 */ 4433 uint8_t pixel_deviation_per_line; 4434 /** 4435 * @max_deviation_line: The max number of deviation line that can keep the timing 4436 * synchronized between the Source and Sink during Replay normal sleep mode. 4437 */ 4438 uint8_t max_deviation_line; 4439 /** 4440 * Length of each horizontal line in ns. 4441 */ 4442 uint32_t line_time_in_ns; 4443 /** 4444 * PHY instance. 4445 */ 4446 uint8_t dpphy_inst; 4447 /** 4448 * Determines if SMU optimzations are enabled/disabled. 4449 */ 4450 uint8_t smu_optimizations_en; 4451 /** 4452 * Determines if timing sync are enabled/disabled. 4453 */ 4454 uint8_t replay_timing_sync_supported; 4455 /* 4456 * Use FSM state for Replay power up/down 4457 */ 4458 uint8_t use_phy_fsm; 4459 /** 4460 * Use for AUX-less ALPM LFPS wake operation 4461 */ 4462 struct dmub_alpm_auxless_data auxless_alpm_data; 4463 /** 4464 * @hpo_stream_enc_inst: HPO stream encoder instance 4465 */ 4466 uint8_t hpo_stream_enc_inst; 4467 /** 4468 * @hpo_link_enc_inst: HPO link encoder instance 4469 */ 4470 uint8_t hpo_link_enc_inst; 4471 /** 4472 * Determines if fast resync in ultra sleep mode is enabled/disabled. 4473 */ 4474 uint8_t replay_support_fast_resync_in_ultra_sleep_mode; 4475 /** 4476 * @pad: Align structure to 4 byte boundary. 4477 */ 4478 uint8_t pad[1]; 4479}; 4480 4481 4482/** 4483 * Replay versions. 4484 */ 4485enum replay_version { 4486 /** 4487 * FreeSync Replay 4488 */ 4489 REPLAY_VERSION_FREESYNC_REPLAY = 0, 4490 /** 4491 * Panel Replay 4492 */ 4493 REPLAY_VERSION_PANEL_REPLAY = 1, 4494 /** 4495 * Replay not supported. 4496 */ 4497 REPLAY_VERSION_UNSUPPORTED = 0xFF, 4498}; 4499 4500/** 4501 * Data passed from driver to FW in a DMUB_CMD___SET_REPLAY_VERSION command. 4502 */ 4503struct dmub_cmd_replay_set_version_data { 4504 /** 4505 * Panel Instance. 4506 * Panel instance to identify which psr_state to use 4507 * Currently the support is only for 0 or 1 4508 */ 4509 uint8_t panel_inst; 4510 /** 4511 * Replay version that FW should implement. 4512 */ 4513 enum replay_version version; 4514 /** 4515 * Explicit padding to 4 byte boundary. 4516 */ 4517 uint8_t pad[3]; 4518}; 4519 4520/** 4521 * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. 4522 */ 4523struct dmub_rb_cmd_replay_set_version { 4524 /** 4525 * Command header. 4526 */ 4527 struct dmub_cmd_header header; 4528 /** 4529 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_VERSION command. 4530 */ 4531 struct dmub_cmd_replay_set_version_data replay_set_version_data; 4532}; 4533 4534/** 4535 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4536 */ 4537struct dmub_rb_cmd_replay_copy_settings { 4538 /** 4539 * Command header. 4540 */ 4541 struct dmub_cmd_header header; 4542 /** 4543 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4544 */ 4545 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4546}; 4547 4548/** 4549 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4550 */ 4551enum replay_enable { 4552 /** 4553 * Disable REPLAY. 4554 */ 4555 REPLAY_DISABLE = 0, 4556 /** 4557 * Enable REPLAY. 4558 */ 4559 REPLAY_ENABLE = 1, 4560}; 4561 4562/** 4563 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_ENABLE command. 4564 */ 4565struct dmub_rb_cmd_smart_power_oled_enable_data { 4566 /** 4567 * SMART_POWER_OLED enable or disable. 4568 */ 4569 uint8_t enable; 4570 /** 4571 * Panel Instance. 4572 * Panel isntance to identify which replay_state to use 4573 * Currently the support is only for 0 or 1 4574 */ 4575 uint8_t panel_inst; 4576 4577 uint16_t peak_nits; 4578 /** 4579 * OTG HW instance. 4580 */ 4581 uint8_t otg_inst; 4582 /** 4583 * DIG FE HW instance. 4584 */ 4585 uint8_t digfe_inst; 4586 /** 4587 * DIG BE HW instance. 4588 */ 4589 uint8_t digbe_inst; 4590 uint8_t debugcontrol; 4591 /* 4592 * vertical interrupt trigger line 4593 */ 4594 uint32_t triggerline; 4595 4596 uint16_t fixed_max_cll; 4597 4598 uint8_t pad[2]; 4599}; 4600 4601/** 4602 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4603 */ 4604struct dmub_rb_cmd_replay_enable_data { 4605 /** 4606 * Replay enable or disable. 4607 */ 4608 uint8_t enable; 4609 /** 4610 * Panel Instance. 4611 * Panel isntance to identify which replay_state to use 4612 * Currently the support is only for 0 or 1 4613 */ 4614 uint8_t panel_inst; 4615 /** 4616 * Phy state to enter. 4617 * Values to use are defined in dmub_phy_fsm_state 4618 */ 4619 uint8_t phy_fsm_state; 4620 /** 4621 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4622 * Set this using enum phy_link_rate. 4623 * This does not support HDMI/DP2 for now. 4624 */ 4625 uint8_t phy_rate; 4626}; 4627 4628/** 4629 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4630 * Replay enable/disable is controlled using action in data. 4631 */ 4632struct dmub_rb_cmd_replay_enable { 4633 /** 4634 * Command header. 4635 */ 4636 struct dmub_cmd_header header; 4637 4638 struct dmub_rb_cmd_replay_enable_data data; 4639}; 4640 4641/** 4642 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4643 */ 4644struct dmub_cmd_replay_set_power_opt_data { 4645 /** 4646 * Panel Instance. 4647 * Panel isntance to identify which replay_state to use 4648 * Currently the support is only for 0 or 1 4649 */ 4650 uint8_t panel_inst; 4651 /** 4652 * Explicit padding to 4 byte boundary. 4653 */ 4654 uint8_t pad[3]; 4655 /** 4656 * REPLAY power option 4657 */ 4658 uint32_t power_opt; 4659}; 4660 4661/** 4662 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4663 */ 4664struct dmub_cmd_replay_set_timing_sync_data { 4665 /** 4666 * Panel Instance. 4667 * Panel isntance to identify which replay_state to use 4668 * Currently the support is only for 0 or 1 4669 */ 4670 uint8_t panel_inst; 4671 /** 4672 * REPLAY set_timing_sync 4673 */ 4674 uint8_t timing_sync_supported; 4675 /** 4676 * Explicit padding to 4 byte boundary. 4677 */ 4678 uint8_t pad[2]; 4679}; 4680 4681/** 4682 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4683 */ 4684struct dmub_cmd_replay_set_pseudo_vtotal { 4685 /** 4686 * Panel Instance. 4687 * Panel isntance to identify which replay_state to use 4688 * Currently the support is only for 0 or 1 4689 */ 4690 uint8_t panel_inst; 4691 /** 4692 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4693 */ 4694 uint16_t vtotal; 4695 /** 4696 * Explicit padding to 4 byte boundary. 4697 */ 4698 uint8_t pad; 4699}; 4700struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4701 /** 4702 * Panel Instance. 4703 * Panel isntance to identify which replay_state to use 4704 * Currently the support is only for 0 or 1 4705 */ 4706 uint8_t panel_inst; 4707 /** 4708 * enabled: set adaptive sync sdp enabled 4709 */ 4710 uint8_t force_disabled; 4711 4712 uint8_t pad[2]; 4713}; 4714struct dmub_cmd_replay_set_general_cmd_data { 4715 /** 4716 * Panel Instance. 4717 * Panel isntance to identify which replay_state to use 4718 * Currently the support is only for 0 or 1 4719 */ 4720 uint8_t panel_inst; 4721 /** 4722 * subtype: replay general cmd sub type 4723 */ 4724 uint8_t subtype; 4725 4726 uint8_t pad[2]; 4727 /** 4728 * config data with param1 and param2 4729 */ 4730 uint32_t param1; 4731 4732 uint32_t param2; 4733}; 4734 4735/** 4736 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4737 */ 4738struct dmub_rb_cmd_replay_set_power_opt { 4739 /** 4740 * Command header. 4741 */ 4742 struct dmub_cmd_header header; 4743 /** 4744 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4745 */ 4746 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4747}; 4748 4749/** 4750 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4751 */ 4752struct dmub_cmd_replay_set_coasting_vtotal_data { 4753 /** 4754 * 16-bit value dicated by driver that indicates the coasting vtotal. 4755 */ 4756 uint16_t coasting_vtotal; 4757 /** 4758 * REPLAY control version. 4759 */ 4760 uint8_t cmd_version; 4761 /** 4762 * Panel Instance. 4763 * Panel isntance to identify which replay_state to use 4764 * Currently the support is only for 0 or 1 4765 */ 4766 uint8_t panel_inst; 4767 /** 4768 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4769 */ 4770 uint16_t coasting_vtotal_high; 4771 /** 4772 * frame skip number. 4773 */ 4774 uint16_t frame_skip_number; 4775}; 4776 4777/** 4778 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4779 */ 4780struct dmub_rb_cmd_replay_set_coasting_vtotal { 4781 /** 4782 * Command header. 4783 */ 4784 struct dmub_cmd_header header; 4785 /** 4786 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4787 */ 4788 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4789}; 4790 4791/** 4792 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4793 */ 4794struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4795 /** 4796 * Command header. 4797 */ 4798 struct dmub_cmd_header header; 4799 /** 4800 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4801 */ 4802 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4803 /** 4804 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4805 */ 4806 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4807}; 4808 4809/** 4810 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4811 */ 4812struct dmub_rb_cmd_replay_set_timing_sync { 4813 /** 4814 * Command header. 4815 */ 4816 struct dmub_cmd_header header; 4817 /** 4818 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4819 */ 4820 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4821}; 4822 4823/** 4824 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4825 */ 4826struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4827 /** 4828 * Command header. 4829 */ 4830 struct dmub_cmd_header header; 4831 /** 4832 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4833 */ 4834 struct dmub_cmd_replay_set_pseudo_vtotal data; 4835}; 4836 4837/** 4838 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4839 */ 4840struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4841 /** 4842 * Command header. 4843 */ 4844 struct dmub_cmd_header header; 4845 /** 4846 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4847 */ 4848 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4849}; 4850 4851/** 4852 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4853 */ 4854struct dmub_rb_cmd_replay_set_general_cmd { 4855 /** 4856 * Command header. 4857 */ 4858 struct dmub_cmd_header header; 4859 /** 4860 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4861 */ 4862 struct dmub_cmd_replay_set_general_cmd_data data; 4863}; 4864 4865/** 4866 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4867 */ 4868struct dmub_cmd_replay_frameupdate_timer_data { 4869 /** 4870 * Panel Instance. 4871 * Panel isntance to identify which replay_state to use 4872 * Currently the support is only for 0 or 1 4873 */ 4874 uint8_t panel_inst; 4875 /** 4876 * Replay Frameupdate Timer Enable or not 4877 */ 4878 uint8_t enable; 4879 /** 4880 * REPLAY force reflash frame update number 4881 */ 4882 uint16_t frameupdate_count; 4883}; 4884/** 4885 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4886 */ 4887struct dmub_rb_cmd_replay_set_frameupdate_timer { 4888 /** 4889 * Command header. 4890 */ 4891 struct dmub_cmd_header header; 4892 /** 4893 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4894 */ 4895 struct dmub_cmd_replay_frameupdate_timer_data data; 4896}; 4897 4898/** 4899 * Definition union of replay command set 4900 */ 4901union dmub_replay_cmd_set { 4902 /** 4903 * Panel Instance. 4904 * Panel isntance to identify which replay_state to use 4905 * Currently the support is only for 0 or 1 4906 */ 4907 uint8_t panel_inst; 4908 /** 4909 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4910 */ 4911 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4912 /** 4913 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4914 */ 4915 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4916 /** 4917 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4918 */ 4919 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4920 /** 4921 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4922 */ 4923 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4924 /** 4925 * Definition of DMUB_CMD__REPLAY_SET_VERSION command data. 4926 */ 4927 struct dmub_cmd_replay_set_version_data version_data; 4928 /** 4929 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4930 */ 4931 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4932}; 4933 4934/** 4935 * SMART POWER OLED command sub-types. 4936 */ 4937enum dmub_cmd_smart_power_oled_type { 4938 4939 /** 4940 * Enable/Disable SMART_POWER_OLED. 4941 */ 4942 DMUB_CMD__SMART_POWER_OLED_ENABLE = 1, 4943 /** 4944 * Get current MaxCLL value if SMART POWER OLED is enabled. 4945 */ 4946 DMUB_CMD__SMART_POWER_OLED_GETMAXCLL = 2, 4947}; 4948 4949/** 4950 * Definition of a DMUB_CMD__SMART_POWER_OLED command. 4951 */ 4952struct dmub_rb_cmd_smart_power_oled_enable { 4953 /** 4954 * Command header. 4955 */ 4956 struct dmub_cmd_header header; 4957 4958 struct dmub_rb_cmd_smart_power_oled_enable_data data; 4959}; 4960 4961struct dmub_cmd_smart_power_oled_getmaxcll_input { 4962 uint8_t panel_inst; 4963 uint8_t pad[3]; 4964}; 4965 4966struct dmub_cmd_smart_power_oled_getmaxcll_output { 4967 uint16_t current_max_cll; 4968 uint8_t pad[2]; 4969}; 4970 4971/** 4972 * Definition of a DMUB_CMD__SMART_POWER_OLED command. 4973 */ 4974struct dmub_rb_cmd_smart_power_oled_getmaxcll { 4975 struct dmub_cmd_header header; /**< Command header */ 4976 /** 4977 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. 4978 */ 4979 union dmub_cmd_smart_power_oled_getmaxcll_data { 4980 struct dmub_cmd_smart_power_oled_getmaxcll_input input; /**< Input */ 4981 struct dmub_cmd_smart_power_oled_getmaxcll_output output; /**< Output */ 4982 uint32_t output_raw; /**< Raw data output */ 4983 } data; 4984}; 4985 4986/** 4987 * Set of HW components that can be locked. 4988 * 4989 * Note: If updating with more HW components, fields 4990 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4991 */ 4992union dmub_hw_lock_flags { 4993 /** 4994 * Set of HW components that can be locked. 4995 */ 4996 struct { 4997 /** 4998 * Lock/unlock OTG master update lock. 4999 */ 5000 uint8_t lock_pipe : 1; 5001 /** 5002 * Lock/unlock cursor. 5003 */ 5004 uint8_t lock_cursor : 1; 5005 /** 5006 * Lock/unlock global update lock. 5007 */ 5008 uint8_t lock_dig : 1; 5009 /** 5010 * Triple buffer lock requires additional hw programming to usual OTG master lock. 5011 */ 5012 uint8_t triple_buffer_lock : 1; 5013 } bits; 5014 5015 /** 5016 * Union for HW Lock flags. 5017 */ 5018 uint8_t u8All; 5019}; 5020 5021/** 5022 * Instances of HW to be locked. 5023 * 5024 * Note: If updating with more HW components, fields 5025 * in dmub_inbox0_cmd_lock_hw must be updated to match. 5026 */ 5027struct dmub_hw_lock_inst_flags { 5028 /** 5029 * OTG HW instance for OTG master update lock. 5030 */ 5031 uint8_t otg_inst; 5032 /** 5033 * OPP instance for cursor lock. 5034 */ 5035 uint8_t opp_inst; 5036 /** 5037 * OTG HW instance for global update lock. 5038 * TODO: Remove, and re-use otg_inst. 5039 */ 5040 uint8_t dig_inst; 5041 /** 5042 * Explicit pad to 4 byte boundary. 5043 */ 5044 uint8_t pad; 5045}; 5046 5047/** 5048 * Clients that can acquire the HW Lock Manager. 5049 * 5050 * Note: If updating with more clients, fields in 5051 * dmub_inbox0_cmd_lock_hw must be updated to match. 5052 */ 5053enum hw_lock_client { 5054 /** 5055 * Driver is the client of HW Lock Manager. 5056 */ 5057 HW_LOCK_CLIENT_DRIVER = 0, 5058 /** 5059 * PSR SU is the client of HW Lock Manager. 5060 */ 5061 HW_LOCK_CLIENT_PSR_SU = 1, 5062 HW_LOCK_CLIENT_SUBVP = 3, 5063 /** 5064 * Replay is the client of HW Lock Manager. 5065 */ 5066 HW_LOCK_CLIENT_REPLAY = 4, 5067 HW_LOCK_CLIENT_FAMS2 = 5, 5068 HW_LOCK_CLIENT_CURSOR_OFFLOAD = 6, 5069 /** 5070 * Invalid client. 5071 */ 5072 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 5073}; 5074 5075/** 5076 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 5077 */ 5078struct dmub_cmd_lock_hw_data { 5079 /** 5080 * Specifies the client accessing HW Lock Manager. 5081 */ 5082 enum hw_lock_client client; 5083 /** 5084 * HW instances to be locked. 5085 */ 5086 struct dmub_hw_lock_inst_flags inst_flags; 5087 /** 5088 * Which components to be locked. 5089 */ 5090 union dmub_hw_lock_flags hw_locks; 5091 /** 5092 * Specifies lock/unlock. 5093 */ 5094 uint8_t lock; 5095 /** 5096 * HW can be unlocked separately from releasing the HW Lock Mgr. 5097 * This flag is set if the client wishes to release the object. 5098 */ 5099 uint8_t should_release; 5100 /** 5101 * Explicit padding to 4 byte boundary. 5102 */ 5103 uint8_t pad; 5104}; 5105 5106/** 5107 * Definition of a DMUB_CMD__HW_LOCK command. 5108 * Command is used by driver and FW. 5109 */ 5110struct dmub_rb_cmd_lock_hw { 5111 /** 5112 * Command header. 5113 */ 5114 struct dmub_cmd_header header; 5115 /** 5116 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 5117 */ 5118 struct dmub_cmd_lock_hw_data lock_hw_data; 5119}; 5120 5121/** 5122 * ABM command sub-types. 5123 */ 5124enum dmub_cmd_abm_type { 5125 /** 5126 * Initialize parameters for ABM algorithm. 5127 * Data is passed through an indirect buffer. 5128 */ 5129 DMUB_CMD__ABM_INIT_CONFIG = 0, 5130 /** 5131 * Set OTG and panel HW instance. 5132 */ 5133 DMUB_CMD__ABM_SET_PIPE = 1, 5134 /** 5135 * Set user requested backklight level. 5136 */ 5137 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 5138 /** 5139 * Set ABM operating/aggression level. 5140 */ 5141 DMUB_CMD__ABM_SET_LEVEL = 3, 5142 /** 5143 * Set ambient light level. 5144 */ 5145 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 5146 /** 5147 * Enable/disable fractional duty cycle for backlight PWM. 5148 */ 5149 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 5150 5151 /** 5152 * unregister vertical interrupt after steady state is reached 5153 */ 5154 DMUB_CMD__ABM_PAUSE = 6, 5155 5156 /** 5157 * Save and Restore ABM state. On save we save parameters, and 5158 * on restore we update state with passed in data. 5159 */ 5160 DMUB_CMD__ABM_SAVE_RESTORE = 7, 5161 5162 /** 5163 * Query ABM caps. 5164 */ 5165 DMUB_CMD__ABM_QUERY_CAPS = 8, 5166 5167 /** 5168 * Set ABM Events 5169 */ 5170 DMUB_CMD__ABM_SET_EVENT = 9, 5171 5172 /** 5173 * Get the current ACE curve. 5174 */ 5175 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 5176 5177 /** 5178 * Get current histogram data 5179 */ 5180 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 5181}; 5182 5183/** 5184 * LSDMA command sub-types. 5185 */ 5186enum dmub_cmd_lsdma_type { 5187 /** 5188 * Initialize parameters for LSDMA. 5189 * Ring buffer is mapped to the ring buffer 5190 */ 5191 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 5192 /** 5193 * LSDMA copies data from source to destination linearly 5194 */ 5195 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 5196 /** 5197 * LSDMA copies data from source to destination linearly in sub window 5198 */ 5199 DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2, 5200 /** 5201 * Send the tiled-to-tiled copy command 5202 */ 5203 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3, 5204 /** 5205 * Send the poll reg write command 5206 */ 5207 DMUB_CMD__LSDMA_POLL_REG_WRITE = 4, 5208 /** 5209 * Send the pio copy command 5210 */ 5211 DMUB_CMD__LSDMA_PIO_COPY = 5, 5212 /** 5213 * Send the pio constfill command 5214 */ 5215 DMUB_CMD__LSDMA_PIO_CONSTFILL = 6, 5216}; 5217 5218struct abm_ace_curve { 5219 /** 5220 * @offsets: ACE curve offsets. 5221 */ 5222 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5223 5224 /** 5225 * @thresholds: ACE curve thresholds. 5226 */ 5227 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5228 5229 /** 5230 * @slopes: ACE curve slopes. 5231 */ 5232 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5233}; 5234 5235struct fixed_pt_format { 5236 /** 5237 * @sign_bit: Indicates whether one bit is reserved for the sign. 5238 */ 5239 bool sign_bit; 5240 5241 /** 5242 * @num_int_bits: Number of bits used for integer part. 5243 */ 5244 uint8_t num_int_bits; 5245 5246 /** 5247 * @num_frac_bits: Number of bits used for fractional part. 5248 */ 5249 uint8_t num_frac_bits; 5250 5251 /** 5252 * @pad: Explicit padding to 4 byte boundary. 5253 */ 5254 uint8_t pad; 5255}; 5256 5257struct abm_caps { 5258 /** 5259 * @num_hg_bins: Number of histogram bins. 5260 */ 5261 uint8_t num_hg_bins; 5262 5263 /** 5264 * @num_ace_segments: Number of ACE curve segments. 5265 */ 5266 uint8_t num_ace_segments; 5267 5268 /** 5269 * @pad: Explicit padding to 4 byte boundary. 5270 */ 5271 uint8_t pad[2]; 5272 5273 /** 5274 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 5275 */ 5276 struct fixed_pt_format ace_thresholds_format; 5277 5278 /** 5279 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 5280 */ 5281 struct fixed_pt_format ace_offsets_format; 5282 5283 /** 5284 * @ace_slopes_format: Format of the ACE slopes. 5285 */ 5286 struct fixed_pt_format ace_slopes_format; 5287}; 5288 5289/** 5290 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 5291 * Requirements: 5292 * - Padded explicitly to 32-bit boundary. 5293 * - Must ensure this structure matches the one on driver-side, 5294 * otherwise it won't be aligned. 5295 */ 5296struct abm_config_table { 5297 /** 5298 * Gamma curve thresholds, used for crgb conversion. 5299 */ 5300 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 5301 /** 5302 * Gamma curve offsets, used for crgb conversion. 5303 */ 5304 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 5305 /** 5306 * Gamma curve slopes, used for crgb conversion. 5307 */ 5308 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 5309 /** 5310 * Custom backlight curve thresholds. 5311 */ 5312 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 5313 /** 5314 * Custom backlight curve offsets. 5315 */ 5316 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 5317 /** 5318 * Ambient light thresholds. 5319 */ 5320 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 5321 /** 5322 * Minimum programmable backlight. 5323 */ 5324 uint16_t min_abm_backlight; // 122B 5325 /** 5326 * Minimum reduction values. 5327 */ 5328 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 5329 /** 5330 * Maximum reduction values. 5331 */ 5332 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 5333 /** 5334 * Bright positive gain. 5335 */ 5336 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 5337 /** 5338 * Dark negative gain. 5339 */ 5340 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 5341 /** 5342 * Hybrid factor. 5343 */ 5344 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 5345 /** 5346 * Contrast factor. 5347 */ 5348 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 5349 /** 5350 * Deviation gain. 5351 */ 5352 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 5353 /** 5354 * Minimum knee. 5355 */ 5356 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 5357 /** 5358 * Maximum knee. 5359 */ 5360 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 5361 /** 5362 * Unused. 5363 */ 5364 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 5365 /** 5366 * Explicit padding to 4 byte boundary. 5367 */ 5368 uint8_t pad3[3]; // 229B 5369 /** 5370 * Backlight ramp reduction. 5371 */ 5372 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 5373 /** 5374 * Backlight ramp start. 5375 */ 5376 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 5377}; 5378 5379/** 5380 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5381 */ 5382struct dmub_cmd_abm_set_pipe_data { 5383 /** 5384 * OTG HW instance. 5385 */ 5386 uint8_t otg_inst; 5387 5388 /** 5389 * Panel Control HW instance. 5390 */ 5391 uint8_t panel_inst; 5392 5393 /** 5394 * Controls how ABM will interpret a set pipe or set level command. 5395 */ 5396 uint8_t set_pipe_option; 5397 5398 /** 5399 * Unused. 5400 * TODO: Remove. 5401 */ 5402 uint8_t ramping_boundary; 5403 5404 /** 5405 * PwrSeq HW Instance. 5406 */ 5407 uint8_t pwrseq_inst; 5408 5409 /** 5410 * Explicit padding to 4 byte boundary. 5411 */ 5412 uint8_t pad[3]; 5413}; 5414 5415/** 5416 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5417 */ 5418struct dmub_rb_cmd_abm_set_pipe { 5419 /** 5420 * Command header. 5421 */ 5422 struct dmub_cmd_header header; 5423 5424 /** 5425 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5426 */ 5427 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 5428}; 5429 5430/** 5431 * Type of backlight control method to be used by ABM module 5432 */ 5433enum dmub_backlight_control_type { 5434 /** 5435 * PWM Backlight control 5436 */ 5437 DMU_BACKLIGHT_CONTROL_PWM = 0, 5438 /** 5439 * VESA Aux-based backlight control 5440 */ 5441 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 5442 /** 5443 * AMD DPCD Aux-based backlight control 5444 */ 5445 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 5446}; 5447 5448/** 5449 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5450 */ 5451struct dmub_cmd_abm_set_backlight_data { 5452 /** 5453 * Number of frames to ramp to backlight user level. 5454 */ 5455 uint32_t frame_ramp; 5456 5457 /** 5458 * Requested backlight level from user. 5459 */ 5460 uint32_t backlight_user_level; 5461 5462 /** 5463 * ABM control version. 5464 */ 5465 uint8_t version; 5466 5467 /** 5468 * Panel Control HW instance mask. 5469 * Bit 0 is Panel Control HW instance 0. 5470 * Bit 1 is Panel Control HW instance 1. 5471 */ 5472 uint8_t panel_mask; 5473 5474 /** 5475 * AUX HW Instance. 5476 */ 5477 uint8_t aux_inst; 5478 5479 /** 5480 * Explicit padding to 4 byte boundary. 5481 */ 5482 uint8_t pad[1]; 5483 5484 /** 5485 * Backlight control type. 5486 * Value 0 is PWM backlight control. 5487 * Value 1 is VAUX backlight control. 5488 * Value 2 is AMD DPCD AUX backlight control. 5489 */ 5490 enum dmub_backlight_control_type backlight_control_type; 5491 5492 /** 5493 * Minimum luminance in nits. 5494 */ 5495 uint32_t min_luminance; 5496 5497 /** 5498 * Maximum luminance in nits. 5499 */ 5500 uint32_t max_luminance; 5501 5502 /** 5503 * Minimum backlight in pwm. 5504 */ 5505 uint32_t min_backlight_pwm; 5506 5507 /** 5508 * Maximum backlight in pwm. 5509 */ 5510 uint32_t max_backlight_pwm; 5511}; 5512 5513/** 5514 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5515 */ 5516struct dmub_rb_cmd_abm_set_backlight { 5517 /** 5518 * Command header. 5519 */ 5520 struct dmub_cmd_header header; 5521 5522 /** 5523 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5524 */ 5525 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 5526}; 5527 5528/** 5529 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5530 */ 5531struct dmub_cmd_abm_set_level_data { 5532 /** 5533 * Set current ABM operating/aggression level. 5534 */ 5535 uint32_t level; 5536 5537 /** 5538 * ABM control version. 5539 */ 5540 uint8_t version; 5541 5542 /** 5543 * Panel Control HW instance mask. 5544 * Bit 0 is Panel Control HW instance 0. 5545 * Bit 1 is Panel Control HW instance 1. 5546 */ 5547 uint8_t panel_mask; 5548 5549 /** 5550 * Explicit padding to 4 byte boundary. 5551 */ 5552 uint8_t pad[2]; 5553}; 5554 5555/** 5556 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5557 */ 5558struct dmub_rb_cmd_abm_set_level { 5559 /** 5560 * Command header. 5561 */ 5562 struct dmub_cmd_header header; 5563 5564 /** 5565 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5566 */ 5567 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5568}; 5569 5570/** 5571 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5572 */ 5573struct dmub_cmd_abm_set_ambient_level_data { 5574 /** 5575 * Ambient light sensor reading from OS. 5576 */ 5577 uint32_t ambient_lux; 5578 5579 /** 5580 * ABM control version. 5581 */ 5582 uint8_t version; 5583 5584 /** 5585 * Panel Control HW instance mask. 5586 * Bit 0 is Panel Control HW instance 0. 5587 * Bit 1 is Panel Control HW instance 1. 5588 */ 5589 uint8_t panel_mask; 5590 5591 /** 5592 * Explicit padding to 4 byte boundary. 5593 */ 5594 uint8_t pad[2]; 5595}; 5596 5597/** 5598 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5599 */ 5600struct dmub_rb_cmd_abm_set_ambient_level { 5601 /** 5602 * Command header. 5603 */ 5604 struct dmub_cmd_header header; 5605 5606 /** 5607 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5608 */ 5609 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5610}; 5611 5612/** 5613 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5614 */ 5615struct dmub_cmd_abm_set_pwm_frac_data { 5616 /** 5617 * Enable/disable fractional duty cycle for backlight PWM. 5618 * TODO: Convert to uint8_t. 5619 */ 5620 uint32_t fractional_pwm; 5621 5622 /** 5623 * ABM control version. 5624 */ 5625 uint8_t version; 5626 5627 /** 5628 * Panel Control HW instance mask. 5629 * Bit 0 is Panel Control HW instance 0. 5630 * Bit 1 is Panel Control HW instance 1. 5631 */ 5632 uint8_t panel_mask; 5633 5634 /** 5635 * Explicit padding to 4 byte boundary. 5636 */ 5637 uint8_t pad[2]; 5638}; 5639 5640/** 5641 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5642 */ 5643struct dmub_rb_cmd_abm_set_pwm_frac { 5644 /** 5645 * Command header. 5646 */ 5647 struct dmub_cmd_header header; 5648 5649 /** 5650 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5651 */ 5652 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5653}; 5654 5655/** 5656 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5657 */ 5658struct dmub_cmd_abm_init_config_data { 5659 /** 5660 * Location of indirect buffer used to pass init data to ABM. 5661 */ 5662 union dmub_addr src; 5663 5664 /** 5665 * Indirect buffer length. 5666 */ 5667 uint16_t bytes; 5668 5669 5670 /** 5671 * ABM control version. 5672 */ 5673 uint8_t version; 5674 5675 /** 5676 * Panel Control HW instance mask. 5677 * Bit 0 is Panel Control HW instance 0. 5678 * Bit 1 is Panel Control HW instance 1. 5679 */ 5680 uint8_t panel_mask; 5681 5682 /** 5683 * Explicit padding to 4 byte boundary. 5684 */ 5685 uint8_t pad[2]; 5686}; 5687 5688/** 5689 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5690 */ 5691struct dmub_rb_cmd_abm_init_config { 5692 /** 5693 * Command header. 5694 */ 5695 struct dmub_cmd_header header; 5696 5697 /** 5698 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5699 */ 5700 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5701}; 5702 5703/** 5704 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5705 */ 5706 5707struct dmub_cmd_abm_pause_data { 5708 5709 /** 5710 * Panel Control HW instance mask. 5711 * Bit 0 is Panel Control HW instance 0. 5712 * Bit 1 is Panel Control HW instance 1. 5713 */ 5714 uint8_t panel_mask; 5715 5716 /** 5717 * OTG hw instance 5718 */ 5719 uint8_t otg_inst; 5720 5721 /** 5722 * Enable or disable ABM pause 5723 */ 5724 uint8_t enable; 5725 5726 /** 5727 * Explicit padding to 4 byte boundary. 5728 */ 5729 uint8_t pad[1]; 5730}; 5731 5732/** 5733 * Definition of a DMUB_CMD__ABM_PAUSE command. 5734 */ 5735struct dmub_rb_cmd_abm_pause { 5736 /** 5737 * Command header. 5738 */ 5739 struct dmub_cmd_header header; 5740 5741 /** 5742 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5743 */ 5744 struct dmub_cmd_abm_pause_data abm_pause_data; 5745}; 5746 5747/** 5748 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5749 */ 5750struct dmub_cmd_abm_query_caps_in { 5751 /** 5752 * Panel instance. 5753 */ 5754 uint8_t panel_inst; 5755 5756 /** 5757 * Explicit padding to 4 byte boundary. 5758 */ 5759 uint8_t pad[3]; 5760}; 5761 5762/** 5763 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5764 */ 5765struct dmub_cmd_abm_query_caps_out { 5766 /** 5767 * SW Algorithm caps. 5768 */ 5769 struct abm_caps sw_caps; 5770 5771 /** 5772 * ABM HW caps. 5773 */ 5774 struct abm_caps hw_caps; 5775}; 5776 5777/** 5778 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5779 */ 5780struct dmub_rb_cmd_abm_query_caps { 5781 /** 5782 * Command header. 5783 */ 5784 struct dmub_cmd_header header; 5785 5786 /** 5787 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5788 */ 5789 union { 5790 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5791 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5792 } data; 5793}; 5794 5795/** 5796 * enum dmub_abm_ace_curve_type - ACE curve type. 5797 */ 5798enum dmub_abm_ace_curve_type { 5799 /** 5800 * ACE curve as defined by the SW layer. 5801 */ 5802 ABM_ACE_CURVE_TYPE__SW = 0, 5803 /** 5804 * ACE curve as defined by the SW to HW translation interface layer. 5805 */ 5806 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5807}; 5808 5809/** 5810 * enum dmub_abm_histogram_type - Histogram type. 5811 */ 5812enum dmub_abm_histogram_type { 5813 /** 5814 * ACE curve as defined by the SW layer. 5815 */ 5816 ABM_HISTOGRAM_TYPE__SW = 0, 5817 /** 5818 * ACE curve as defined by the SW to HW translation interface layer. 5819 */ 5820 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5821}; 5822 5823/** 5824 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5825 */ 5826struct dmub_rb_cmd_abm_get_ace_curve { 5827 /** 5828 * Command header. 5829 */ 5830 struct dmub_cmd_header header; 5831 5832 /** 5833 * Address where ACE curve should be copied. 5834 */ 5835 union dmub_addr dest; 5836 5837 /** 5838 * Type of ACE curve being queried. 5839 */ 5840 enum dmub_abm_ace_curve_type ace_type; 5841 5842 /** 5843 * Indirect buffer length. 5844 */ 5845 uint16_t bytes; 5846 5847 /** 5848 * eDP panel instance. 5849 */ 5850 uint8_t panel_inst; 5851 5852 /** 5853 * Explicit padding to 4 byte boundary. 5854 */ 5855 uint8_t pad; 5856}; 5857 5858/** 5859 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5860 */ 5861struct dmub_rb_cmd_abm_get_histogram { 5862 /** 5863 * Command header. 5864 */ 5865 struct dmub_cmd_header header; 5866 5867 /** 5868 * Address where Histogram should be copied. 5869 */ 5870 union dmub_addr dest; 5871 5872 /** 5873 * Type of Histogram being queried. 5874 */ 5875 enum dmub_abm_histogram_type histogram_type; 5876 5877 /** 5878 * Indirect buffer length. 5879 */ 5880 uint16_t bytes; 5881 5882 /** 5883 * eDP panel instance. 5884 */ 5885 uint8_t panel_inst; 5886 5887 /** 5888 * Explicit padding to 4 byte boundary. 5889 */ 5890 uint8_t pad; 5891}; 5892 5893/** 5894 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5895 */ 5896struct dmub_rb_cmd_abm_save_restore { 5897 /** 5898 * Command header. 5899 */ 5900 struct dmub_cmd_header header; 5901 5902 /** 5903 * OTG hw instance 5904 */ 5905 uint8_t otg_inst; 5906 5907 /** 5908 * Enable or disable ABM pause 5909 */ 5910 uint8_t freeze; 5911 5912 /** 5913 * Explicit padding to 4 byte boundary. 5914 */ 5915 uint8_t debug; 5916 5917 /** 5918 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5919 */ 5920 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5921}; 5922 5923/** 5924 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5925 */ 5926 5927struct dmub_cmd_abm_set_event_data { 5928 5929 /** 5930 * VB Scaling Init. Strength Mapping 5931 * Byte 0: 0~255 for VB level 0 5932 * Byte 1: 0~255 for VB level 1 5933 * Byte 2: 0~255 for VB level 2 5934 * Byte 3: 0~255 for VB level 3 5935 */ 5936 uint32_t vb_scaling_strength_mapping; 5937 /** 5938 * VariBright Scaling Enable 5939 */ 5940 uint8_t vb_scaling_enable; 5941 /** 5942 * Panel Control HW instance mask. 5943 * Bit 0 is Panel Control HW instance 0. 5944 * Bit 1 is Panel Control HW instance 1. 5945 */ 5946 uint8_t panel_mask; 5947 5948 /** 5949 * Explicit padding to 4 byte boundary. 5950 */ 5951 uint8_t pad[2]; 5952}; 5953 5954/** 5955 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5956 */ 5957struct dmub_rb_cmd_abm_set_event { 5958 /** 5959 * Command header. 5960 */ 5961 struct dmub_cmd_header header; 5962 5963 /** 5964 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5965 */ 5966 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5967}; 5968 5969/** 5970 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5971 */ 5972struct dmub_cmd_query_feature_caps_data { 5973 /** 5974 * DMUB feature capabilities. 5975 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5976 */ 5977 struct dmub_feature_caps feature_caps; 5978}; 5979 5980/** 5981 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5982 */ 5983struct dmub_rb_cmd_query_feature_caps { 5984 /** 5985 * Command header. 5986 */ 5987 struct dmub_cmd_header header; 5988 /** 5989 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5990 */ 5991 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5992}; 5993 5994/** 5995 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5996 */ 5997struct dmub_cmd_visual_confirm_color_data { 5998 /** 5999 * DMUB visual confirm color 6000 */ 6001 struct dmub_visual_confirm_color visual_confirm_color; 6002}; 6003 6004/** 6005 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6006 */ 6007struct dmub_rb_cmd_get_visual_confirm_color { 6008 /** 6009 * Command header. 6010 */ 6011 struct dmub_cmd_header header; 6012 /** 6013 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6014 */ 6015 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 6016}; 6017 6018/** 6019 * enum dmub_cmd_panel_cntl_type - Panel control command. 6020 */ 6021enum dmub_cmd_panel_cntl_type { 6022 /** 6023 * Initializes embedded panel hardware blocks. 6024 */ 6025 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 6026 /** 6027 * Queries backlight info for the embedded panel. 6028 */ 6029 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 6030 /** 6031 * Sets the PWM Freq as per user's requirement. 6032 */ 6033 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 6034}; 6035 6036/** 6037 * struct dmub_cmd_panel_cntl_data - Panel control data. 6038 */ 6039struct dmub_cmd_panel_cntl_data { 6040 uint32_t pwrseq_inst; /**< pwrseq instance */ 6041 uint32_t current_backlight; /* in/out */ 6042 uint32_t bl_pwm_cntl; /* in/out */ 6043 uint32_t bl_pwm_period_cntl; /* in/out */ 6044 uint32_t bl_pwm_ref_div1; /* in/out */ 6045 uint8_t is_backlight_on : 1; /* in/out */ 6046 uint8_t is_powered_on : 1; /* in/out */ 6047 uint8_t padding[3]; 6048 uint32_t bl_pwm_ref_div2; /* in/out */ 6049 uint8_t reserved[4]; 6050}; 6051 6052/** 6053 * struct dmub_rb_cmd_panel_cntl - Panel control command. 6054 */ 6055struct dmub_rb_cmd_panel_cntl { 6056 struct dmub_cmd_header header; /**< header */ 6057 struct dmub_cmd_panel_cntl_data data; /**< payload */ 6058}; 6059 6060struct dmub_optc_state { 6061 uint32_t v_total_max; 6062 uint32_t v_total_min; 6063 uint32_t tg_inst; 6064}; 6065 6066struct dmub_rb_cmd_drr_update { 6067 struct dmub_cmd_header header; 6068 struct dmub_optc_state dmub_optc_state_req; 6069}; 6070 6071struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 6072 uint32_t pix_clk_100hz; 6073 uint8_t max_ramp_step; 6074 uint8_t pipes; 6075 uint8_t min_refresh_in_hz; 6076 uint8_t pipe_count; 6077 uint8_t pipe_index[4]; 6078}; 6079 6080struct dmub_cmd_fw_assisted_mclk_switch_config { 6081 uint8_t fams_enabled; 6082 uint8_t visual_confirm_enabled; 6083 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 6084 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 6085}; 6086 6087struct dmub_rb_cmd_fw_assisted_mclk_switch { 6088 struct dmub_cmd_header header; 6089 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 6090}; 6091 6092/** 6093 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6094 */ 6095struct dmub_cmd_lvtma_control_data { 6096 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 6097 uint8_t bypass_panel_control_wait; 6098 uint8_t reserved_0[2]; /**< For future use */ 6099 uint8_t pwrseq_inst; /**< LVTMA control instance */ 6100 uint8_t reserved_1[3]; /**< For future use */ 6101}; 6102 6103/** 6104 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6105 */ 6106struct dmub_rb_cmd_lvtma_control { 6107 /** 6108 * Command header. 6109 */ 6110 struct dmub_cmd_header header; 6111 /** 6112 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6113 */ 6114 struct dmub_cmd_lvtma_control_data data; 6115}; 6116 6117/** 6118 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6119 */ 6120struct dmub_rb_cmd_transmitter_query_dp_alt_data { 6121 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 6122 uint8_t is_usb; /**< is phy is usb */ 6123 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 6124 uint8_t is_dp4; /**< is dp in 4 lane */ 6125}; 6126 6127/** 6128 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6129 */ 6130struct dmub_rb_cmd_transmitter_query_dp_alt { 6131 struct dmub_cmd_header header; /**< header */ 6132 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 6133}; 6134 6135struct phy_test_mode { 6136 uint8_t mode; 6137 uint8_t pat0; 6138 uint8_t pad[2]; 6139}; 6140 6141/** 6142 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6143 */ 6144struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 6145 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 6146 uint8_t mode; /**< HDMI/DP/DP2 etc */ 6147 uint8_t lane_num; /**< Number of lanes */ 6148 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 6149 struct phy_test_mode test_mode; 6150 enum dmub_phy_fsm_state state; 6151 uint32_t status; 6152 uint8_t pad; 6153}; 6154 6155/** 6156 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6157 */ 6158struct dmub_rb_cmd_transmitter_set_phy_fsm { 6159 struct dmub_cmd_header header; /**< header */ 6160 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 6161}; 6162 6163/** 6164 * Maximum number of bytes a chunk sent to DMUB for parsing 6165 */ 6166#define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 6167 6168/** 6169 * Represent a chunk of CEA blocks sent to DMUB for parsing 6170 */ 6171struct dmub_cmd_send_edid_cea { 6172 uint16_t offset; /**< offset into the CEA block */ 6173 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 6174 uint16_t cea_total_length; /**< total length of the CEA block */ 6175 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 6176 uint8_t pad[3]; /**< padding and for future expansion */ 6177}; 6178 6179/** 6180 * Result of VSDB parsing from CEA block 6181 */ 6182struct dmub_cmd_edid_cea_amd_vsdb { 6183 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 6184 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 6185 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 6186 uint16_t min_frame_rate; /**< Maximum frame rate */ 6187 uint16_t max_frame_rate; /**< Minimum frame rate */ 6188}; 6189 6190/** 6191 * Result of sending a CEA chunk 6192 */ 6193struct dmub_cmd_edid_cea_ack { 6194 uint16_t offset; /**< offset of the chunk into the CEA block */ 6195 uint8_t success; /**< 1 if this sending of chunk succeeded */ 6196 uint8_t pad; /**< padding and for future expansion */ 6197}; 6198 6199/** 6200 * Specify whether the result is an ACK/NACK or the parsing has finished 6201 */ 6202enum dmub_cmd_edid_cea_reply_type { 6203 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 6204 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 6205}; 6206 6207/** 6208 * Definition of a DMUB_CMD__EDID_CEA command. 6209 */ 6210struct dmub_rb_cmd_edid_cea { 6211 struct dmub_cmd_header header; /**< Command header */ 6212 union dmub_cmd_edid_cea_data { 6213 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 6214 struct dmub_cmd_edid_cea_output { /**< output with results */ 6215 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 6216 union { 6217 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 6218 struct dmub_cmd_edid_cea_ack ack; 6219 }; 6220 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 6221 } data; /**< Command data */ 6222 6223}; 6224 6225/** 6226 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 6227 */ 6228struct dmub_cmd_cable_id_input { 6229 uint8_t phy_inst; /**< phy inst for cable id data */ 6230}; 6231 6232/** 6233 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 6234 */ 6235struct dmub_cmd_cable_id_output { 6236 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 6237 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 6238 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 6239 uint8_t RESERVED :2; /**< reserved means not defined */ 6240}; 6241 6242/** 6243 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 6244 */ 6245struct dmub_rb_cmd_get_usbc_cable_id { 6246 struct dmub_cmd_header header; /**< Command header */ 6247 /** 6248 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 6249 */ 6250 union dmub_cmd_cable_id_data { 6251 struct dmub_cmd_cable_id_input input; /**< Input */ 6252 struct dmub_cmd_cable_id_output output; /**< Output */ 6253 uint8_t output_raw; /**< Raw data output */ 6254 } data; 6255}; 6256 6257enum dmub_cmd_fused_io_sub_type { 6258 DMUB_CMD__FUSED_IO_EXECUTE = 0, 6259 DMUB_CMD__FUSED_IO_ABORT = 1, 6260}; 6261 6262enum dmub_cmd_fused_request_type { 6263 FUSED_REQUEST_READ, 6264 FUSED_REQUEST_WRITE, 6265 FUSED_REQUEST_POLL, 6266}; 6267 6268enum dmub_cmd_fused_request_status { 6269 FUSED_REQUEST_STATUS_SUCCESS, 6270 FUSED_REQUEST_STATUS_BEGIN, 6271 FUSED_REQUEST_STATUS_SUBMIT, 6272 FUSED_REQUEST_STATUS_REPLY, 6273 FUSED_REQUEST_STATUS_POLL, 6274 FUSED_REQUEST_STATUS_ABORTED, 6275 FUSED_REQUEST_STATUS_FAILED = 0x80, 6276 FUSED_REQUEST_STATUS_INVALID, 6277 FUSED_REQUEST_STATUS_BUSY, 6278 FUSED_REQUEST_STATUS_TIMEOUT, 6279 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 6280}; 6281 6282struct dmub_cmd_fused_request { 6283 uint8_t status; 6284 uint8_t type : 2; 6285 uint8_t _reserved0 : 3; 6286 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 6287 uint8_t identifier; 6288 uint8_t _reserved1; 6289 uint32_t timeout_us; 6290 union dmub_cmd_fused_request_location { 6291 struct dmub_cmd_fused_request_location_i2c { 6292 uint8_t is_aux : 1; // False 6293 uint8_t ddc_line : 3; 6294 uint8_t over_aux : 1; 6295 uint8_t _reserved0 : 3; 6296 uint8_t address; 6297 uint8_t offset; 6298 uint8_t length; 6299 } i2c; 6300 struct dmub_cmd_fused_request_location_aux { 6301 uint32_t is_aux : 1; // True 6302 uint32_t ddc_line : 3; 6303 uint32_t address : 20; 6304 uint32_t length : 8; // Automatically split into 16B transactions 6305 } aux; 6306 } u; 6307 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 6308}; 6309 6310struct dmub_rb_cmd_fused_io { 6311 struct dmub_cmd_header header; 6312 struct dmub_cmd_fused_request request; 6313}; 6314 6315/** 6316 * Command type of a DMUB_CMD__SECURE_DISPLAY command 6317 */ 6318enum dmub_cmd_secure_display_type { 6319 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 6320 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 6321 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 6322 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 6323 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 6324}; 6325 6326#define MAX_ROI_NUM 2 6327 6328struct dmub_cmd_roi_info { 6329 uint16_t x_start; 6330 uint16_t x_end; 6331 uint16_t y_start; 6332 uint16_t y_end; 6333 uint8_t otg_id; 6334 uint8_t phy_id; 6335}; 6336 6337struct dmub_cmd_roi_window_ctl { 6338 uint16_t x_start; 6339 uint16_t x_end; 6340 uint16_t y_start; 6341 uint16_t y_end; 6342 bool enable; 6343}; 6344 6345struct dmub_cmd_roi_ctl_info { 6346 uint8_t otg_id; 6347 uint8_t phy_id; 6348 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 6349}; 6350 6351/** 6352 * Definition of a DMUB_CMD__SECURE_DISPLAY command 6353 */ 6354struct dmub_rb_cmd_secure_display { 6355 struct dmub_cmd_header header; 6356 /** 6357 * Data passed from driver to dmub firmware. 6358 */ 6359 struct dmub_cmd_roi_info roi_info; 6360 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 6361}; 6362 6363/** 6364 * Command type of a DMUB_CMD__PSP command 6365 */ 6366enum dmub_cmd_psp_type { 6367 DMUB_CMD__PSP_ASSR_ENABLE = 0 6368}; 6369 6370/** 6371 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 6372 */ 6373struct dmub_cmd_assr_enable_data { 6374 /** 6375 * ASSR enable or disable. 6376 */ 6377 uint8_t enable; 6378 /** 6379 * PHY port type. 6380 * Indicates eDP / non-eDP port type 6381 */ 6382 uint8_t phy_port_type; 6383 /** 6384 * PHY port ID. 6385 */ 6386 uint8_t phy_port_id; 6387 /** 6388 * Link encoder index. 6389 */ 6390 uint8_t link_enc_index; 6391 /** 6392 * HPO mode. 6393 */ 6394 uint8_t hpo_mode; 6395 6396 /** 6397 * Reserved field. 6398 */ 6399 uint8_t reserved[7]; 6400}; 6401 6402/** 6403 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6404 */ 6405struct dmub_rb_cmd_assr_enable { 6406 /** 6407 * Command header. 6408 */ 6409 struct dmub_cmd_header header; 6410 6411 /** 6412 * Assr data. 6413 */ 6414 struct dmub_cmd_assr_enable_data assr_data; 6415 6416 /** 6417 * Reserved field. 6418 */ 6419 uint32_t reserved[3]; 6420}; 6421 6422/** 6423 * Current definition of "ips_mode" from driver 6424 */ 6425enum ips_residency_mode { 6426 IPS_RESIDENCY__IPS1_MAX, 6427 IPS_RESIDENCY__IPS2, 6428 IPS_RESIDENCY__IPS1_RCG, 6429 IPS_RESIDENCY__IPS1_ONO2_ON, 6430 IPS_RESIDENCY__IPS1_Z8_RETENTION, 6431 IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS, 6432 IPS_RESIDENCY__PG_ONO_CURRENT_STATE 6433}; 6434 6435#define NUM_IPS_HISTOGRAM_BUCKETS 16 6436 6437/** 6438 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats 6439 */ 6440struct dmub_ips_residency_info { 6441 uint32_t residency_millipercent; 6442 uint32_t entry_counter; 6443 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; 6444 uint64_t total_time_us; 6445 uint64_t total_inactive_time_us; 6446 uint32_t ono_pg_state_at_collection; 6447 uint32_t ono_pg_state_last_seen_in_ips; 6448}; 6449 6450/** 6451 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command. 6452 */ 6453struct dmub_cmd_ips_residency_cntl_data { 6454 uint8_t panel_inst; 6455 uint8_t start_measurement; 6456 uint8_t padding[2]; // align to 4-byte boundary 6457}; 6458 6459struct dmub_rb_cmd_ips_residency_cntl { 6460 struct dmub_cmd_header header; 6461 struct dmub_cmd_ips_residency_cntl_data cntl_data; 6462}; 6463 6464/** 6465 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command. 6466 */ 6467struct dmub_cmd_ips_query_residency_info_data { 6468 union dmub_addr dest; 6469 uint32_t size; 6470 uint32_t ips_mode; 6471 uint8_t panel_inst; 6472 uint8_t padding[3]; // align to 4-byte boundary 6473}; 6474 6475struct dmub_rb_cmd_ips_query_residency_info { 6476 struct dmub_cmd_header header; 6477 struct dmub_cmd_ips_query_residency_info_data info_data; 6478}; 6479 6480/** 6481 * struct dmub_cmd_cursor_offload_init_data - Payload for cursor offload init command. 6482 */ 6483struct dmub_cmd_cursor_offload_init_data { 6484 union dmub_addr state_addr; /**< State address for dmub_cursor_offload */ 6485 uint32_t state_size; /**< State size for dmub_cursor_offload */ 6486}; 6487 6488/** 6489 * struct dmub_rb_cmd_cursor_offload_init - Data for initializing cursor offload. 6490 */ 6491struct dmub_rb_cmd_cursor_offload_init { 6492 struct dmub_cmd_header header; 6493 struct dmub_cmd_cursor_offload_init_data init_data; 6494}; 6495 6496/** 6497 * struct dmub_cmd_cursor_offload_stream_data - Payload for cursor offload stream command. 6498 */ 6499struct dmub_cmd_cursor_offload_stream_data { 6500 uint32_t otg_inst: 4; /**< OTG instance to control */ 6501 uint32_t reserved: 28; /**< Reserved for future use */ 6502 uint32_t line_time_in_ns; /**< Line time in ns for the OTG */ 6503 uint32_t v_total_max; /**< OTG v_total_max */ 6504}; 6505 6506/** 6507 * struct dmub_rb_cmd_cursor_offload_stream_cntl - Controls a stream for cursor offload. 6508 */ 6509struct dmub_rb_cmd_cursor_offload_stream_cntl { 6510 struct dmub_cmd_header header; 6511 struct dmub_cmd_cursor_offload_stream_data data; 6512}; 6513 6514/** 6515 * Data passed from driver to FW in a DMUB_CMD__PR_ENABLE command. 6516 */ 6517struct dmub_cmd_pr_enable_data { 6518 /** 6519 * Panel Replay enable or disable. 6520 */ 6521 uint8_t enable; 6522 /** 6523 * Panel Instance. 6524 * Panel isntance to identify which replay_state to use 6525 * Currently the support is only for 0 or 1 6526 */ 6527 uint8_t panel_inst; 6528 /** 6529 * Phy state to enter. 6530 * Values to use are defined in dmub_phy_fsm_state 6531 */ 6532 uint8_t phy_fsm_state; 6533 /** 6534 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 6535 * Set this using enum phy_link_rate. 6536 * This does not support HDMI/DP2 for now. 6537 */ 6538 uint8_t phy_rate; 6539 /** 6540 * @hpo_stream_enc_inst: HPO stream encoder instance 6541 */ 6542 uint8_t hpo_stream_enc_inst; 6543 /** 6544 * @hpo_link_enc_inst: HPO link encoder instance 6545 */ 6546 uint8_t hpo_link_enc_inst; 6547 /** 6548 * @pad: Align structure to 4 byte boundary. 6549 */ 6550 uint8_t pad[2]; 6551}; 6552 6553/** 6554 * Definition of a DMUB_CMD__PR_ENABLE command. 6555 * Panel Replay enable/disable is controlled using action in data. 6556 */ 6557struct dmub_rb_cmd_pr_enable { 6558 /** 6559 * Command header. 6560 */ 6561 struct dmub_cmd_header header; 6562 6563 struct dmub_cmd_pr_enable_data data; 6564}; 6565 6566/** 6567 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. 6568 */ 6569struct dmub_cmd_pr_copy_settings_data { 6570 /** 6571 * Flags that can be set by driver to change some replay behaviour. 6572 */ 6573 union pr_debug_flags debug; 6574 6575 /** 6576 * @flags: Flags used to determine feature functionality. 6577 */ 6578 union pr_hw_flags flags; 6579 6580 /** 6581 * DPP HW instance. 6582 */ 6583 uint8_t dpp_inst; 6584 /** 6585 * OTG HW instance. 6586 */ 6587 uint8_t otg_inst; 6588 /** 6589 * DIG FE HW instance. 6590 */ 6591 uint8_t digfe_inst; 6592 /** 6593 * DIG BE HW instance. 6594 */ 6595 uint8_t digbe_inst; 6596 /** 6597 * AUX HW instance. 6598 */ 6599 uint8_t aux_inst; 6600 /** 6601 * Panel Instance. 6602 * Panel isntance to identify which psr_state to use 6603 * Currently the support is only for 0 or 1 6604 */ 6605 uint8_t panel_inst; 6606 /** 6607 * Length of each horizontal line in ns. 6608 */ 6609 uint32_t line_time_in_ns; 6610 /** 6611 * PHY instance. 6612 */ 6613 uint8_t dpphy_inst; 6614 /** 6615 * Determines if SMU optimzations are enabled/disabled. 6616 */ 6617 uint8_t smu_optimizations_en; 6618 /* 6619 * Use FSM state for Replay power up/down 6620 */ 6621 uint8_t use_phy_fsm; 6622 /* 6623 * Use FSFT afftet pixel clk 6624 */ 6625 uint32_t pix_clk_100hz; 6626 /* 6627 * Use Original pixel clock 6628 */ 6629 uint32_t sink_pix_clk_100hz; 6630 /** 6631 * Use for AUX-less ALPM LFPS wake operation 6632 */ 6633 struct dmub_alpm_auxless_data auxless_alpm_data; 6634 /** 6635 * @hpo_stream_enc_inst: HPO stream encoder instance 6636 */ 6637 uint8_t hpo_stream_enc_inst; 6638 /** 6639 * @hpo_link_enc_inst: HPO link encoder instance 6640 */ 6641 uint8_t hpo_link_enc_inst; 6642 /** 6643 * @pad: Align structure to 4 byte boundary. 6644 */ 6645 uint8_t pad[2]; 6646}; 6647 6648/** 6649 * Definition of a DMUB_CMD__PR_COPY_SETTINGS command. 6650 */ 6651struct dmub_rb_cmd_pr_copy_settings { 6652 /** 6653 * Command header. 6654 */ 6655 struct dmub_cmd_header header; 6656 /** 6657 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. 6658 */ 6659 struct dmub_cmd_pr_copy_settings_data data; 6660}; 6661 6662struct dmub_cmd_pr_update_state_data { 6663 /** 6664 * Panel Instance. 6665 * Panel isntance to identify which psr_state to use 6666 * Currently the support is only for 0 or 1 6667 */ 6668 uint8_t panel_inst; 6669 6670 uint8_t pad[3]; // align to 4-byte boundary 6671 /* 6672 * Update flags to control the update behavior. 6673 */ 6674 uint32_t update_flag; 6675 /** 6676 * state/data to set. 6677 */ 6678 uint32_t coasting_vtotal; 6679 uint32_t sync_mode; 6680}; 6681 6682struct dmub_cmd_pr_general_cmd_data { 6683 /** 6684 * Panel Instance. 6685 * Panel isntance to identify which psr_state to use 6686 * Currently the support is only for 0 or 1 6687 */ 6688 uint8_t panel_inst; 6689 /** 6690 * subtype: PR general cmd sub type 6691 */ 6692 uint8_t subtype; 6693 6694 uint8_t pad[2]; 6695 /** 6696 * config data by different subtypes 6697 */ 6698 union { 6699 uint32_t u32All; 6700 } data; 6701}; 6702 6703/** 6704 * Definition of a DMUB_CMD__PR_UPDATE_STATE command. 6705 */ 6706struct dmub_rb_cmd_pr_update_state { 6707 /** 6708 * Command header. 6709 */ 6710 struct dmub_cmd_header header; 6711 /** 6712 * Data passed from driver to FW in a DMUB_CMD__PR_UPDATE_STATE command. 6713 */ 6714 struct dmub_cmd_pr_update_state_data data; 6715}; 6716 6717/** 6718 * Definition of a DMUB_CMD__PR_GENERAL_CMD command. 6719 */ 6720struct dmub_rb_cmd_pr_general_cmd { 6721 /** 6722 * Command header. 6723 */ 6724 struct dmub_cmd_header header; 6725 /** 6726 * Data passed from driver to FW in a DMUB_CMD__PR_GENERAL_CMD command. 6727 */ 6728 struct dmub_cmd_pr_general_cmd_data data; 6729}; 6730 6731/** 6732 * union dmub_rb_cmd - DMUB inbox command. 6733 */ 6734union dmub_rb_cmd { 6735 /** 6736 * Elements shared with all commands. 6737 */ 6738 struct dmub_rb_cmd_common cmd_common; 6739 /** 6740 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 6741 */ 6742 struct dmub_rb_cmd_read_modify_write read_modify_write; 6743 /** 6744 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 6745 */ 6746 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 6747 /** 6748 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 6749 */ 6750 struct dmub_rb_cmd_burst_write burst_write; 6751 /** 6752 * Definition of a DMUB_CMD__REG_REG_WAIT command. 6753 */ 6754 struct dmub_rb_cmd_reg_wait reg_wait; 6755 /** 6756 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 6757 */ 6758 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 6759 /** 6760 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 6761 */ 6762 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 6763 /** 6764 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 6765 */ 6766 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 6767 /** 6768 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 6769 */ 6770 struct dmub_rb_cmd_dpphy_init dpphy_init; 6771 /** 6772 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 6773 */ 6774 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 6775 /** 6776 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 6777 */ 6778 struct dmub_rb_cmd_domain_control domain_control; 6779 /** 6780 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 6781 */ 6782 struct dmub_rb_cmd_psr_set_version psr_set_version; 6783 /** 6784 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 6785 */ 6786 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 6787 /** 6788 * Definition of a DMUB_CMD__PSR_ENABLE command. 6789 */ 6790 struct dmub_rb_cmd_psr_enable psr_enable; 6791 /** 6792 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 6793 */ 6794 struct dmub_rb_cmd_psr_set_level psr_set_level; 6795 /** 6796 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 6797 */ 6798 struct dmub_rb_cmd_psr_force_static psr_force_static; 6799 /** 6800 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 6801 */ 6802 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 6803 /** 6804 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 6805 */ 6806 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 6807 /** 6808 * Definition of a DMUB_CMD__HW_LOCK command. 6809 * Command is used by driver and FW. 6810 */ 6811 struct dmub_rb_cmd_lock_hw lock_hw; 6812 /** 6813 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 6814 */ 6815 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 6816 /** 6817 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 6818 */ 6819 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 6820 /** 6821 * Definition of a DMUB_CMD__PLAT_54186_WA command. 6822 */ 6823 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 6824 /** 6825 * Definition of a DMUB_CMD__MALL command. 6826 */ 6827 struct dmub_rb_cmd_mall mall; 6828 6829 /** 6830 * Definition of a DMUB_CMD__CAB command. 6831 */ 6832 struct dmub_rb_cmd_cab_for_ss cab; 6833 6834 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 6835 6836 /** 6837 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 6838 */ 6839 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 6840 6841 /** 6842 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 6843 */ 6844 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 6845 6846 /** 6847 * Definition of DMUB_CMD__PANEL_CNTL commands. 6848 */ 6849 struct dmub_rb_cmd_panel_cntl panel_cntl; 6850 6851 /** 6852 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 6853 */ 6854 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 6855 6856 /** 6857 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 6858 */ 6859 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 6860 6861 /** 6862 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 6863 */ 6864 struct dmub_rb_cmd_abm_set_level abm_set_level; 6865 6866 /** 6867 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 6868 */ 6869 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 6870 6871 /** 6872 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 6873 */ 6874 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 6875 6876 /** 6877 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 6878 */ 6879 struct dmub_rb_cmd_abm_init_config abm_init_config; 6880 6881 /** 6882 * Definition of a DMUB_CMD__ABM_PAUSE command. 6883 */ 6884 struct dmub_rb_cmd_abm_pause abm_pause; 6885 6886 /** 6887 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6888 */ 6889 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 6890 6891 /** 6892 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 6893 */ 6894 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 6895 6896 /** 6897 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6898 */ 6899 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 6900 6901 /** 6902 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6903 */ 6904 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 6905 6906 /** 6907 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6908 */ 6909 struct dmub_rb_cmd_abm_set_event abm_set_event; 6910 6911 /** 6912 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 6913 */ 6914 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 6915 6916 /** 6917 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 6918 */ 6919 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6920 6921 /** 6922 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6923 */ 6924 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6925 6926 /** 6927 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6928 */ 6929 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6930 struct dmub_rb_cmd_drr_update drr_update; 6931 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6932 6933 /** 6934 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6935 */ 6936 struct dmub_rb_cmd_lvtma_control lvtma_control; 6937 /** 6938 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6939 */ 6940 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6941 /** 6942 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6943 */ 6944 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6945 /** 6946 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6947 */ 6948 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6949 /** 6950 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6951 */ 6952 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6953 /** 6954 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6955 */ 6956 struct dmub_rb_cmd_set_config_request set_config_request; 6957 /** 6958 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6959 */ 6960 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6961 /** 6962 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6963 */ 6964 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6965 /** 6966 * Definition of a DMUB_CMD__EDID_CEA command. 6967 */ 6968 struct dmub_rb_cmd_edid_cea edid_cea; 6969 /** 6970 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 6971 */ 6972 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 6973 6974 /** 6975 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 6976 */ 6977 struct dmub_rb_cmd_query_hpd_state query_hpd; 6978 /** 6979 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 6980 */ 6981 struct dmub_rb_cmd_secure_display secure_display; 6982 6983 /** 6984 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 6985 */ 6986 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 6987 /** 6988 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 6989 */ 6990 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 6991 /** 6992 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6993 */ 6994 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6995 /** 6996 * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. 6997 */ 6998 struct dmub_rb_cmd_replay_set_version replay_set_version; 6999 /* 7000 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 7001 */ 7002 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 7003 /** 7004 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 7005 */ 7006 struct dmub_rb_cmd_replay_enable replay_enable; 7007 /** 7008 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 7009 */ 7010 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 7011 /** 7012 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 7013 */ 7014 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 7015 /** 7016 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 7017 */ 7018 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 7019 7020 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 7021 /** 7022 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 7023 */ 7024 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 7025 /** 7026 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 7027 */ 7028 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 7029 /** 7030 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 7031 */ 7032 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 7033 /** 7034 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 7035 */ 7036 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 7037 /** 7038 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 7039 */ 7040 struct dmub_rb_cmd_assr_enable assr_enable; 7041 7042 struct dmub_rb_cmd_fams2 fams2_config; 7043 7044 struct dmub_rb_cmd_ib ib_fams2_config; 7045 7046 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 7047 7048 struct dmub_rb_cmd_fams2_flip fams2_flip; 7049 7050 struct dmub_rb_cmd_fused_io fused_io; 7051 7052 /** 7053 * Definition of a DMUB_CMD__LSDMA command. 7054 */ 7055 struct dmub_rb_cmd_lsdma lsdma; 7056 7057 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; 7058 7059 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; 7060 /** 7061 * Definition of a DMUB_CMD__CURSOR_OFFLOAD_INIT command. 7062 */ 7063 struct dmub_rb_cmd_cursor_offload_init cursor_offload_init; 7064 /** 7065 * Definition of a DMUB_CMD__CURSOR_OFFLOAD control commands. 7066 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE 7067 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE 7068 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM 7069 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_UPDATE_DRR 7070 */ 7071 struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl; 7072 /** 7073 * Definition of a DMUB_CMD__SMART_POWER_OLED_ENABLE command. 7074 */ 7075 struct dmub_rb_cmd_smart_power_oled_enable smart_power_oled_enable; 7076 /** 7077 * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. 7078 */ 7079 struct dmub_rb_cmd_smart_power_oled_getmaxcll smart_power_oled_getmaxcll; 7080 /* 7081 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 7082 */ 7083 struct dmub_rb_cmd_pr_copy_settings pr_copy_settings; 7084 /** 7085 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 7086 */ 7087 struct dmub_rb_cmd_pr_enable pr_enable; 7088 7089 struct dmub_rb_cmd_pr_update_state pr_update_state; 7090 7091 struct dmub_rb_cmd_pr_general_cmd pr_general_cmd; 7092}; 7093 7094/** 7095 * union dmub_rb_out_cmd - Outbox command 7096 */ 7097union dmub_rb_out_cmd { 7098 /** 7099 * Parameters common to every command. 7100 */ 7101 struct dmub_rb_cmd_common cmd_common; 7102 /** 7103 * AUX reply command. 7104 */ 7105 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 7106 /** 7107 * HPD notify command. 7108 */ 7109 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 7110 /** 7111 * SET_CONFIG reply command. 7112 */ 7113 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 7114 /** 7115 * DPIA notification command. 7116 */ 7117 struct dmub_rb_cmd_dpia_notification dpia_notification; 7118 /** 7119 * HPD sense notification command. 7120 */ 7121 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 7122 struct dmub_rb_cmd_fused_io fused_io; 7123}; 7124#pragma pack(pop) 7125 7126 7127//============================================================================== 7128//</DMUB_CMD>=================================================================== 7129//============================================================================== 7130//< DMUB_RB>==================================================================== 7131//============================================================================== 7132 7133/** 7134 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 7135 */ 7136struct dmub_rb_init_params { 7137 void *ctx; /**< Caller provided context pointer */ 7138 void *base_address; /**< CPU base address for ring's data */ 7139 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 7140 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 7141 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 7142}; 7143 7144/** 7145 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 7146 */ 7147struct dmub_rb { 7148 void *base_address; /**< CPU address for the ring's data */ 7149 uint32_t rptr; /**< Read pointer for consumer in bytes */ 7150 uint32_t wrpt; /**< Write pointer for producer in bytes */ 7151 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 7152 7153 void *ctx; /**< Caller provided context pointer */ 7154 void *dmub; /**< Pointer to the DMUB interface */ 7155}; 7156 7157/** 7158 * @brief Checks if the ringbuffer is empty. 7159 * 7160 * @param rb DMUB Ringbuffer 7161 * @return true if empty 7162 * @return false otherwise 7163 */ 7164static inline bool dmub_rb_empty(struct dmub_rb *rb) 7165{ 7166 return (rb->wrpt == rb->rptr); 7167} 7168 7169/** 7170 * @brief gets number of outstanding requests in the RB 7171 * 7172 * @param rb DMUB Ringbuffer 7173 * @return true if full 7174 */ 7175static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 7176{ 7177 uint32_t data_count; 7178 7179 if (rb->wrpt >= rb->rptr) 7180 data_count = rb->wrpt - rb->rptr; 7181 else 7182 data_count = rb->capacity - (rb->rptr - rb->wrpt); 7183 7184 return data_count / DMUB_RB_CMD_SIZE; 7185} 7186 7187/** 7188 * @brief gets number of free buffers in the RB 7189 * 7190 * @param rb DMUB Ringbuffer 7191 * @return true if full 7192 */ 7193static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 7194{ 7195 uint32_t data_count; 7196 7197 if (rb->wrpt >= rb->rptr) 7198 data_count = rb->wrpt - rb->rptr; 7199 else 7200 data_count = rb->capacity - (rb->rptr - rb->wrpt); 7201 7202 /* +1 because 1 entry is always unusable */ 7203 data_count += DMUB_RB_CMD_SIZE; 7204 7205 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 7206} 7207 7208/** 7209 * @brief Checks if the ringbuffer is full 7210 * 7211 * @param rb DMUB Ringbuffer 7212 * @return true if full 7213 * @return false otherwise 7214 */ 7215static inline bool dmub_rb_full(struct dmub_rb *rb) 7216{ 7217 uint32_t data_count; 7218 7219 if (rb->wrpt >= rb->rptr) 7220 data_count = rb->wrpt - rb->rptr; 7221 else 7222 data_count = rb->capacity - (rb->rptr - rb->wrpt); 7223 7224 /* -1 because 1 entry is always unusable */ 7225 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 7226} 7227 7228/** 7229 * @brief Pushes a command into the ringbuffer 7230 * 7231 * @param rb DMUB ringbuffer 7232 * @param cmd The command to push 7233 * @return true if the ringbuffer was not full 7234 * @return false otherwise 7235 */ 7236static inline bool dmub_rb_push_front(struct dmub_rb *rb, 7237 const union dmub_rb_cmd *cmd) 7238{ 7239 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 7240 const uint8_t *src = (const uint8_t *)cmd; 7241 uint8_t i; 7242 7243 if (rb->capacity == 0) 7244 return false; 7245 7246 if (dmub_rb_full(rb)) 7247 return false; 7248 7249 // copying data 7250 for (i = 0; i < DMUB_RB_CMD_SIZE; i++) 7251 *dst++ = *src++; 7252 7253 rb->wrpt += DMUB_RB_CMD_SIZE; 7254 7255 if (rb->wrpt >= rb->capacity) 7256 rb->wrpt %= rb->capacity; 7257 7258 return true; 7259} 7260 7261/** 7262 * @brief Pushes a command into the DMUB outbox ringbuffer 7263 * 7264 * @param rb DMUB outbox ringbuffer 7265 * @param cmd Outbox command 7266 * @return true if not full 7267 * @return false otherwise 7268 */ 7269static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 7270 const union dmub_rb_out_cmd *cmd) 7271{ 7272 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 7273 const uint8_t *src = (const uint8_t *)cmd; 7274 7275 if (rb->capacity == 0) 7276 return false; 7277 7278 if (dmub_rb_full(rb)) 7279 return false; 7280 7281 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 7282 7283 rb->wrpt += DMUB_RB_CMD_SIZE; 7284 7285 if (rb->wrpt >= rb->capacity) 7286 rb->wrpt %= rb->capacity; 7287 7288 return true; 7289} 7290 7291/** 7292 * @brief Returns the next unprocessed command in the ringbuffer. 7293 * 7294 * @param rb DMUB ringbuffer 7295 * @param cmd The command to return 7296 * @return true if not empty 7297 * @return false otherwise 7298 */ 7299static inline bool dmub_rb_front(struct dmub_rb *rb, 7300 union dmub_rb_cmd **cmd) 7301{ 7302 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 7303 7304 if (dmub_rb_empty(rb)) 7305 return false; 7306 7307 *cmd = (union dmub_rb_cmd *)rb_cmd; 7308 7309 return true; 7310} 7311 7312/** 7313 * @brief Determines the next ringbuffer offset. 7314 * 7315 * @param rb DMUB inbox ringbuffer 7316 * @param num_cmds Number of commands 7317 * @param next_rptr The next offset in the ringbuffer 7318 */ 7319static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 7320 uint32_t num_cmds, 7321 uint32_t *next_rptr) 7322{ 7323 if (rb->capacity == 0) 7324 return; 7325 7326 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 7327 7328 if (*next_rptr >= rb->capacity) 7329 *next_rptr %= rb->capacity; 7330} 7331 7332/** 7333 * @brief Returns a pointer to a command in the inbox. 7334 * 7335 * @param rb DMUB inbox ringbuffer 7336 * @param cmd The inbox command to return 7337 * @param rptr The ringbuffer offset 7338 * @return true if not empty 7339 * @return false otherwise 7340 */ 7341static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 7342 union dmub_rb_cmd **cmd, 7343 uint32_t rptr) 7344{ 7345 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 7346 7347 if (dmub_rb_empty(rb)) 7348 return false; 7349 7350 *cmd = (union dmub_rb_cmd *)rb_cmd; 7351 7352 return true; 7353} 7354 7355/** 7356 * @brief Returns the next unprocessed command in the outbox. 7357 * 7358 * @param rb DMUB outbox ringbuffer 7359 * @param cmd The outbox command to return 7360 * @return true if not empty 7361 * @return false otherwise 7362 */ 7363static inline bool dmub_rb_out_front(struct dmub_rb *rb, 7364 union dmub_rb_out_cmd *cmd) 7365{ 7366 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 7367 uint64_t *dst = (uint64_t *)cmd; 7368 uint8_t i; 7369 7370 if (dmub_rb_empty(rb)) 7371 return false; 7372 7373 // copying data 7374 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 7375 *dst++ = *src++; 7376 7377 return true; 7378} 7379 7380/** 7381 * @brief Removes the front entry in the ringbuffer. 7382 * 7383 * @param rb DMUB ringbuffer 7384 * @return true if the command was removed 7385 * @return false if there were no commands 7386 */ 7387static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 7388{ 7389 if (rb->capacity == 0) 7390 return false; 7391 7392 if (dmub_rb_empty(rb)) 7393 return false; 7394 7395 rb->rptr += DMUB_RB_CMD_SIZE; 7396 7397 if (rb->rptr >= rb->capacity) 7398 rb->rptr %= rb->capacity; 7399 7400 return true; 7401} 7402 7403/** 7404 * @brief Flushes commands in the ringbuffer to framebuffer memory. 7405 * 7406 * Avoids a race condition where DMCUB accesses memory while 7407 * there are still writes in flight to framebuffer. 7408 * 7409 * @param rb DMUB ringbuffer 7410 */ 7411static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 7412{ 7413 uint32_t rptr = rb->rptr; 7414 uint32_t wptr = rb->wrpt; 7415 7416 if (rb->capacity == 0) 7417 return; 7418 7419 while (rptr != wptr) { 7420 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 7421 uint8_t i; 7422 7423 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 7424 (void)READ_ONCE(*data++); 7425 7426 rptr += DMUB_RB_CMD_SIZE; 7427 if (rptr >= rb->capacity) 7428 rptr %= rb->capacity; 7429 } 7430} 7431 7432/** 7433 * @brief Initializes a DMCUB ringbuffer 7434 * 7435 * @param rb DMUB ringbuffer 7436 * @param init_params initial configuration for the ringbuffer 7437 */ 7438static inline void dmub_rb_init(struct dmub_rb *rb, 7439 struct dmub_rb_init_params *init_params) 7440{ 7441 rb->base_address = init_params->base_address; 7442 rb->capacity = init_params->capacity; 7443 rb->rptr = init_params->read_ptr; 7444 rb->wrpt = init_params->write_ptr; 7445} 7446 7447/** 7448 * @brief Copies output data from in/out commands into the given command. 7449 * 7450 * @param rb DMUB ringbuffer 7451 * @param cmd Command to copy data into 7452 */ 7453static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 7454 union dmub_rb_cmd *cmd) 7455{ 7456 // Copy rb entry back into command 7457 uint8_t *rd_ptr = (rb->rptr == 0) ? 7458 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 7459 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 7460 7461 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 7462} 7463 7464//============================================================================== 7465//</DMUB_RB>==================================================================== 7466//============================================================================== 7467#endif /* _DMUB_CMD_H_ */
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