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dcn401_resource.c

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linux-6.19.14/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c C 
   1// SPDX-License-Identifier: MIT
   2//
   3// Copyright 2024 Advanced Micro Devices, Inc.
   4
   5#include "dm_services.h"
   6#include "dc.h"
   7
   8#include "dcn32/dcn32_init.h"
   9#include "dcn401/dcn401_init.h"
  10
  11#include "resource.h"
  12#include "include/irq_service_interface.h"
  13#include "dcn401_resource.h"
  14
  15#include "dcn20/dcn20_resource.h"
  16#include "dcn30/dcn30_resource.h"
  17#include "dcn32/dcn32_resource.h"
  18#include "dcn321/dcn321_resource.h"
  19
  20#include "dcn10/dcn10_ipp.h"
  21#include "dcn401/dcn401_hubbub.h"
  22#include "dcn401/dcn401_mpc.h"
  23#include "dcn401/dcn401_hubp.h"
  24#include "irq/dcn401/irq_service_dcn401.h"
  25#include "dcn401/dcn401_dpp.h"
  26#include "dcn401/dcn401_optc.h"
  27#include "dcn20/dcn20_hwseq.h"
  28#include "dcn30/dcn30_hwseq.h"
  29#include "dce110/dce110_hwseq.h"
  30#include "dcn20/dcn20_opp.h"
  31#include "dcn401/dcn401_dsc.h"
  32#include "dcn30/dcn30_vpg.h"
  33#include "dcn31/dcn31_vpg.h"
  34#include "dcn30/dcn30_afmt.h"
  35#include "dcn30/dcn30_dio_stream_encoder.h"
  36#include "dcn401/dcn401_dio_stream_encoder.h"
  37#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  38#include "dcn31/dcn31_hpo_dp_link_encoder.h"
  39#include "dcn32/dcn32_hpo_dp_link_encoder.h"
  40#include "dcn31/dcn31_apg.h"
  41#include "dcn31/dcn31_dio_link_encoder.h"
  42#include "dcn401/dcn401_dio_link_encoder.h"
  43#include "dcn10/dcn10_link_encoder.h"
  44#include "dcn321/dcn321_dio_link_encoder.h"
  45#include "dce/dce_clock_source.h"
  46#include "dce/dce_audio.h"
  47#include "dce/dce_hwseq.h"
  48#include "clk_mgr.h"
  49#include "virtual/virtual_stream_encoder.h"
  50#include "dml/display_mode_vba.h"
  51#include "dcn401/dcn401_dccg.h"
  52#include "dcn10/dcn10_resource.h"
  53#include "link_service.h"
  54#include "link_enc_cfg.h"
  55#include "dcn31/dcn31_panel_cntl.h"
  56
  57#include "dcn30/dcn30_dwb.h"
  58#include "dcn32/dcn32_mmhubbub.h"
  59
  60#include "dcn/dcn_4_1_0_offset.h"
  61#include "dcn/dcn_4_1_0_sh_mask.h"
  62#include "nbif/nbif_6_3_1_offset.h"
  63
  64#include "reg_helper.h"
  65#include "dce/dmub_abm.h"
  66#include "dce/dmub_psr.h"
  67#include "dce/dce_aux.h"
  68#include "dce/dce_i2c.h"
  69
  70#include "dml/dcn30/display_mode_vba_30.h"
  71#include "vm_helper.h"
  72#include "dcn20/dcn20_vmid.h"
  73
  74#include "dc_state_priv.h"
  75
  76#include "dml2_0/dml2_wrapper.h"
  77
  78#define DC_LOGGER_INIT(logger)
  79
  80enum dcn401_clk_src_array_id {
  81	DCN401_CLK_SRC_PLL0,
  82	DCN401_CLK_SRC_PLL1,
  83	DCN401_CLK_SRC_PLL2,
  84	DCN401_CLK_SRC_PLL3,
  85	//DCN401_CLK_SRC_PLL4,
  86	DCN401_CLK_SRC_TOTAL
  87};
  88
  89/* begin *********************
  90 * macros to expend register list macro defined in HW object header file
  91 */
  92
  93/* DCN */
  94#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
  95
  96#define BASE(seg) BASE_INNER(seg)
  97
  98#define SR(reg_name)\
  99	REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 100		reg ## reg_name
 101#define SR_ARR(reg_name, id)\
 102	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 103		reg ## reg_name
 104#define SR_ARR_INIT(reg_name, id, value)\
 105	REG_STRUCT[id].reg_name =  value
 106
 107#define SRI(reg_name, block, id)\
 108	REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 109		reg ## block ## id ## _ ## reg_name
 110
 111#define SRI_ARR(reg_name, block, id)\
 112	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 113		reg ## block ## id ## _ ## reg_name
 114
 115/*
 116 * Used when a reg_name would otherwise begin with an integer
 117 */
 118#define SRI_ARR_US(reg_name, block, id)\
 119	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \
 120		reg ## block ## id ## reg_name
 121#define SR_ARR_I2C(reg_name, id) \
 122	REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 123
 124#define SRI_ARR_I2C(reg_name, block, id)\
 125	REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 126		reg ## block ## id ## _ ## reg_name
 127
 128#define SRI_ARR_ALPHABET(reg_name, block, index, id)\
 129	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 130		reg ## block ## id ## _ ## reg_name
 131
 132#define SRI2(reg_name, block, id)\
 133	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 134		reg ## reg_name
 135#define SRI2_ARR(reg_name, block, id)\
 136	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 137		reg ## reg_name
 138
 139#define SRIR(var_name, reg_name, block, id)\
 140	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 141		reg ## block ## id ## _ ## reg_name
 142
 143#define SRII(reg_name, block, id)\
 144	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 145		reg ## block ## id ## _ ## reg_name
 146
 147#define SRII_ARR_2(reg_name, block, id, inst)\
 148	REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 149		reg ## block ## id ## _ ## reg_name
 150
 151#define SRII_MPC_RMU(reg_name, block, id)\
 152	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 153		reg ## block ## id ## _ ## reg_name
 154
 155#define SRII_DWB(reg_name, temp_name, block, id)\
 156	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 157		reg ## block ## id ## _ ## temp_name
 158
 159#define DCCG_SRII(reg_name, block, id)\
 160	REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 161		reg ## block ## id ## _ ## reg_name
 162
 163#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
 164	.field_name = reg_name ## __ ## field_name ## post_fix
 165
 166#define VUPDATE_SRII(reg_name, block, id)\
 167	REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 168		reg ## reg_name ## _ ## block ## id
 169
 170/* NBIO */
 171#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
 172
 173#define NBIO_BASE(seg) \
 174	NBIO_BASE_INNER(seg)
 175
 176#define NBIO_SR(reg_name)\
 177	REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
 178		regBIF_BX0_ ## reg_name
 179#define NBIO_SR_ARR(reg_name, id)\
 180	REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
 181		regBIF_BX0_ ## reg_name
 182
 183#define CTX ctx
 184#define REG(reg_name) \
 185	(ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
 186
 187static struct bios_registers bios_regs;
 188
 189#define bios_regs_init() \
 190		NBIO_SR(BIOS_SCRATCH_3),\
 191		NBIO_SR(BIOS_SCRATCH_6)
 192
 193#define clk_src_regs_init(index, pllid)\
 194	CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
 195
 196static struct dce110_clk_src_regs clk_src_regs[5];
 197
 198static const struct dce110_clk_src_shift cs_shift = {
 199		CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
 200};
 201
 202static const struct dce110_clk_src_mask cs_mask = {
 203		CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
 204};
 205
 206#define abm_regs_init(id)\
 207		ABM_DCN401_REG_LIST_RI(id)
 208
 209static struct dce_abm_registers abm_regs[4];
 210
 211static const struct dce_abm_shift abm_shift = {
 212		ABM_MASK_SH_LIST_DCN401(__SHIFT)
 213};
 214
 215static const struct dce_abm_mask abm_mask = {
 216		ABM_MASK_SH_LIST_DCN401(_MASK)
 217};
 218
 219#define audio_regs_init(id)\
 220		AUD_COMMON_REG_LIST_RI(id)
 221
 222static struct dce_audio_registers audio_regs[5];
 223
 224#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 225		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 226		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 227		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 228
 229static const struct dce_audio_shift audio_shift = {
 230		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 231};
 232
 233static const struct dce_audio_mask audio_mask = {
 234		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 235};
 236
 237#define vpg_regs_init(id)\
 238		VPG_DCN401_REG_LIST_RI(id)
 239
 240static struct dcn31_vpg_registers vpg_regs[9];
 241
 242static const struct dcn31_vpg_shift vpg_shift = {
 243	DCN31_VPG_MASK_SH_LIST(__SHIFT)
 244};
 245
 246static const struct dcn31_vpg_mask vpg_mask = {
 247	DCN31_VPG_MASK_SH_LIST(_MASK)
 248};
 249
 250#define afmt_regs_init(id)\
 251		AFMT_DCN3_REG_LIST_RI(id)
 252
 253static struct dcn30_afmt_registers afmt_regs[5];
 254
 255static const struct dcn30_afmt_shift afmt_shift = {
 256	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 257};
 258
 259static const struct dcn30_afmt_mask afmt_mask = {
 260	DCN3_AFMT_MASK_SH_LIST(_MASK)
 261};
 262
 263#define apg_regs_init(id)\
 264	APG_DCN31_REG_LIST_RI(id)
 265
 266static struct dcn31_apg_registers apg_regs[4];
 267
 268static const struct dcn31_apg_shift apg_shift = {
 269	DCN31_APG_MASK_SH_LIST(__SHIFT)
 270};
 271
 272static const struct dcn31_apg_mask apg_mask = {
 273		DCN31_APG_MASK_SH_LIST(_MASK)
 274};
 275
 276#define stream_enc_regs_init(id)\
 277	SE_DCN4_01_REG_LIST_RI(id)
 278
 279static struct dcn10_stream_enc_registers stream_enc_regs[4];
 280
 281static const struct dcn10_stream_encoder_shift se_shift = {
 282		SE_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
 283};
 284
 285static const struct dcn10_stream_encoder_mask se_mask = {
 286		SE_COMMON_MASK_SH_LIST_DCN401(_MASK)
 287};
 288
 289#define aux_regs_init(id)\
 290	DCN2_AUX_REG_LIST_RI(id)
 291
 292static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
 293
 294#define hpd_regs_init(id)\
 295	HPD_REG_LIST_RI(id)
 296
 297static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
 298
 299#define link_regs_init(id, phyid)\
 300	LE_DCN401_REG_LIST_RI(id)
 301
 302static struct dcn10_link_enc_registers link_enc_regs[4];
 303
 304
 305static const struct dcn10_link_enc_shift le_shift = {
 306	LINK_ENCODER_MASK_SH_LIST_DCN401(__SHIFT)
 307};
 308
 309
 310static const struct dcn10_link_enc_mask le_mask = {
 311	LINK_ENCODER_MASK_SH_LIST_DCN401(_MASK)
 312};
 313
 314
 315#define hpo_dp_stream_encoder_reg_init(id)\
 316	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
 317
 318static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
 319
 320static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 321	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 322};
 323
 324static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 325	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 326};
 327
 328
 329#define hpo_dp_link_encoder_reg_init(id)\
 330	DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
 331	/*DCN3_1_RDPCSTX_REG_LIST(0),*/
 332	/*DCN3_1_RDPCSTX_REG_LIST(1),*/
 333	/*DCN3_1_RDPCSTX_REG_LIST(2),*/
 334	/*DCN3_1_RDPCSTX_REG_LIST(3),*/
 335
 336static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4];
 337
 338static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 339	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 340};
 341
 342static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 343	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 344};
 345
 346#define dpp_regs_init(id)\
 347	DPP_REG_LIST_DCN401_COMMON_RI(id)
 348
 349static struct dcn401_dpp_registers dpp_regs[4];
 350
 351static const struct dcn401_dpp_shift tf_shift = {
 352		DPP_REG_LIST_SH_MASK_DCN401_COMMON(__SHIFT)
 353};
 354
 355static const struct dcn401_dpp_mask tf_mask = {
 356		DPP_REG_LIST_SH_MASK_DCN401_COMMON(_MASK)
 357};
 358
 359#define opp_regs_init(id)\
 360	OPP_REG_LIST_DCN401_RI(id)
 361
 362static struct dcn20_opp_registers opp_regs[4];
 363
 364static const struct dcn20_opp_shift opp_shift = {
 365	OPP_MASK_SH_LIST_DCN20(__SHIFT)
 366};
 367
 368static const struct dcn20_opp_mask opp_mask = {
 369	OPP_MASK_SH_LIST_DCN20(_MASK)
 370};
 371
 372#define aux_engine_regs_init(id) \
 373	AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
 374	SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
 375	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
 376	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)
 377
 378static struct dce110_aux_registers aux_engine_regs[5];
 379
 380static const struct dce110_aux_registers_shift aux_shift = {
 381	DCN_AUX_MASK_SH_LIST(__SHIFT)
 382};
 383
 384static const struct dce110_aux_registers_mask aux_mask = {
 385	DCN_AUX_MASK_SH_LIST(_MASK)
 386};
 387
 388#define dwbc_regs_dcn401_init(id)\
 389	DWBC_COMMON_REG_LIST_DCN30_RI(id)
 390
 391static struct dcn30_dwbc_registers dwbc401_regs[1];
 392
 393static const struct dcn30_dwbc_shift dwbc401_shift = {
 394	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 395};
 396
 397static const struct dcn30_dwbc_mask dwbc401_mask = {
 398	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 399};
 400
 401
 402#define mcif_wb_regs_dcn3_init(id)\
 403	MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
 404
 405static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
 406
 407static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 408	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 409};
 410
 411static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 412	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
 413};
 414
 415#define dsc_regs_init(id)\
 416	DSC_REG_LIST_DCN401_RI(id)
 417
 418static struct dcn401_dsc_registers dsc_regs[4];
 419
 420static const struct dcn401_dsc_shift dsc_shift = {
 421	DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)
 422};
 423
 424static const struct dcn401_dsc_mask dsc_mask = {
 425	DSC_REG_LIST_SH_MASK_DCN401(_MASK)
 426};
 427
 428static struct dcn401_mpc_registers mpc_regs;
 429
 430#define dcn_mpc_regs_init()\
 431	MPC_REG_LIST_DCN4_01_RI(0),\
 432	MPC_REG_LIST_DCN4_01_RI(1),\
 433	MPC_REG_LIST_DCN4_01_RI(2),\
 434	MPC_REG_LIST_DCN4_01_RI(3),\
 435	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
 436	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
 437	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
 438	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
 439	MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
 440
 441static const struct dcn401_mpc_shift mpc_shift = {
 442	MPC_COMMON_MASK_SH_LIST_DCN4_01(__SHIFT)
 443};
 444
 445static const struct dcn401_mpc_mask mpc_mask = {
 446	MPC_COMMON_MASK_SH_LIST_DCN4_01(_MASK)
 447};
 448
 449#define optc_regs_init(id)\
 450	OPTC_COMMON_REG_LIST_DCN401_RI(id)
 451
 452static struct dcn_optc_registers optc_regs[4];
 453
 454static const struct dcn_optc_shift optc_shift = {
 455	OPTC_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
 456};
 457
 458static const struct dcn_optc_mask optc_mask = {
 459	OPTC_COMMON_MASK_SH_LIST_DCN401(_MASK)
 460};
 461
 462#define hubp_regs_init(id)\
 463	HUBP_REG_LIST_DCN401_RI(id)
 464
 465static struct dcn_hubp2_registers hubp_regs[4];
 466
 467static const struct dcn_hubp2_shift hubp_shift = {
 468		HUBP_MASK_SH_LIST_DCN401(__SHIFT)
 469};
 470
 471static const struct dcn_hubp2_mask hubp_mask = {
 472		HUBP_MASK_SH_LIST_DCN401(_MASK)
 473};
 474
 475static struct dcn_hubbub_registers hubbub_reg;
 476#define hubbub_reg_init()\
 477		HUBBUB_REG_LIST_DCN4_01_RI(0)
 478
 479static const struct dcn_hubbub_shift hubbub_shift = {
 480		HUBBUB_MASK_SH_LIST_DCN4_01(__SHIFT)
 481};
 482
 483static const struct dcn_hubbub_mask hubbub_mask = {
 484		HUBBUB_MASK_SH_LIST_DCN4_01(_MASK)
 485};
 486
 487static struct dccg_registers dccg_regs;
 488
 489#define dccg_regs_init()\
 490	DCCG_REG_LIST_DCN401_RI()
 491
 492static const struct dccg_shift dccg_shift = {
 493		DCCG_MASK_SH_LIST_DCN401(__SHIFT)
 494};
 495
 496static const struct dccg_mask dccg_mask = {
 497		DCCG_MASK_SH_LIST_DCN401(_MASK)
 498};
 499
 500#define SRII2(reg_name_pre, reg_name_post, id)\
 501	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 502			## id ## _ ## reg_name_post ## _BASE_IDX) + \
 503			reg ## reg_name_pre ## id ## _ ## reg_name_post
 504
 505
 506#define HWSEQ_DCN401_REG_LIST()\
 507	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 508	SR(DIO_MEM_PWR_CTRL), \
 509	SR(ODM_MEM_PWR_CTRL3), \
 510	SR(MMHUBBUB_MEM_PWR_CNTL), \
 511	SR(DCCG_GATE_DISABLE_CNTL), \
 512	SR(DCCG_GATE_DISABLE_CNTL2), \
 513	SR(DCFCLK_CNTL),\
 514	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 515	SRII(PIXEL_RATE_CNTL, OTG, 0), \
 516	SRII(PIXEL_RATE_CNTL, OTG, 1),\
 517	SRII(PIXEL_RATE_CNTL, OTG, 2),\
 518	SRII(PIXEL_RATE_CNTL, OTG, 3),\
 519	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 520	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 521	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 522	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 523	SR(MICROSECOND_TIME_BASE_DIV), \
 524	SR(MILLISECOND_TIME_BASE_DIV), \
 525	SR(DISPCLK_FREQ_CHANGE_CNTL), \
 526	SR(RBBMIF_TIMEOUT_DIS), \
 527	SR(RBBMIF_TIMEOUT_DIS_2), \
 528	SR(DCHUBBUB_CRC_CTRL), \
 529	SR(DPP_TOP0_DPP_CRC_CTRL), \
 530	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 531	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 532	SR(MPC_CRC_CTRL), \
 533	SR(MPC_CRC_RESULT_GB), \
 534	SR(MPC_CRC_RESULT_C), \
 535	SR(MPC_CRC_RESULT_AR), \
 536	SR(DOMAIN0_PG_CONFIG), \
 537	SR(DOMAIN1_PG_CONFIG), \
 538	SR(DOMAIN2_PG_CONFIG), \
 539	SR(DOMAIN3_PG_CONFIG), \
 540	SR(DOMAIN16_PG_CONFIG), \
 541	SR(DOMAIN17_PG_CONFIG), \
 542	SR(DOMAIN18_PG_CONFIG), \
 543	SR(DOMAIN19_PG_CONFIG), \
 544	SR(DOMAIN22_PG_CONFIG), \
 545	SR(DOMAIN23_PG_CONFIG), \
 546	SR(DOMAIN24_PG_CONFIG), \
 547	SR(DOMAIN25_PG_CONFIG), \
 548	SR(DOMAIN0_PG_STATUS), \
 549	SR(DOMAIN1_PG_STATUS), \
 550	SR(DOMAIN2_PG_STATUS), \
 551	SR(DOMAIN3_PG_STATUS), \
 552	SR(DOMAIN16_PG_STATUS), \
 553	SR(DOMAIN17_PG_STATUS), \
 554	SR(DOMAIN18_PG_STATUS), \
 555	SR(DOMAIN19_PG_STATUS), \
 556	SR(DOMAIN22_PG_STATUS), \
 557	SR(DOMAIN23_PG_STATUS), \
 558	SR(DOMAIN24_PG_STATUS), \
 559	SR(DOMAIN25_PG_STATUS), \
 560	SR(DC_IP_REQUEST_CNTL), \
 561	SR(AZALIA_AUDIO_DTO), \
 562	SR(HPO_TOP_HW_CONTROL),\
 563	SR(AZALIA_CONTROLLER_CLOCK_GATING)
 564
 565static struct dce_hwseq_registers hwseq_reg;
 566
 567#define hwseq_reg_init()\
 568	HWSEQ_DCN401_REG_LIST()
 569
 570#define HWSEQ_DCN401_MASK_SH_LIST(mask_sh)\
 571	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 572	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 573	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 574	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 575	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 576	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 577	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 578	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 579	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 580	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 581	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 582	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 583	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 584	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 585	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 586	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 587	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 588	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 589	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 590	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 591	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 592	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 593	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 594	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 595	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 596	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 597	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 598	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 599	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 600	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 601	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 602	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 603	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 604	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 605	HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 606	HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 607	HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 608	HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 609	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 610	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 611	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 612	HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \
 613	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 614	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)
 615
 616static const struct dce_hwseq_shift hwseq_shift = {
 617		HWSEQ_DCN401_MASK_SH_LIST(__SHIFT)
 618};
 619
 620static const struct dce_hwseq_mask hwseq_mask = {
 621		HWSEQ_DCN401_MASK_SH_LIST(_MASK)
 622};
 623
 624#define vmid_regs_init(id)\
 625		DCN20_VMID_REG_LIST_RI(id)
 626
 627static struct dcn_vmid_registers vmid_regs[16];
 628
 629static const struct dcn20_vmid_shift vmid_shifts = {
 630		DCN20_VMID_MASK_SH_LIST(__SHIFT)
 631};
 632
 633static const struct dcn20_vmid_mask vmid_masks = {
 634		DCN20_VMID_MASK_SH_LIST(_MASK)
 635};
 636
 637static const struct resource_caps res_cap_dcn4_01 = {
 638	.num_timing_generator = 4,
 639	.num_opp = 4,
 640	.num_video_plane = 4,
 641	.num_audio = 4,
 642	.num_stream_encoder = 4,
 643	.num_hpo_dp_stream_encoder = 4,
 644	.num_hpo_dp_link_encoder = 4,
 645	.num_pll = 4,
 646	.num_dwb = 1,
 647	.num_ddc = 4,
 648	.num_vmid = 16,
 649	.num_mpc_3dlut = 4,
 650	.num_dsc = 4,
 651};
 652
 653static const struct dc_plane_cap plane_cap = {
 654	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 655	.per_pixel_alpha = true,
 656
 657	.pixel_format_support = {
 658			.argb8888 = true,
 659			.nv12 = true,
 660			.fp16 = true,
 661			.p010 = true,
 662			.ayuv = false,
 663	},
 664
 665	.max_upscale_factor = {
 666			.argb8888 = 16000,
 667			.nv12 = 16000,
 668			.fp16 = 16000
 669	},
 670
 671	// 6:1 downscaling ratio: 1000/6 = 166.666
 672	.max_downscale_factor = {
 673			.argb8888 = 167,
 674			.nv12 = 167,
 675			.fp16 = 167
 676	},
 677	64,
 678	64
 679};
 680
 681static const struct dc_debug_options debug_defaults_drv = {
 682	.disable_dmcu = true,
 683	.force_abm_enable = false,
 684	.clock_trace = true,
 685	.disable_pplib_clock_request = false,
 686	.pipe_split_policy = MPC_SPLIT_AVOID,
 687	.force_single_disp_pipe_split = false,
 688	.disable_dcc = DCC_ENABLE,
 689	.vsr_support = true,
 690	.performance_trace = false,
 691	.max_downscale_src_width = 7680,/*upto 8K*/
 692	.disable_pplib_wm_range = false,
 693	.scl_reset_length10 = true,
 694	.sanity_checks = false,
 695	.underflow_assert_delay_us = 0xFFFFFFFF,
 696	.dwb_fi_phase = -1, // -1 = disable,
 697	.dmub_command_table = true,
 698	.enable_mem_low_power = {
 699		.bits = {
 700			.vga = false,
 701			.i2c = false,
 702			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 703			.dscl = false,
 704			.cm = false,
 705			.mpc = false,
 706			.optc = true,
 707		}
 708	},
 709	.use_max_lb = true,
 710	.force_disable_subvp = false,
 711	.disable_force_pstate_allow_on_hw_release = false,
 712	.exit_idle_opt_for_cursor_updates = true,
 713	.using_dml2 = true,
 714	.using_dml21 = true,
 715	.enable_single_display_2to1_odm_policy = true,
 716
 717	//must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
 718	.enable_double_buffered_dsc_pg_support = true,
 719	.enable_dp_dig_pixel_rate_div_policy = 1,
 720	.allow_sw_cursor_fallback = false,
 721	.alloc_extra_way_for_cursor = true,
 722	.min_prefetch_in_strobe_ns = 60000, // 60us
 723	.disable_unbounded_requesting = false,
 724	.dcc_meta_propagation_delay_us = 10,
 725	.fams_version = {
 726		.minor = 1,
 727		.major = 2,
 728	}, //v2.1
 729	.fams2_config = {
 730		.bits = {
 731			.enable = true,
 732			.enable_offload_flip = true,
 733			.enable_stall_recovery = true,
 734		}
 735	},
 736	.force_cositing = CHROMA_COSITING_NONE + 1,
 737};
 738
 739static const struct dc_check_config config_defaults = {
 740	.enable_legacy_fast_update = false,
 741};
 742
 743static struct dce_aux *dcn401_aux_engine_create(
 744	struct dc_context *ctx,
 745	uint32_t inst)
 746{
 747	struct aux_engine_dce110 *aux_engine =
 748		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 749
 750	if (!aux_engine)
 751		return NULL;
 752
 753#undef REG_STRUCT
 754#define REG_STRUCT aux_engine_regs
 755	aux_engine_regs_init(0),
 756	aux_engine_regs_init(1),
 757	aux_engine_regs_init(2),
 758	aux_engine_regs_init(3);
 759
 760	dce110_aux_engine_construct(aux_engine, ctx, inst,
 761				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 762				    &aux_engine_regs[inst],
 763					&aux_mask,
 764					&aux_shift,
 765					ctx->dc->caps.extended_aux_timeout_support);
 766
 767	return &aux_engine->base;
 768}
 769#define i2c_inst_regs_init(id)\
 770	I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
 771
 772static struct dce_i2c_registers i2c_hw_regs[5];
 773
 774static const struct dce_i2c_shift i2c_shifts = {
 775		I2C_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
 776};
 777
 778static const struct dce_i2c_mask i2c_masks = {
 779		I2C_COMMON_MASK_SH_LIST_DCN401(_MASK)
 780};
 781
 782static struct dce_i2c_hw *dcn401_i2c_hw_create(
 783	struct dc_context *ctx,
 784	uint32_t inst)
 785{
 786	struct dce_i2c_hw *dce_i2c_hw =
 787		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 788
 789	if (!dce_i2c_hw)
 790		return NULL;
 791
 792#undef REG_STRUCT
 793#define REG_STRUCT i2c_hw_regs
 794		i2c_inst_regs_init(1),
 795		i2c_inst_regs_init(2),
 796		i2c_inst_regs_init(3),
 797		i2c_inst_regs_init(4);
 798
 799	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 800				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 801
 802	return dce_i2c_hw;
 803}
 804
 805static struct clock_source *dcn401_clock_source_create(
 806		struct dc_context *ctx,
 807		struct dc_bios *bios,
 808		enum clock_source_id id,
 809		const struct dce110_clk_src_regs *regs,
 810		bool dp_clk_src)
 811{
 812	struct dce110_clk_src *clk_src =
 813		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 814
 815	if (!clk_src)
 816		return NULL;
 817
 818	if (dcn401_clk_src_construct(clk_src, ctx, bios, id,
 819			regs, &cs_shift, &cs_mask)) {
 820		clk_src->base.dp_clk_src = dp_clk_src;
 821		return &clk_src->base;
 822	}
 823
 824	kfree(clk_src);
 825	BREAK_TO_DEBUGGER();
 826	return NULL;
 827}
 828
 829static struct hubbub *dcn401_hubbub_create(struct dc_context *ctx)
 830{
 831	int i;
 832
 833	struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
 834					  GFP_KERNEL);
 835
 836	if (!hubbub2)
 837		return NULL;
 838
 839
 840#undef REG_STRUCT
 841#define REG_STRUCT hubbub_reg
 842	hubbub_reg_init();
 843
 844#undef REG_STRUCT
 845#define REG_STRUCT vmid_regs
 846	vmid_regs_init(0),
 847	vmid_regs_init(1),
 848	vmid_regs_init(2),
 849	vmid_regs_init(3),
 850	vmid_regs_init(4),
 851	vmid_regs_init(5),
 852	vmid_regs_init(6),
 853	vmid_regs_init(7),
 854	vmid_regs_init(8),
 855	vmid_regs_init(9),
 856	vmid_regs_init(10),
 857	vmid_regs_init(11),
 858	vmid_regs_init(12),
 859	vmid_regs_init(13),
 860	vmid_regs_init(14),
 861	vmid_regs_init(15);
 862
 863	hubbub401_construct(hubbub2, ctx,
 864			&hubbub_reg,
 865			&hubbub_shift,
 866			&hubbub_mask,
 867			DCN4_01_DEFAULT_DET_SIZE, //nominal (default) detile buffer size in kbytes,
 868			8, //dml2 ip_params_st.pixel_chunk_size_kbytes
 869			DCN4_01_CRB_SIZE_KB); //dml2 ip_params_st.config_return_buffer_size_in_kbytes
 870
 871	for (i = 0; i < res_cap_dcn4_01.num_vmid; i++) {
 872		struct dcn20_vmid *vmid = &hubbub2->vmid[i];
 873
 874		vmid->ctx = ctx;
 875
 876		vmid->regs = &vmid_regs[i];
 877		vmid->shifts = &vmid_shifts;
 878		vmid->masks = &vmid_masks;
 879	}
 880
 881	return &hubbub2->base;
 882}
 883
 884static struct hubp *dcn401_hubp_create(
 885	struct dc_context *ctx,
 886	uint32_t inst)
 887{
 888	struct dcn20_hubp *hubp2 =
 889		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
 890
 891	if (!hubp2)
 892		return NULL;
 893
 894#undef REG_STRUCT
 895#define REG_STRUCT hubp_regs
 896		hubp_regs_init(0),
 897		hubp_regs_init(1),
 898		hubp_regs_init(2),
 899		hubp_regs_init(3);
 900
 901	if (hubp401_construct(hubp2, ctx, inst,
 902			&hubp_regs[inst], &hubp_shift, &hubp_mask))
 903		return &hubp2->base;
 904
 905	BREAK_TO_DEBUGGER();
 906	kfree(hubp2);
 907	return NULL;
 908}
 909
 910static void dcn401_dpp_destroy(struct dpp **dpp)
 911{
 912	kfree(TO_DCN401_DPP(*dpp));
 913	*dpp = NULL;
 914}
 915
 916static struct dpp *dcn401_dpp_create(
 917	struct dc_context *ctx,
 918	uint32_t inst)
 919{
 920	struct dcn401_dpp *dpp401 =
 921		kzalloc(sizeof(struct dcn401_dpp), GFP_KERNEL);
 922
 923	if (!dpp401)
 924		return NULL;
 925
 926#undef REG_STRUCT
 927#define REG_STRUCT dpp_regs
 928	dpp_regs_init(0),
 929	dpp_regs_init(1),
 930	dpp_regs_init(2),
 931	dpp_regs_init(3);
 932
 933	if (dpp401_construct(dpp401, ctx, inst,
 934			&dpp_regs[inst], &tf_shift, &tf_mask))
 935		return &dpp401->base;
 936
 937	BREAK_TO_DEBUGGER();
 938	kfree(dpp401);
 939	return NULL;
 940}
 941
 942static struct mpc *dcn401_mpc_create(
 943		struct dc_context *ctx,
 944		int num_mpcc,
 945		int num_rmu)
 946{
 947	struct dcn401_mpc *mpc401 = kzalloc(sizeof(struct dcn401_mpc),
 948					  GFP_KERNEL);
 949
 950	if (!mpc401)
 951		return NULL;
 952
 953#undef REG_STRUCT
 954#define REG_STRUCT mpc_regs
 955	dcn_mpc_regs_init();
 956
 957	dcn401_mpc_construct(mpc401, ctx,
 958			&mpc_regs,
 959			&mpc_shift,
 960			&mpc_mask,
 961			num_mpcc,
 962			num_rmu);
 963
 964	return &mpc401->base;
 965}
 966
 967static struct output_pixel_processor *dcn401_opp_create(
 968	struct dc_context *ctx, uint32_t inst)
 969{
 970	struct dcn20_opp *opp4 =
 971		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 972
 973	if (!opp4) {
 974		BREAK_TO_DEBUGGER();
 975		return NULL;
 976	}
 977
 978#undef REG_STRUCT
 979#define REG_STRUCT opp_regs
 980	opp_regs_init(0),
 981	opp_regs_init(1),
 982	opp_regs_init(2),
 983	opp_regs_init(3);
 984
 985	dcn20_opp_construct(opp4, ctx, inst,
 986			&opp_regs[inst], &opp_shift, &opp_mask);
 987	return &opp4->base;
 988}
 989
 990
 991static struct timing_generator *dcn401_timing_generator_create(
 992		struct dc_context *ctx,
 993		uint32_t instance)
 994{
 995	struct optc *tgn10 =
 996		kzalloc(sizeof(struct optc), GFP_KERNEL);
 997
 998	if (!tgn10)
 999		return NULL;
1000#undef REG_STRUCT
1001#define REG_STRUCT optc_regs
1002	optc_regs_init(0),
1003	optc_regs_init(1),
1004	optc_regs_init(2),
1005	optc_regs_init(3);
1006
1007	tgn10->base.inst = instance;
1008	tgn10->base.ctx = ctx;
1009
1010	tgn10->tg_regs = &optc_regs[instance];
1011	tgn10->tg_shift = &optc_shift;
1012	tgn10->tg_mask = &optc_mask;
1013
1014	dcn401_timing_generator_init(tgn10);
1015
1016	return &tgn10->base;
1017}
1018
1019static const struct encoder_feature_support link_enc_feature = {
1020		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1021		.max_hdmi_pixel_clock = 600000,
1022		.hdmi_ycbcr420_supported = true,
1023		.dp_ycbcr420_supported = true,
1024		.fec_supported = true,
1025		.flags.bits.IS_HBR2_CAPABLE = true,
1026		.flags.bits.IS_HBR3_CAPABLE = true,
1027		.flags.bits.IS_TPS3_CAPABLE = true,
1028		.flags.bits.IS_TPS4_CAPABLE = true
1029};
1030
1031static struct link_encoder *dcn401_link_encoder_create(
1032	struct dc_context *ctx,
1033	const struct encoder_init_data *enc_init_data)
1034{
1035	struct dcn20_link_encoder *enc20 =
1036		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1037
1038	if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1039		return NULL;
1040
1041#undef REG_STRUCT
1042#define REG_STRUCT link_enc_aux_regs
1043	aux_regs_init(0),
1044	aux_regs_init(1),
1045	aux_regs_init(2),
1046	aux_regs_init(3);
1047
1048#undef REG_STRUCT
1049#define REG_STRUCT link_enc_hpd_regs
1050	hpd_regs_init(0),
1051	hpd_regs_init(1),
1052	hpd_regs_init(2),
1053	hpd_regs_init(3);
1054#undef REG_STRUCT
1055#define REG_STRUCT link_enc_regs
1056	link_regs_init(0, A),
1057	link_regs_init(1, B),
1058	link_regs_init(2, C),
1059	link_regs_init(3, D);
1060
1061	dcn401_link_encoder_construct(enc20,
1062			enc_init_data,
1063			&link_enc_feature,
1064			&link_enc_regs[enc_init_data->transmitter],
1065			&link_enc_aux_regs[enc_init_data->channel - 1],
1066			&link_enc_hpd_regs[enc_init_data->hpd_source],
1067			&le_shift,
1068			&le_mask);
1069	return &enc20->enc10.base;
1070}
1071
1072static void read_dce_straps(
1073	struct dc_context *ctx,
1074	struct resource_straps *straps)
1075{
1076	generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1077		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1078
1079}
1080
1081static struct audio *dcn401_create_audio(
1082		struct dc_context *ctx, unsigned int inst)
1083{
1084
1085#undef REG_STRUCT
1086#define REG_STRUCT audio_regs
1087	audio_regs_init(0),
1088	audio_regs_init(1),
1089	audio_regs_init(2),
1090	audio_regs_init(3),
1091	audio_regs_init(4);
1092
1093	return dce_audio_create(ctx, inst,
1094			&audio_regs[inst], &audio_shift, &audio_mask);
1095}
1096
1097static struct vpg *dcn401_vpg_create(
1098	struct dc_context *ctx,
1099	uint32_t inst)
1100{
1101	struct dcn31_vpg *vpg4 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1102
1103	if (!vpg4)
1104		return NULL;
1105
1106
1107#undef REG_STRUCT
1108#define REG_STRUCT vpg_regs
1109	vpg_regs_init(0),
1110	vpg_regs_init(1),
1111	vpg_regs_init(2),
1112	vpg_regs_init(3),
1113	vpg_regs_init(4),
1114	vpg_regs_init(5),
1115	vpg_regs_init(6),
1116	vpg_regs_init(7),
1117	vpg_regs_init(8);
1118
1119	vpg31_construct(vpg4, ctx, inst,
1120			&vpg_regs[inst],
1121			&vpg_shift,
1122			&vpg_mask);
1123
1124	return &vpg4->base;
1125}
1126
1127static struct afmt *dcn401_afmt_create(
1128	struct dc_context *ctx,
1129	uint32_t inst)
1130{
1131	struct dcn30_afmt *afmt401 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1132
1133	if (!afmt401)
1134		return NULL;
1135
1136#undef REG_STRUCT
1137#define REG_STRUCT afmt_regs
1138	afmt_regs_init(0),
1139	afmt_regs_init(1),
1140	afmt_regs_init(2),
1141	afmt_regs_init(3),
1142	afmt_regs_init(4);
1143
1144	afmt3_construct(afmt401, ctx, inst,
1145			&afmt_regs[inst],
1146			&afmt_shift,
1147			&afmt_mask);
1148
1149	return &afmt401->base;
1150}
1151
1152static struct apg *dcn401_apg_create(
1153	struct dc_context *ctx,
1154	uint32_t inst)
1155{
1156	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1157
1158	if (!apg31)
1159		return NULL;
1160
1161#undef REG_STRUCT
1162#define REG_STRUCT apg_regs
1163	apg_regs_init(0),
1164	apg_regs_init(1),
1165	apg_regs_init(2),
1166	apg_regs_init(3);
1167
1168	apg31_construct(apg31, ctx, inst,
1169			&apg_regs[inst],
1170			&apg_shift,
1171			&apg_mask);
1172
1173	return &apg31->base;
1174}
1175
1176static struct stream_encoder *dcn401_stream_encoder_create(
1177	enum engine_id eng_id,
1178	struct dc_context *ctx)
1179{
1180	struct dcn10_stream_encoder *enc1;
1181	struct vpg *vpg;
1182	struct afmt *afmt;
1183	int vpg_inst;
1184	int afmt_inst;
1185
1186	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1187	if (eng_id <= ENGINE_ID_DIGF) {
1188		vpg_inst = eng_id;
1189		afmt_inst = eng_id;
1190	} else
1191		return NULL;
1192
1193	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1194	vpg = dcn401_vpg_create(ctx, vpg_inst);
1195	afmt = dcn401_afmt_create(ctx, afmt_inst);
1196
1197	if (!enc1 || !vpg || !afmt || eng_id >= ARRAY_SIZE(stream_enc_regs)) {
1198		kfree(enc1);
1199		kfree(vpg);
1200		kfree(afmt);
1201		return NULL;
1202	}
1203#undef REG_STRUCT
1204#define REG_STRUCT stream_enc_regs
1205	stream_enc_regs_init(0),
1206	stream_enc_regs_init(1),
1207	stream_enc_regs_init(2),
1208	stream_enc_regs_init(3);
1209	//stream_enc_regs_init(4);
1210
1211	dcn401_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1212					eng_id, vpg, afmt,
1213					&stream_enc_regs[eng_id],
1214					&se_shift, &se_mask);
1215	return &enc1->base;
1216}
1217
1218static struct hpo_dp_stream_encoder *dcn401_hpo_dp_stream_encoder_create(
1219	enum engine_id eng_id,
1220	struct dc_context *ctx)
1221{
1222	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1223	struct vpg *vpg;
1224	struct apg *apg;
1225	uint32_t hpo_dp_inst;
1226	uint32_t vpg_inst;
1227	uint32_t apg_inst;
1228
1229	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1230	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1231
1232	/* Mapping of VPG register blocks to HPO DP block instance:
1233	 * VPG[6] -> HPO_DP[0]
1234	 * VPG[7] -> HPO_DP[1]
1235	 * VPG[8] -> HPO_DP[2]
1236	 * VPG[9] -> HPO_DP[3]
1237	 */
1238	vpg_inst = hpo_dp_inst + 5;
1239
1240	/* Mapping of APG register blocks to HPO DP block instance:
1241	 * APG[0] -> HPO_DP[0]
1242	 * APG[1] -> HPO_DP[1]
1243	 * APG[2] -> HPO_DP[2]
1244	 * APG[3] -> HPO_DP[3]
1245	 */
1246	apg_inst = hpo_dp_inst;
1247
1248	/* allocate HPO stream encoder and create VPG sub-block */
1249	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1250	vpg = dcn401_vpg_create(ctx, vpg_inst);
1251	apg = dcn401_apg_create(ctx, apg_inst);
1252
1253	if (!hpo_dp_enc31 || !vpg || !apg) {
1254		kfree(hpo_dp_enc31);
1255		kfree(vpg);
1256		kfree(apg);
1257		return NULL;
1258	}
1259
1260#undef REG_STRUCT
1261#define REG_STRUCT hpo_dp_stream_enc_regs
1262	hpo_dp_stream_encoder_reg_init(0),
1263	hpo_dp_stream_encoder_reg_init(1),
1264	hpo_dp_stream_encoder_reg_init(2),
1265	hpo_dp_stream_encoder_reg_init(3);
1266
1267	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1268					hpo_dp_inst, eng_id, vpg, apg,
1269					&hpo_dp_stream_enc_regs[hpo_dp_inst],
1270					&hpo_dp_se_shift, &hpo_dp_se_mask);
1271
1272	return &hpo_dp_enc31->base;
1273}
1274
1275static struct hpo_dp_link_encoder *dcn401_hpo_dp_link_encoder_create(
1276	uint8_t inst,
1277	struct dc_context *ctx)
1278{
1279	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1280
1281	/* allocate HPO link encoder */
1282	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1283	if (!hpo_dp_enc31)
1284		return NULL; /* out of memory */
1285
1286#undef REG_STRUCT
1287#define REG_STRUCT hpo_dp_link_enc_regs
1288	hpo_dp_link_encoder_reg_init(0),
1289	hpo_dp_link_encoder_reg_init(1),
1290	hpo_dp_link_encoder_reg_init(2),
1291	hpo_dp_link_encoder_reg_init(3);
1292
1293	hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1294					&hpo_dp_link_enc_regs[inst],
1295					&hpo_dp_le_shift, &hpo_dp_le_mask);
1296
1297	return &hpo_dp_enc31->base;
1298}
1299
1300static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans)
1301{
1302	unsigned int num_available_chans = 1;
1303
1304	/* channels for MALL must be a power of 2 */
1305	while (num_chans > 1) {
1306		num_available_chans = (num_available_chans << 1);
1307		num_chans = (num_chans >> 1);
1308	}
1309
1310	/* cannot be odd */
1311	num_available_chans &= ~1;
1312
1313	/* clamp to max available channels for MALL per ASIC */
1314	if (ASICREV_IS_GC_12_0_0_A0(dc->ctx->asic_id.hw_internal_rev)) {
1315		num_available_chans = num_available_chans > 16 ? 16 : num_available_chans;
1316	} else if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) {
1317		num_available_chans = num_available_chans > 8 ? 8 : num_available_chans;
1318	}
1319
1320	return num_available_chans;
1321}
1322
1323static struct dce_hwseq *dcn401_hwseq_create(
1324	struct dc_context *ctx)
1325{
1326	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1327
1328#undef REG_STRUCT
1329#define REG_STRUCT hwseq_reg
1330	hwseq_reg_init();
1331
1332	if (hws) {
1333		hws->ctx = ctx;
1334		hws->regs = &hwseq_reg;
1335		hws->shifts = &hwseq_shift;
1336		hws->masks = &hwseq_mask;
1337	}
1338
1339	return hws;
1340}
1341static const struct resource_create_funcs res_create_funcs = {
1342	.read_dce_straps = read_dce_straps,
1343	.create_audio = dcn401_create_audio,
1344	.create_stream_encoder = dcn401_stream_encoder_create,
1345	.create_hpo_dp_stream_encoder = dcn401_hpo_dp_stream_encoder_create,
1346	.create_hpo_dp_link_encoder = dcn401_hpo_dp_link_encoder_create,
1347	.create_hwseq = dcn401_hwseq_create,
1348};
1349
1350static void dcn401_dsc_destroy(struct display_stream_compressor **dsc)
1351{
1352	kfree(container_of(*dsc, struct dcn401_dsc, base));
1353	*dsc = NULL;
1354}
1355
1356static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
1357{
1358	unsigned int i;
1359
1360	for (i = 0; i < pool->base.stream_enc_count; i++) {
1361		if (pool->base.stream_enc[i] != NULL) {
1362			if (pool->base.stream_enc[i]->vpg != NULL) {
1363				kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1364				pool->base.stream_enc[i]->vpg = NULL;
1365			}
1366			if (pool->base.stream_enc[i]->afmt != NULL) {
1367				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1368				pool->base.stream_enc[i]->afmt = NULL;
1369			}
1370			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1371			pool->base.stream_enc[i] = NULL;
1372		}
1373	}
1374
1375	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1376		if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1377			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1378				kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1379				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1380			}
1381			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1382				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1383				pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1384			}
1385			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1386			pool->base.hpo_dp_stream_enc[i] = NULL;
1387		}
1388	}
1389
1390	for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1391		if (pool->base.hpo_dp_link_enc[i] != NULL) {
1392			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1393			pool->base.hpo_dp_link_enc[i] = NULL;
1394		}
1395	}
1396
1397	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1398		if (pool->base.dscs[i] != NULL)
1399			dcn401_dsc_destroy(&pool->base.dscs[i]);
1400	}
1401
1402	if (pool->base.mpc != NULL) {
1403		kfree(TO_DCN20_MPC(pool->base.mpc));
1404		pool->base.mpc = NULL;
1405	}
1406	if (pool->base.hubbub != NULL) {
1407		kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1408		pool->base.hubbub = NULL;
1409	}
1410	for (i = 0; i < pool->base.pipe_count; i++) {
1411		if (pool->base.dpps[i] != NULL)
1412			dcn401_dpp_destroy(&pool->base.dpps[i]);
1413
1414		if (pool->base.ipps[i] != NULL)
1415			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1416
1417		if (pool->base.hubps[i] != NULL) {
1418			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1419			pool->base.hubps[i] = NULL;
1420		}
1421
1422		if (pool->base.irqs != NULL) {
1423			dal_irq_service_destroy(&pool->base.irqs);
1424		}
1425	}
1426
1427	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1428		if (pool->base.engines[i] != NULL)
1429			dce110_engine_destroy(&pool->base.engines[i]);
1430		if (pool->base.hw_i2cs[i] != NULL) {
1431			kfree(pool->base.hw_i2cs[i]);
1432			pool->base.hw_i2cs[i] = NULL;
1433		}
1434		if (pool->base.sw_i2cs[i] != NULL) {
1435			kfree(pool->base.sw_i2cs[i]);
1436			pool->base.sw_i2cs[i] = NULL;
1437		}
1438	}
1439
1440	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1441		if (pool->base.opps[i] != NULL)
1442			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1443	}
1444
1445	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1446		if (pool->base.timing_generators[i] != NULL)	{
1447			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1448			pool->base.timing_generators[i] = NULL;
1449		}
1450	}
1451
1452	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1453		if (pool->base.dwbc[i] != NULL) {
1454			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1455			pool->base.dwbc[i] = NULL;
1456		}
1457		if (pool->base.mcif_wb[i] != NULL) {
1458			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1459			pool->base.mcif_wb[i] = NULL;
1460		}
1461	}
1462
1463	for (i = 0; i < pool->base.audio_count; i++) {
1464		if (pool->base.audios[i])
1465			dce_aud_destroy(&pool->base.audios[i]);
1466	}
1467
1468	for (i = 0; i < pool->base.clk_src_count; i++) {
1469		if (pool->base.clock_sources[i] != NULL) {
1470			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1471			pool->base.clock_sources[i] = NULL;
1472		}
1473	}
1474
1475	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1476		if (pool->base.mpc_lut[i] != NULL) {
1477			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1478			pool->base.mpc_lut[i] = NULL;
1479		}
1480		if (pool->base.mpc_shaper[i] != NULL) {
1481			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1482			pool->base.mpc_shaper[i] = NULL;
1483		}
1484	}
1485
1486	if (pool->base.dp_clock_source != NULL) {
1487		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1488		pool->base.dp_clock_source = NULL;
1489	}
1490
1491	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1492		if (pool->base.multiple_abms[i] != NULL)
1493			dce_abm_destroy(&pool->base.multiple_abms[i]);
1494	}
1495
1496	if (pool->base.psr != NULL)
1497		dmub_psr_destroy(&pool->base.psr);
1498
1499	if (pool->base.dccg != NULL)
1500		dcn_dccg_destroy(&pool->base.dccg);
1501
1502	if (pool->base.oem_device != NULL) {
1503		struct dc *dc = pool->base.oem_device->ctx->dc;
1504
1505		dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1506	}
1507}
1508
1509
1510static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1511{
1512	int i;
1513	uint32_t dwb_count = pool->res_cap->num_dwb;
1514
1515	for (i = 0; i < dwb_count; i++) {
1516		struct dcn30_dwbc *dwbc401 = kzalloc(sizeof(struct dcn30_dwbc),
1517						    GFP_KERNEL);
1518
1519		if (!dwbc401) {
1520			dm_error("DC: failed to create dwbc401!\n");
1521			return false;
1522		}
1523
1524
1525#undef REG_STRUCT
1526#define REG_STRUCT dwbc401_regs
1527		dwbc_regs_dcn401_init(0);
1528
1529		dcn30_dwbc_construct(dwbc401, ctx,
1530				&dwbc401_regs[i],
1531				&dwbc401_shift,
1532				&dwbc401_mask,
1533				i);
1534
1535		pool->dwbc[i] = &dwbc401->base;
1536
1537	}
1538	return true;
1539}
1540
1541static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1542{
1543	int i;
1544	uint32_t dwb_count = pool->res_cap->num_dwb;
1545
1546	for (i = 0; i < dwb_count; i++) {
1547		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1548						    GFP_KERNEL);
1549
1550		if (!mcif_wb30) {
1551			dm_error("DC: failed to create mcif_wb30!\n");
1552			return false;
1553		}
1554
1555#undef REG_STRUCT
1556#define REG_STRUCT mcif_wb30_regs
1557		mcif_wb_regs_dcn3_init(0);
1558
1559		dcn32_mmhubbub_construct(mcif_wb30, ctx,
1560				&mcif_wb30_regs[i],
1561				&mcif_wb30_shift,
1562				&mcif_wb30_mask,
1563				i);
1564
1565		pool->mcif_wb[i] = &mcif_wb30->base;
1566	}
1567	return true;
1568}
1569
1570static struct display_stream_compressor *dcn401_dsc_create(
1571	struct dc_context *ctx, uint32_t inst)
1572{
1573	struct dcn401_dsc *dsc =
1574		kzalloc(sizeof(struct dcn401_dsc), GFP_KERNEL);
1575
1576	if (!dsc) {
1577		BREAK_TO_DEBUGGER();
1578		return NULL;
1579	}
1580
1581#undef REG_STRUCT
1582#define REG_STRUCT dsc_regs
1583	dsc_regs_init(0),
1584	dsc_regs_init(1),
1585	dsc_regs_init(2),
1586	dsc_regs_init(3);
1587
1588	dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1589	dsc401_set_fgcg(dsc,
1590			       ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1591
1592	//dsc->max_image_width = 6016;
1593	dsc->max_image_width = 5760;
1594
1595	return &dsc->base;
1596}
1597
1598static void dcn401_destroy_resource_pool(struct resource_pool **pool)
1599{
1600	struct dcn401_resource_pool *dcn401_pool = TO_DCN401_RES_POOL(*pool);
1601
1602	dcn401_resource_destruct(dcn401_pool);
1603	kfree(dcn401_pool);
1604	*pool = NULL;
1605}
1606
1607static struct dc_cap_funcs cap_funcs = {
1608	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
1609	.get_subvp_en = dcn32_subvp_in_use,
1610};
1611
1612static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1613{
1614	/* re-calculate the available MALL size if required */
1615	if (bw_params->num_channels > 0) {
1616		dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
1617			dc, bw_params->num_channels) *
1618			dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1619		dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1620	}
1621
1622	DC_FP_START();
1623
1624	if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
1625		dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1626
1627	if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
1628		dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
1629
1630	DC_FP_END();
1631}
1632
1633enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1634{
1635	plane_state->tiling_info.gfxversion = DcGfxAddr3;
1636	plane_state->tiling_info.gfx_addr3.swizzle = DC_ADDR3_SW_64KB_2D;
1637	return DC_OK;
1638}
1639
1640enum dc_status dcn401_validate_bandwidth(struct dc *dc,
1641		struct dc_state *context,
1642		enum dc_validate_mode validate_mode)
1643{
1644	unsigned int i;
1645	enum dc_status status = DC_OK;
1646	const struct dc_stream_state *stream;
1647
1648	/* reset cursor limitations on subvp */
1649	for (i = 0; i < context->stream_count; i++) {
1650		stream = context->streams[i];
1651
1652		if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) {
1653			dc_state_set_stream_cursor_subvp_limit(stream, context, false);
1654		}
1655	}
1656
1657	if (dc->debug.using_dml2)
1658		status = dml2_validate(dc, context,
1659				context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1660				validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1661
1662	if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) {
1663		/* check new stream configuration still supports cursor if subvp used */
1664		for (i = 0; i < context->stream_count; i++) {
1665			stream = context->streams[i];
1666
1667			if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM &&
1668					stream->cursor_position.enable &&
1669					!dc_stream_check_cursor_attributes(stream, context, &stream->cursor_attributes))	{
1670				/* hw cursor cannot be supported with subvp active, so disable subvp for now */
1671				dc_state_set_stream_cursor_subvp_limit(stream, context, true);
1672				status = DC_FAIL_HW_CURSOR_SUPPORT;
1673			}
1674		}
1675	}
1676
1677	if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) {
1678		/* attempt to validate again with subvp disabled due to cursor */
1679		if (dc->debug.using_dml2)
1680			status = dml2_validate(dc, context,
1681					context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1682					validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1683	}
1684
1685	return status;
1686}
1687
1688void dcn401_prepare_mcache_programming(struct dc *dc,
1689		struct dc_state *context)
1690{
1691	if (dc->debug.using_dml21)
1692		dml2_prepare_mcache_programming(dc, context,
1693				context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);
1694}
1695
1696static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
1697{
1698	const struct dc_stream_state *stream = pipe_ctx->stream;
1699	struct dc_link *link = stream->link;
1700	struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
1701	struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;
1702
1703	pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1704
1705	if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)
1706		pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;
1707
1708	if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)
1709		link_enc = link_enc_cfg_get_link_enc(link);
1710	if (link_enc)
1711		pixel_clk_params->encoder_object_id = link_enc->id;
1712
1713	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1714	pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1715	/* TODO: un-hardcode*/
1716
1717	/* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1718
1719	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1720		LINK_RATE_REF_FREQ_IN_KHZ;
1721	pixel_clk_params->flags.ENABLE_SS = 0;
1722	pixel_clk_params->color_depth =
1723		stream->timing.display_color_depth;
1724	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1725	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1726
1727	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1728		pixel_clk_params->color_depth = COLOR_DEPTH_888;
1729
1730	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1731		pixel_clk_params->requested_pix_clk_100hz *= 2;
1732	if (dc_is_tmds_signal(stream->signal) &&
1733			stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1734		pixel_clk_params->requested_pix_clk_100hz /= 2;
1735
1736	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1737			pipe_ctx->clock_source,
1738			&pipe_ctx->stream_res.pix_clk_params,
1739			&pipe_ctx->pll_settings);
1740
1741	pixel_clk_params->dio_se_pix_per_cycle = 1;
1742	if (dc_is_tmds_signal(stream->signal) &&
1743			stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1744		pixel_clk_params->dio_se_pix_per_cycle = 2;
1745	} else if (dc_is_dp_signal(stream->signal)) {
1746		/* round up to nearest power of 2, or max at 8 pixels per cycle */
1747		if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1748			pixel_clk_params->dio_se_pix_per_cycle = 8;
1749		} else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1750			pixel_clk_params->dio_se_pix_per_cycle = 4;
1751		} else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1752			pixel_clk_params->dio_se_pix_per_cycle = 2;
1753		} else {
1754			pixel_clk_params->dio_se_pix_per_cycle = 1;
1755		}
1756	}
1757}
1758
1759static int dcn401_get_power_profile(const struct dc_state *context)
1760{
1761	int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
1762	int dpm_level = 0;
1763
1764	for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
1765		if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 ||
1766			uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1767			break;
1768		if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1769			dpm_level++;
1770	}
1771
1772	return dpm_level;
1773}
1774
1775static unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)
1776{
1777	return pipe_ctx->global_sync.dcn4x.vstartup_lines;
1778}
1779
1780static struct resource_funcs dcn401_res_pool_funcs = {
1781	.destroy = dcn401_destroy_resource_pool,
1782	.link_enc_create = dcn401_link_encoder_create,
1783	.link_enc_create_minimal = NULL,
1784	.panel_cntl_create = dcn32_panel_cntl_create,
1785	.validate_bandwidth = dcn401_validate_bandwidth,
1786	.calculate_wm_and_dlg = NULL,
1787	.populate_dml_pipes = NULL,
1788	.acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1789	.acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1790	.release_pipe = dcn20_release_pipe,
1791	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1792	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1793	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1794	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1795	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1796	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1797	.acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1798	.release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1799	.update_bw_bounding_box = dcn401_update_bw_bounding_box,
1800	.patch_unknown_plane_state = dcn401_patch_unknown_plane_state,
1801	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1802	.add_phantom_pipes = dcn32_add_phantom_pipes,
1803	.prepare_mcache_programming = dcn401_prepare_mcache_programming,
1804	.build_pipe_pix_clk_params = dcn401_build_pipe_pix_clk_params,
1805	.calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
1806	.get_power_profile = dcn401_get_power_profile,
1807	.get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe,
1808	.get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size
1809};
1810
1811static uint32_t read_pipe_fuses(struct dc_context *ctx)
1812{
1813	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1814	/* DCN401 support max 4 pipes */
1815	value = value & 0xf;
1816	return value;
1817}
1818
1819
1820static bool dcn401_resource_construct(
1821	uint8_t num_virtual_links,
1822	struct dc *dc,
1823	struct dcn401_resource_pool *pool)
1824{
1825	int i, j;
1826	struct dc_context *ctx = dc->ctx;
1827	struct irq_service_init_data init_data;
1828	struct ddc_service_init_data ddc_init_data = {0};
1829	uint32_t pipe_fuses = 0;
1830	uint32_t num_pipes  = 4;
1831
1832#undef REG_STRUCT
1833#define REG_STRUCT bios_regs
1834	bios_regs_init();
1835
1836#undef REG_STRUCT
1837#define REG_STRUCT clk_src_regs
1838	clk_src_regs_init(0, A),
1839	clk_src_regs_init(1, B),
1840	clk_src_regs_init(2, C),
1841	clk_src_regs_init(3, D);
1842
1843#undef REG_STRUCT
1844#define REG_STRUCT abm_regs
1845		abm_regs_init(0),
1846		abm_regs_init(1),
1847		abm_regs_init(2),
1848		abm_regs_init(3);
1849
1850#undef REG_STRUCT
1851#define REG_STRUCT dccg_regs
1852	dccg_regs_init();
1853
1854	ctx->dc_bios->regs = &bios_regs;
1855
1856	pool->base.res_cap = &res_cap_dcn4_01;
1857
1858	/* max number of pipes for ASIC before checking for pipe fuses */
1859	num_pipes  = pool->base.res_cap->num_timing_generator;
1860	pipe_fuses = read_pipe_fuses(ctx);
1861
1862	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1863		if (pipe_fuses & 1 << i)
1864			num_pipes--;
1865
1866	if (pipe_fuses & 1)
1867		ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
1868
1869	if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
1870		ASSERT(0); //Entire DCN is harvested!
1871
1872	pool->base.funcs = &dcn401_res_pool_funcs;
1873
1874	/*************************************************
1875	 *  Resource + asic cap harcoding                *
1876	 *************************************************/
1877	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1878	pool->base.timing_generator_count = num_pipes;
1879	pool->base.pipe_count = num_pipes;
1880	pool->base.mpcc_count = num_pipes;
1881	dc->caps.max_downscale_ratio = 600;
1882	dc->caps.i2c_speed_in_khz = 95;
1883	dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/
1884	/* used to set cursor pitch, so must be aligned to power of 2 (HW actually supported 78x78) */
1885	dc->caps.max_cursor_size = 64;
1886	dc->caps.max_buffered_cursor_size = 64;
1887	dc->caps.cursor_not_scaled = true;
1888	dc->caps.min_horizontal_blanking_period = 80;
1889	dc->caps.dmdata_alloc_size = 2048;
1890	dc->caps.mall_size_per_mem_channel = 4;
1891	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1892	dc->caps.cache_line_size = 64;
1893	dc->caps.cache_num_ways = 16;
1894
1895	/* Calculate the available MALL space */
1896	dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
1897		dc, dc->ctx->dc_bios->vram_info.num_chans) *
1898		dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1899	dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1900
1901	dc->caps.subvp_fw_processing_delay_us = 15;
1902	dc->caps.subvp_drr_max_vblank_margin_us = 40;
1903	dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
1904	dc->caps.subvp_swath_height_margin_lines = 16;
1905	dc->caps.subvp_pstate_allow_width_us = 20;
1906	dc->caps.subvp_vertical_int_margin_us = 30;
1907	dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
1908
1909	dc->caps.max_slave_planes = 3;
1910	dc->caps.max_slave_yuv_planes = 3;
1911	dc->caps.max_slave_rgb_planes = 3;
1912	dc->caps.post_blend_color_processing = true;
1913	dc->caps.force_dp_tps4_for_cp2520 = true;
1914	dc->caps.dp_hpo = true;
1915	dc->caps.dp_hdmi21_pcon_support = true;
1916	dc->caps.edp_dsc_support = true;
1917	dc->caps.extended_aux_timeout_support = true;
1918	dc->caps.dmcub_support = true;
1919	dc->caps.max_v_total = (1 << 15) - 1;
1920	dc->caps.vtotal_limited_by_fp2 = true;
1921
1922	if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))
1923		dc->caps.dcc_plane_width_limit = 7680;
1924
1925	/* Color pipeline capabilities */
1926	dc->caps.color.dpp.dcn_arch = 1;
1927	dc->caps.color.dpp.input_lut_shared = 0;
1928	dc->caps.color.dpp.icsc = 1;
1929	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1930	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1931	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1932	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1933	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1934	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1935	dc->caps.color.dpp.post_csc = 1;
1936	dc->caps.color.dpp.gamma_corr = 1;
1937	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1938
1939	dc->caps.color.dpp.hw_3d_lut = 0;
1940	dc->caps.color.dpp.ogam_ram = 0;
1941	// no OGAM ROM on DCN2 and later ASICs
1942	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1943	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1944	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1945	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1946	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1947	dc->caps.color.dpp.ocsc = 0;
1948
1949	dc->caps.color.mpc.gamut_remap = 1;
1950	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
1951	dc->caps.color.mpc.ogam_ram = 1;
1952	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1953	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1954	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1955	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1956	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1957	dc->caps.color.mpc.ocsc = 1;
1958	dc->caps.color.mpc.preblend = true;
1959	dc->config.use_spl = true;
1960	dc->config.prefer_easf = true;
1961
1962	dc->config.dcn_sharpness_range.sdr_rgb_min = 0;
1963	dc->config.dcn_sharpness_range.sdr_rgb_max = 1750;
1964	dc->config.dcn_sharpness_range.sdr_rgb_mid = 750;
1965	dc->config.dcn_sharpness_range.sdr_yuv_min = 0;
1966	dc->config.dcn_sharpness_range.sdr_yuv_max = 3500;
1967	dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500;
1968	dc->config.dcn_sharpness_range.hdr_rgb_min = 0;
1969	dc->config.dcn_sharpness_range.hdr_rgb_max = 2750;
1970	dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500;
1971
1972	dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0;
1973	dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250;
1974	dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;
1975	dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0;
1976	dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500;
1977	dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;
1978	dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0;
1979	dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750;
1980	dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;
1981
1982	dc->config.dc_mode_clk_limit_support = true;
1983	dc->config.enable_windowed_mpo_odm = true;
1984	dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */
1985
1986	/* read VBIOS LTTPR caps */
1987	{
1988		if (ctx->dc_bios->funcs->get_lttpr_caps) {
1989			enum bp_result bp_query_result;
1990			uint8_t is_vbios_lttpr_enable = 0;
1991
1992			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1993			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1994		}
1995
1996		/* interop bit is implicit */
1997		{
1998			dc->caps.vbios_lttpr_aware = true;
1999		}
2000	}
2001	dc->check_config = config_defaults;
2002
2003	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2004		dc->debug = debug_defaults_drv;
2005
2006	// Init the vm_helper
2007	if (dc->vm_helper)
2008		vm_helper_init(dc->vm_helper, 16);
2009
2010	/*************************************************
2011	 *  Create resources                             *
2012	 *************************************************/
2013
2014	/* Clock Sources for Pixel Clock*/
2015	pool->base.clock_sources[DCN401_CLK_SRC_PLL0] =
2016			dcn401_clock_source_create(ctx, ctx->dc_bios,
2017				CLOCK_SOURCE_COMBO_PHY_PLL0,
2018				&clk_src_regs[0], false);
2019	pool->base.clock_sources[DCN401_CLK_SRC_PLL1] =
2020			dcn401_clock_source_create(ctx, ctx->dc_bios,
2021				CLOCK_SOURCE_COMBO_PHY_PLL1,
2022				&clk_src_regs[1], false);
2023	pool->base.clock_sources[DCN401_CLK_SRC_PLL2] =
2024			dcn401_clock_source_create(ctx, ctx->dc_bios,
2025				CLOCK_SOURCE_COMBO_PHY_PLL2,
2026				&clk_src_regs[2], false);
2027	pool->base.clock_sources[DCN401_CLK_SRC_PLL3] =
2028			dcn401_clock_source_create(ctx, ctx->dc_bios,
2029				CLOCK_SOURCE_COMBO_PHY_PLL3,
2030				&clk_src_regs[3], false);
2031	// pool->base.clock_sources[DCN401_CLK_SRC_PLL4] =
2032	// 		dcn401_clock_source_create(ctx, ctx->dc_bios,
2033	// 			CLOCK_SOURCE_COMBO_PHY_PLL4,
2034	// 			&clk_src_regs[4], false);
2035
2036	pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL;
2037
2038	/* todo: not reuse phy_pll registers */
2039	pool->base.dp_clock_source =
2040			dcn401_clock_source_create(ctx, ctx->dc_bios,
2041				CLOCK_SOURCE_ID_DP_DTO,
2042				&clk_src_regs[0], true);
2043
2044	for (i = 0; i < pool->base.clk_src_count; i++) {
2045		if (pool->base.clock_sources[i] == NULL) {
2046			dm_error("DC: failed to create clock sources!\n");
2047			BREAK_TO_DEBUGGER();
2048			goto create_fail;
2049		}
2050	}
2051
2052	/* DCCG */
2053	pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2054	if (pool->base.dccg == NULL) {
2055		dm_error("DC: failed to create dccg!\n");
2056		BREAK_TO_DEBUGGER();
2057		goto create_fail;
2058	}
2059
2060	/* IRQ Service */
2061	init_data.ctx = dc->ctx;
2062	pool->base.irqs = dal_irq_service_dcn401_create(&init_data);
2063	if (!pool->base.irqs)
2064		goto create_fail;
2065
2066	/* HUBBUB */
2067	pool->base.hubbub = dcn401_hubbub_create(ctx);
2068	if (pool->base.hubbub == NULL) {
2069		BREAK_TO_DEBUGGER();
2070		dm_error("DC: failed to create hubbub!\n");
2071		goto create_fail;
2072	}
2073
2074	/* HUBPs, DPPs, OPPs, TGs, ABMs */
2075	for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2076
2077		/* if pipe is disabled, skip instance of HW pipe,
2078		 * i.e, skip ASIC register instance
2079		 */
2080		if (pipe_fuses & 1 << i)
2081			continue;
2082
2083		pool->base.hubps[j] = dcn401_hubp_create(ctx, i);
2084		if (pool->base.hubps[j] == NULL) {
2085			BREAK_TO_DEBUGGER();
2086			dm_error(
2087				"DC: failed to create hubps!\n");
2088			goto create_fail;
2089		}
2090
2091		pool->base.dpps[j] = dcn401_dpp_create(ctx, i);
2092		if (pool->base.dpps[j] == NULL) {
2093			BREAK_TO_DEBUGGER();
2094			dm_error(
2095				"DC: failed to create dpps!\n");
2096			goto create_fail;
2097		}
2098
2099		pool->base.opps[j] = dcn401_opp_create(ctx, i);
2100		if (pool->base.opps[j] == NULL) {
2101			BREAK_TO_DEBUGGER();
2102			dm_error(
2103				"DC: failed to create output pixel processor!\n");
2104			goto create_fail;
2105		}
2106
2107		pool->base.timing_generators[j] = dcn401_timing_generator_create(
2108				ctx, i);
2109		if (pool->base.timing_generators[j] == NULL) {
2110			BREAK_TO_DEBUGGER();
2111			dm_error("DC: failed to create tg!\n");
2112			goto create_fail;
2113		}
2114
2115		pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2116				&abm_regs[i],
2117				&abm_shift,
2118				&abm_mask);
2119		if (pool->base.multiple_abms[j] == NULL) {
2120			dm_error("DC: failed to create abm for pipe %d!\n", i);
2121			BREAK_TO_DEBUGGER();
2122			goto create_fail;
2123		}
2124
2125		/* index for resource pool arrays for next valid pipe */
2126		j++;
2127	}
2128
2129	/* PSR */
2130	pool->base.psr = dmub_psr_create(ctx);
2131	if (pool->base.psr == NULL) {
2132		dm_error("DC: failed to create psr obj!\n");
2133		BREAK_TO_DEBUGGER();
2134		goto create_fail;
2135	}
2136
2137	/* MPCCs */
2138	pool->base.mpc = dcn401_mpc_create(ctx,  pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2139	if (pool->base.mpc == NULL) {
2140		BREAK_TO_DEBUGGER();
2141		dm_error("DC: failed to create mpc!\n");
2142		goto create_fail;
2143	}
2144
2145	/* DSCs */
2146	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2147		pool->base.dscs[i] = dcn401_dsc_create(ctx, i);
2148		if (pool->base.dscs[i] == NULL) {
2149			BREAK_TO_DEBUGGER();
2150			dm_error("DC: failed to create display stream compressor %d!\n", i);
2151			goto create_fail;
2152		}
2153	}
2154
2155	/* DWB */
2156	if (!dcn401_dwbc_create(ctx, &pool->base)) {
2157		BREAK_TO_DEBUGGER();
2158		dm_error("DC: failed to create dwbc!\n");
2159		goto create_fail;
2160	}
2161
2162	/* MMHUBBUB */
2163	if (!dcn401_mmhubbub_create(ctx, &pool->base)) {
2164		BREAK_TO_DEBUGGER();
2165		dm_error("DC: failed to create mcif_wb!\n");
2166		goto create_fail;
2167	}
2168
2169	/* AUX and I2C */
2170	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2171		pool->base.engines[i] = dcn401_aux_engine_create(ctx, i);
2172		if (pool->base.engines[i] == NULL) {
2173			BREAK_TO_DEBUGGER();
2174			dm_error(
2175				"DC:failed to create aux engine!!\n");
2176			goto create_fail;
2177		}
2178		pool->base.hw_i2cs[i] = dcn401_i2c_hw_create(ctx, i);
2179		if (pool->base.hw_i2cs[i] == NULL) {
2180			BREAK_TO_DEBUGGER();
2181			dm_error(
2182				"DC:failed to create hw i2c!!\n");
2183			goto create_fail;
2184		}
2185		pool->base.sw_i2cs[i] = NULL;
2186	}
2187
2188	/* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2189	if (!resource_construct(num_virtual_links, dc, &pool->base,
2190			&res_create_funcs))
2191		goto create_fail;
2192
2193	/* HW Sequencer init functions and Plane caps */
2194	dcn401_hw_sequencer_init_functions(dc);
2195
2196	dc->caps.max_planes =  pool->base.pipe_count;
2197
2198	for (i = 0; i < dc->caps.max_planes; ++i)
2199		dc->caps.planes[i] = plane_cap;
2200
2201	dc->caps.max_odm_combine_factor = 4;
2202
2203	dc->cap_funcs = cap_funcs;
2204
2205	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2206		ddc_init_data.ctx = dc->ctx;
2207		ddc_init_data.link = NULL;
2208		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2209		ddc_init_data.id.enum_id = 0;
2210		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2211		pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2212	} else {
2213		pool->base.oem_device = NULL;
2214	}
2215
2216	//For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided
2217	if (dc->config.sdpif_request_limit_words_per_umc == 0)
2218		dc->config.sdpif_request_limit_words_per_umc = 16;
2219
2220	dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2221	dc->dml2_options.use_native_soc_bb_construction = true;
2222	dc->dml2_options.minimize_dispclk_using_odm = true;
2223	dc->dml2_options.map_dc_pipes_with_callbacks = true;
2224	dc->dml2_options.force_tdlut_enable = true;
2225
2226	resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2227	dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2228	dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2229	dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2230
2231	dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2232	dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2233	dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2234	dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2235
2236	dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2237	dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2238
2239	dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2240	dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2241	dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2242	dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2243	dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2244	dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2245	dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2246
2247	dc->dml2_options.max_segments_per_hubp = 20;
2248	dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;
2249
2250	/* SPL */
2251	dc->caps.scl_caps.sharpener_support = true;
2252
2253	/* init DC limited DML2 options */
2254	memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
2255	dc->dml2_dc_power_options.use_clock_dc_limits = true;
2256
2257	return true;
2258
2259create_fail:
2260
2261	dcn401_resource_destruct(pool);
2262
2263	return false;
2264}
2265
2266struct resource_pool *dcn401_create_resource_pool(
2267		const struct dc_init_data *init_data,
2268		struct dc *dc)
2269{
2270	struct dcn401_resource_pool *pool =
2271		kzalloc(sizeof(struct dcn401_resource_pool), GFP_KERNEL);
2272
2273	if (!pool)
2274		return NULL;
2275
2276	if (dcn401_resource_construct(init_data->num_virtual_links, dc, pool))
2277		return &pool->base;
2278
2279	BREAK_TO_DEBUGGER();
2280	kfree(pool);
2281	return NULL;
2282}
~/ Read-only file preview.