dcn36_resource.h

 1/* SPDX-License-Identifier: MIT */
 2/* Copyright 2025 Advanced Micro Devices, Inc. */
 3
 4#ifndef _DCN36_RESOURCE_H_
 5#define _DCN36_RESOURCE_H_
 6
 7#include "core_types.h"
 8
 9extern struct _vcs_dpi_ip_params_st dcn3_6_ip;
10extern struct _vcs_dpi_soc_bounding_box_st dcn3_6_soc;
11
12#define TO_DCN36_RES_POOL(pool)\
13	container_of(pool, struct dcn36_resource_pool, base)
14
15struct dcn36_resource_pool {
16	struct resource_pool base;
17};
18
19struct resource_pool *dcn36_create_resource_pool(
20		const struct dc_init_data *init_data,
21		struct dc *dc);
22
23#define HWSEQ_DCN36_REG_LIST()\
24	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
25	SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
26	SR(DIO_MEM_PWR_CTRL), \
27	SR(ODM_MEM_PWR_CTRL3), \
28	SR(MMHUBBUB_MEM_PWR_CNTL), \
29	SR(DCCG_GATE_DISABLE_CNTL), \
30	SR(DCCG_GATE_DISABLE_CNTL2), \
31	SR(DCCG_GATE_DISABLE_CNTL4), \
32	SR(DCCG_GATE_DISABLE_CNTL5), \
33	SR(DCFCLK_CNTL),\
34	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
35	SRII(PIXEL_RATE_CNTL, OTG, 0), \
36	SRII(PIXEL_RATE_CNTL, OTG, 1),\
37	SRII(PIXEL_RATE_CNTL, OTG, 2),\
38	SRII(PIXEL_RATE_CNTL, OTG, 3),\
39	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
40	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
41	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
42	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
43	SR(MICROSECOND_TIME_BASE_DIV), \
44	SR(MILLISECOND_TIME_BASE_DIV), \
45	SR(DISPCLK_FREQ_CHANGE_CNTL), \
46	SR(RBBMIF_TIMEOUT_DIS), \
47	SR(RBBMIF_TIMEOUT_DIS_2), \
48	SR(DCHUBBUB_CRC_CTRL), \
49	SR(DPP_TOP0_DPP_CRC_CTRL), \
50	SR(MPC_CRC_CTRL), \
51	SR(DOMAIN0_PG_CONFIG), \
52	SR(DOMAIN1_PG_CONFIG), \
53	SR(DOMAIN2_PG_CONFIG), \
54	SR(DOMAIN3_PG_CONFIG), \
55	SR(DOMAIN16_PG_CONFIG), \
56	SR(DOMAIN17_PG_CONFIG), \
57	SR(DOMAIN18_PG_CONFIG), \
58	SR(DOMAIN19_PG_CONFIG), \
59	SR(DOMAIN0_PG_STATUS), \
60	SR(DOMAIN1_PG_STATUS), \
61	SR(DOMAIN2_PG_STATUS), \
62	SR(DOMAIN3_PG_STATUS), \
63	SR(DOMAIN16_PG_STATUS), \
64	SR(DOMAIN17_PG_STATUS), \
65	SR(DOMAIN18_PG_STATUS), \
66	SR(DOMAIN19_PG_STATUS), \
67	SR(DC_IP_REQUEST_CNTL), \
68	SR(AZALIA_AUDIO_DTO), \
69	SR(AZALIA_CONTROLLER_CLOCK_GATING), \
70	SR(HPO_TOP_HW_CONTROL),\
71	SR(DMU_CLK_CNTL)
72
73#endif /* _DCN36_RESOURCE_H_ */