dcn36_resource.c

   1/* SPDX-License-Identifier: MIT */
   2/* Copyright 2025 Advanced Micro Devices, Inc. */
   3
   4#include "dm_services.h"
   5#include "dc.h"
   6
   7#include "dcn31/dcn31_init.h"
   8#include "dcn35/dcn35_init.h"
   9#include "dcn36/dcn36_resource.h"
  10
  11#include "resource.h"
  12#include "include/irq_service_interface.h"
  13#include "dcn36_resource.h"
  14#include "dml2_0/dml2_wrapper.h"
  15
  16#include "dcn20/dcn20_resource.h"
  17#include "dcn30/dcn30_resource.h"
  18#include "dcn31/dcn31_resource.h"
  19#include "dcn32/dcn32_resource.h"
  20#include "dcn35/dcn35_resource.h"
  21
  22#include "dcn10/dcn10_ipp.h"
  23#include "dcn30/dcn30_hubbub.h"
  24#include "dcn31/dcn31_hubbub.h"
  25#include "dcn35/dcn35_hubbub.h"
  26#include "dcn32/dcn32_mpc.h"
  27#include "dcn35/dcn35_hubp.h"
  28#include "irq/dcn36/irq_service_dcn36.h"
  29#include "dcn35/dcn35_dpp.h"
  30#include "dcn35/dcn35_optc.h"
  31#include "dcn20/dcn20_hwseq.h"
  32#include "dcn30/dcn30_hwseq.h"
  33#include "dce110/dce110_hwseq.h"
  34#include "dcn35/dcn35_opp.h"
  35#include "dcn35/dcn35_dsc.h"
  36#include "dcn30/dcn30_vpg.h"
  37#include "dcn30/dcn30_afmt.h"
  38#include "dcn31/dcn31_dio_link_encoder.h"
  39#include "dcn35/dcn35_dio_stream_encoder.h"
  40#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  41#include "dcn31/dcn31_hpo_dp_link_encoder.h"
  42#include "dcn32/dcn32_hpo_dp_link_encoder.h"
  43#include "link_service.h"
  44#include "dcn31/dcn31_apg.h"
  45#include "dcn32/dcn32_dio_link_encoder.h"
  46#include "dcn31/dcn31_vpg.h"
  47#include "dcn31/dcn31_afmt.h"
  48#include "dce/dce_clock_source.h"
  49#include "dce/dce_audio.h"
  50#include "dce/dce_hwseq.h"
  51#include "clk_mgr.h"
  52#include "virtual/virtual_stream_encoder.h"
  53#include "dce110/dce110_resource.h"
  54#include "dml/display_mode_vba.h"
  55#include "dcn35/dcn35_dccg.h"
  56#include "dcn35/dcn35_pg_cntl.h"
  57#include "dcn10/dcn10_resource.h"
  58#include "dcn31/dcn31_panel_cntl.h"
  59#include "dcn35/dcn35_hwseq.h"
  60#include "dcn35/dcn35_dio_link_encoder.h"
  61#include "dml/dcn31/dcn31_fpu.h" /*todo*/
  62#include "dml/dcn35/dcn35_fpu.h"
  63#include "dcn35/dcn35_dwb.h"
  64#include "dcn35/dcn35_mmhubbub.h"
  65
  66#include "dcn/dcn_3_6_0_offset.h"
  67#include "dcn/dcn_3_6_0_sh_mask.h"
  68
  69#define regBIF_BX2_BIOS_SCRATCH_2                                             0x2ffc004e
  70#define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX                                    5
  71
  72#define regBIF_BX2_BIOS_SCRATCH_3                                             0x2ffc004f
  73#define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX                                    5
  74
  75#define regBIF_BX2_BIOS_SCRATCH_6                                             0x2ffc0052
  76#define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX                                    5
  77
  78#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                   0x0
  79#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                     0x0000000FL
  80
  81#include "reg_helper.h"
  82#include "dce/dmub_abm.h"
  83#include "dce/dmub_psr.h"
  84#include "dce/dmub_replay.h"
  85#include "dce/dce_aux.h"
  86#include "dce/dce_i2c.h"
  87#include "dml/dcn31/display_mode_vba_31.h" /*temp*/
  88#include "vm_helper.h"
  89#include "dcn20/dcn20_vmid.h"
  90
  91#include "dc_state_priv.h"
  92
  93#include "link_enc_cfg.h"
  94#define DC_LOGGER_INIT(logger)
  95
  96enum dcn36_clk_src_array_id {
  97	DCN36_CLK_SRC_PLL0,
  98	DCN36_CLK_SRC_PLL1,
  99	DCN36_CLK_SRC_PLL2,
 100	DCN36_CLK_SRC_PLL3,
 101	DCN36_CLK_SRC_PLL4,
 102	DCN36_CLK_SRC_TOTAL
 103};
 104
 105/* begin *********************
 106 * macros to expend register list macro defined in HW object header file
 107 */
 108
 109/* DCN */
 110/* TODO awful hack. fixup dcn20_dwb.h */
 111#undef BASE_INNER
 112#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
 113
 114#define BASE(seg) BASE_INNER(seg)
 115
 116#define SR(reg_name)\
 117		REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 118					reg ## reg_name
 119
 120#define SR_ARR(reg_name, id) \
 121	REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 122
 123#define SR_ARR_INIT(reg_name, id, value) \
 124	REG_STRUCT[id].reg_name = value
 125
 126#define SRI(reg_name, block, id)\
 127	REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 128					reg ## block ## id ## _ ## reg_name
 129
 130#define SRI_ARR(reg_name, block, id)\
 131	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 132		reg ## block ## id ## _ ## reg_name
 133
 134#define SR_ARR_I2C(reg_name, id) \
 135	REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 136
 137#define SRI_ARR_I2C(reg_name, block, id)\
 138	REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 139		reg ## block ## id ## _ ## reg_name
 140
 141#define SRI_ARR_ALPHABET(reg_name, block, index, id)\
 142	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 143		reg ## block ## id ## _ ## reg_name
 144
 145#define SRI2(reg_name, block, id)\
 146	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 147					reg ## reg_name
 148
 149#define SRI2_ARR(reg_name, block, id)\
 150	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +	\
 151		reg ## reg_name
 152
 153#define SRIR(var_name, reg_name, block, id)\
 154	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 155					reg ## block ## id ## _ ## reg_name
 156
 157#define SRII(reg_name, block, id)\
 158	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 159					reg ## block ## id ## _ ## reg_name
 160
 161#define SRII_ARR_2(reg_name, block, id, inst)\
 162	REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 163		reg ## block ## id ## _ ## reg_name
 164
 165#define SRII_MPC_RMU(reg_name, block, id)\
 166	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 167					reg ## block ## id ## _ ## reg_name
 168
 169#define SRII_DWB(reg_name, temp_name, block, id)\
 170	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 171		reg ## block ## id ## _ ## temp_name
 172
 173#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
 174	.field_name = reg_name ## __ ## field_name ## post_fix
 175
 176#define DCCG_SRII(reg_name, block, id)\
 177	REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 178		reg ## block ## id ## _ ## reg_name
 179
 180#define VUPDATE_SRII(reg_name, block, id)\
 181	REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 182		reg ## reg_name ## _ ## block ## id
 183
 184/* NBIO */
 185#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
 186
 187#define NBIO_BASE(seg) \
 188	NBIO_BASE_INNER(seg)
 189
 190#define NBIO_SR(reg_name)\
 191	REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 192				regBIF_BX2_ ## reg_name
 193
 194#define NBIO_SR_ARR(reg_name, id)\
 195	REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 196		regBIF_BX2_ ## reg_name
 197
 198#define bios_regs_init() \
 199		( \
 200		NBIO_SR(BIOS_SCRATCH_3),\
 201		NBIO_SR(BIOS_SCRATCH_6)\
 202		)
 203
 204static struct bios_registers bios_regs;
 205
 206#define clk_src_regs_init(index, pllid)\
 207	CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
 208
 209static struct dce110_clk_src_regs clk_src_regs[5];
 210
 211static const struct dce110_clk_src_shift cs_shift = {
 212		CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
 213};
 214
 215static const struct dce110_clk_src_mask cs_mask = {
 216		CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
 217};
 218
 219#define abm_regs_init(id)\
 220		ABM_DCN32_REG_LIST_RI(id)
 221
 222static struct dce_abm_registers abm_regs[4];
 223
 224static const struct dce_abm_shift abm_shift = {
 225		ABM_MASK_SH_LIST_DCN35(__SHIFT)
 226};
 227
 228static const struct dce_abm_mask abm_mask = {
 229		ABM_MASK_SH_LIST_DCN35(_MASK)
 230};
 231
 232#define audio_regs_init(id)\
 233		AUD_COMMON_REG_LIST_RI(id)
 234
 235static struct dce_audio_registers audio_regs[7];
 236
 237
 238#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 239		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 240		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 241		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 242
 243static const struct dce_audio_shift audio_shift = {
 244		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 245};
 246
 247static const struct dce_audio_mask audio_mask = {
 248		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 249};
 250
 251#define vpg_regs_init(id)\
 252	VPG_DCN31_REG_LIST_RI(id)
 253
 254static struct dcn31_vpg_registers vpg_regs[10];
 255
 256static const struct dcn31_vpg_shift vpg_shift = {
 257	DCN31_VPG_MASK_SH_LIST(__SHIFT)
 258};
 259
 260static const struct dcn31_vpg_mask vpg_mask = {
 261	DCN31_VPG_MASK_SH_LIST(_MASK)
 262};
 263
 264#define afmt_regs_init(id)\
 265	AFMT_DCN31_REG_LIST_RI(id)
 266
 267static struct dcn31_afmt_registers afmt_regs[6];
 268
 269static const struct dcn31_afmt_shift afmt_shift = {
 270	DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 271};
 272
 273static const struct dcn31_afmt_mask afmt_mask = {
 274	DCN31_AFMT_MASK_SH_LIST(_MASK)
 275};
 276
 277#define apg_regs_init(id)\
 278	APG_DCN31_REG_LIST_RI(id)
 279
 280static struct dcn31_apg_registers apg_regs[4];
 281
 282static const struct dcn31_apg_shift apg_shift = {
 283	DCN31_APG_MASK_SH_LIST(__SHIFT)
 284};
 285
 286static const struct dcn31_apg_mask apg_mask = {
 287	DCN31_APG_MASK_SH_LIST(_MASK)
 288};
 289
 290#define stream_enc_regs_init(id)\
 291	SE_DCN35_REG_LIST_RI(id)
 292
 293static struct dcn10_stream_enc_registers stream_enc_regs[5];
 294
 295static const struct dcn10_stream_encoder_shift se_shift = {
 296		SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 297};
 298
 299static const struct dcn10_stream_encoder_mask se_mask = {
 300		SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
 301};
 302
 303#define aux_regs_init(id)\
 304	DCN2_AUX_REG_LIST_RI(id)
 305
 306static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
 307
 308#define hpd_regs_init(id)\
 309	HPD_REG_LIST_RI(id)
 310
 311static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
 312
 313
 314static const struct dce110_aux_registers_shift aux_shift = {
 315	DCN_AUX_MASK_SH_LIST(__SHIFT)
 316};
 317
 318static const struct dce110_aux_registers_mask aux_mask = {
 319	DCN_AUX_MASK_SH_LIST(_MASK)
 320};
 321
 322#define link_regs_init(id, phyid)\
 323	( \
 324	LE_DCN35_REG_LIST_RI(id), \
 325	UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
 326	)
 327
 328static struct dcn10_link_enc_registers link_enc_regs[5];
 329
 330static const struct dcn10_link_enc_shift le_shift = {
 331	LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
 332	//DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 333};
 334
 335static const struct dcn10_link_enc_mask le_mask = {
 336	LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
 337	//DPCS_DCN31_MASK_SH_LIST(_MASK)
 338};
 339
 340#define hpo_dp_stream_encoder_reg_init(id)\
 341	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
 342
 343static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
 344
 345static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 346	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 347};
 348
 349static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 350	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 351};
 352
 353#define hpo_dp_link_encoder_reg_init(id)\
 354	DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
 355
 356static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
 357
 358static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 359	DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
 360};
 361
 362static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 363	DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
 364};
 365
 366#define dpp_regs_init(id)\
 367	DPP_REG_LIST_DCN35_RI(id)
 368
 369static struct dcn3_dpp_registers dpp_regs[4];
 370
 371static const struct dcn35_dpp_shift tf_shift = {
 372		DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
 373};
 374
 375static const struct dcn35_dpp_mask tf_mask = {
 376		DPP_REG_LIST_SH_MASK_DCN35(_MASK)
 377};
 378
 379#define opp_regs_init(id)\
 380	OPP_REG_LIST_DCN35_RI(id)
 381
 382static struct dcn35_opp_registers opp_regs[4];
 383
 384static const struct dcn35_opp_shift opp_shift = {
 385	OPP_MASK_SH_LIST_DCN35(__SHIFT)
 386};
 387
 388static const struct dcn35_opp_mask opp_mask = {
 389	OPP_MASK_SH_LIST_DCN35(_MASK)
 390};
 391
 392#define aux_engine_regs_init(id)\
 393	( \
 394	AUX_COMMON_REG_LIST0_RI(id), \
 395	SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
 396	SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
 397	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
 398	)
 399
 400static struct dce110_aux_registers aux_engine_regs[5];
 401
 402#define dwbc_regs_dcn3_init(id)\
 403	DWBC_COMMON_REG_LIST_DCN30_RI(id)
 404
 405static struct dcn30_dwbc_registers dwbc35_regs[1];
 406
 407static const struct dcn35_dwbc_shift dwbc35_shift = {
 408	DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 409};
 410
 411static const struct dcn35_dwbc_mask dwbc35_mask = {
 412	DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
 413};
 414
 415#define mcif_wb_regs_dcn3_init(id)\
 416	MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
 417
 418static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
 419
 420static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
 421	MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 422};
 423
 424static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
 425	MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 426};
 427
 428#define dsc_regsDCN35_init(id)\
 429	DSC_REG_LIST_DCN20_RI(id)
 430
 431static struct dcn20_dsc_registers dsc_regs[4];
 432
 433static const struct dcn35_dsc_shift dsc_shift = {
 434	DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
 435};
 436
 437static const struct dcn35_dsc_mask dsc_mask = {
 438	DSC_REG_LIST_SH_MASK_DCN35(_MASK)
 439};
 440
 441static struct dcn30_mpc_registers mpc_regs;
 442
 443#define dcn_mpc_regs_init() \
 444	MPC_REG_LIST_DCN3_2_RI(0),\
 445	MPC_REG_LIST_DCN3_2_RI(1),\
 446	MPC_REG_LIST_DCN3_2_RI(2),\
 447	MPC_REG_LIST_DCN3_2_RI(3),\
 448	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
 449	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
 450	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
 451	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
 452	MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
 453
 454static const struct dcn30_mpc_shift mpc_shift = {
 455	MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 456};
 457
 458static const struct dcn30_mpc_mask mpc_mask = {
 459	MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
 460};
 461
 462#define optc_regs_init(id)\
 463	OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
 464
 465static struct dcn_optc_registers optc_regs[4];
 466
 467static const struct dcn_optc_shift optc_shift = {
 468	OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 469};
 470
 471static const struct dcn_optc_mask optc_mask = {
 472	OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 473};
 474
 475#define hubp_regs_init(id)\
 476	HUBP_REG_LIST_DCN30_RI(id)
 477
 478static struct dcn_hubp2_registers hubp_regs[4];
 479
 480
 481static const struct dcn35_hubp2_shift hubp_shift = {
 482		HUBP_MASK_SH_LIST_DCN35(__SHIFT)
 483};
 484
 485static const struct dcn35_hubp2_mask hubp_mask = {
 486		HUBP_MASK_SH_LIST_DCN35(_MASK)
 487};
 488
 489static struct dcn_hubbub_registers hubbub_reg;
 490
 491#define hubbub_reg_init()\
 492		HUBBUB_REG_LIST_DCN35(0)
 493
 494static const struct dcn_hubbub_shift hubbub_shift = {
 495		HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
 496};
 497
 498static const struct dcn_hubbub_mask hubbub_mask = {
 499		HUBBUB_MASK_SH_LIST_DCN35(_MASK)
 500};
 501
 502static struct dccg_registers dccg_regs;
 503
 504#define dccg_regs_init()\
 505	DCCG_REG_LIST_DCN35()
 506
 507static const struct dccg_shift dccg_shift = {
 508		DCCG_MASK_SH_LIST_DCN35(__SHIFT)
 509};
 510
 511static const struct dccg_mask dccg_mask = {
 512		DCCG_MASK_SH_LIST_DCN35(_MASK)
 513};
 514
 515static struct pg_cntl_registers pg_cntl_regs;
 516
 517#define pg_cntl_dcn35_regs_init() \
 518	PG_CNTL_REG_LIST_DCN35()
 519
 520static const struct pg_cntl_shift pg_cntl_shift = {
 521		PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
 522};
 523
 524static const struct pg_cntl_mask pg_cntl_mask = {
 525		PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
 526};
 527
 528#define SRII2(reg_name_pre, reg_name_post, id)\
 529	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 530			## id ## _ ## reg_name_post ## _BASE_IDX) + \
 531			reg ## reg_name_pre ## id ## _ ## reg_name_post
 532
 533static struct dce_hwseq_registers hwseq_reg;
 534
 535#define hwseq_reg_init()\
 536	HWSEQ_DCN36_REG_LIST()
 537
 538#define HWSEQ_DCN36_MASK_SH_LIST(mask_sh)\
 539	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 540	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 541	HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 542	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 543	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 544	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 545	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 546	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 547	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 548	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 549	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 550	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 551	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 552	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 553	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 554	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 555	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 556	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 557	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 558	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 559	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 560	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 561	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 562	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 563	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 564	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 565	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 566	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 567	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 568	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 569	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 570	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 571	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 572	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 573	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 574	HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 575	HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 576	HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 577	HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 578	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 579	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 580	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 581	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 582	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 583	HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 584	HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
 585	HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
 586	HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
 587	HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
 588	HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 589	HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 590	HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 591	HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 592	HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 593	HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
 594	HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
 595	HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
 596	HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
 597	HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
 598	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
 599	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
 600	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
 601	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
 602	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
 603	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
 604	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
 605	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
 606	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
 607	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
 608	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
 609	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 610	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 611	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 612	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 613	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
 614	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
 615	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
 616	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
 617	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
 618	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
 619	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
 620	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
 621	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
 622	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
 623	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
 624	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
 625	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
 626
 627static const struct dce_hwseq_shift hwseq_shift = {
 628		HWSEQ_DCN36_MASK_SH_LIST(__SHIFT)
 629};
 630
 631static const struct dce_hwseq_mask hwseq_mask = {
 632		HWSEQ_DCN36_MASK_SH_LIST(_MASK)
 633};
 634
 635#define vmid_regs_init(id)\
 636		DCN20_VMID_REG_LIST_RI(id)
 637
 638static struct dcn_vmid_registers vmid_regs[16];
 639
 640static const struct dcn20_vmid_shift vmid_shifts = {
 641		DCN20_VMID_MASK_SH_LIST(__SHIFT)
 642};
 643
 644static const struct dcn20_vmid_mask vmid_masks = {
 645		DCN20_VMID_MASK_SH_LIST(_MASK)
 646};
 647
 648static const struct resource_caps res_cap_dcn36 = {
 649	.num_timing_generator = 4,
 650	.num_opp = 4,
 651	.num_video_plane = 4,
 652	.num_audio = 5,
 653	.num_stream_encoder = 5,
 654	.num_dig_link_enc = 5,
 655	.num_hpo_dp_stream_encoder = 4,
 656	.num_hpo_dp_link_encoder = 2,
 657	.num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
 658	.num_dwb = 1,
 659	.num_ddc = 5,
 660	.num_vmid = 16,
 661	.num_mpc_3dlut = 2,
 662	.num_dsc = 4,
 663};
 664
 665static const struct dc_plane_cap plane_cap = {
 666	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 667	.per_pixel_alpha = true,
 668
 669	.pixel_format_support = {
 670			.argb8888 = true,
 671			.nv12 = true,
 672			.fp16 = true,
 673			.p010 = true,
 674			.ayuv = false,
 675	},
 676
 677	.max_upscale_factor = {
 678			.argb8888 = 16000,
 679			.nv12 = 16000,
 680			.fp16 = 16000
 681	},
 682
 683	// 6:1 downscaling ratio: 1000/6 = 166.666
 684	.max_downscale_factor = {
 685			.argb8888 = 250,
 686			.nv12 = 167,
 687			.fp16 = 167
 688	},
 689	64,
 690	64
 691};
 692
 693static const struct dc_debug_options debug_defaults_drv = {
 694	.disable_dmcu = true,
 695	.force_abm_enable = false,
 696	.clock_trace = true,
 697	.disable_pplib_clock_request = false,
 698	.pipe_split_policy = MPC_SPLIT_AVOID,
 699	.force_single_disp_pipe_split = false,
 700	.disable_dcc = DCC_ENABLE,
 701	.disable_dpp_power_gate = true,
 702	.disable_hubp_power_gate = true,
 703	.disable_optc_power_gate = true, /*should the same as above two*/
 704	.disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
 705	.disable_clock_gate = false,
 706	.disable_dsc_power_gate = true,
 707	.vsr_support = true,
 708	.performance_trace = false,
 709	.max_downscale_src_width = 4096,/*upto true 4k*/
 710	.disable_pplib_wm_range = false,
 711	.scl_reset_length10 = true,
 712	.sanity_checks = false,
 713	.underflow_assert_delay_us = 0xFFFFFFFF,
 714	.dwb_fi_phase = -1, // -1 = disable,
 715	.dmub_command_table = true,
 716	.pstate_enabled = true,
 717	.use_max_lb = true,
 718	.enable_mem_low_power = {
 719		.bits = {
 720			.vga = false,
 721			.i2c = true,
 722			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 723			.dscl = true,
 724			.cm = true,
 725			.mpc = true,
 726			.optc = true,
 727			.vpg = true,
 728			.afmt = true,
 729		}
 730	},
 731	.root_clock_optimization = {
 732		.bits = {
 733			.dpp = true,
 734			.dsc = true,/*dscclk and dsc pg*/
 735			.hdmistream = true,
 736			.hdmichar = true,
 737			.dpstream = true,
 738			.symclk32_se = true,
 739			.symclk32_le = true,
 740			.symclk_fe = true,
 741			.physymclk = false,
 742			.dpiasymclk = true,
 743		}
 744	},
 745	.seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
 746	.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
 747	.minimum_z8_residency_time = 1, /* Always allow when other conditions are met */
 748	.using_dml2 = true,
 749	.support_eDP1_5 = true,
 750	.enable_hpo_pg_support = false,
 751	.enable_single_display_2to1_odm_policy = true,
 752	.disable_idle_power_optimizations = false,
 753	.dmcub_emulation = false,
 754	.disable_boot_optimizations = false,
 755	.disable_unbounded_requesting = false,
 756	.disable_mem_low_power = false,
 757	//must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
 758	.enable_double_buffered_dsc_pg_support = true,
 759	.enable_dp_dig_pixel_rate_div_policy = 1,
 760	.disable_z10 = false,
 761	.ignore_pg = true,
 762	.psp_disabled_wa = true,
 763	.ips2_eval_delay_us = 2000,
 764	.ips2_entry_delay_us = 800,
 765	.disable_dmub_reallow_idle = false,
 766	.static_screen_wait_frames = 2,
 767	.disable_timeout = true,
 768	.min_disp_clk_khz = 50000,
 769};
 770
 771static const struct dc_check_config config_defaults = {
 772	.enable_legacy_fast_update = false,
 773};
 774
 775static const struct dc_panel_config panel_config_defaults = {
 776	.psr = {
 777		.disable_psr = false,
 778		.disallow_psrsu = false,
 779		.disallow_replay = false,
 780	},
 781	.ilr = {
 782		.optimize_edp_link_rate = true,
 783	},
 784};
 785
 786static void dcn35_dpp_destroy(struct dpp **dpp)
 787{
 788	kfree(TO_DCN20_DPP(*dpp));
 789	*dpp = NULL;
 790}
 791
 792static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
 793{
 794	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 795	bool success = (dpp != NULL);
 796
 797	if (!success)
 798		return NULL;
 799
 800#undef REG_STRUCT
 801#define REG_STRUCT dpp_regs
 802	dpp_regs_init(0),
 803	dpp_regs_init(1),
 804	dpp_regs_init(2),
 805	dpp_regs_init(3);
 806
 807	success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
 808				  &tf_mask);
 809	if (success) {
 810		dpp35_set_fgcg(
 811			dpp,
 812			ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
 813		return &dpp->base;
 814	}
 815
 816	BREAK_TO_DEBUGGER();
 817	kfree(dpp);
 818	return NULL;
 819}
 820
 821static struct output_pixel_processor *dcn35_opp_create(
 822	struct dc_context *ctx, uint32_t inst)
 823{
 824	struct dcn20_opp *opp =
 825		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 826
 827	if (!opp) {
 828		BREAK_TO_DEBUGGER();
 829		return NULL;
 830	}
 831
 832#undef REG_STRUCT
 833#define REG_STRUCT opp_regs
 834	opp_regs_init(0),
 835	opp_regs_init(1),
 836	opp_regs_init(2),
 837	opp_regs_init(3);
 838
 839	dcn35_opp_construct(opp, ctx, inst,
 840			&opp_regs[inst], &opp_shift, &opp_mask);
 841
 842	dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
 843
 844	return &opp->base;
 845}
 846
 847static struct dce_aux *dcn31_aux_engine_create(
 848	struct dc_context *ctx,
 849	uint32_t inst)
 850{
 851	struct aux_engine_dce110 *aux_engine =
 852		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 853
 854	if (!aux_engine)
 855		return NULL;
 856
 857#undef REG_STRUCT
 858#define REG_STRUCT aux_engine_regs
 859	aux_engine_regs_init(0),
 860	aux_engine_regs_init(1),
 861	aux_engine_regs_init(2),
 862	aux_engine_regs_init(3),
 863	aux_engine_regs_init(4);
 864
 865	dce110_aux_engine_construct(aux_engine, ctx, inst,
 866				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 867				    &aux_engine_regs[inst],
 868					&aux_mask,
 869					&aux_shift,
 870					ctx->dc->caps.extended_aux_timeout_support);
 871
 872	return &aux_engine->base;
 873}
 874
 875#define i2c_inst_regs_init(id)\
 876	I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
 877
 878static struct dce_i2c_registers i2c_hw_regs[5];
 879
 880static const struct dce_i2c_shift i2c_shifts = {
 881		I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 882};
 883
 884static const struct dce_i2c_mask i2c_masks = {
 885		I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
 886};
 887
 888/* ========================================================== */
 889
 890/*
 891 * DPIA index | Preferred Encoder     |    Host Router
 892 *   0        |      C                |       0
 893 *   1        |      First Available  |       0
 894 *   2        |      D                |       1
 895 *   3        |      First Available  |       1
 896 */
 897/* ========================================================== */
 898static const enum engine_id dpia_to_preferred_enc_id_table[] = {
 899		ENGINE_ID_DIGC,
 900		ENGINE_ID_DIGC,
 901		ENGINE_ID_DIGD,
 902		ENGINE_ID_DIGD
 903};
 904
 905static enum engine_id dcn36_get_preferred_eng_id_dpia(unsigned int dpia_index)
 906{
 907	return dpia_to_preferred_enc_id_table[dpia_index];
 908}
 909
 910static struct dce_i2c_hw *dcn31_i2c_hw_create(
 911	struct dc_context *ctx,
 912	uint32_t inst)
 913{
 914	struct dce_i2c_hw *dce_i2c_hw =
 915		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 916
 917	if (!dce_i2c_hw)
 918		return NULL;
 919
 920#undef REG_STRUCT
 921#define REG_STRUCT i2c_hw_regs
 922	i2c_inst_regs_init(1),
 923	i2c_inst_regs_init(2),
 924	i2c_inst_regs_init(3),
 925	i2c_inst_regs_init(4),
 926	i2c_inst_regs_init(5);
 927
 928	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 929				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 930
 931	return dce_i2c_hw;
 932}
 933static struct mpc *dcn35_mpc_create(
 934		struct dc_context *ctx,
 935		int num_mpcc,
 936		int num_rmu)
 937{
 938	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
 939
 940	if (!mpc30)
 941		return NULL;
 942
 943#undef REG_STRUCT
 944#define REG_STRUCT mpc_regs
 945	dcn_mpc_regs_init();
 946
 947	dcn32_mpc_construct(mpc30, ctx,
 948			&mpc_regs,
 949			&mpc_shift,
 950			&mpc_mask,
 951			num_mpcc,
 952			num_rmu);
 953
 954	return &mpc30->base;
 955}
 956
 957static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
 958{
 959	int i;
 960
 961	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
 962					  GFP_KERNEL);
 963
 964	if (!hubbub3)
 965		return NULL;
 966
 967#undef REG_STRUCT
 968#define REG_STRUCT hubbub_reg
 969	hubbub_reg_init();
 970
 971#undef REG_STRUCT
 972#define REG_STRUCT vmid_regs
 973	vmid_regs_init(0),
 974	vmid_regs_init(1),
 975	vmid_regs_init(2),
 976	vmid_regs_init(3),
 977	vmid_regs_init(4),
 978	vmid_regs_init(5),
 979	vmid_regs_init(6),
 980	vmid_regs_init(7),
 981	vmid_regs_init(8),
 982	vmid_regs_init(9),
 983	vmid_regs_init(10),
 984	vmid_regs_init(11),
 985	vmid_regs_init(12),
 986	vmid_regs_init(13),
 987	vmid_regs_init(14),
 988	vmid_regs_init(15);
 989
 990	hubbub35_construct(hubbub3, ctx,
 991			&hubbub_reg,
 992			&hubbub_shift,
 993			&hubbub_mask,
 994			384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
 995			8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
 996			1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
 997
 998
 999	for (i = 0; i < res_cap_dcn36.num_vmid; i++) {
1000		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1001
1002		vmid->ctx = ctx;
1003
1004		vmid->regs = &vmid_regs[i];
1005		vmid->shifts = &vmid_shifts;
1006		vmid->masks = &vmid_masks;
1007	}
1008
1009	return &hubbub3->base;
1010}
1011
1012static struct timing_generator *dcn35_timing_generator_create(
1013		struct dc_context *ctx,
1014		uint32_t instance)
1015{
1016	struct optc *tgn10 =
1017		kzalloc(sizeof(struct optc), GFP_KERNEL);
1018
1019	if (!tgn10)
1020		return NULL;
1021
1022#undef REG_STRUCT
1023#define REG_STRUCT optc_regs
1024	optc_regs_init(0),
1025	optc_regs_init(1),
1026	optc_regs_init(2),
1027	optc_regs_init(3);
1028
1029	tgn10->base.inst = instance;
1030	tgn10->base.ctx = ctx;
1031
1032	tgn10->tg_regs = &optc_regs[instance];
1033	tgn10->tg_shift = &optc_shift;
1034	tgn10->tg_mask = &optc_mask;
1035
1036	dcn35_timing_generator_init(tgn10);
1037
1038	return &tgn10->base;
1039}
1040
1041static const struct encoder_feature_support link_enc_feature = {
1042		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1043		.max_hdmi_pixel_clock = 600000,
1044		.hdmi_ycbcr420_supported = true,
1045		.dp_ycbcr420_supported = true,
1046		.fec_supported = true,
1047		.flags.bits.IS_HBR2_CAPABLE = true,
1048		.flags.bits.IS_HBR3_CAPABLE = true,
1049		.flags.bits.IS_TPS3_CAPABLE = true,
1050		.flags.bits.IS_TPS4_CAPABLE = true
1051};
1052
1053static struct link_encoder *dcn35_link_encoder_create(
1054	struct dc_context *ctx,
1055	const struct encoder_init_data *enc_init_data)
1056{
1057	struct dcn20_link_encoder *enc20 =
1058		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1059
1060	if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1061		return NULL;
1062
1063#undef REG_STRUCT
1064#define REG_STRUCT link_enc_aux_regs
1065	aux_regs_init(0),
1066	aux_regs_init(1),
1067	aux_regs_init(2),
1068	aux_regs_init(3),
1069	aux_regs_init(4);
1070
1071#undef REG_STRUCT
1072#define REG_STRUCT link_enc_hpd_regs
1073	hpd_regs_init(0),
1074	hpd_regs_init(1),
1075	hpd_regs_init(2),
1076	hpd_regs_init(3),
1077	hpd_regs_init(4);
1078
1079#undef REG_STRUCT
1080#define REG_STRUCT link_enc_regs
1081	link_regs_init(0, A),
1082	link_regs_init(1, B),
1083	link_regs_init(2, C),
1084	link_regs_init(3, D),
1085	link_regs_init(4, E);
1086
1087	dcn35_link_encoder_construct(enc20,
1088			enc_init_data,
1089			&link_enc_feature,
1090			&link_enc_regs[enc_init_data->transmitter],
1091			&link_enc_aux_regs[enc_init_data->channel - 1],
1092			&link_enc_hpd_regs[enc_init_data->hpd_source],
1093			&le_shift,
1094			&le_mask);
1095
1096	return &enc20->enc10.base;
1097}
1098
1099/* Create a minimal link encoder object not associated with a particular
1100 * physical connector.
1101 * resource_funcs.link_enc_create_minimal
1102 */
1103static struct link_encoder *dcn31_link_enc_create_minimal(
1104		struct dc_context *ctx, enum engine_id eng_id)
1105{
1106	struct dcn20_link_encoder *enc20;
1107
1108	if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1109		return NULL;
1110
1111	enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1112	if (!enc20)
1113		return NULL;
1114
1115	dcn31_link_encoder_construct_minimal(
1116			enc20,
1117			ctx,
1118			&link_enc_feature,
1119			&link_enc_regs[eng_id - ENGINE_ID_DIGA],
1120			eng_id);
1121
1122	return &enc20->enc10.base;
1123}
1124
1125static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1126{
1127	struct dcn31_panel_cntl *panel_cntl =
1128		kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1129
1130	if (!panel_cntl)
1131		return NULL;
1132
1133	dcn31_panel_cntl_construct(panel_cntl, init_data);
1134
1135	return &panel_cntl->base;
1136}
1137
1138static void read_dce_straps(
1139	struct dc_context *ctx,
1140	struct resource_straps *straps)
1141{
1142	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1143		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1144
1145}
1146
1147static struct audio *dcn31_create_audio(
1148		struct dc_context *ctx, unsigned int inst)
1149{
1150
1151#undef REG_STRUCT
1152#define REG_STRUCT audio_regs
1153	audio_regs_init(0),
1154	audio_regs_init(1),
1155	audio_regs_init(2),
1156	audio_regs_init(3),
1157	audio_regs_init(4);
1158	audio_regs_init(5);
1159	audio_regs_init(6);
1160
1161	return dce_audio_create(ctx, inst,
1162			&audio_regs[inst], &audio_shift, &audio_mask);
1163}
1164
1165static struct vpg *dcn31_vpg_create(
1166	struct dc_context *ctx,
1167	uint32_t inst)
1168{
1169	struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1170
1171	if (!vpg31)
1172		return NULL;
1173
1174#undef REG_STRUCT
1175#define REG_STRUCT vpg_regs
1176	vpg_regs_init(0),
1177	vpg_regs_init(1),
1178	vpg_regs_init(2),
1179	vpg_regs_init(3),
1180	vpg_regs_init(4),
1181	vpg_regs_init(5),
1182	vpg_regs_init(6),
1183	vpg_regs_init(7),
1184	vpg_regs_init(8),
1185	vpg_regs_init(9);
1186
1187	vpg31_construct(vpg31, ctx, inst,
1188			&vpg_regs[inst],
1189			&vpg_shift,
1190			&vpg_mask);
1191
1192	return &vpg31->base;
1193}
1194
1195static struct afmt *dcn31_afmt_create(
1196	struct dc_context *ctx,
1197	uint32_t inst)
1198{
1199	struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1200
1201	if (!afmt31)
1202		return NULL;
1203
1204#undef REG_STRUCT
1205#define REG_STRUCT afmt_regs
1206	afmt_regs_init(0),
1207	afmt_regs_init(1),
1208	afmt_regs_init(2),
1209	afmt_regs_init(3),
1210	afmt_regs_init(4),
1211	afmt_regs_init(5);
1212
1213	afmt31_construct(afmt31, ctx, inst,
1214			&afmt_regs[inst],
1215			&afmt_shift,
1216			&afmt_mask);
1217
1218	// Light sleep by default, no need to power down here
1219
1220	return &afmt31->base;
1221}
1222
1223static struct apg *dcn31_apg_create(
1224	struct dc_context *ctx,
1225	uint32_t inst)
1226{
1227	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1228
1229	if (!apg31)
1230		return NULL;
1231
1232#undef REG_STRUCT
1233#define REG_STRUCT apg_regs
1234	apg_regs_init(0),
1235	apg_regs_init(1),
1236	apg_regs_init(2),
1237	apg_regs_init(3);
1238
1239	apg31_construct(apg31, ctx, inst,
1240			&apg_regs[inst],
1241			&apg_shift,
1242			&apg_mask);
1243
1244	return &apg31->base;
1245}
1246
1247static struct stream_encoder *dcn35_stream_encoder_create(
1248	enum engine_id eng_id,
1249	struct dc_context *ctx)
1250{
1251	struct dcn10_stream_encoder *enc1;
1252	struct vpg *vpg;
1253	struct afmt *afmt;
1254	int vpg_inst;
1255	int afmt_inst;
1256
1257	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1258	if (eng_id <= ENGINE_ID_DIGF) {
1259		vpg_inst = eng_id;
1260		afmt_inst = eng_id;
1261	} else
1262		return NULL;
1263
1264	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1265	vpg = dcn31_vpg_create(ctx, vpg_inst);
1266	afmt = dcn31_afmt_create(ctx, afmt_inst);
1267
1268	if (!enc1 || !vpg || !afmt) {
1269		kfree(enc1);
1270		kfree(vpg);
1271		kfree(afmt);
1272		return NULL;
1273	}
1274
1275#undef REG_STRUCT
1276#define REG_STRUCT stream_enc_regs
1277	stream_enc_regs_init(0),
1278	stream_enc_regs_init(1),
1279	stream_enc_regs_init(2),
1280	stream_enc_regs_init(3),
1281	stream_enc_regs_init(4);
1282
1283	dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1284					eng_id, vpg, afmt,
1285					&stream_enc_regs[eng_id],
1286					&se_shift, &se_mask);
1287
1288	return &enc1->base;
1289}
1290
1291static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1292	enum engine_id eng_id,
1293	struct dc_context *ctx)
1294{
1295	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1296	struct vpg *vpg;
1297	struct apg *apg;
1298	uint32_t hpo_dp_inst;
1299	uint32_t vpg_inst;
1300	uint32_t apg_inst;
1301
1302	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1303	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1304
1305	/* Mapping of VPG register blocks to HPO DP block instance:
1306	 * VPG[6] -> HPO_DP[0]
1307	 * VPG[7] -> HPO_DP[1]
1308	 * VPG[8] -> HPO_DP[2]
1309	 * VPG[9] -> HPO_DP[3]
1310	 */
1311	vpg_inst = hpo_dp_inst + 6;
1312
1313	/* Mapping of APG register blocks to HPO DP block instance:
1314	 * APG[0] -> HPO_DP[0]
1315	 * APG[1] -> HPO_DP[1]
1316	 * APG[2] -> HPO_DP[2]
1317	 * APG[3] -> HPO_DP[3]
1318	 */
1319	apg_inst = hpo_dp_inst;
1320
1321	/* allocate HPO stream encoder and create VPG sub-block */
1322	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1323	vpg = dcn31_vpg_create(ctx, vpg_inst);
1324	apg = dcn31_apg_create(ctx, apg_inst);
1325
1326	if (!hpo_dp_enc31 || !vpg || !apg) {
1327		kfree(hpo_dp_enc31);
1328		kfree(vpg);
1329		kfree(apg);
1330		return NULL;
1331	}
1332
1333#undef REG_STRUCT
1334#define REG_STRUCT hpo_dp_stream_enc_regs
1335	hpo_dp_stream_encoder_reg_init(0),
1336	hpo_dp_stream_encoder_reg_init(1),
1337	hpo_dp_stream_encoder_reg_init(2),
1338	hpo_dp_stream_encoder_reg_init(3);
1339
1340	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1341					hpo_dp_inst, eng_id, vpg, apg,
1342					&hpo_dp_stream_enc_regs[hpo_dp_inst],
1343					&hpo_dp_se_shift, &hpo_dp_se_mask);
1344
1345	return &hpo_dp_enc31->base;
1346}
1347
1348static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1349	uint8_t inst,
1350	struct dc_context *ctx)
1351{
1352	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1353
1354	/* allocate HPO link encoder */
1355	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1356	if (!hpo_dp_enc31)
1357		return NULL; /* out of memory */
1358
1359#undef REG_STRUCT
1360#define REG_STRUCT hpo_dp_link_enc_regs
1361	hpo_dp_link_encoder_reg_init(0),
1362	hpo_dp_link_encoder_reg_init(1);
1363
1364	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1365					&hpo_dp_link_enc_regs[inst],
1366					&hpo_dp_le_shift, &hpo_dp_le_mask);
1367
1368	return &hpo_dp_enc31->base;
1369}
1370
1371static struct dce_hwseq *dcn36_hwseq_create(
1372	struct dc_context *ctx)
1373{
1374	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1375
1376#undef REG_STRUCT
1377#define REG_STRUCT hwseq_reg
1378	hwseq_reg_init();
1379
1380	if (hws) {
1381		hws->ctx = ctx;
1382		hws->regs = &hwseq_reg;
1383		hws->shifts = &hwseq_shift;
1384		hws->masks = &hwseq_mask;
1385	}
1386	return hws;
1387}
1388static const struct resource_create_funcs res_create_funcs = {
1389	.read_dce_straps = read_dce_straps,
1390	.create_audio = dcn31_create_audio,
1391	.create_stream_encoder = dcn35_stream_encoder_create,
1392	.create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1393	.create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1394	.create_hwseq = dcn36_hwseq_create,
1395};
1396
1397static void dcn36_resource_destruct(struct dcn36_resource_pool *pool)
1398{
1399	unsigned int i;
1400
1401	for (i = 0; i < pool->base.stream_enc_count; i++) {
1402		if (pool->base.stream_enc[i] != NULL) {
1403			if (pool->base.stream_enc[i]->vpg != NULL) {
1404				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1405				pool->base.stream_enc[i]->vpg = NULL;
1406			}
1407			if (pool->base.stream_enc[i]->afmt != NULL) {
1408				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1409				pool->base.stream_enc[i]->afmt = NULL;
1410			}
1411			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1412			pool->base.stream_enc[i] = NULL;
1413		}
1414	}
1415
1416	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1417		if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1418			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1419				kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1420				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1421			}
1422			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1423				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1424				pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1425			}
1426			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1427			pool->base.hpo_dp_stream_enc[i] = NULL;
1428		}
1429	}
1430
1431	for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1432		if (pool->base.hpo_dp_link_enc[i] != NULL) {
1433			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1434			pool->base.hpo_dp_link_enc[i] = NULL;
1435		}
1436	}
1437
1438	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1439		if (pool->base.dscs[i] != NULL)
1440			dcn20_dsc_destroy(&pool->base.dscs[i]);
1441	}
1442
1443	if (pool->base.mpc != NULL) {
1444		kfree(TO_DCN20_MPC(pool->base.mpc));
1445		pool->base.mpc = NULL;
1446	}
1447	if (pool->base.hubbub != NULL) {
1448		kfree(pool->base.hubbub);
1449		pool->base.hubbub = NULL;
1450	}
1451	for (i = 0; i < pool->base.pipe_count; i++) {
1452		if (pool->base.dpps[i] != NULL)
1453			dcn35_dpp_destroy(&pool->base.dpps[i]);
1454
1455		if (pool->base.ipps[i] != NULL)
1456			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1457
1458		if (pool->base.hubps[i] != NULL) {
1459			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1460			pool->base.hubps[i] = NULL;
1461		}
1462
1463		if (pool->base.irqs != NULL) {
1464			dal_irq_service_destroy(&pool->base.irqs);
1465		}
1466	}
1467
1468	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1469		if (pool->base.engines[i] != NULL)
1470			dce110_engine_destroy(&pool->base.engines[i]);
1471		if (pool->base.hw_i2cs[i] != NULL) {
1472			kfree(pool->base.hw_i2cs[i]);
1473			pool->base.hw_i2cs[i] = NULL;
1474		}
1475		if (pool->base.sw_i2cs[i] != NULL) {
1476			kfree(pool->base.sw_i2cs[i]);
1477			pool->base.sw_i2cs[i] = NULL;
1478		}
1479	}
1480
1481	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1482		if (pool->base.opps[i] != NULL)
1483			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1484	}
1485
1486	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1487		if (pool->base.timing_generators[i] != NULL)	{
1488			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1489			pool->base.timing_generators[i] = NULL;
1490		}
1491	}
1492
1493	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1494		if (pool->base.dwbc[i] != NULL) {
1495			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1496			pool->base.dwbc[i] = NULL;
1497		}
1498		if (pool->base.mcif_wb[i] != NULL) {
1499			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1500			pool->base.mcif_wb[i] = NULL;
1501		}
1502	}
1503
1504	for (i = 0; i < pool->base.audio_count; i++) {
1505		if (pool->base.audios[i])
1506			dce_aud_destroy(&pool->base.audios[i]);
1507	}
1508
1509	for (i = 0; i < pool->base.clk_src_count; i++) {
1510		if (pool->base.clock_sources[i] != NULL) {
1511			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1512			pool->base.clock_sources[i] = NULL;
1513		}
1514	}
1515
1516	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1517		if (pool->base.mpc_lut[i] != NULL) {
1518			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1519			pool->base.mpc_lut[i] = NULL;
1520		}
1521		if (pool->base.mpc_shaper[i] != NULL) {
1522			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1523			pool->base.mpc_shaper[i] = NULL;
1524		}
1525	}
1526
1527	if (pool->base.dp_clock_source != NULL) {
1528		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1529		pool->base.dp_clock_source = NULL;
1530	}
1531
1532	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1533		if (pool->base.multiple_abms[i] != NULL)
1534			dce_abm_destroy(&pool->base.multiple_abms[i]);
1535	}
1536
1537	if (pool->base.psr != NULL)
1538		dmub_psr_destroy(&pool->base.psr);
1539
1540	if (pool->base.replay != NULL)
1541		dmub_replay_destroy(&pool->base.replay);
1542
1543	if (pool->base.pg_cntl != NULL)
1544		dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1545
1546	if (pool->base.dccg != NULL)
1547		dcn_dccg_destroy(&pool->base.dccg);
1548}
1549
1550static struct hubp *dcn35_hubp_create(
1551	struct dc_context *ctx,
1552	uint32_t inst)
1553{
1554	struct dcn20_hubp *hubp2 =
1555		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1556
1557	if (!hubp2)
1558		return NULL;
1559
1560#undef REG_STRUCT
1561#define REG_STRUCT hubp_regs
1562	hubp_regs_init(0),
1563	hubp_regs_init(1),
1564	hubp_regs_init(2),
1565	hubp_regs_init(3);
1566
1567	if (hubp35_construct(hubp2, ctx, inst,
1568			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1569		return &hubp2->base;
1570
1571	BREAK_TO_DEBUGGER();
1572	kfree(hubp2);
1573	return NULL;
1574}
1575
1576static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1577{
1578	dcn35_dwbc_set_fgcg(
1579		dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1580}
1581
1582static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1583{
1584	int i;
1585	uint32_t pipe_count = pool->res_cap->num_dwb;
1586
1587	for (i = 0; i < pipe_count; i++) {
1588		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1589						    GFP_KERNEL);
1590
1591		if (!dwbc30) {
1592			dm_error("DC: failed to create dwbc30!\n");
1593			return false;
1594		}
1595
1596#undef REG_STRUCT
1597#define REG_STRUCT dwbc35_regs
1598		dwbc_regs_dcn3_init(0);
1599
1600		dcn35_dwbc_construct(dwbc30, ctx,
1601				&dwbc35_regs[i],
1602				&dwbc35_shift,
1603				&dwbc35_mask,
1604				i);
1605
1606		pool->dwbc[i] = &dwbc30->base;
1607
1608		dcn35_dwbc_init(dwbc30, ctx);
1609	}
1610	return true;
1611}
1612
1613static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1614				struct dc_context *ctx)
1615{
1616	dcn35_mmhubbub_set_fgcg(
1617		mcif_wb30,
1618		ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1619}
1620
1621static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1622{
1623	int i;
1624	uint32_t pipe_count = pool->res_cap->num_dwb;
1625
1626	for (i = 0; i < pipe_count; i++) {
1627		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1628						    GFP_KERNEL);
1629
1630		if (!mcif_wb30) {
1631			dm_error("DC: failed to create mcif_wb30!\n");
1632			return false;
1633		}
1634
1635#undef REG_STRUCT
1636#define REG_STRUCT mcif_wb35_regs
1637		mcif_wb_regs_dcn3_init(0);
1638
1639		dcn35_mmhubbub_construct(mcif_wb30, ctx,
1640				&mcif_wb35_regs[i],
1641				&mcif_wb35_shift,
1642				&mcif_wb35_mask,
1643				i);
1644
1645		dcn35_mmhubbub_init(mcif_wb30, ctx);
1646
1647		pool->mcif_wb[i] = &mcif_wb30->base;
1648	}
1649	return true;
1650}
1651
1652static struct display_stream_compressor *dcn35_dsc_create(
1653	struct dc_context *ctx, uint32_t inst)
1654{
1655	struct dcn20_dsc *dsc =
1656		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1657
1658	if (!dsc) {
1659		BREAK_TO_DEBUGGER();
1660		return NULL;
1661	}
1662
1663#undef REG_STRUCT
1664#define REG_STRUCT dsc_regs
1665	dsc_regsDCN35_init(0),
1666	dsc_regsDCN35_init(1),
1667	dsc_regsDCN35_init(2),
1668	dsc_regsDCN35_init(3);
1669
1670	dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1671	dsc35_set_fgcg(dsc,
1672		       ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1673	return &dsc->base;
1674}
1675
1676static void dcn36_destroy_resource_pool(struct resource_pool **pool)
1677{
1678	struct dcn36_resource_pool *dcn36_pool = TO_DCN36_RES_POOL(*pool);
1679
1680	dcn36_resource_destruct(dcn36_pool);
1681	kfree(dcn36_pool);
1682	*pool = NULL;
1683}
1684
1685static struct clock_source *dcn35_clock_source_create(
1686		struct dc_context *ctx,
1687		struct dc_bios *bios,
1688		enum clock_source_id id,
1689		const struct dce110_clk_src_regs *regs,
1690		bool dp_clk_src)
1691{
1692	struct dce110_clk_src *clk_src =
1693		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1694
1695	if (!clk_src)
1696		return NULL;
1697
1698	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1699			regs, &cs_shift, &cs_mask)) {
1700		clk_src->base.dp_clk_src = dp_clk_src;
1701		return &clk_src->base;
1702	}
1703
1704	kfree(clk_src);
1705	BREAK_TO_DEBUGGER();
1706	return NULL;
1707}
1708
1709static struct dc_cap_funcs cap_funcs = {
1710	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1711};
1712
1713static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1714{
1715	*panel_config = panel_config_defaults;
1716}
1717
1718
1719static enum dc_status dcn35_validate_bandwidth(struct dc *dc,
1720		struct dc_state *context,
1721		enum dc_validate_mode validate_mode)
1722{
1723	bool out = false;
1724
1725	out = dml2_validate(dc, context,
1726			context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1727			validate_mode);
1728
1729	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1730		return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1731
1732	DC_FP_START();
1733	dcn35_decide_zstate_support(dc, context);
1734	DC_FP_END();
1735
1736	return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1737}
1738
1739
1740static int populate_dml_pipes_from_context_fpu(struct dc *dc,
1741					       struct dc_state *context,
1742					       display_e2e_pipe_params_st *pipes,
1743					       enum dc_validate_mode validate_mode)
1744{
1745	int ret;
1746
1747	DC_FP_START();
1748	ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1749	DC_FP_END();
1750
1751	return ret;
1752}
1753
1754static struct resource_funcs dcn36_res_pool_funcs = {
1755	.destroy = dcn36_destroy_resource_pool,
1756	.link_enc_create = dcn35_link_encoder_create,
1757	.link_enc_create_minimal = dcn31_link_enc_create_minimal,
1758	.link_encs_assign = link_enc_cfg_link_encs_assign,
1759	.link_enc_unassign = link_enc_cfg_link_enc_unassign,
1760	.panel_cntl_create = dcn31_panel_cntl_create,
1761	.validate_bandwidth = dcn35_validate_bandwidth,
1762	.calculate_wm_and_dlg = NULL,
1763	.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1764	.populate_dml_pipes = populate_dml_pipes_from_context_fpu,
1765	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1766	.release_pipe = dcn20_release_pipe,
1767	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1768	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1769	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1770	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1771	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1772	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1773	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1774	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1775	.update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,
1776	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1777	.get_panel_config_defaults = dcn35_get_panel_config_defaults,
1778	.get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia,
1779	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1780	.update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1781	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
1782};
1783
1784static bool dcn36_resource_construct(
1785	uint8_t num_virtual_links,
1786	struct dc *dc,
1787	struct dcn36_resource_pool *pool)
1788{
1789	int i;
1790	struct dc_context *ctx = dc->ctx;
1791	struct irq_service_init_data init_data;
1792
1793#undef REG_STRUCT
1794#define REG_STRUCT bios_regs
1795	bios_regs_init();
1796
1797#undef REG_STRUCT
1798#define REG_STRUCT clk_src_regs
1799	clk_src_regs_init(0, A),
1800	clk_src_regs_init(1, B),
1801	clk_src_regs_init(2, C),
1802	clk_src_regs_init(3, D),
1803	clk_src_regs_init(4, E);
1804
1805#undef REG_STRUCT
1806#define REG_STRUCT abm_regs
1807	abm_regs_init(0),
1808	abm_regs_init(1),
1809	abm_regs_init(2),
1810	abm_regs_init(3);
1811
1812#undef REG_STRUCT
1813#define REG_STRUCT dccg_regs
1814	dccg_regs_init();
1815
1816	ctx->dc_bios->regs = &bios_regs;
1817
1818	pool->base.res_cap = &res_cap_dcn36;
1819
1820	pool->base.funcs = &dcn36_res_pool_funcs;
1821
1822	/*************************************************
1823	 *  Resource + asic cap harcoding                *
1824	 *************************************************/
1825	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1826	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1827	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1828	dc->caps.max_downscale_ratio = 600;
1829	dc->caps.i2c_speed_in_khz = 100;
1830	dc->caps.i2c_speed_in_khz_hdcp = 100;
1831	dc->caps.max_cursor_size = 256;
1832	dc->caps.min_horizontal_blanking_period = 80;
1833	dc->caps.dmdata_alloc_size = 2048;
1834	dc->caps.max_slave_planes = 3;
1835	dc->caps.max_slave_yuv_planes = 3;
1836	dc->caps.max_slave_rgb_planes = 3;
1837	dc->caps.post_blend_color_processing = true;
1838	dc->caps.force_dp_tps4_for_cp2520 = true;
1839	if (dc->config.forceHBR2CP2520)
1840		dc->caps.force_dp_tps4_for_cp2520 = false;
1841	dc->caps.dp_hpo = true;
1842	dc->caps.dp_hdmi21_pcon_support = true;
1843
1844	dc->caps.edp_dsc_support = true;
1845	dc->caps.extended_aux_timeout_support = true;
1846	dc->caps.dmcub_support = true;
1847	dc->caps.is_apu = true;
1848	dc->caps.seamless_odm = true;
1849
1850	dc->caps.zstate_support = true;
1851	dc->caps.ips_support = true;
1852	dc->caps.max_v_total = (1 << 15) - 1;
1853	dc->caps.vtotal_limited_by_fp2 = true;
1854
1855	/* Color pipeline capabilities */
1856	dc->caps.color.dpp.dcn_arch = 1;
1857	dc->caps.color.dpp.input_lut_shared = 0;
1858	dc->caps.color.dpp.icsc = 1;
1859	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1860	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1861	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1862	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1863	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1864	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1865	dc->caps.color.dpp.post_csc = 1;
1866	dc->caps.color.dpp.gamma_corr = 1;
1867	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1868
1869	dc->caps.color.dpp.hw_3d_lut = 0;
1870	dc->caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1
1871	// no OGAM ROM on DCN301
1872	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1873	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1874	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1875	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1876	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1877	dc->caps.color.dpp.ocsc = 0;
1878
1879	dc->caps.color.mpc.gamut_remap = 1;
1880	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1881	dc->caps.color.mpc.ogam_ram = 1;
1882	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1883	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1884	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1885	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1886	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1887	dc->caps.color.mpc.ocsc = 1;
1888	dc->caps.color.mpc.preblend = true;
1889
1890	dc->caps.num_of_host_routers = 2;
1891	dc->caps.num_of_dpias_per_host_router = 2;
1892
1893	/* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1894	 * to provide some margin.
1895	 * It's expected for furture ASIC to have equal or higher value, in order to
1896	 * have determinstic power improvement from generate to genration.
1897	 * (i.e., we should not expect new ASIC generation with lower vmin rate)
1898	 */
1899	dc->caps.max_disp_clock_khz_at_vmin = 650000;
1900
1901	/* Sequential ONO is based on ASIC. */
1902	if (dc->ctx->asic_id.hw_internal_rev >= 0x40)
1903		dc->caps.sequential_ono = true;
1904
1905	/* Use pipe context based otg sync logic */
1906	dc->config.use_pipe_ctx_sync_logic = true;
1907
1908	dc->config.disable_hbr_audio_dp2 = true;
1909	/* read VBIOS LTTPR caps */
1910	{
1911		if (ctx->dc_bios->funcs->get_lttpr_caps) {
1912			enum bp_result bp_query_result;
1913			uint8_t is_vbios_lttpr_enable = 0;
1914
1915			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1916			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1917		}
1918
1919		/* interop bit is implicit */
1920		{
1921			dc->caps.vbios_lttpr_aware = true;
1922		}
1923	}
1924	dc->check_config = config_defaults;
1925
1926	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1927		dc->debug = debug_defaults_drv;
1928
1929	/*HW default is to have all the FGCG enabled, SW no need to program them*/
1930	dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
1931	// Init the vm_helper
1932	if (dc->vm_helper)
1933		vm_helper_init(dc->vm_helper, 16);
1934
1935	/*************************************************
1936	 *  Create resources                             *
1937	 *************************************************/
1938
1939	/* Clock Sources for Pixel Clock*/
1940	pool->base.clock_sources[DCN36_CLK_SRC_PLL0] =
1941			dcn35_clock_source_create(ctx, ctx->dc_bios,
1942				CLOCK_SOURCE_COMBO_PHY_PLL0,
1943				&clk_src_regs[0], false);
1944	pool->base.clock_sources[DCN36_CLK_SRC_PLL1] =
1945			dcn35_clock_source_create(ctx, ctx->dc_bios,
1946				CLOCK_SOURCE_COMBO_PHY_PLL1,
1947				&clk_src_regs[1], false);
1948	pool->base.clock_sources[DCN36_CLK_SRC_PLL2] =
1949			dcn35_clock_source_create(ctx, ctx->dc_bios,
1950				CLOCK_SOURCE_COMBO_PHY_PLL2,
1951				&clk_src_regs[2], false);
1952	pool->base.clock_sources[DCN36_CLK_SRC_PLL3] =
1953			dcn35_clock_source_create(ctx, ctx->dc_bios,
1954				CLOCK_SOURCE_COMBO_PHY_PLL3,
1955				&clk_src_regs[3], false);
1956	pool->base.clock_sources[DCN36_CLK_SRC_PLL4] =
1957			dcn35_clock_source_create(ctx, ctx->dc_bios,
1958				CLOCK_SOURCE_COMBO_PHY_PLL4,
1959				&clk_src_regs[4], false);
1960
1961	pool->base.clk_src_count = DCN36_CLK_SRC_TOTAL;
1962
1963	/* todo: not reuse phy_pll registers */
1964	pool->base.dp_clock_source =
1965			dcn35_clock_source_create(ctx, ctx->dc_bios,
1966				CLOCK_SOURCE_ID_DP_DTO,
1967				&clk_src_regs[0], true);
1968
1969	for (i = 0; i < pool->base.clk_src_count; i++) {
1970		if (pool->base.clock_sources[i] == NULL) {
1971			dm_error("DC: failed to create clock sources!\n");
1972			BREAK_TO_DEBUGGER();
1973			goto create_fail;
1974		}
1975	}
1976	/*temp till dml2 fully work without dml1*/
1977	dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
1978
1979	/* TODO: DCCG */
1980	pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1981	if (pool->base.dccg == NULL) {
1982		dm_error("DC: failed to create dccg!\n");
1983		BREAK_TO_DEBUGGER();
1984		goto create_fail;
1985	}
1986
1987#undef REG_STRUCT
1988#define REG_STRUCT pg_cntl_regs
1989	pg_cntl_dcn35_regs_init();
1990
1991	pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
1992	if (pool->base.pg_cntl == NULL) {
1993		dm_error("DC: failed to create power gate control!\n");
1994		BREAK_TO_DEBUGGER();
1995		goto create_fail;
1996	}
1997
1998	/* TODO: IRQ */
1999	init_data.ctx = dc->ctx;
2000	pool->base.irqs = dal_irq_service_dcn36_create(&init_data);
2001	if (!pool->base.irqs)
2002		goto create_fail;
2003
2004	/* HUBBUB */
2005	pool->base.hubbub = dcn35_hubbub_create(ctx);
2006	if (pool->base.hubbub == NULL) {
2007		BREAK_TO_DEBUGGER();
2008		dm_error("DC: failed to create hubbub!\n");
2009		goto create_fail;
2010	}
2011
2012	/* HUBPs, DPPs, OPPs and TGs */
2013	for (i = 0; i < pool->base.pipe_count; i++) {
2014		pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
2015		if (pool->base.hubps[i] == NULL) {
2016			BREAK_TO_DEBUGGER();
2017			dm_error(
2018				"DC: failed to create hubps!\n");
2019			goto create_fail;
2020		}
2021
2022		pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
2023		if (pool->base.dpps[i] == NULL) {
2024			BREAK_TO_DEBUGGER();
2025			dm_error(
2026				"DC: failed to create dpps!\n");
2027			goto create_fail;
2028		}
2029	}
2030
2031	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2032		pool->base.opps[i] = dcn35_opp_create(ctx, i);
2033		if (pool->base.opps[i] == NULL) {
2034			BREAK_TO_DEBUGGER();
2035			dm_error(
2036				"DC: failed to create output pixel processor!\n");
2037			goto create_fail;
2038		}
2039	}
2040
2041	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2042		pool->base.timing_generators[i] = dcn35_timing_generator_create(
2043				ctx, i);
2044		if (pool->base.timing_generators[i] == NULL) {
2045			BREAK_TO_DEBUGGER();
2046			dm_error("DC: failed to create tg!\n");
2047			goto create_fail;
2048		}
2049	}
2050	pool->base.timing_generator_count = i;
2051
2052	/* PSR */
2053	pool->base.psr = dmub_psr_create(ctx);
2054	if (pool->base.psr == NULL) {
2055		dm_error("DC: failed to create psr obj!\n");
2056		BREAK_TO_DEBUGGER();
2057		goto create_fail;
2058	}
2059
2060	/* Replay */
2061	pool->base.replay = dmub_replay_create(ctx);
2062	if (pool->base.replay == NULL) {
2063		dm_error("DC: failed to create replay obj!\n");
2064		BREAK_TO_DEBUGGER();
2065		goto create_fail;
2066	}
2067
2068	/* ABM */
2069	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2070		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2071				&abm_regs[i],
2072				&abm_shift,
2073				&abm_mask);
2074		if (pool->base.multiple_abms[i] == NULL) {
2075			dm_error("DC: failed to create abm for pipe %d!\n", i);
2076			BREAK_TO_DEBUGGER();
2077			goto create_fail;
2078		}
2079	}
2080
2081	/* MPC and DSC */
2082	pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2083	if (pool->base.mpc == NULL) {
2084		BREAK_TO_DEBUGGER();
2085		dm_error("DC: failed to create mpc!\n");
2086		goto create_fail;
2087	}
2088
2089	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2090		pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2091		if (pool->base.dscs[i] == NULL) {
2092			BREAK_TO_DEBUGGER();
2093			dm_error("DC: failed to create display stream compressor %d!\n", i);
2094			goto create_fail;
2095		}
2096	}
2097
2098	/* DWB and MMHUBBUB */
2099	if (!dcn35_dwbc_create(ctx, &pool->base)) {
2100		BREAK_TO_DEBUGGER();
2101		dm_error("DC: failed to create dwbc!\n");
2102		goto create_fail;
2103	}
2104
2105	if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2106		BREAK_TO_DEBUGGER();
2107		dm_error("DC: failed to create mcif_wb!\n");
2108		goto create_fail;
2109	}
2110
2111	/* AUX and I2C */
2112	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2113		pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2114		if (pool->base.engines[i] == NULL) {
2115			BREAK_TO_DEBUGGER();
2116			dm_error(
2117				"DC:failed to create aux engine!!\n");
2118			goto create_fail;
2119		}
2120		pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2121		if (pool->base.hw_i2cs[i] == NULL) {
2122			BREAK_TO_DEBUGGER();
2123			dm_error(
2124				"DC:failed to create hw i2c!!\n");
2125			goto create_fail;
2126		}
2127		pool->base.sw_i2cs[i] = NULL;
2128	}
2129
2130	/* DCN3.5 has 6 DPIA */
2131	pool->base.usb4_dpia_count = 4;
2132	if (dc->debug.dpia_debug.bits.disable_dpia)
2133		pool->base.usb4_dpia_count = 0;
2134
2135	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2136	if (!resource_construct(num_virtual_links, dc, &pool->base,
2137			&res_create_funcs))
2138		goto create_fail;
2139
2140	/* HW Sequencer and Plane caps */
2141	dcn35_hw_sequencer_construct(dc);
2142
2143	dc->caps.max_planes =  pool->base.pipe_count;
2144
2145	for (i = 0; i < dc->caps.max_planes; ++i)
2146		dc->caps.planes[i] = plane_cap;
2147
2148	dc->caps.max_odm_combine_factor = 4;
2149
2150	dc->cap_funcs = cap_funcs;
2151
2152	dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2153
2154	dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2155	dc->dml2_options.use_native_soc_bb_construction = true;
2156	dc->dml2_options.minimize_dispclk_using_odm = false;
2157	if (dc->config.EnableMinDispClkODM)
2158		dc->dml2_options.minimize_dispclk_using_odm = true;
2159	dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2160
2161	resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2162	dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2163
2164	dc->dml2_options.max_segments_per_hubp = 24;
2165	dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2166	dc->dml2_options.override_det_buffer_size_kbytes = true;
2167
2168	if (dc->config.sdpif_request_limit_words_per_umc == 0)
2169		dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2170
2171	return true;
2172
2173create_fail:
2174
2175	dcn36_resource_destruct(pool);
2176
2177	return false;
2178}
2179
2180struct resource_pool *dcn36_create_resource_pool(
2181		const struct dc_init_data *init_data,
2182		struct dc *dc)
2183{
2184	struct dcn36_resource_pool *pool =
2185		kzalloc(sizeof(struct dcn36_resource_pool), GFP_KERNEL);
2186
2187	if (!pool)
2188		return NULL;
2189
2190	if (dcn36_resource_construct(init_data->num_virtual_links, dc, pool))
2191		return &pool->base;
2192
2193	BREAK_TO_DEBUGGER();
2194	kfree(pool);
2195	return NULL;
2196}