dcn351_resource.c

   1/* SPDX-License-Identifier: MIT */
   2/* Copyright 2024 Advanced Micro Devices, Inc. */
   3
   4
   5#include "dm_services.h"
   6#include "dc.h"
   7
   8#include "dcn31/dcn31_init.h"
   9#include "dcn351/dcn351_init.h"
  10
  11#include "resource.h"
  12#include "include/irq_service_interface.h"
  13#include "dcn351_resource.h"
  14
  15#include "dcn20/dcn20_resource.h"
  16#include "dcn30/dcn30_resource.h"
  17#include "dcn31/dcn31_resource.h"
  18#include "dcn32/dcn32_resource.h"
  19#include "dcn35/dcn35_resource.h"
  20
  21#include "dcn10/dcn10_ipp.h"
  22#include "dcn30/dcn30_hubbub.h"
  23#include "dcn31/dcn31_hubbub.h"
  24#include "dcn35/dcn35_hubbub.h"
  25#include "dcn32/dcn32_mpc.h"
  26#include "dcn35/dcn35_hubp.h"
  27#include "irq/dcn351/irq_service_dcn351.h"
  28#include "dcn35/dcn35_dpp.h"
  29#include "dcn35/dcn35_optc.h"
  30#include "dcn20/dcn20_hwseq.h"
  31#include "dcn30/dcn30_hwseq.h"
  32#include "dce110/dce110_hwseq.h"
  33#include "dcn35/dcn35_opp.h"
  34#include "dcn35/dcn35_dsc.h"
  35#include "dcn30/dcn30_vpg.h"
  36#include "dcn30/dcn30_afmt.h"
  37
  38#include "dcn31/dcn31_dio_link_encoder.h"
  39#include "dcn35/dcn35_dio_stream_encoder.h"
  40#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  41#include "dcn31/dcn31_hpo_dp_link_encoder.h"
  42#include "dcn32/dcn32_hpo_dp_link_encoder.h"
  43#include "link_service.h"
  44#include "dcn31/dcn31_apg.h"
  45#include "dcn32/dcn32_dio_link_encoder.h"
  46#include "dcn31/dcn31_vpg.h"
  47#include "dcn31/dcn31_afmt.h"
  48#include "dce/dce_clock_source.h"
  49#include "dce/dce_audio.h"
  50#include "dce/dce_hwseq.h"
  51#include "clk_mgr.h"
  52#include "virtual/virtual_stream_encoder.h"
  53#include "dce110/dce110_resource.h"
  54#include "dml/display_mode_vba.h"
  55#include "dcn35/dcn35_dccg.h"
  56#include "dcn35/dcn35_pg_cntl.h"
  57#include "dcn10/dcn10_resource.h"
  58#include "dcn31/dcn31_panel_cntl.h"
  59#include "dcn35/dcn35_hwseq.h"
  60#include "dcn35/dcn35_dio_link_encoder.h"
  61#include "dml/dcn31/dcn31_fpu.h" /*todo*/
  62#include "dml/dcn35/dcn35_fpu.h"
  63#include "dml/dcn351/dcn351_fpu.h"
  64#include "dcn35/dcn35_dwb.h"
  65#include "dcn35/dcn35_mmhubbub.h"
  66
  67#include "dcn/dcn_3_5_1_offset.h"
  68#include "dcn/dcn_3_5_1_sh_mask.h"
  69#include "nbio/nbio_7_11_0_offset.h"
  70#include "mmhub/mmhub_3_3_0_offset.h"
  71#include "mmhub/mmhub_3_3_0_sh_mask.h"
  72
  73#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                   0x0
  74#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                     0x0000000FL
  75
  76#include "reg_helper.h"
  77#include "dce/dmub_abm.h"
  78#include "dce/dmub_psr.h"
  79#include "dce/dmub_replay.h"
  80#include "dce/dce_aux.h"
  81#include "dce/dce_i2c.h"
  82#include "dml/dcn31/display_mode_vba_31.h" /*temp*/
  83#include "vm_helper.h"
  84#include "dcn20/dcn20_vmid.h"
  85
  86#include "dml2_0/dml2_wrapper.h"
  87
  88#include "link_enc_cfg.h"
  89#define DC_LOGGER_INIT(logger)
  90
  91enum dcn351_clk_src_array_id {
  92	DCN351_CLK_SRC_PLL0,
  93	DCN351_CLK_SRC_PLL1,
  94	DCN351_CLK_SRC_PLL2,
  95	DCN351_CLK_SRC_PLL3,
  96	DCN351_CLK_SRC_PLL4,
  97	DCN351_CLK_SRC_TOTAL
  98};
  99
 100/* begin *********************
 101 * macros to expend register list macro defined in HW object header file
 102 */
 103
 104/* DCN */
 105/* TODO awful hack. fixup dcn20_dwb.h */
 106#undef BASE_INNER
 107#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
 108
 109#define BASE(seg) BASE_INNER(seg)
 110
 111#define SR(reg_name)\
 112		REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 113					reg ## reg_name
 114
 115#define SR_ARR(reg_name, id) \
 116	REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 117
 118#define SR_ARR_INIT(reg_name, id, value) \
 119	REG_STRUCT[id].reg_name = value
 120
 121#define SRI(reg_name, block, id)\
 122	REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 123					reg ## block ## id ## _ ## reg_name
 124
 125#define SRI_ARR(reg_name, block, id)\
 126	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 127		reg ## block ## id ## _ ## reg_name
 128
 129#define SR_ARR_I2C(reg_name, id) \
 130	REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 131
 132#define SRI_ARR_I2C(reg_name, block, id)\
 133	REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 134		reg ## block ## id ## _ ## reg_name
 135
 136#define SRI_ARR_ALPHABET(reg_name, block, index, id)\
 137	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 138		reg ## block ## id ## _ ## reg_name
 139
 140#define SRI2(reg_name, block, id)\
 141	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 142					reg ## reg_name
 143
 144#define SRI2_ARR(reg_name, block, id)\
 145	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +	\
 146		reg ## reg_name
 147
 148#define SRIR(var_name, reg_name, block, id)\
 149	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 150					reg ## block ## id ## _ ## reg_name
 151
 152#define SRII(reg_name, block, id)\
 153	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 154					reg ## block ## id ## _ ## reg_name
 155
 156#define SRII_ARR_2(reg_name, block, id, inst)\
 157	REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 158		reg ## block ## id ## _ ## reg_name
 159
 160#define SRII_MPC_RMU(reg_name, block, id)\
 161	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 162					reg ## block ## id ## _ ## reg_name
 163
 164#define SRII_DWB(reg_name, temp_name, block, id)\
 165	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 166		reg ## block ## id ## _ ## temp_name
 167
 168#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
 169	.field_name = reg_name ## __ ## field_name ## post_fix
 170
 171#define DCCG_SRII(reg_name, block, id)\
 172	REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 173		reg ## block ## id ## _ ## reg_name
 174
 175#define VUPDATE_SRII(reg_name, block, id)\
 176	REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 177		reg ## reg_name ## _ ## block ## id
 178
 179/* NBIO */
 180#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
 181
 182#define NBIO_BASE(seg) \
 183	NBIO_BASE_INNER(seg)
 184
 185#define NBIO_SR(reg_name)\
 186	REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
 187				regBIF_BX1_ ## reg_name
 188
 189#define NBIO_SR_ARR(reg_name, id)\
 190	REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
 191		regBIF_BX1_ ## reg_name
 192
 193#define bios_regs_init() \
 194		( \
 195		NBIO_SR(BIOS_SCRATCH_3),\
 196		NBIO_SR(BIOS_SCRATCH_6)\
 197		)
 198
 199static struct bios_registers bios_regs;
 200
 201#define clk_src_regs_init(index, pllid)\
 202	CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
 203
 204static struct dce110_clk_src_regs clk_src_regs[5];
 205
 206static const struct dce110_clk_src_shift cs_shift = {
 207		CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
 208};
 209
 210static const struct dce110_clk_src_mask cs_mask = {
 211		CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
 212};
 213
 214#define abm_regs_init(id)\
 215		ABM_DCN32_REG_LIST_RI(id)
 216
 217static struct dce_abm_registers abm_regs[4];
 218
 219static const struct dce_abm_shift abm_shift = {
 220		ABM_MASK_SH_LIST_DCN35(__SHIFT)
 221};
 222
 223static const struct dce_abm_mask abm_mask = {
 224		ABM_MASK_SH_LIST_DCN35(_MASK)
 225};
 226
 227#define audio_regs_init(id)\
 228		AUD_COMMON_REG_LIST_RI(id)
 229
 230static struct dce_audio_registers audio_regs[7];
 231
 232
 233#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 234		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 235		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 236		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 237
 238static const struct dce_audio_shift audio_shift = {
 239		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 240};
 241
 242static const struct dce_audio_mask audio_mask = {
 243		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 244};
 245
 246#define vpg_regs_init(id)\
 247	VPG_DCN31_REG_LIST_RI(id)
 248
 249static struct dcn31_vpg_registers vpg_regs[10];
 250
 251static const struct dcn31_vpg_shift vpg_shift = {
 252	DCN31_VPG_MASK_SH_LIST(__SHIFT)
 253};
 254
 255static const struct dcn31_vpg_mask vpg_mask = {
 256	DCN31_VPG_MASK_SH_LIST(_MASK)
 257};
 258
 259#define afmt_regs_init(id)\
 260	AFMT_DCN31_REG_LIST_RI(id)
 261
 262static struct dcn31_afmt_registers afmt_regs[6];
 263
 264static const struct dcn31_afmt_shift afmt_shift = {
 265	DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 266};
 267
 268static const struct dcn31_afmt_mask afmt_mask = {
 269	DCN31_AFMT_MASK_SH_LIST(_MASK)
 270};
 271
 272#define apg_regs_init(id)\
 273	APG_DCN31_REG_LIST_RI(id)
 274
 275static struct dcn31_apg_registers apg_regs[4];
 276
 277static const struct dcn31_apg_shift apg_shift = {
 278	DCN31_APG_MASK_SH_LIST(__SHIFT)
 279};
 280
 281static const struct dcn31_apg_mask apg_mask = {
 282	DCN31_APG_MASK_SH_LIST(_MASK)
 283};
 284
 285#define stream_enc_regs_init(id)\
 286	SE_DCN35_REG_LIST_RI(id)
 287
 288static struct dcn10_stream_enc_registers stream_enc_regs[5];
 289
 290static const struct dcn10_stream_encoder_shift se_shift = {
 291		SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 292};
 293
 294static const struct dcn10_stream_encoder_mask se_mask = {
 295		SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
 296};
 297
 298#define aux_regs_init(id)\
 299	DCN2_AUX_REG_LIST_RI(id)
 300
 301static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
 302
 303#define hpd_regs_init(id)\
 304	HPD_REG_LIST_RI(id)
 305
 306static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
 307
 308
 309static const struct dce110_aux_registers_shift aux_shift = {
 310	DCN_AUX_MASK_SH_LIST(__SHIFT)
 311};
 312
 313static const struct dce110_aux_registers_mask aux_mask = {
 314	DCN_AUX_MASK_SH_LIST(_MASK)
 315};
 316
 317#define link_regs_init(id, phyid)\
 318	( \
 319	LE_DCN35_REG_LIST_RI(id), \
 320	UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
 321	)
 322
 323static struct dcn10_link_enc_registers link_enc_regs[5];
 324
 325static const struct dcn10_link_enc_shift le_shift = {
 326	LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
 327	//DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 328};
 329
 330static const struct dcn10_link_enc_mask le_mask = {
 331	LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
 332	//DPCS_DCN31_MASK_SH_LIST(_MASK)
 333};
 334
 335#define hpo_dp_stream_encoder_reg_init(id)\
 336	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
 337
 338static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
 339
 340static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 341	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 342};
 343
 344static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 345	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 346};
 347
 348#define hpo_dp_link_encoder_reg_init(id)\
 349	DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
 350	/*DCN3_1_RDPCSTX_REG_LIST(0),*/
 351	/*DCN3_1_RDPCSTX_REG_LIST(1),*/
 352	/*DCN3_1_RDPCSTX_REG_LIST(2),*/
 353	/*DCN3_1_RDPCSTX_REG_LIST(3),*/
 354
 355static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
 356
 357static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 358	DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
 359};
 360
 361static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 362	DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
 363};
 364
 365#define dpp_regs_init(id)\
 366	DPP_REG_LIST_DCN35_RI(id)
 367
 368static struct dcn3_dpp_registers dpp_regs[4];
 369
 370static const struct dcn35_dpp_shift tf_shift = {
 371		DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
 372};
 373
 374static const struct dcn35_dpp_mask tf_mask = {
 375		DPP_REG_LIST_SH_MASK_DCN35(_MASK)
 376};
 377
 378#define opp_regs_init(id)\
 379	OPP_REG_LIST_DCN35_RI(id)
 380
 381static struct dcn35_opp_registers opp_regs[4];
 382
 383static const struct dcn35_opp_shift opp_shift = {
 384	OPP_MASK_SH_LIST_DCN35(__SHIFT)
 385};
 386
 387static const struct dcn35_opp_mask opp_mask = {
 388	OPP_MASK_SH_LIST_DCN35(_MASK)
 389};
 390
 391#define aux_engine_regs_init(id)\
 392	( \
 393	AUX_COMMON_REG_LIST0_RI(id), \
 394	SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
 395	SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
 396	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
 397	)
 398
 399static struct dce110_aux_registers aux_engine_regs[5];
 400
 401#define dwbc_regs_dcn3_init(id)\
 402	DWBC_COMMON_REG_LIST_DCN30_RI(id)
 403
 404static struct dcn30_dwbc_registers dwbc35_regs[1];
 405
 406static const struct dcn35_dwbc_shift dwbc35_shift = {
 407	DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 408};
 409
 410static const struct dcn35_dwbc_mask dwbc35_mask = {
 411	DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
 412};
 413
 414#define mcif_wb_regs_dcn3_init(id)\
 415	MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
 416
 417static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
 418
 419static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
 420	MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 421};
 422
 423static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
 424	MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 425};
 426
 427#define dsc_regsDCN35_init(id)\
 428	DSC_REG_LIST_DCN20_RI(id)
 429
 430static struct dcn20_dsc_registers dsc_regs[4];
 431
 432static const struct dcn35_dsc_shift dsc_shift = {
 433	DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
 434};
 435
 436static const struct dcn35_dsc_mask dsc_mask = {
 437	DSC_REG_LIST_SH_MASK_DCN35(_MASK)
 438};
 439
 440static struct dcn30_mpc_registers mpc_regs;
 441
 442#define dcn_mpc_regs_init() \
 443	MPC_REG_LIST_DCN3_2_RI(0),\
 444	MPC_REG_LIST_DCN3_2_RI(1),\
 445	MPC_REG_LIST_DCN3_2_RI(2),\
 446	MPC_REG_LIST_DCN3_2_RI(3),\
 447	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
 448	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
 449	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
 450	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
 451	MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
 452
 453static const struct dcn30_mpc_shift mpc_shift = {
 454	MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 455};
 456
 457static const struct dcn30_mpc_mask mpc_mask = {
 458	MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
 459};
 460
 461#define optc_regs_init(id)\
 462	OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
 463
 464static struct dcn_optc_registers optc_regs[4];
 465
 466static const struct dcn_optc_shift optc_shift = {
 467	OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 468};
 469
 470static const struct dcn_optc_mask optc_mask = {
 471	OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 472};
 473
 474#define hubp_regs_init(id)\
 475	HUBP_REG_LIST_DCN30_RI(id)
 476
 477static struct dcn_hubp2_registers hubp_regs[4];
 478
 479
 480static const struct dcn35_hubp2_shift hubp_shift = {
 481		HUBP_MASK_SH_LIST_DCN35(__SHIFT)
 482};
 483
 484static const struct dcn35_hubp2_mask hubp_mask = {
 485		HUBP_MASK_SH_LIST_DCN35(_MASK)
 486};
 487
 488static struct dcn_hubbub_registers hubbub_reg;
 489
 490#define hubbub_reg_init()\
 491		HUBBUB_REG_LIST_DCN35(0)
 492
 493static const struct dcn_hubbub_shift hubbub_shift = {
 494		HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
 495};
 496
 497static const struct dcn_hubbub_mask hubbub_mask = {
 498		HUBBUB_MASK_SH_LIST_DCN35(_MASK)
 499};
 500
 501static struct dccg_registers dccg_regs;
 502
 503#define dccg_regs_init()\
 504	DCCG_REG_LIST_DCN35()
 505
 506static const struct dccg_shift dccg_shift = {
 507		DCCG_MASK_SH_LIST_DCN35(__SHIFT)
 508};
 509
 510static const struct dccg_mask dccg_mask = {
 511		DCCG_MASK_SH_LIST_DCN35(_MASK)
 512};
 513
 514static struct pg_cntl_registers pg_cntl_regs;
 515
 516#define pg_cntl_dcn35_regs_init() \
 517	PG_CNTL_REG_LIST_DCN35()
 518
 519static const struct pg_cntl_shift pg_cntl_shift = {
 520		PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
 521};
 522
 523static const struct pg_cntl_mask pg_cntl_mask = {
 524		PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
 525};
 526
 527#define SRII2(reg_name_pre, reg_name_post, id)\
 528	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 529			## id ## _ ## reg_name_post ## _BASE_IDX) + \
 530			reg ## reg_name_pre ## id ## _ ## reg_name_post
 531
 532static struct dce_hwseq_registers hwseq_reg;
 533
 534#define hwseq_reg_init()\
 535	HWSEQ_DCN35_REG_LIST()
 536
 537#define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
 538	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 539	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 540	HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 541	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 542	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 543	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 544	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 545	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 546	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 547	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 548	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 549	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 550	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 551	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 552	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 553	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 554	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 555	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 556	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 557	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 558	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 559	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 560	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 561	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 562	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 563	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 564	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 565	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 566	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 567	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 568	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 569	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 570	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 571	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 572	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 573	HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 574	HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 575	HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 576	HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 577	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 578	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 579	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 580	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 581	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 582	HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 583	HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
 584	HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
 585	HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
 586	HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
 587	HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 588	HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 589	HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 590	HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 591	HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 592	HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
 593	HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
 594	HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
 595	HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
 596	HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
 597	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
 598	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
 599	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
 600	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
 601	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
 602	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
 603	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
 604	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
 605	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
 606	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
 607	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
 608	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 609	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 610	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 611	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 612	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
 613	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
 614	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
 615	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
 616	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
 617	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
 618	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
 619	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
 620	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
 621	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
 622	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
 623	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
 624	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
 625
 626static const struct dce_hwseq_shift hwseq_shift = {
 627		HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
 628};
 629
 630static const struct dce_hwseq_mask hwseq_mask = {
 631		HWSEQ_DCN35_MASK_SH_LIST(_MASK)
 632};
 633
 634#define vmid_regs_init(id)\
 635		DCN20_VMID_REG_LIST_RI(id)
 636
 637static struct dcn_vmid_registers vmid_regs[16];
 638
 639static const struct dcn20_vmid_shift vmid_shifts = {
 640		DCN20_VMID_MASK_SH_LIST(__SHIFT)
 641};
 642
 643static const struct dcn20_vmid_mask vmid_masks = {
 644		DCN20_VMID_MASK_SH_LIST(_MASK)
 645};
 646
 647static const struct resource_caps res_cap_dcn351 = {
 648	.num_timing_generator = 4,
 649	.num_opp = 4,
 650	.num_video_plane = 4,
 651	.num_audio = 5,
 652	.num_stream_encoder = 5,
 653	.num_dig_link_enc = 5,
 654	.num_hpo_dp_stream_encoder = 4,
 655	.num_hpo_dp_link_encoder = 2,
 656	.num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
 657	.num_dwb = 1,
 658	.num_ddc = 5,
 659	.num_vmid = 16,
 660	.num_mpc_3dlut = 2,
 661	.num_dsc = 4,
 662};
 663
 664static const struct dc_plane_cap plane_cap = {
 665	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 666	.per_pixel_alpha = true,
 667
 668	.pixel_format_support = {
 669			.argb8888 = true,
 670			.nv12 = true,
 671			.fp16 = true,
 672			.p010 = true,
 673			.ayuv = false,
 674	},
 675
 676	.max_upscale_factor = {
 677			.argb8888 = 16000,
 678			.nv12 = 16000,
 679			.fp16 = 16000
 680	},
 681
 682	// 6:1 downscaling ratio: 1000/6 = 166.666
 683	.max_downscale_factor = {
 684			.argb8888 = 250,
 685			.nv12 = 167,
 686			.fp16 = 167
 687	},
 688	64,
 689	64
 690};
 691
 692static const struct dc_debug_options debug_defaults_drv = {
 693	.disable_dmcu = true,
 694	.force_abm_enable = false,
 695	.clock_trace = true,
 696	.disable_pplib_clock_request = false,
 697	.pipe_split_policy = MPC_SPLIT_AVOID,
 698	.force_single_disp_pipe_split = false,
 699	.disable_dcc = DCC_ENABLE,
 700	.disable_dpp_power_gate = true,
 701	.disable_hubp_power_gate = true,
 702	.disable_optc_power_gate = true, /*should the same as above two*/
 703	.disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
 704	.disable_clock_gate = false,
 705	.disable_dsc_power_gate = true,
 706	.vsr_support = true,
 707	.performance_trace = false,
 708	.max_downscale_src_width = 4096,/*upto true 4k*/
 709	.disable_pplib_wm_range = false,
 710	.scl_reset_length10 = true,
 711	.sanity_checks = false,
 712	.underflow_assert_delay_us = 0xFFFFFFFF,
 713	.dwb_fi_phase = -1, // -1 = disable,
 714	.dmub_command_table = true,
 715	.pstate_enabled = true,
 716	.use_max_lb = true,
 717	.enable_mem_low_power = {
 718		.bits = {
 719			.vga = false,
 720			.i2c = true,
 721			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 722			.dscl = true,
 723			.cm = true,
 724			.mpc = true,
 725			.optc = true,
 726			.vpg = true,
 727			.afmt = true,
 728		}
 729	},
 730	.root_clock_optimization = {
 731		.bits = {
 732			.dpp = true,
 733			.dsc = true,/*dscclk and dsc pg*/
 734			.hdmistream = true,
 735			.hdmichar = true,
 736			.dpstream = true,
 737			.symclk32_se = true,
 738			.symclk32_le = false,
 739			.symclk_fe = true,
 740			.physymclk = false,
 741			.dpiasymclk = true,
 742		}
 743	},
 744	.seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
 745	.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
 746	.minimum_z8_residency_time = 1,
 747	.using_dml2 = true,
 748	.support_eDP1_5 = true,
 749	.enable_hpo_pg_support = false,
 750	.enable_single_display_2to1_odm_policy = true,
 751	.disable_idle_power_optimizations = false,
 752	.dmcub_emulation = false,
 753	.disable_boot_optimizations = false,
 754	.disable_unbounded_requesting = false,
 755	.disable_mem_low_power = false,
 756	//must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
 757	.enable_double_buffered_dsc_pg_support = true,
 758	.enable_dp_dig_pixel_rate_div_policy = 1,
 759	.disable_z10 = false,
 760	.ignore_pg = true,
 761	.psp_disabled_wa = true,
 762	.ips2_eval_delay_us = 2000,
 763	.ips2_entry_delay_us = 800,
 764	.disable_dmub_reallow_idle = false,
 765	.static_screen_wait_frames = 2,
 766	.notify_dpia_hr_bw = true,
 767	.min_disp_clk_khz = 50000,
 768};
 769
 770static const struct dc_check_config config_defaults = {
 771	.enable_legacy_fast_update = true,
 772};
 773
 774static const struct dc_panel_config panel_config_defaults = {
 775	.psr = {
 776		.disable_psr = false,
 777		.disallow_psrsu = false,
 778		.disallow_replay = false,
 779	},
 780	.ilr = {
 781		.optimize_edp_link_rate = true,
 782	},
 783};
 784
 785static void dcn35_dpp_destroy(struct dpp **dpp)
 786{
 787	kfree(TO_DCN20_DPP(*dpp));
 788	*dpp = NULL;
 789}
 790
 791static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
 792{
 793	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 794	bool success = (dpp != NULL);
 795
 796	if (!success)
 797		return NULL;
 798
 799#undef REG_STRUCT
 800#define REG_STRUCT dpp_regs
 801	dpp_regs_init(0),
 802	dpp_regs_init(1),
 803	dpp_regs_init(2),
 804	dpp_regs_init(3);
 805
 806	success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
 807				  &tf_mask);
 808	if (success) {
 809		dpp35_set_fgcg(
 810			dpp,
 811			ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
 812		return &dpp->base;
 813	}
 814
 815	BREAK_TO_DEBUGGER();
 816	kfree(dpp);
 817	return NULL;
 818}
 819
 820static struct output_pixel_processor *dcn35_opp_create(
 821	struct dc_context *ctx, uint32_t inst)
 822{
 823	struct dcn20_opp *opp =
 824		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 825
 826	if (!opp) {
 827		BREAK_TO_DEBUGGER();
 828		return NULL;
 829	}
 830
 831#undef REG_STRUCT
 832#define REG_STRUCT opp_regs
 833	opp_regs_init(0),
 834	opp_regs_init(1),
 835	opp_regs_init(2),
 836	opp_regs_init(3);
 837
 838	dcn35_opp_construct(opp, ctx, inst,
 839			&opp_regs[inst], &opp_shift, &opp_mask);
 840
 841	dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
 842
 843	return &opp->base;
 844}
 845
 846static struct dce_aux *dcn31_aux_engine_create(
 847	struct dc_context *ctx,
 848	uint32_t inst)
 849{
 850	struct aux_engine_dce110 *aux_engine =
 851		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 852
 853	if (!aux_engine)
 854		return NULL;
 855
 856#undef REG_STRUCT
 857#define REG_STRUCT aux_engine_regs
 858	aux_engine_regs_init(0),
 859	aux_engine_regs_init(1),
 860	aux_engine_regs_init(2),
 861	aux_engine_regs_init(3),
 862	aux_engine_regs_init(4);
 863
 864	dce110_aux_engine_construct(aux_engine, ctx, inst,
 865				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 866				    &aux_engine_regs[inst],
 867					&aux_mask,
 868					&aux_shift,
 869					ctx->dc->caps.extended_aux_timeout_support);
 870
 871	return &aux_engine->base;
 872}
 873
 874#define i2c_inst_regs_init(id)\
 875	I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
 876
 877static struct dce_i2c_registers i2c_hw_regs[5];
 878
 879static const struct dce_i2c_shift i2c_shifts = {
 880		I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 881};
 882
 883static const struct dce_i2c_mask i2c_masks = {
 884		I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
 885};
 886
 887/* ========================================================== */
 888
 889/*
 890 * DPIA index | Preferred Encoder     |    Host Router
 891 *   0        |      C                |       0
 892 *   1        |      First Available  |       0
 893 *   2        |      D                |       1
 894 *   3        |      First Available  |       1
 895 */
 896/* ========================================================== */
 897static const enum engine_id dpia_to_preferred_enc_id_table[] = {
 898		ENGINE_ID_DIGC,
 899		ENGINE_ID_DIGC,
 900		ENGINE_ID_DIGD,
 901		ENGINE_ID_DIGD
 902};
 903
 904static enum engine_id dcn351_get_preferred_eng_id_dpia(unsigned int dpia_index)
 905{
 906	return dpia_to_preferred_enc_id_table[dpia_index];
 907}
 908
 909static struct dce_i2c_hw *dcn31_i2c_hw_create(
 910	struct dc_context *ctx,
 911	uint32_t inst)
 912{
 913	struct dce_i2c_hw *dce_i2c_hw =
 914		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 915
 916	if (!dce_i2c_hw)
 917		return NULL;
 918
 919#undef REG_STRUCT
 920#define REG_STRUCT i2c_hw_regs
 921	i2c_inst_regs_init(1),
 922	i2c_inst_regs_init(2),
 923	i2c_inst_regs_init(3),
 924	i2c_inst_regs_init(4),
 925	i2c_inst_regs_init(5);
 926
 927	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 928				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 929
 930	return dce_i2c_hw;
 931}
 932static struct mpc *dcn35_mpc_create(
 933		struct dc_context *ctx,
 934		int num_mpcc,
 935		int num_rmu)
 936{
 937	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
 938
 939	if (!mpc30)
 940		return NULL;
 941
 942#undef REG_STRUCT
 943#define REG_STRUCT mpc_regs
 944	dcn_mpc_regs_init();
 945
 946	dcn32_mpc_construct(mpc30, ctx,
 947			&mpc_regs,
 948			&mpc_shift,
 949			&mpc_mask,
 950			num_mpcc,
 951			num_rmu);
 952
 953	return &mpc30->base;
 954}
 955
 956static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
 957{
 958	int i;
 959
 960	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
 961					  GFP_KERNEL);
 962
 963	if (!hubbub3)
 964		return NULL;
 965
 966#undef REG_STRUCT
 967#define REG_STRUCT hubbub_reg
 968	hubbub_reg_init();
 969
 970#undef REG_STRUCT
 971#define REG_STRUCT vmid_regs
 972	vmid_regs_init(0),
 973	vmid_regs_init(1),
 974	vmid_regs_init(2),
 975	vmid_regs_init(3),
 976	vmid_regs_init(4),
 977	vmid_regs_init(5),
 978	vmid_regs_init(6),
 979	vmid_regs_init(7),
 980	vmid_regs_init(8),
 981	vmid_regs_init(9),
 982	vmid_regs_init(10),
 983	vmid_regs_init(11),
 984	vmid_regs_init(12),
 985	vmid_regs_init(13),
 986	vmid_regs_init(14),
 987	vmid_regs_init(15);
 988
 989	hubbub35_construct(hubbub3, ctx,
 990			&hubbub_reg,
 991			&hubbub_shift,
 992			&hubbub_mask,
 993			384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
 994			8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
 995			1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
 996
 997
 998	for (i = 0; i < res_cap_dcn351.num_vmid; i++) {
 999		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1000
1001		vmid->ctx = ctx;
1002
1003		vmid->regs = &vmid_regs[i];
1004		vmid->shifts = &vmid_shifts;
1005		vmid->masks = &vmid_masks;
1006	}
1007
1008	return &hubbub3->base;
1009}
1010
1011static struct timing_generator *dcn35_timing_generator_create(
1012		struct dc_context *ctx,
1013		uint32_t instance)
1014{
1015	struct optc *tgn10 =
1016		kzalloc(sizeof(struct optc), GFP_KERNEL);
1017
1018	if (!tgn10)
1019		return NULL;
1020
1021#undef REG_STRUCT
1022#define REG_STRUCT optc_regs
1023	optc_regs_init(0),
1024	optc_regs_init(1),
1025	optc_regs_init(2),
1026	optc_regs_init(3);
1027
1028	tgn10->base.inst = instance;
1029	tgn10->base.ctx = ctx;
1030
1031	tgn10->tg_regs = &optc_regs[instance];
1032	tgn10->tg_shift = &optc_shift;
1033	tgn10->tg_mask = &optc_mask;
1034
1035	dcn35_timing_generator_init(tgn10);
1036
1037	return &tgn10->base;
1038}
1039
1040static const struct encoder_feature_support link_enc_feature = {
1041		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1042		.max_hdmi_pixel_clock = 600000,
1043		.hdmi_ycbcr420_supported = true,
1044		.dp_ycbcr420_supported = true,
1045		.fec_supported = true,
1046		.flags.bits.IS_HBR2_CAPABLE = true,
1047		.flags.bits.IS_HBR3_CAPABLE = true,
1048		.flags.bits.IS_TPS3_CAPABLE = true,
1049		.flags.bits.IS_TPS4_CAPABLE = true
1050};
1051
1052static struct link_encoder *dcn35_link_encoder_create(
1053	struct dc_context *ctx,
1054	const struct encoder_init_data *enc_init_data)
1055{
1056	struct dcn20_link_encoder *enc20 =
1057		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1058
1059	if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1060		return NULL;
1061
1062#undef REG_STRUCT
1063#define REG_STRUCT link_enc_aux_regs
1064	aux_regs_init(0),
1065	aux_regs_init(1),
1066	aux_regs_init(2),
1067	aux_regs_init(3),
1068	aux_regs_init(4);
1069
1070#undef REG_STRUCT
1071#define REG_STRUCT link_enc_hpd_regs
1072	hpd_regs_init(0),
1073	hpd_regs_init(1),
1074	hpd_regs_init(2),
1075	hpd_regs_init(3),
1076	hpd_regs_init(4);
1077
1078#undef REG_STRUCT
1079#define REG_STRUCT link_enc_regs
1080	link_regs_init(0, A),
1081	link_regs_init(1, B),
1082	link_regs_init(2, C),
1083	link_regs_init(3, D),
1084	link_regs_init(4, E);
1085
1086	dcn35_link_encoder_construct(enc20,
1087			enc_init_data,
1088			&link_enc_feature,
1089			&link_enc_regs[enc_init_data->transmitter],
1090			&link_enc_aux_regs[enc_init_data->channel - 1],
1091			&link_enc_hpd_regs[enc_init_data->hpd_source],
1092			&le_shift,
1093			&le_mask);
1094
1095	return &enc20->enc10.base;
1096}
1097
1098/* Create a minimal link encoder object not associated with a particular
1099 * physical connector.
1100 * resource_funcs.link_enc_create_minimal
1101 */
1102static struct link_encoder *dcn31_link_enc_create_minimal(
1103		struct dc_context *ctx, enum engine_id eng_id)
1104{
1105	struct dcn20_link_encoder *enc20;
1106
1107	if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1108		return NULL;
1109
1110	enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1111	if (!enc20)
1112		return NULL;
1113
1114	dcn31_link_encoder_construct_minimal(
1115			enc20,
1116			ctx,
1117			&link_enc_feature,
1118			&link_enc_regs[eng_id - ENGINE_ID_DIGA],
1119			eng_id);
1120
1121	return &enc20->enc10.base;
1122}
1123
1124static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1125{
1126	struct dcn31_panel_cntl *panel_cntl =
1127		kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1128
1129	if (!panel_cntl)
1130		return NULL;
1131
1132	dcn31_panel_cntl_construct(panel_cntl, init_data);
1133
1134	return &panel_cntl->base;
1135}
1136
1137static void read_dce_straps(
1138	struct dc_context *ctx,
1139	struct resource_straps *straps)
1140{
1141	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1142		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1143
1144}
1145
1146static struct audio *dcn31_create_audio(
1147		struct dc_context *ctx, unsigned int inst)
1148{
1149
1150#undef REG_STRUCT
1151#define REG_STRUCT audio_regs
1152	audio_regs_init(0),
1153	audio_regs_init(1),
1154	audio_regs_init(2),
1155	audio_regs_init(3),
1156	audio_regs_init(4);
1157	audio_regs_init(5);
1158	audio_regs_init(6);
1159
1160	return dce_audio_create(ctx, inst,
1161			&audio_regs[inst], &audio_shift, &audio_mask);
1162}
1163
1164static struct vpg *dcn31_vpg_create(
1165	struct dc_context *ctx,
1166	uint32_t inst)
1167{
1168	struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1169
1170	if (!vpg31)
1171		return NULL;
1172
1173#undef REG_STRUCT
1174#define REG_STRUCT vpg_regs
1175	vpg_regs_init(0),
1176	vpg_regs_init(1),
1177	vpg_regs_init(2),
1178	vpg_regs_init(3),
1179	vpg_regs_init(4),
1180	vpg_regs_init(5),
1181	vpg_regs_init(6),
1182	vpg_regs_init(7),
1183	vpg_regs_init(8),
1184	vpg_regs_init(9);
1185
1186	vpg31_construct(vpg31, ctx, inst,
1187			&vpg_regs[inst],
1188			&vpg_shift,
1189			&vpg_mask);
1190
1191	return &vpg31->base;
1192}
1193
1194static struct afmt *dcn31_afmt_create(
1195	struct dc_context *ctx,
1196	uint32_t inst)
1197{
1198	struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1199
1200	if (!afmt31)
1201		return NULL;
1202
1203#undef REG_STRUCT
1204#define REG_STRUCT afmt_regs
1205	afmt_regs_init(0),
1206	afmt_regs_init(1),
1207	afmt_regs_init(2),
1208	afmt_regs_init(3),
1209	afmt_regs_init(4),
1210	afmt_regs_init(5);
1211
1212	afmt31_construct(afmt31, ctx, inst,
1213			&afmt_regs[inst],
1214			&afmt_shift,
1215			&afmt_mask);
1216
1217	// Light sleep by default, no need to power down here
1218
1219	return &afmt31->base;
1220}
1221
1222static struct apg *dcn31_apg_create(
1223	struct dc_context *ctx,
1224	uint32_t inst)
1225{
1226	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1227
1228	if (!apg31)
1229		return NULL;
1230
1231#undef REG_STRUCT
1232#define REG_STRUCT apg_regs
1233	apg_regs_init(0),
1234	apg_regs_init(1),
1235	apg_regs_init(2),
1236	apg_regs_init(3);
1237
1238	apg31_construct(apg31, ctx, inst,
1239			&apg_regs[inst],
1240			&apg_shift,
1241			&apg_mask);
1242
1243	return &apg31->base;
1244}
1245
1246static struct stream_encoder *dcn35_stream_encoder_create(
1247	enum engine_id eng_id,
1248	struct dc_context *ctx)
1249{
1250	struct dcn10_stream_encoder *enc1;
1251	struct vpg *vpg;
1252	struct afmt *afmt;
1253	int vpg_inst;
1254	int afmt_inst;
1255
1256	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1257	if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1258		return NULL;
1259
1260	vpg_inst = eng_id;
1261	afmt_inst = eng_id;
1262
1263	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1264	vpg = dcn31_vpg_create(ctx, vpg_inst);
1265	afmt = dcn31_afmt_create(ctx, afmt_inst);
1266
1267	if (!enc1 || !vpg || !afmt) {
1268		kfree(enc1);
1269		kfree(vpg);
1270		kfree(afmt);
1271		return NULL;
1272	}
1273
1274#undef REG_STRUCT
1275#define REG_STRUCT stream_enc_regs
1276	stream_enc_regs_init(0),
1277	stream_enc_regs_init(1),
1278	stream_enc_regs_init(2),
1279	stream_enc_regs_init(3),
1280	stream_enc_regs_init(4);
1281
1282	dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1283					eng_id, vpg, afmt,
1284					&stream_enc_regs[eng_id],
1285					&se_shift, &se_mask);
1286
1287	return &enc1->base;
1288}
1289
1290static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1291	enum engine_id eng_id,
1292	struct dc_context *ctx)
1293{
1294	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1295	struct vpg *vpg;
1296	struct apg *apg;
1297	uint32_t hpo_dp_inst;
1298	uint32_t vpg_inst;
1299	uint32_t apg_inst;
1300
1301	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1302	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1303
1304	/* Mapping of VPG register blocks to HPO DP block instance:
1305	 * VPG[6] -> HPO_DP[0]
1306	 * VPG[7] -> HPO_DP[1]
1307	 * VPG[8] -> HPO_DP[2]
1308	 * VPG[9] -> HPO_DP[3]
1309	 */
1310	vpg_inst = hpo_dp_inst + 6;
1311
1312	/* Mapping of APG register blocks to HPO DP block instance:
1313	 * APG[0] -> HPO_DP[0]
1314	 * APG[1] -> HPO_DP[1]
1315	 * APG[2] -> HPO_DP[2]
1316	 * APG[3] -> HPO_DP[3]
1317	 */
1318	apg_inst = hpo_dp_inst;
1319
1320	/* allocate HPO stream encoder and create VPG sub-block */
1321	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1322	vpg = dcn31_vpg_create(ctx, vpg_inst);
1323	apg = dcn31_apg_create(ctx, apg_inst);
1324
1325	if (!hpo_dp_enc31 || !vpg || !apg) {
1326		kfree(hpo_dp_enc31);
1327		kfree(vpg);
1328		kfree(apg);
1329		return NULL;
1330	}
1331
1332#undef REG_STRUCT
1333#define REG_STRUCT hpo_dp_stream_enc_regs
1334	hpo_dp_stream_encoder_reg_init(0),
1335	hpo_dp_stream_encoder_reg_init(1),
1336	hpo_dp_stream_encoder_reg_init(2),
1337	hpo_dp_stream_encoder_reg_init(3);
1338
1339	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1340					hpo_dp_inst, eng_id, vpg, apg,
1341					&hpo_dp_stream_enc_regs[hpo_dp_inst],
1342					&hpo_dp_se_shift, &hpo_dp_se_mask);
1343
1344	return &hpo_dp_enc31->base;
1345}
1346
1347static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1348	uint8_t inst,
1349	struct dc_context *ctx)
1350{
1351	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1352
1353	/* allocate HPO link encoder */
1354	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1355	if (!hpo_dp_enc31)
1356		return NULL; /* out of memory */
1357
1358#undef REG_STRUCT
1359#define REG_STRUCT hpo_dp_link_enc_regs
1360	hpo_dp_link_encoder_reg_init(0),
1361	hpo_dp_link_encoder_reg_init(1);
1362
1363	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1364					&hpo_dp_link_enc_regs[inst],
1365					&hpo_dp_le_shift, &hpo_dp_le_mask);
1366
1367	return &hpo_dp_enc31->base;
1368}
1369
1370static struct dce_hwseq *dcn351_hwseq_create(
1371	struct dc_context *ctx)
1372{
1373	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1374
1375#undef REG_STRUCT
1376#define REG_STRUCT hwseq_reg
1377	hwseq_reg_init();
1378
1379	if (hws) {
1380		hws->ctx = ctx;
1381		hws->regs = &hwseq_reg;
1382		hws->shifts = &hwseq_shift;
1383		hws->masks = &hwseq_mask;
1384	}
1385	return hws;
1386}
1387static const struct resource_create_funcs res_create_funcs = {
1388	.read_dce_straps = read_dce_straps,
1389	.create_audio = dcn31_create_audio,
1390	.create_stream_encoder = dcn35_stream_encoder_create,
1391	.create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1392	.create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1393	.create_hwseq = dcn351_hwseq_create,
1394};
1395
1396static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)
1397{
1398	unsigned int i;
1399
1400	for (i = 0; i < pool->base.stream_enc_count; i++) {
1401		if (pool->base.stream_enc[i] != NULL) {
1402			if (pool->base.stream_enc[i]->vpg != NULL) {
1403				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1404				pool->base.stream_enc[i]->vpg = NULL;
1405			}
1406			if (pool->base.stream_enc[i]->afmt != NULL) {
1407				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1408				pool->base.stream_enc[i]->afmt = NULL;
1409			}
1410			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1411			pool->base.stream_enc[i] = NULL;
1412		}
1413	}
1414
1415	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1416		if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1417			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1418				kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1419				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1420			}
1421			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1422				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1423				pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1424			}
1425			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1426			pool->base.hpo_dp_stream_enc[i] = NULL;
1427		}
1428	}
1429
1430	for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1431		if (pool->base.hpo_dp_link_enc[i] != NULL) {
1432			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1433			pool->base.hpo_dp_link_enc[i] = NULL;
1434		}
1435	}
1436
1437	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1438		if (pool->base.dscs[i] != NULL)
1439			dcn20_dsc_destroy(&pool->base.dscs[i]);
1440	}
1441
1442	if (pool->base.mpc != NULL) {
1443		kfree(TO_DCN20_MPC(pool->base.mpc));
1444		pool->base.mpc = NULL;
1445	}
1446	if (pool->base.hubbub != NULL) {
1447		kfree(pool->base.hubbub);
1448		pool->base.hubbub = NULL;
1449	}
1450	for (i = 0; i < pool->base.pipe_count; i++) {
1451		if (pool->base.dpps[i] != NULL)
1452			dcn35_dpp_destroy(&pool->base.dpps[i]);
1453
1454		if (pool->base.ipps[i] != NULL)
1455			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1456
1457		if (pool->base.hubps[i] != NULL) {
1458			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1459			pool->base.hubps[i] = NULL;
1460		}
1461
1462		if (pool->base.irqs != NULL) {
1463			dal_irq_service_destroy(&pool->base.irqs);
1464		}
1465	}
1466
1467	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1468		if (pool->base.engines[i] != NULL)
1469			dce110_engine_destroy(&pool->base.engines[i]);
1470		if (pool->base.hw_i2cs[i] != NULL) {
1471			kfree(pool->base.hw_i2cs[i]);
1472			pool->base.hw_i2cs[i] = NULL;
1473		}
1474		if (pool->base.sw_i2cs[i] != NULL) {
1475			kfree(pool->base.sw_i2cs[i]);
1476			pool->base.sw_i2cs[i] = NULL;
1477		}
1478	}
1479
1480	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1481		if (pool->base.opps[i] != NULL)
1482			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1483	}
1484
1485	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1486		if (pool->base.timing_generators[i] != NULL)	{
1487			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1488			pool->base.timing_generators[i] = NULL;
1489		}
1490	}
1491
1492	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1493		if (pool->base.dwbc[i] != NULL) {
1494			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1495			pool->base.dwbc[i] = NULL;
1496		}
1497		if (pool->base.mcif_wb[i] != NULL) {
1498			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1499			pool->base.mcif_wb[i] = NULL;
1500		}
1501	}
1502
1503	for (i = 0; i < pool->base.audio_count; i++) {
1504		if (pool->base.audios[i])
1505			dce_aud_destroy(&pool->base.audios[i]);
1506	}
1507
1508	for (i = 0; i < pool->base.clk_src_count; i++) {
1509		if (pool->base.clock_sources[i] != NULL) {
1510			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1511			pool->base.clock_sources[i] = NULL;
1512		}
1513	}
1514
1515	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1516		if (pool->base.mpc_lut[i] != NULL) {
1517			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1518			pool->base.mpc_lut[i] = NULL;
1519		}
1520		if (pool->base.mpc_shaper[i] != NULL) {
1521			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1522			pool->base.mpc_shaper[i] = NULL;
1523		}
1524	}
1525
1526	if (pool->base.dp_clock_source != NULL) {
1527		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1528		pool->base.dp_clock_source = NULL;
1529	}
1530
1531	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1532		if (pool->base.multiple_abms[i] != NULL)
1533			dce_abm_destroy(&pool->base.multiple_abms[i]);
1534	}
1535
1536	if (pool->base.psr != NULL)
1537		dmub_psr_destroy(&pool->base.psr);
1538
1539	if (pool->base.replay != NULL)
1540		dmub_replay_destroy(&pool->base.replay);
1541
1542	if (pool->base.pg_cntl != NULL)
1543		dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1544
1545	if (pool->base.dccg != NULL)
1546		dcn_dccg_destroy(&pool->base.dccg);
1547}
1548
1549static struct hubp *dcn35_hubp_create(
1550	struct dc_context *ctx,
1551	uint32_t inst)
1552{
1553	struct dcn20_hubp *hubp2 =
1554		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1555
1556	if (!hubp2)
1557		return NULL;
1558
1559#undef REG_STRUCT
1560#define REG_STRUCT hubp_regs
1561	hubp_regs_init(0),
1562	hubp_regs_init(1),
1563	hubp_regs_init(2),
1564	hubp_regs_init(3);
1565
1566	if (hubp35_construct(hubp2, ctx, inst,
1567			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1568		return &hubp2->base;
1569
1570	BREAK_TO_DEBUGGER();
1571	kfree(hubp2);
1572	return NULL;
1573}
1574
1575static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1576{
1577	dcn35_dwbc_set_fgcg(
1578		dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1579}
1580
1581static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1582{
1583	int i;
1584	uint32_t pipe_count = pool->res_cap->num_dwb;
1585
1586	for (i = 0; i < pipe_count; i++) {
1587		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1588						    GFP_KERNEL);
1589
1590		if (!dwbc30) {
1591			dm_error("DC: failed to create dwbc30!\n");
1592			return false;
1593		}
1594
1595#undef REG_STRUCT
1596#define REG_STRUCT dwbc35_regs
1597		dwbc_regs_dcn3_init(0);
1598
1599		dcn35_dwbc_construct(dwbc30, ctx,
1600				&dwbc35_regs[i],
1601				&dwbc35_shift,
1602				&dwbc35_mask,
1603				i);
1604
1605		pool->dwbc[i] = &dwbc30->base;
1606
1607		dcn35_dwbc_init(dwbc30, ctx);
1608	}
1609	return true;
1610}
1611
1612static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1613				struct dc_context *ctx)
1614{
1615	dcn35_mmhubbub_set_fgcg(
1616		mcif_wb30,
1617		ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1618}
1619
1620static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1621{
1622	int i;
1623	uint32_t pipe_count = pool->res_cap->num_dwb;
1624
1625	for (i = 0; i < pipe_count; i++) {
1626		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1627						    GFP_KERNEL);
1628
1629		if (!mcif_wb30) {
1630			dm_error("DC: failed to create mcif_wb30!\n");
1631			return false;
1632		}
1633
1634#undef REG_STRUCT
1635#define REG_STRUCT mcif_wb35_regs
1636		mcif_wb_regs_dcn3_init(0);
1637
1638		dcn35_mmhubbub_construct(mcif_wb30, ctx,
1639				&mcif_wb35_regs[i],
1640				&mcif_wb35_shift,
1641				&mcif_wb35_mask,
1642				i);
1643
1644		dcn35_mmhubbub_init(mcif_wb30, ctx);
1645
1646		pool->mcif_wb[i] = &mcif_wb30->base;
1647	}
1648	return true;
1649}
1650
1651static struct display_stream_compressor *dcn35_dsc_create(
1652	struct dc_context *ctx, uint32_t inst)
1653{
1654	struct dcn20_dsc *dsc =
1655		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1656
1657	if (!dsc) {
1658		BREAK_TO_DEBUGGER();
1659		return NULL;
1660	}
1661
1662#undef REG_STRUCT
1663#define REG_STRUCT dsc_regs
1664	dsc_regsDCN35_init(0),
1665	dsc_regsDCN35_init(1),
1666	dsc_regsDCN35_init(2),
1667	dsc_regsDCN35_init(3);
1668
1669	dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1670	dsc35_set_fgcg(dsc,
1671		       ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1672	return &dsc->base;
1673}
1674
1675static void dcn351_destroy_resource_pool(struct resource_pool **pool)
1676{
1677	struct dcn351_resource_pool *dcn351_pool = TO_DCN351_RES_POOL(*pool);
1678
1679	dcn351_resource_destruct(dcn351_pool);
1680	kfree(dcn351_pool);
1681	*pool = NULL;
1682}
1683
1684static struct clock_source *dcn35_clock_source_create(
1685		struct dc_context *ctx,
1686		struct dc_bios *bios,
1687		enum clock_source_id id,
1688		const struct dce110_clk_src_regs *regs,
1689		bool dp_clk_src)
1690{
1691	struct dce110_clk_src *clk_src =
1692		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1693
1694	if (!clk_src)
1695		return NULL;
1696
1697	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1698			regs, &cs_shift, &cs_mask)) {
1699		clk_src->base.dp_clk_src = dp_clk_src;
1700		return &clk_src->base;
1701	}
1702
1703	kfree(clk_src);
1704	BREAK_TO_DEBUGGER();
1705	return NULL;
1706}
1707
1708static struct dc_cap_funcs cap_funcs = {
1709	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1710};
1711
1712static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1713{
1714	*panel_config = panel_config_defaults;
1715}
1716
1717
1718static enum dc_status dcn351_validate_bandwidth(struct dc *dc,
1719		struct dc_state *context,
1720		enum dc_validate_mode validate_mode)
1721{
1722	bool out = false;
1723
1724	out = dml2_validate(dc, context,
1725			context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1726			validate_mode);
1727
1728	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1729		return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1730
1731	DC_FP_START();
1732	dcn35_decide_zstate_support(dc, context);
1733	DC_FP_END();
1734
1735	return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1736}
1737
1738static int populate_dml_pipes_from_context_fpu(struct dc *dc,
1739					       struct dc_state *context,
1740					       display_e2e_pipe_params_st *pipes,
1741					       enum dc_validate_mode validate_mode)
1742{
1743	int ret;
1744
1745	DC_FP_START();
1746	ret = dcn351_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1747	DC_FP_END();
1748
1749	return ret;
1750
1751}
1752
1753static struct resource_funcs dcn351_res_pool_funcs = {
1754	.destroy = dcn351_destroy_resource_pool,
1755	.link_enc_create = dcn35_link_encoder_create,
1756	.link_enc_create_minimal = dcn31_link_enc_create_minimal,
1757	.link_encs_assign = link_enc_cfg_link_encs_assign,
1758	.link_enc_unassign = link_enc_cfg_link_enc_unassign,
1759	.panel_cntl_create = dcn31_panel_cntl_create,
1760	.validate_bandwidth = dcn351_validate_bandwidth,
1761	.calculate_wm_and_dlg = NULL,
1762	.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1763	.populate_dml_pipes = populate_dml_pipes_from_context_fpu,
1764	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1765	.release_pipe = dcn20_release_pipe,
1766	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1767	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1768	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1769	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1770	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1771	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1772	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1773	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1774	.update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu,
1775	.patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
1776	.get_panel_config_defaults = dcn35_get_panel_config_defaults,
1777	.get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia,
1778	.get_det_buffer_size = dcn31_get_det_buffer_size,
1779	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1780	.update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1781	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
1782};
1783
1784static bool dcn351_resource_construct(
1785	uint8_t num_virtual_links,
1786	struct dc *dc,
1787	struct dcn351_resource_pool *pool)
1788{
1789	int i;
1790	struct dc_context *ctx = dc->ctx;
1791	struct irq_service_init_data init_data;
1792
1793#undef REG_STRUCT
1794#define REG_STRUCT bios_regs
1795	bios_regs_init();
1796
1797#undef REG_STRUCT
1798#define REG_STRUCT clk_src_regs
1799	clk_src_regs_init(0, A),
1800	clk_src_regs_init(1, B),
1801	clk_src_regs_init(2, C),
1802	clk_src_regs_init(3, D),
1803	clk_src_regs_init(4, E);
1804
1805#undef REG_STRUCT
1806#define REG_STRUCT abm_regs
1807	abm_regs_init(0),
1808	abm_regs_init(1),
1809	abm_regs_init(2),
1810	abm_regs_init(3);
1811
1812#undef REG_STRUCT
1813#define REG_STRUCT dccg_regs
1814	dccg_regs_init();
1815
1816	ctx->dc_bios->regs = &bios_regs;
1817
1818	pool->base.res_cap = &res_cap_dcn351;
1819
1820	pool->base.funcs = &dcn351_res_pool_funcs;
1821
1822	/*************************************************
1823	 *  Resource + asic cap harcoding                *
1824	 *************************************************/
1825	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1826	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1827	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1828	dc->caps.max_downscale_ratio = 600;
1829	dc->caps.i2c_speed_in_khz = 100;
1830	dc->caps.i2c_speed_in_khz_hdcp = 100;
1831	dc->caps.max_cursor_size = 256;
1832	dc->caps.min_horizontal_blanking_period = 80;
1833	dc->caps.dmdata_alloc_size = 2048;
1834	dc->caps.max_slave_planes = 3;
1835	dc->caps.max_slave_yuv_planes = 3;
1836	dc->caps.max_slave_rgb_planes = 3;
1837	dc->caps.post_blend_color_processing = true;
1838	dc->caps.force_dp_tps4_for_cp2520 = true;
1839	if (dc->config.forceHBR2CP2520)
1840		dc->caps.force_dp_tps4_for_cp2520 = false;
1841	dc->caps.dp_hpo = true;
1842	dc->caps.dp_hdmi21_pcon_support = true;
1843
1844	dc->caps.edp_dsc_support = true;
1845	dc->caps.extended_aux_timeout_support = true;
1846	dc->caps.dmcub_support = true;
1847	dc->caps.is_apu = true;
1848	dc->caps.seamless_odm = true;
1849
1850	dc->caps.zstate_support = true;
1851	dc->caps.ips_support = true;
1852	dc->caps.max_v_total = (1 << 15) - 1;
1853	dc->caps.vtotal_limited_by_fp2 = true;
1854
1855	/* Color pipeline capabilities */
1856	dc->caps.color.dpp.dcn_arch = 1;
1857	dc->caps.color.dpp.input_lut_shared = 0;
1858	dc->caps.color.dpp.icsc = 1;
1859	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1860	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1861	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1862	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1863	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1864	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1865	dc->caps.color.dpp.post_csc = 1;
1866	dc->caps.color.dpp.gamma_corr = 1;
1867	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1868
1869	dc->caps.color.dpp.hw_3d_lut = 0;
1870	dc->caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1
1871	// no OGAM ROM on DCN301
1872	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1873	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1874	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1875	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1876	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1877	dc->caps.color.dpp.ocsc = 0;
1878
1879	dc->caps.color.mpc.gamut_remap = 1;
1880	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1881	dc->caps.color.mpc.ogam_ram = 1;
1882	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1883	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1884	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1885	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1886	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1887	dc->caps.color.mpc.ocsc = 1;
1888	dc->caps.color.mpc.preblend = true;
1889
1890	dc->caps.num_of_host_routers = 2;
1891	dc->caps.num_of_dpias_per_host_router = 2;
1892
1893	/* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1894	 * to provide some margin.
1895	 * It's expected for furture ASIC to have equal or higher value, in order to
1896	 * have determinstic power improvement from generate to genration.
1897	 * (i.e., we should not expect new ASIC generation with lower vmin rate)
1898	 */
1899	dc->caps.max_disp_clock_khz_at_vmin = 650000;
1900
1901	/* Use pipe context based otg sync logic */
1902	dc->config.use_pipe_ctx_sync_logic = true;
1903
1904
1905	/* Use psp mailbox to enable assr */
1906	dc->config.use_assr_psp_message = true;
1907
1908	/* read VBIOS LTTPR caps */
1909	{
1910		if (ctx->dc_bios->funcs->get_lttpr_caps) {
1911			enum bp_result bp_query_result;
1912			uint8_t is_vbios_lttpr_enable = 0;
1913
1914			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1915			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1916		}
1917
1918		/* interop bit is implicit */
1919		{
1920			dc->caps.vbios_lttpr_aware = true;
1921		}
1922	}
1923	dc->check_config = config_defaults;
1924
1925	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1926		dc->debug = debug_defaults_drv;
1927
1928	/*HW default is to have all the FGCG enabled, SW no need to program them*/
1929	dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
1930	// Init the vm_helper
1931	if (dc->vm_helper)
1932		vm_helper_init(dc->vm_helper, 16);
1933
1934	/*************************************************
1935	 *  Create resources                             *
1936	 *************************************************/
1937
1938	/* Clock Sources for Pixel Clock*/
1939	pool->base.clock_sources[DCN351_CLK_SRC_PLL0] =
1940			dcn35_clock_source_create(ctx, ctx->dc_bios,
1941				CLOCK_SOURCE_COMBO_PHY_PLL0,
1942				&clk_src_regs[0], false);
1943	pool->base.clock_sources[DCN351_CLK_SRC_PLL1] =
1944			dcn35_clock_source_create(ctx, ctx->dc_bios,
1945				CLOCK_SOURCE_COMBO_PHY_PLL1,
1946				&clk_src_regs[1], false);
1947	pool->base.clock_sources[DCN351_CLK_SRC_PLL2] =
1948			dcn35_clock_source_create(ctx, ctx->dc_bios,
1949				CLOCK_SOURCE_COMBO_PHY_PLL2,
1950				&clk_src_regs[2], false);
1951	pool->base.clock_sources[DCN351_CLK_SRC_PLL3] =
1952			dcn35_clock_source_create(ctx, ctx->dc_bios,
1953				CLOCK_SOURCE_COMBO_PHY_PLL3,
1954				&clk_src_regs[3], false);
1955	pool->base.clock_sources[DCN351_CLK_SRC_PLL4] =
1956			dcn35_clock_source_create(ctx, ctx->dc_bios,
1957				CLOCK_SOURCE_COMBO_PHY_PLL4,
1958				&clk_src_regs[4], false);
1959
1960	pool->base.clk_src_count = DCN351_CLK_SRC_TOTAL;
1961
1962	/* todo: not reuse phy_pll registers */
1963	pool->base.dp_clock_source =
1964			dcn35_clock_source_create(ctx, ctx->dc_bios,
1965				CLOCK_SOURCE_ID_DP_DTO,
1966				&clk_src_regs[0], true);
1967
1968	for (i = 0; i < pool->base.clk_src_count; i++) {
1969		if (pool->base.clock_sources[i] == NULL) {
1970			dm_error("DC: failed to create clock sources!\n");
1971			BREAK_TO_DEBUGGER();
1972			goto create_fail;
1973		}
1974	}
1975	/*temp till dml2 fully work without dml1*/
1976	dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
1977
1978	/* TODO: DCCG */
1979	pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1980	if (pool->base.dccg == NULL) {
1981		dm_error("DC: failed to create dccg!\n");
1982		BREAK_TO_DEBUGGER();
1983		goto create_fail;
1984	}
1985
1986#undef REG_STRUCT
1987#define REG_STRUCT pg_cntl_regs
1988	pg_cntl_dcn35_regs_init();
1989
1990	pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
1991	if (pool->base.pg_cntl == NULL) {
1992		dm_error("DC: failed to create power gate control!\n");
1993		BREAK_TO_DEBUGGER();
1994		goto create_fail;
1995	}
1996
1997	/* TODO: IRQ */
1998	init_data.ctx = dc->ctx;
1999	pool->base.irqs = dal_irq_service_dcn351_create(&init_data);
2000	if (!pool->base.irqs)
2001		goto create_fail;
2002
2003	/* HUBBUB */
2004	pool->base.hubbub = dcn35_hubbub_create(ctx);
2005	if (pool->base.hubbub == NULL) {
2006		BREAK_TO_DEBUGGER();
2007		dm_error("DC: failed to create hubbub!\n");
2008		goto create_fail;
2009	}
2010
2011	/* HUBPs, DPPs, OPPs and TGs */
2012	for (i = 0; i < pool->base.pipe_count; i++) {
2013		pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
2014		if (pool->base.hubps[i] == NULL) {
2015			BREAK_TO_DEBUGGER();
2016			dm_error(
2017				"DC: failed to create hubps!\n");
2018			goto create_fail;
2019		}
2020
2021		pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
2022		if (pool->base.dpps[i] == NULL) {
2023			BREAK_TO_DEBUGGER();
2024			dm_error(
2025				"DC: failed to create dpps!\n");
2026			goto create_fail;
2027		}
2028	}
2029
2030	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2031		pool->base.opps[i] = dcn35_opp_create(ctx, i);
2032		if (pool->base.opps[i] == NULL) {
2033			BREAK_TO_DEBUGGER();
2034			dm_error(
2035				"DC: failed to create output pixel processor!\n");
2036			goto create_fail;
2037		}
2038	}
2039
2040	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2041		pool->base.timing_generators[i] = dcn35_timing_generator_create(
2042				ctx, i);
2043		if (pool->base.timing_generators[i] == NULL) {
2044			BREAK_TO_DEBUGGER();
2045			dm_error("DC: failed to create tg!\n");
2046			goto create_fail;
2047		}
2048	}
2049	pool->base.timing_generator_count = i;
2050
2051	/* PSR */
2052	pool->base.psr = dmub_psr_create(ctx);
2053	if (pool->base.psr == NULL) {
2054		dm_error("DC: failed to create psr obj!\n");
2055		BREAK_TO_DEBUGGER();
2056		goto create_fail;
2057	}
2058
2059	/* Replay */
2060	pool->base.replay = dmub_replay_create(ctx);
2061	if (pool->base.replay == NULL) {
2062		dm_error("DC: failed to create replay obj!\n");
2063		BREAK_TO_DEBUGGER();
2064		goto create_fail;
2065	}
2066
2067	/* ABM */
2068	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2069		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2070				&abm_regs[i],
2071				&abm_shift,
2072				&abm_mask);
2073		if (pool->base.multiple_abms[i] == NULL) {
2074			dm_error("DC: failed to create abm for pipe %d!\n", i);
2075			BREAK_TO_DEBUGGER();
2076			goto create_fail;
2077		}
2078	}
2079
2080	/* MPC and DSC */
2081	pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2082	if (pool->base.mpc == NULL) {
2083		BREAK_TO_DEBUGGER();
2084		dm_error("DC: failed to create mpc!\n");
2085		goto create_fail;
2086	}
2087
2088	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2089		pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2090		if (pool->base.dscs[i] == NULL) {
2091			BREAK_TO_DEBUGGER();
2092			dm_error("DC: failed to create display stream compressor %d!\n", i);
2093			goto create_fail;
2094		}
2095	}
2096
2097	/* DWB and MMHUBBUB */
2098	if (!dcn35_dwbc_create(ctx, &pool->base)) {
2099		BREAK_TO_DEBUGGER();
2100		dm_error("DC: failed to create dwbc!\n");
2101		goto create_fail;
2102	}
2103
2104	if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2105		BREAK_TO_DEBUGGER();
2106		dm_error("DC: failed to create mcif_wb!\n");
2107		goto create_fail;
2108	}
2109
2110	/* AUX and I2C */
2111	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2112		pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2113		if (pool->base.engines[i] == NULL) {
2114			BREAK_TO_DEBUGGER();
2115			dm_error(
2116				"DC:failed to create aux engine!!\n");
2117			goto create_fail;
2118		}
2119		pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2120		if (pool->base.hw_i2cs[i] == NULL) {
2121			BREAK_TO_DEBUGGER();
2122			dm_error(
2123				"DC:failed to create hw i2c!!\n");
2124			goto create_fail;
2125		}
2126		pool->base.sw_i2cs[i] = NULL;
2127	}
2128
2129	/* DCN3.5 has 6 DPIA */
2130	pool->base.usb4_dpia_count = 4;
2131	if (dc->debug.dpia_debug.bits.disable_dpia)
2132		pool->base.usb4_dpia_count = 0;
2133
2134	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2135	if (!resource_construct(num_virtual_links, dc, &pool->base,
2136			&res_create_funcs))
2137		goto create_fail;
2138
2139	/* HW Sequencer and Plane caps */
2140	dcn351_hw_sequencer_construct(dc);
2141
2142	dc->caps.max_planes =  pool->base.pipe_count;
2143
2144	for (i = 0; i < dc->caps.max_planes; ++i)
2145		dc->caps.planes[i] = plane_cap;
2146
2147	dc->caps.max_odm_combine_factor = 4;
2148
2149	dc->cap_funcs = cap_funcs;
2150
2151
2152	dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2153
2154	dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2155	dc->dml2_options.use_native_soc_bb_construction = true;
2156	dc->dml2_options.minimize_dispclk_using_odm = false;
2157	if (dc->config.EnableMinDispClkODM)
2158		dc->dml2_options.minimize_dispclk_using_odm = true;
2159	dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2160
2161	resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2162	dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2163
2164	dc->dml2_options.max_segments_per_hubp = 24;
2165	dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2166	dc->dml2_options.override_det_buffer_size_kbytes = true;
2167
2168	if (dc->config.sdpif_request_limit_words_per_umc == 0)
2169		dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2170
2171	return true;
2172
2173create_fail:
2174
2175	dcn351_resource_destruct(pool);
2176
2177	return false;
2178}
2179
2180struct resource_pool *dcn351_create_resource_pool(
2181		const struct dc_init_data *init_data,
2182		struct dc *dc)
2183{
2184	struct dcn351_resource_pool *pool =
2185		kzalloc(sizeof(struct dcn351_resource_pool), GFP_KERNEL);
2186
2187	if (!pool)
2188		return NULL;
2189
2190	if (dcn351_resource_construct(init_data->num_virtual_links, dc, pool))
2191		return &pool->base;
2192
2193	BREAK_TO_DEBUGGER();
2194	kfree(pool);
2195	return NULL;
2196}