dcn35_resource.c

   1/* SPDX-License-Identifier: MIT */
   2/*
   3 * Copyright 2023 Advanced Micro Devices, Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: AMD
  24 *
  25 */
  26
  27#include "dm_services.h"
  28#include "dc.h"
  29
  30#include "dcn31/dcn31_init.h"
  31#include "dcn35/dcn35_init.h"
  32
  33#include "resource.h"
  34#include "include/irq_service_interface.h"
  35#include "dcn35_resource.h"
  36#include "dml2_0/dml2_wrapper.h"
  37
  38#include "dcn20/dcn20_resource.h"
  39#include "dcn30/dcn30_resource.h"
  40#include "dcn31/dcn31_resource.h"
  41#include "dcn32/dcn32_resource.h"
  42
  43#include "dcn10/dcn10_ipp.h"
  44#include "dcn30/dcn30_hubbub.h"
  45#include "dcn31/dcn31_hubbub.h"
  46#include "dcn35/dcn35_hubbub.h"
  47#include "dcn32/dcn32_mpc.h"
  48#include "dcn35/dcn35_hubp.h"
  49#include "irq/dcn35/irq_service_dcn35.h"
  50#include "dcn35/dcn35_dpp.h"
  51#include "dcn35/dcn35_optc.h"
  52#include "dcn20/dcn20_hwseq.h"
  53#include "dcn30/dcn30_hwseq.h"
  54#include "dce110/dce110_hwseq.h"
  55#include "dcn35/dcn35_opp.h"
  56#include "dcn35/dcn35_dsc.h"
  57#include "dcn30/dcn30_vpg.h"
  58#include "dcn30/dcn30_afmt.h"
  59#include "dcn31/dcn31_dio_link_encoder.h"
  60#include "dcn35/dcn35_dio_stream_encoder.h"
  61#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  62#include "dcn31/dcn31_hpo_dp_link_encoder.h"
  63#include "dcn32/dcn32_hpo_dp_link_encoder.h"
  64#include "link_service.h"
  65#include "dcn31/dcn31_apg.h"
  66#include "dcn32/dcn32_dio_link_encoder.h"
  67#include "dcn31/dcn31_vpg.h"
  68#include "dcn31/dcn31_afmt.h"
  69#include "dce/dce_clock_source.h"
  70#include "dce/dce_audio.h"
  71#include "dce/dce_hwseq.h"
  72#include "clk_mgr.h"
  73#include "virtual/virtual_stream_encoder.h"
  74#include "dce110/dce110_resource.h"
  75#include "dml/display_mode_vba.h"
  76#include "dcn35/dcn35_dccg.h"
  77#include "dcn35/dcn35_pg_cntl.h"
  78#include "dcn10/dcn10_resource.h"
  79#include "dcn31/dcn31_panel_cntl.h"
  80#include "dcn35/dcn35_hwseq.h"
  81#include "dcn35/dcn35_dio_link_encoder.h"
  82#include "dml/dcn31/dcn31_fpu.h" /*todo*/
  83#include "dml/dcn35/dcn35_fpu.h"
  84#include "dcn35/dcn35_dwb.h"
  85#include "dcn35/dcn35_mmhubbub.h"
  86
  87#include "dcn/dcn_3_5_0_offset.h"
  88#include "dcn/dcn_3_5_0_sh_mask.h"
  89#include "nbio/nbio_7_11_0_offset.h"
  90#include "mmhub/mmhub_3_3_0_offset.h"
  91#include "mmhub/mmhub_3_3_0_sh_mask.h"
  92
  93#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                   0x0
  94#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                     0x0000000FL
  95
  96#include "reg_helper.h"
  97#include "dce/dmub_abm.h"
  98#include "dce/dmub_psr.h"
  99#include "dce/dmub_replay.h"
 100#include "dce/dce_aux.h"
 101#include "dce/dce_i2c.h"
 102#include "dml/dcn31/display_mode_vba_31.h" /*temp*/
 103#include "vm_helper.h"
 104#include "dcn20/dcn20_vmid.h"
 105
 106#include "dc_state_priv.h"
 107
 108#include "link_enc_cfg.h"
 109#define DC_LOGGER_INIT(logger)
 110
 111enum dcn35_clk_src_array_id {
 112	DCN35_CLK_SRC_PLL0,
 113	DCN35_CLK_SRC_PLL1,
 114	DCN35_CLK_SRC_PLL2,
 115	DCN35_CLK_SRC_PLL3,
 116	DCN35_CLK_SRC_PLL4,
 117	DCN35_CLK_SRC_TOTAL
 118};
 119
 120/* begin *********************
 121 * macros to expend register list macro defined in HW object header file
 122 */
 123
 124/* DCN */
 125/* TODO awful hack. fixup dcn20_dwb.h */
 126#undef BASE_INNER
 127#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
 128
 129#define BASE(seg) BASE_INNER(seg)
 130
 131#define SR(reg_name)\
 132		REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 133					reg ## reg_name
 134
 135#define SR_ARR(reg_name, id) \
 136	REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 137
 138#define SR_ARR_INIT(reg_name, id, value) \
 139	REG_STRUCT[id].reg_name = value
 140
 141#define SRI(reg_name, block, id)\
 142	REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 143					reg ## block ## id ## _ ## reg_name
 144
 145#define SRI_ARR(reg_name, block, id)\
 146	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 147		reg ## block ## id ## _ ## reg_name
 148
 149#define SR_ARR_I2C(reg_name, id) \
 150	REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 151
 152#define SRI_ARR_I2C(reg_name, block, id)\
 153	REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 154		reg ## block ## id ## _ ## reg_name
 155
 156#define SRI_ARR_ALPHABET(reg_name, block, index, id)\
 157	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 158		reg ## block ## id ## _ ## reg_name
 159
 160#define SRI2(reg_name, block, id)\
 161	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 162					reg ## reg_name
 163
 164#define SRI2_ARR(reg_name, block, id)\
 165	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +	\
 166		reg ## reg_name
 167
 168#define SRIR(var_name, reg_name, block, id)\
 169	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 170					reg ## block ## id ## _ ## reg_name
 171
 172#define SRII(reg_name, block, id)\
 173	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 174					reg ## block ## id ## _ ## reg_name
 175
 176#define SRII_ARR_2(reg_name, block, id, inst)\
 177	REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 178		reg ## block ## id ## _ ## reg_name
 179
 180#define SRII_MPC_RMU(reg_name, block, id)\
 181	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 182					reg ## block ## id ## _ ## reg_name
 183
 184#define SRII_DWB(reg_name, temp_name, block, id)\
 185	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 186		reg ## block ## id ## _ ## temp_name
 187
 188#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
 189	.field_name = reg_name ## __ ## field_name ## post_fix
 190
 191#define DCCG_SRII(reg_name, block, id)\
 192	REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 193		reg ## block ## id ## _ ## reg_name
 194
 195#define VUPDATE_SRII(reg_name, block, id)\
 196	REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 197		reg ## reg_name ## _ ## block ## id
 198
 199/* NBIO */
 200#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
 201
 202#define NBIO_BASE(seg) \
 203	NBIO_BASE_INNER(seg)
 204
 205#define NBIO_SR(reg_name)\
 206	REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
 207				regBIF_BX1_ ## reg_name
 208
 209#define NBIO_SR_ARR(reg_name, id)\
 210	REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
 211		regBIF_BX1_ ## reg_name
 212
 213#define bios_regs_init() \
 214		( \
 215		NBIO_SR(BIOS_SCRATCH_3),\
 216		NBIO_SR(BIOS_SCRATCH_6)\
 217		)
 218
 219static struct bios_registers bios_regs;
 220
 221#define clk_src_regs_init(index, pllid)\
 222	CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
 223
 224static struct dce110_clk_src_regs clk_src_regs[5];
 225
 226static const struct dce110_clk_src_shift cs_shift = {
 227		CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
 228};
 229
 230static const struct dce110_clk_src_mask cs_mask = {
 231		CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
 232};
 233
 234#define abm_regs_init(id)\
 235		ABM_DCN32_REG_LIST_RI(id)
 236
 237static struct dce_abm_registers abm_regs[4];
 238
 239static const struct dce_abm_shift abm_shift = {
 240		ABM_MASK_SH_LIST_DCN35(__SHIFT)
 241};
 242
 243static const struct dce_abm_mask abm_mask = {
 244		ABM_MASK_SH_LIST_DCN35(_MASK)
 245};
 246
 247#define audio_regs_init(id)\
 248		AUD_COMMON_REG_LIST_RI(id)
 249
 250static struct dce_audio_registers audio_regs[7];
 251
 252
 253#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 254		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 255		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 256		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 257
 258static const struct dce_audio_shift audio_shift = {
 259		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 260};
 261
 262static const struct dce_audio_mask audio_mask = {
 263		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 264};
 265
 266#define vpg_regs_init(id)\
 267	VPG_DCN31_REG_LIST_RI(id)
 268
 269static struct dcn31_vpg_registers vpg_regs[10];
 270
 271static const struct dcn31_vpg_shift vpg_shift = {
 272	DCN31_VPG_MASK_SH_LIST(__SHIFT)
 273};
 274
 275static const struct dcn31_vpg_mask vpg_mask = {
 276	DCN31_VPG_MASK_SH_LIST(_MASK)
 277};
 278
 279#define afmt_regs_init(id)\
 280	AFMT_DCN31_REG_LIST_RI(id)
 281
 282static struct dcn31_afmt_registers afmt_regs[6];
 283
 284static const struct dcn31_afmt_shift afmt_shift = {
 285	DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 286};
 287
 288static const struct dcn31_afmt_mask afmt_mask = {
 289	DCN31_AFMT_MASK_SH_LIST(_MASK)
 290};
 291
 292#define apg_regs_init(id)\
 293	APG_DCN31_REG_LIST_RI(id)
 294
 295static struct dcn31_apg_registers apg_regs[4];
 296
 297static const struct dcn31_apg_shift apg_shift = {
 298	DCN31_APG_MASK_SH_LIST(__SHIFT)
 299};
 300
 301static const struct dcn31_apg_mask apg_mask = {
 302	DCN31_APG_MASK_SH_LIST(_MASK)
 303};
 304
 305#define stream_enc_regs_init(id)\
 306	SE_DCN35_REG_LIST_RI(id)
 307
 308static struct dcn10_stream_enc_registers stream_enc_regs[5];
 309
 310static const struct dcn10_stream_encoder_shift se_shift = {
 311		SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 312};
 313
 314static const struct dcn10_stream_encoder_mask se_mask = {
 315		SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
 316};
 317
 318#define aux_regs_init(id)\
 319	DCN2_AUX_REG_LIST_RI(id)
 320
 321static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
 322
 323#define hpd_regs_init(id)\
 324	HPD_REG_LIST_RI(id)
 325
 326static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
 327
 328
 329static const struct dce110_aux_registers_shift aux_shift = {
 330	DCN_AUX_MASK_SH_LIST(__SHIFT)
 331};
 332
 333static const struct dce110_aux_registers_mask aux_mask = {
 334	DCN_AUX_MASK_SH_LIST(_MASK)
 335};
 336
 337#define link_regs_init(id, phyid)\
 338	( \
 339	LE_DCN35_REG_LIST_RI(id), \
 340	UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
 341	)
 342
 343static struct dcn10_link_enc_registers link_enc_regs[5];
 344
 345static const struct dcn10_link_enc_shift le_shift = {
 346	LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
 347	//DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 348};
 349
 350static const struct dcn10_link_enc_mask le_mask = {
 351	LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
 352	//DPCS_DCN31_MASK_SH_LIST(_MASK)
 353};
 354
 355#define hpo_dp_stream_encoder_reg_init(id)\
 356	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
 357
 358static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
 359
 360static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 361	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 362};
 363
 364static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 365	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 366};
 367
 368#define hpo_dp_link_encoder_reg_init(id)\
 369	DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
 370	/*DCN3_1_RDPCSTX_REG_LIST(0),*/
 371	/*DCN3_1_RDPCSTX_REG_LIST(1),*/
 372	/*DCN3_1_RDPCSTX_REG_LIST(2),*/
 373	/*DCN3_1_RDPCSTX_REG_LIST(3),*/
 374
 375static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
 376
 377static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 378	DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
 379};
 380
 381static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 382	DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
 383};
 384
 385#define dpp_regs_init(id)\
 386	DPP_REG_LIST_DCN35_RI(id)
 387
 388static struct dcn3_dpp_registers dpp_regs[4];
 389
 390static const struct dcn35_dpp_shift tf_shift = {
 391		DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
 392};
 393
 394static const struct dcn35_dpp_mask tf_mask = {
 395		DPP_REG_LIST_SH_MASK_DCN35(_MASK)
 396};
 397
 398#define opp_regs_init(id)\
 399	OPP_REG_LIST_DCN35_RI(id)
 400
 401static struct dcn35_opp_registers opp_regs[4];
 402
 403static const struct dcn35_opp_shift opp_shift = {
 404	OPP_MASK_SH_LIST_DCN35(__SHIFT)
 405};
 406
 407static const struct dcn35_opp_mask opp_mask = {
 408	OPP_MASK_SH_LIST_DCN35(_MASK)
 409};
 410
 411#define aux_engine_regs_init(id)\
 412	( \
 413	AUX_COMMON_REG_LIST0_RI(id), \
 414	SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
 415	SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
 416	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
 417	)
 418
 419static struct dce110_aux_registers aux_engine_regs[5];
 420
 421#define dwbc_regs_dcn3_init(id)\
 422	DWBC_COMMON_REG_LIST_DCN30_RI(id)
 423
 424static struct dcn30_dwbc_registers dwbc35_regs[1];
 425
 426static const struct dcn35_dwbc_shift dwbc35_shift = {
 427	DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 428};
 429
 430static const struct dcn35_dwbc_mask dwbc35_mask = {
 431	DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
 432};
 433
 434#define mcif_wb_regs_dcn3_init(id)\
 435	MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
 436
 437static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
 438
 439static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
 440	MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 441};
 442
 443static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
 444	MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 445};
 446
 447#define dsc_regsDCN35_init(id)\
 448	DSC_REG_LIST_DCN20_RI(id)
 449
 450static struct dcn20_dsc_registers dsc_regs[4];
 451
 452static const struct dcn35_dsc_shift dsc_shift = {
 453	DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
 454};
 455
 456static const struct dcn35_dsc_mask dsc_mask = {
 457	DSC_REG_LIST_SH_MASK_DCN35(_MASK)
 458};
 459
 460static struct dcn30_mpc_registers mpc_regs;
 461
 462#define dcn_mpc_regs_init() \
 463	MPC_REG_LIST_DCN3_2_RI(0),\
 464	MPC_REG_LIST_DCN3_2_RI(1),\
 465	MPC_REG_LIST_DCN3_2_RI(2),\
 466	MPC_REG_LIST_DCN3_2_RI(3),\
 467	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
 468	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
 469	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
 470	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
 471	MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
 472
 473static const struct dcn30_mpc_shift mpc_shift = {
 474	MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 475};
 476
 477static const struct dcn30_mpc_mask mpc_mask = {
 478	MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
 479};
 480
 481#define optc_regs_init(id)\
 482	OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
 483
 484static struct dcn_optc_registers optc_regs[4];
 485
 486static const struct dcn_optc_shift optc_shift = {
 487	OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 488};
 489
 490static const struct dcn_optc_mask optc_mask = {
 491	OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 492};
 493
 494#define hubp_regs_init(id)\
 495	HUBP_REG_LIST_DCN30_RI(id)
 496
 497static struct dcn_hubp2_registers hubp_regs[4];
 498
 499
 500static const struct dcn35_hubp2_shift hubp_shift = {
 501		HUBP_MASK_SH_LIST_DCN35(__SHIFT)
 502};
 503
 504static const struct dcn35_hubp2_mask hubp_mask = {
 505		HUBP_MASK_SH_LIST_DCN35(_MASK)
 506};
 507
 508static struct dcn_hubbub_registers hubbub_reg;
 509
 510#define hubbub_reg_init()\
 511		HUBBUB_REG_LIST_DCN35(0)
 512
 513static const struct dcn_hubbub_shift hubbub_shift = {
 514		HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
 515};
 516
 517static const struct dcn_hubbub_mask hubbub_mask = {
 518		HUBBUB_MASK_SH_LIST_DCN35(_MASK)
 519};
 520
 521static struct dccg_registers dccg_regs;
 522
 523#define dccg_regs_init()\
 524	DCCG_REG_LIST_DCN35()
 525
 526static const struct dccg_shift dccg_shift = {
 527		DCCG_MASK_SH_LIST_DCN35(__SHIFT)
 528};
 529
 530static const struct dccg_mask dccg_mask = {
 531		DCCG_MASK_SH_LIST_DCN35(_MASK)
 532};
 533
 534static struct pg_cntl_registers pg_cntl_regs;
 535
 536#define pg_cntl_dcn35_regs_init() \
 537	PG_CNTL_REG_LIST_DCN35()
 538
 539static const struct pg_cntl_shift pg_cntl_shift = {
 540		PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
 541};
 542
 543static const struct pg_cntl_mask pg_cntl_mask = {
 544		PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
 545};
 546
 547#define SRII2(reg_name_pre, reg_name_post, id)\
 548	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 549			## id ## _ ## reg_name_post ## _BASE_IDX) + \
 550			reg ## reg_name_pre ## id ## _ ## reg_name_post
 551
 552static struct dce_hwseq_registers hwseq_reg;
 553
 554#define hwseq_reg_init()\
 555	HWSEQ_DCN35_REG_LIST()
 556
 557#define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
 558	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 559	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 560	HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 561	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 562	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 563	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 564	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 565	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 566	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 567	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 568	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 569	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 570	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 571	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 572	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 573	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 574	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 575	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 576	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 577	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 578	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 579	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 580	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 581	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 582	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 583	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 584	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 585	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 586	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 587	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 588	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 589	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 590	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 591	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 592	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 593	HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 594	HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 595	HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 596	HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 597	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 598	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 599	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 600	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 601	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 602	HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 603	HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
 604	HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
 605	HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
 606	HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
 607	HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 608	HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 609	HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 610	HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 611	HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 612	HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
 613	HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
 614	HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
 615	HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
 616	HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
 617	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
 618	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
 619	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
 620	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
 621	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
 622	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
 623	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
 624	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
 625	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
 626	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
 627	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
 628	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 629	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 630	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 631	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
 632	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
 633	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
 634	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
 635	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
 636	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
 637	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
 638	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
 639	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
 640	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
 641	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
 642	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
 643	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
 644	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
 645
 646static const struct dce_hwseq_shift hwseq_shift = {
 647		HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
 648};
 649
 650static const struct dce_hwseq_mask hwseq_mask = {
 651		HWSEQ_DCN35_MASK_SH_LIST(_MASK)
 652};
 653
 654#define vmid_regs_init(id)\
 655		DCN20_VMID_REG_LIST_RI(id)
 656
 657static struct dcn_vmid_registers vmid_regs[16];
 658
 659static const struct dcn20_vmid_shift vmid_shifts = {
 660		DCN20_VMID_MASK_SH_LIST(__SHIFT)
 661};
 662
 663static const struct dcn20_vmid_mask vmid_masks = {
 664		DCN20_VMID_MASK_SH_LIST(_MASK)
 665};
 666
 667static const struct resource_caps res_cap_dcn35 = {
 668	.num_timing_generator = 4,
 669	.num_opp = 4,
 670	.num_video_plane = 4,
 671	.num_audio = 5,
 672	.num_stream_encoder = 5,
 673	.num_dig_link_enc = 5,
 674	.num_hpo_dp_stream_encoder = 4,
 675	.num_hpo_dp_link_encoder = 2,
 676	.num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
 677	.num_dwb = 1,
 678	.num_ddc = 5,
 679	.num_vmid = 16,
 680	.num_mpc_3dlut = 2,
 681	.num_dsc = 4,
 682};
 683
 684static const struct dc_plane_cap plane_cap = {
 685	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 686	.per_pixel_alpha = true,
 687
 688	.pixel_format_support = {
 689			.argb8888 = true,
 690			.nv12 = true,
 691			.fp16 = true,
 692			.p010 = true,
 693			.ayuv = false,
 694	},
 695
 696	.max_upscale_factor = {
 697			.argb8888 = 16000,
 698			.nv12 = 16000,
 699			.fp16 = 16000
 700	},
 701
 702	// 6:1 downscaling ratio: 1000/6 = 166.666
 703	.max_downscale_factor = {
 704			.argb8888 = 250,
 705			.nv12 = 167,
 706			.fp16 = 167
 707	},
 708	64,
 709	64
 710};
 711
 712static const struct dc_debug_options debug_defaults_drv = {
 713	.disable_dmcu = true,
 714	.force_abm_enable = false,
 715	.clock_trace = true,
 716	.disable_pplib_clock_request = false,
 717	.pipe_split_policy = MPC_SPLIT_AVOID,
 718	.force_single_disp_pipe_split = false,
 719	.disable_dcc = DCC_ENABLE,
 720	.disable_dpp_power_gate = true,
 721	.disable_hubp_power_gate = true,
 722	.disable_optc_power_gate = true, /*should the same as above two*/
 723	.disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
 724	.disable_clock_gate = false,
 725	.disable_dsc_power_gate = true,
 726	.vsr_support = true,
 727	.performance_trace = false,
 728	.max_downscale_src_width = 4096,/*upto true 4k*/
 729	.disable_pplib_wm_range = false,
 730	.scl_reset_length10 = true,
 731	.sanity_checks = false,
 732	.underflow_assert_delay_us = 0xFFFFFFFF,
 733	.dwb_fi_phase = -1, // -1 = disable,
 734	.dmub_command_table = true,
 735	.pstate_enabled = true,
 736	.use_max_lb = true,
 737	.enable_mem_low_power = {
 738		.bits = {
 739			.vga = false,
 740			.i2c = true,
 741			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 742			.dscl = true,
 743			.cm = true,
 744			.mpc = true,
 745			.optc = true,
 746			.vpg = true,
 747			.afmt = true,
 748		}
 749	},
 750	.root_clock_optimization = {
 751		.bits = {
 752			.dpp = true,
 753			.dsc = true,/*dscclk and dsc pg*/
 754			.hdmistream = true,
 755			.hdmichar = true,
 756			.dpstream = true,
 757			.symclk32_se = true,
 758			.symclk32_le = true,
 759			.symclk_fe = true,
 760			.physymclk = false,
 761			.dpiasymclk = true,
 762		}
 763	},
 764	.seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
 765	.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
 766	.minimum_z8_residency_time = 1, /* Always allow when other conditions are met */
 767	.using_dml2 = true,
 768	.support_eDP1_5 = true,
 769	.enable_hpo_pg_support = false,
 770	.enable_single_display_2to1_odm_policy = true,
 771	.disable_idle_power_optimizations = false,
 772	.dmcub_emulation = false,
 773	.disable_boot_optimizations = false,
 774	.disable_unbounded_requesting = false,
 775	.disable_mem_low_power = false,
 776	//must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
 777	.enable_double_buffered_dsc_pg_support = true,
 778	.enable_dp_dig_pixel_rate_div_policy = 1,
 779	.disable_z10 = false,
 780	.ignore_pg = true,
 781	.psp_disabled_wa = true,
 782	.ips2_eval_delay_us = 2000,
 783	.ips2_entry_delay_us = 800,
 784	.disable_dmub_reallow_idle = false,
 785	.static_screen_wait_frames = 2,
 786	.disable_timeout = true,
 787	.min_disp_clk_khz = 50000,
 788};
 789
 790static const struct dc_check_config config_defaults = {
 791	.enable_legacy_fast_update = true,
 792};
 793
 794static const struct dc_panel_config panel_config_defaults = {
 795	.psr = {
 796		.disable_psr = false,
 797		.disallow_psrsu = false,
 798		.disallow_replay = false,
 799	},
 800	.ilr = {
 801		.optimize_edp_link_rate = true,
 802	},
 803};
 804
 805static void dcn35_dpp_destroy(struct dpp **dpp)
 806{
 807	kfree(TO_DCN20_DPP(*dpp));
 808	*dpp = NULL;
 809}
 810
 811static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
 812{
 813	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 814	bool success = (dpp != NULL);
 815
 816	if (!success)
 817		return NULL;
 818
 819#undef REG_STRUCT
 820#define REG_STRUCT dpp_regs
 821	dpp_regs_init(0),
 822	dpp_regs_init(1),
 823	dpp_regs_init(2),
 824	dpp_regs_init(3);
 825
 826	success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
 827				  &tf_mask);
 828	if (success) {
 829		dpp35_set_fgcg(
 830			dpp,
 831			ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
 832		return &dpp->base;
 833	}
 834
 835	BREAK_TO_DEBUGGER();
 836	kfree(dpp);
 837	return NULL;
 838}
 839
 840static struct output_pixel_processor *dcn35_opp_create(
 841	struct dc_context *ctx, uint32_t inst)
 842{
 843	struct dcn20_opp *opp =
 844		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 845
 846	if (!opp) {
 847		BREAK_TO_DEBUGGER();
 848		return NULL;
 849	}
 850
 851#undef REG_STRUCT
 852#define REG_STRUCT opp_regs
 853	opp_regs_init(0),
 854	opp_regs_init(1),
 855	opp_regs_init(2),
 856	opp_regs_init(3);
 857
 858	dcn35_opp_construct(opp, ctx, inst,
 859			&opp_regs[inst], &opp_shift, &opp_mask);
 860
 861	dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
 862
 863	return &opp->base;
 864}
 865
 866static struct dce_aux *dcn31_aux_engine_create(
 867	struct dc_context *ctx,
 868	uint32_t inst)
 869{
 870	struct aux_engine_dce110 *aux_engine =
 871		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 872
 873	if (!aux_engine)
 874		return NULL;
 875
 876#undef REG_STRUCT
 877#define REG_STRUCT aux_engine_regs
 878	aux_engine_regs_init(0),
 879	aux_engine_regs_init(1),
 880	aux_engine_regs_init(2),
 881	aux_engine_regs_init(3),
 882	aux_engine_regs_init(4);
 883
 884	dce110_aux_engine_construct(aux_engine, ctx, inst,
 885				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 886				    &aux_engine_regs[inst],
 887					&aux_mask,
 888					&aux_shift,
 889					ctx->dc->caps.extended_aux_timeout_support);
 890
 891	return &aux_engine->base;
 892}
 893
 894#define i2c_inst_regs_init(id)\
 895	I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
 896
 897static struct dce_i2c_registers i2c_hw_regs[5];
 898
 899static const struct dce_i2c_shift i2c_shifts = {
 900		I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 901};
 902
 903static const struct dce_i2c_mask i2c_masks = {
 904		I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
 905};
 906
 907/* ========================================================== */
 908
 909/*
 910 * DPIA index | Preferred Encoder     |    Host Router
 911 *   0        |      C                |       0
 912 *   1        |      First Available  |       0
 913 *   2        |      D                |       1
 914 *   3        |      First Available  |       1
 915 */
 916/* ========================================================== */
 917static const enum engine_id dpia_to_preferred_enc_id_table[] = {
 918		ENGINE_ID_DIGC,
 919		ENGINE_ID_DIGC,
 920		ENGINE_ID_DIGD,
 921		ENGINE_ID_DIGD
 922};
 923
 924static enum engine_id dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index)
 925{
 926	return dpia_to_preferred_enc_id_table[dpia_index];
 927}
 928
 929static struct dce_i2c_hw *dcn31_i2c_hw_create(
 930	struct dc_context *ctx,
 931	uint32_t inst)
 932{
 933	struct dce_i2c_hw *dce_i2c_hw =
 934		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 935
 936	if (!dce_i2c_hw)
 937		return NULL;
 938
 939#undef REG_STRUCT
 940#define REG_STRUCT i2c_hw_regs
 941	i2c_inst_regs_init(1),
 942	i2c_inst_regs_init(2),
 943	i2c_inst_regs_init(3),
 944	i2c_inst_regs_init(4),
 945	i2c_inst_regs_init(5);
 946
 947	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 948				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 949
 950	return dce_i2c_hw;
 951}
 952static struct mpc *dcn35_mpc_create(
 953		struct dc_context *ctx,
 954		int num_mpcc,
 955		int num_rmu)
 956{
 957	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
 958
 959	if (!mpc30)
 960		return NULL;
 961
 962#undef REG_STRUCT
 963#define REG_STRUCT mpc_regs
 964	dcn_mpc_regs_init();
 965
 966	dcn32_mpc_construct(mpc30, ctx,
 967			&mpc_regs,
 968			&mpc_shift,
 969			&mpc_mask,
 970			num_mpcc,
 971			num_rmu);
 972
 973	return &mpc30->base;
 974}
 975
 976static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
 977{
 978	int i;
 979
 980	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
 981					  GFP_KERNEL);
 982
 983	if (!hubbub3)
 984		return NULL;
 985
 986#undef REG_STRUCT
 987#define REG_STRUCT hubbub_reg
 988	hubbub_reg_init();
 989
 990#undef REG_STRUCT
 991#define REG_STRUCT vmid_regs
 992	vmid_regs_init(0),
 993	vmid_regs_init(1),
 994	vmid_regs_init(2),
 995	vmid_regs_init(3),
 996	vmid_regs_init(4),
 997	vmid_regs_init(5),
 998	vmid_regs_init(6),
 999	vmid_regs_init(7),
1000	vmid_regs_init(8),
1001	vmid_regs_init(9),
1002	vmid_regs_init(10),
1003	vmid_regs_init(11),
1004	vmid_regs_init(12),
1005	vmid_regs_init(13),
1006	vmid_regs_init(14),
1007	vmid_regs_init(15);
1008
1009	hubbub35_construct(hubbub3, ctx,
1010			&hubbub_reg,
1011			&hubbub_shift,
1012			&hubbub_mask,
1013			384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
1014			8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
1015			1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
1016
1017
1018	for (i = 0; i < res_cap_dcn35.num_vmid; i++) {
1019		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1020
1021		vmid->ctx = ctx;
1022
1023		vmid->regs = &vmid_regs[i];
1024		vmid->shifts = &vmid_shifts;
1025		vmid->masks = &vmid_masks;
1026	}
1027
1028	return &hubbub3->base;
1029}
1030
1031static struct timing_generator *dcn35_timing_generator_create(
1032		struct dc_context *ctx,
1033		uint32_t instance)
1034{
1035	struct optc *tgn10 =
1036		kzalloc(sizeof(struct optc), GFP_KERNEL);
1037
1038	if (!tgn10)
1039		return NULL;
1040
1041#undef REG_STRUCT
1042#define REG_STRUCT optc_regs
1043	optc_regs_init(0),
1044	optc_regs_init(1),
1045	optc_regs_init(2),
1046	optc_regs_init(3);
1047
1048	tgn10->base.inst = instance;
1049	tgn10->base.ctx = ctx;
1050
1051	tgn10->tg_regs = &optc_regs[instance];
1052	tgn10->tg_shift = &optc_shift;
1053	tgn10->tg_mask = &optc_mask;
1054
1055	dcn35_timing_generator_init(tgn10);
1056
1057	return &tgn10->base;
1058}
1059
1060static const struct encoder_feature_support link_enc_feature = {
1061		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1062		.max_hdmi_pixel_clock = 600000,
1063		.hdmi_ycbcr420_supported = true,
1064		.dp_ycbcr420_supported = true,
1065		.fec_supported = true,
1066		.flags.bits.IS_HBR2_CAPABLE = true,
1067		.flags.bits.IS_HBR3_CAPABLE = true,
1068		.flags.bits.IS_TPS3_CAPABLE = true,
1069		.flags.bits.IS_TPS4_CAPABLE = true
1070};
1071
1072static struct link_encoder *dcn35_link_encoder_create(
1073	struct dc_context *ctx,
1074	const struct encoder_init_data *enc_init_data)
1075{
1076	struct dcn20_link_encoder *enc20 =
1077		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1078
1079	if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1080		return NULL;
1081
1082#undef REG_STRUCT
1083#define REG_STRUCT link_enc_aux_regs
1084	aux_regs_init(0),
1085	aux_regs_init(1),
1086	aux_regs_init(2),
1087	aux_regs_init(3),
1088	aux_regs_init(4);
1089
1090#undef REG_STRUCT
1091#define REG_STRUCT link_enc_hpd_regs
1092	hpd_regs_init(0),
1093	hpd_regs_init(1),
1094	hpd_regs_init(2),
1095	hpd_regs_init(3),
1096	hpd_regs_init(4);
1097
1098#undef REG_STRUCT
1099#define REG_STRUCT link_enc_regs
1100	link_regs_init(0, A),
1101	link_regs_init(1, B),
1102	link_regs_init(2, C),
1103	link_regs_init(3, D),
1104	link_regs_init(4, E);
1105
1106	dcn35_link_encoder_construct(enc20,
1107			enc_init_data,
1108			&link_enc_feature,
1109			&link_enc_regs[enc_init_data->transmitter],
1110			&link_enc_aux_regs[enc_init_data->channel - 1],
1111			&link_enc_hpd_regs[enc_init_data->hpd_source],
1112			&le_shift,
1113			&le_mask);
1114
1115	return &enc20->enc10.base;
1116}
1117
1118/* Create a minimal link encoder object not associated with a particular
1119 * physical connector.
1120 * resource_funcs.link_enc_create_minimal
1121 */
1122static struct link_encoder *dcn31_link_enc_create_minimal(
1123		struct dc_context *ctx, enum engine_id eng_id)
1124{
1125	struct dcn20_link_encoder *enc20;
1126
1127	if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1128		return NULL;
1129
1130	enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1131	if (!enc20)
1132		return NULL;
1133
1134	dcn31_link_encoder_construct_minimal(
1135			enc20,
1136			ctx,
1137			&link_enc_feature,
1138			&link_enc_regs[eng_id - ENGINE_ID_DIGA],
1139			eng_id);
1140
1141	return &enc20->enc10.base;
1142}
1143
1144static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1145{
1146	struct dcn31_panel_cntl *panel_cntl =
1147		kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1148
1149	if (!panel_cntl)
1150		return NULL;
1151
1152	dcn31_panel_cntl_construct(panel_cntl, init_data);
1153
1154	return &panel_cntl->base;
1155}
1156
1157static void read_dce_straps(
1158	struct dc_context *ctx,
1159	struct resource_straps *straps)
1160{
1161	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1162		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1163
1164}
1165
1166static struct audio *dcn31_create_audio(
1167		struct dc_context *ctx, unsigned int inst)
1168{
1169
1170#undef REG_STRUCT
1171#define REG_STRUCT audio_regs
1172	audio_regs_init(0),
1173	audio_regs_init(1),
1174	audio_regs_init(2),
1175	audio_regs_init(3),
1176	audio_regs_init(4);
1177	audio_regs_init(5);
1178	audio_regs_init(6);
1179
1180	return dce_audio_create(ctx, inst,
1181			&audio_regs[inst], &audio_shift, &audio_mask);
1182}
1183
1184static struct vpg *dcn31_vpg_create(
1185	struct dc_context *ctx,
1186	uint32_t inst)
1187{
1188	struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1189
1190	if (!vpg31)
1191		return NULL;
1192
1193#undef REG_STRUCT
1194#define REG_STRUCT vpg_regs
1195	vpg_regs_init(0),
1196	vpg_regs_init(1),
1197	vpg_regs_init(2),
1198	vpg_regs_init(3),
1199	vpg_regs_init(4),
1200	vpg_regs_init(5),
1201	vpg_regs_init(6),
1202	vpg_regs_init(7),
1203	vpg_regs_init(8),
1204	vpg_regs_init(9);
1205
1206	vpg31_construct(vpg31, ctx, inst,
1207			&vpg_regs[inst],
1208			&vpg_shift,
1209			&vpg_mask);
1210
1211	return &vpg31->base;
1212}
1213
1214static struct afmt *dcn31_afmt_create(
1215	struct dc_context *ctx,
1216	uint32_t inst)
1217{
1218	struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1219
1220	if (!afmt31)
1221		return NULL;
1222
1223#undef REG_STRUCT
1224#define REG_STRUCT afmt_regs
1225	afmt_regs_init(0),
1226	afmt_regs_init(1),
1227	afmt_regs_init(2),
1228	afmt_regs_init(3),
1229	afmt_regs_init(4),
1230	afmt_regs_init(5);
1231
1232	afmt31_construct(afmt31, ctx, inst,
1233			&afmt_regs[inst],
1234			&afmt_shift,
1235			&afmt_mask);
1236
1237	// Light sleep by default, no need to power down here
1238
1239	return &afmt31->base;
1240}
1241
1242static struct apg *dcn31_apg_create(
1243	struct dc_context *ctx,
1244	uint32_t inst)
1245{
1246	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1247
1248	if (!apg31)
1249		return NULL;
1250
1251#undef REG_STRUCT
1252#define REG_STRUCT apg_regs
1253	apg_regs_init(0),
1254	apg_regs_init(1),
1255	apg_regs_init(2),
1256	apg_regs_init(3);
1257
1258	apg31_construct(apg31, ctx, inst,
1259			&apg_regs[inst],
1260			&apg_shift,
1261			&apg_mask);
1262
1263	return &apg31->base;
1264}
1265
1266static struct stream_encoder *dcn35_stream_encoder_create(
1267	enum engine_id eng_id,
1268	struct dc_context *ctx)
1269{
1270	struct dcn10_stream_encoder *enc1;
1271	struct vpg *vpg;
1272	struct afmt *afmt;
1273	int vpg_inst;
1274	int afmt_inst;
1275
1276	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1277	if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1278		return NULL;
1279
1280	vpg_inst = eng_id;
1281	afmt_inst = eng_id;
1282
1283	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1284	vpg = dcn31_vpg_create(ctx, vpg_inst);
1285	afmt = dcn31_afmt_create(ctx, afmt_inst);
1286
1287	if (!enc1 || !vpg || !afmt) {
1288		kfree(enc1);
1289		kfree(vpg);
1290		kfree(afmt);
1291		return NULL;
1292	}
1293
1294#undef REG_STRUCT
1295#define REG_STRUCT stream_enc_regs
1296	stream_enc_regs_init(0),
1297	stream_enc_regs_init(1),
1298	stream_enc_regs_init(2),
1299	stream_enc_regs_init(3),
1300	stream_enc_regs_init(4);
1301
1302	dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1303					eng_id, vpg, afmt,
1304					&stream_enc_regs[eng_id],
1305					&se_shift, &se_mask);
1306
1307	return &enc1->base;
1308}
1309
1310static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1311	enum engine_id eng_id,
1312	struct dc_context *ctx)
1313{
1314	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1315	struct vpg *vpg;
1316	struct apg *apg;
1317	uint32_t hpo_dp_inst;
1318	uint32_t vpg_inst;
1319	uint32_t apg_inst;
1320
1321	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1322	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1323
1324	/* Mapping of VPG register blocks to HPO DP block instance:
1325	 * VPG[6] -> HPO_DP[0]
1326	 * VPG[7] -> HPO_DP[1]
1327	 * VPG[8] -> HPO_DP[2]
1328	 * VPG[9] -> HPO_DP[3]
1329	 */
1330	vpg_inst = hpo_dp_inst + 6;
1331
1332	/* Mapping of APG register blocks to HPO DP block instance:
1333	 * APG[0] -> HPO_DP[0]
1334	 * APG[1] -> HPO_DP[1]
1335	 * APG[2] -> HPO_DP[2]
1336	 * APG[3] -> HPO_DP[3]
1337	 */
1338	apg_inst = hpo_dp_inst;
1339
1340	/* allocate HPO stream encoder and create VPG sub-block */
1341	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1342	vpg = dcn31_vpg_create(ctx, vpg_inst);
1343	apg = dcn31_apg_create(ctx, apg_inst);
1344
1345	if (!hpo_dp_enc31 || !vpg || !apg) {
1346		kfree(hpo_dp_enc31);
1347		kfree(vpg);
1348		kfree(apg);
1349		return NULL;
1350	}
1351
1352#undef REG_STRUCT
1353#define REG_STRUCT hpo_dp_stream_enc_regs
1354	hpo_dp_stream_encoder_reg_init(0),
1355	hpo_dp_stream_encoder_reg_init(1),
1356	hpo_dp_stream_encoder_reg_init(2),
1357	hpo_dp_stream_encoder_reg_init(3);
1358
1359	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1360					hpo_dp_inst, eng_id, vpg, apg,
1361					&hpo_dp_stream_enc_regs[hpo_dp_inst],
1362					&hpo_dp_se_shift, &hpo_dp_se_mask);
1363
1364	return &hpo_dp_enc31->base;
1365}
1366
1367static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1368	uint8_t inst,
1369	struct dc_context *ctx)
1370{
1371	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1372
1373	/* allocate HPO link encoder */
1374	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1375	if (!hpo_dp_enc31)
1376		return NULL; /* out of memory */
1377
1378#undef REG_STRUCT
1379#define REG_STRUCT hpo_dp_link_enc_regs
1380	hpo_dp_link_encoder_reg_init(0),
1381	hpo_dp_link_encoder_reg_init(1);
1382
1383	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1384					&hpo_dp_link_enc_regs[inst],
1385					&hpo_dp_le_shift, &hpo_dp_le_mask);
1386
1387	return &hpo_dp_enc31->base;
1388}
1389
1390static struct dce_hwseq *dcn35_hwseq_create(
1391	struct dc_context *ctx)
1392{
1393	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1394
1395#undef REG_STRUCT
1396#define REG_STRUCT hwseq_reg
1397	hwseq_reg_init();
1398
1399	if (hws) {
1400		hws->ctx = ctx;
1401		hws->regs = &hwseq_reg;
1402		hws->shifts = &hwseq_shift;
1403		hws->masks = &hwseq_mask;
1404	}
1405	return hws;
1406}
1407static const struct resource_create_funcs res_create_funcs = {
1408	.read_dce_straps = read_dce_straps,
1409	.create_audio = dcn31_create_audio,
1410	.create_stream_encoder = dcn35_stream_encoder_create,
1411	.create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1412	.create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1413	.create_hwseq = dcn35_hwseq_create,
1414};
1415
1416static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)
1417{
1418	unsigned int i;
1419
1420	for (i = 0; i < pool->base.stream_enc_count; i++) {
1421		if (pool->base.stream_enc[i] != NULL) {
1422			if (pool->base.stream_enc[i]->vpg != NULL) {
1423				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1424				pool->base.stream_enc[i]->vpg = NULL;
1425			}
1426			if (pool->base.stream_enc[i]->afmt != NULL) {
1427				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1428				pool->base.stream_enc[i]->afmt = NULL;
1429			}
1430			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1431			pool->base.stream_enc[i] = NULL;
1432		}
1433	}
1434
1435	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1436		if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1437			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1438				kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1439				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1440			}
1441			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1442				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1443				pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1444			}
1445			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1446			pool->base.hpo_dp_stream_enc[i] = NULL;
1447		}
1448	}
1449
1450	for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1451		if (pool->base.hpo_dp_link_enc[i] != NULL) {
1452			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1453			pool->base.hpo_dp_link_enc[i] = NULL;
1454		}
1455	}
1456
1457	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1458		if (pool->base.dscs[i] != NULL)
1459			dcn20_dsc_destroy(&pool->base.dscs[i]);
1460	}
1461
1462	if (pool->base.mpc != NULL) {
1463		kfree(TO_DCN20_MPC(pool->base.mpc));
1464		pool->base.mpc = NULL;
1465	}
1466	if (pool->base.hubbub != NULL) {
1467		kfree(pool->base.hubbub);
1468		pool->base.hubbub = NULL;
1469	}
1470	for (i = 0; i < pool->base.pipe_count; i++) {
1471		if (pool->base.dpps[i] != NULL)
1472			dcn35_dpp_destroy(&pool->base.dpps[i]);
1473
1474		if (pool->base.ipps[i] != NULL)
1475			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1476
1477		if (pool->base.hubps[i] != NULL) {
1478			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1479			pool->base.hubps[i] = NULL;
1480		}
1481
1482		if (pool->base.irqs != NULL) {
1483			dal_irq_service_destroy(&pool->base.irqs);
1484		}
1485	}
1486
1487	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1488		if (pool->base.engines[i] != NULL)
1489			dce110_engine_destroy(&pool->base.engines[i]);
1490		if (pool->base.hw_i2cs[i] != NULL) {
1491			kfree(pool->base.hw_i2cs[i]);
1492			pool->base.hw_i2cs[i] = NULL;
1493		}
1494		if (pool->base.sw_i2cs[i] != NULL) {
1495			kfree(pool->base.sw_i2cs[i]);
1496			pool->base.sw_i2cs[i] = NULL;
1497		}
1498	}
1499
1500	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1501		if (pool->base.opps[i] != NULL)
1502			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1503	}
1504
1505	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1506		if (pool->base.timing_generators[i] != NULL)	{
1507			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1508			pool->base.timing_generators[i] = NULL;
1509		}
1510	}
1511
1512	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1513		if (pool->base.dwbc[i] != NULL) {
1514			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1515			pool->base.dwbc[i] = NULL;
1516		}
1517		if (pool->base.mcif_wb[i] != NULL) {
1518			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1519			pool->base.mcif_wb[i] = NULL;
1520		}
1521	}
1522
1523	for (i = 0; i < pool->base.audio_count; i++) {
1524		if (pool->base.audios[i])
1525			dce_aud_destroy(&pool->base.audios[i]);
1526	}
1527
1528	for (i = 0; i < pool->base.clk_src_count; i++) {
1529		if (pool->base.clock_sources[i] != NULL) {
1530			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1531			pool->base.clock_sources[i] = NULL;
1532		}
1533	}
1534
1535	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1536		if (pool->base.mpc_lut[i] != NULL) {
1537			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1538			pool->base.mpc_lut[i] = NULL;
1539		}
1540		if (pool->base.mpc_shaper[i] != NULL) {
1541			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1542			pool->base.mpc_shaper[i] = NULL;
1543		}
1544	}
1545
1546	if (pool->base.dp_clock_source != NULL) {
1547		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1548		pool->base.dp_clock_source = NULL;
1549	}
1550
1551	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1552		if (pool->base.multiple_abms[i] != NULL)
1553			dce_abm_destroy(&pool->base.multiple_abms[i]);
1554	}
1555
1556	if (pool->base.psr != NULL)
1557		dmub_psr_destroy(&pool->base.psr);
1558
1559	if (pool->base.replay != NULL)
1560		dmub_replay_destroy(&pool->base.replay);
1561
1562	if (pool->base.pg_cntl != NULL)
1563		dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1564
1565	if (pool->base.dccg != NULL)
1566		dcn_dccg_destroy(&pool->base.dccg);
1567}
1568
1569static struct hubp *dcn35_hubp_create(
1570	struct dc_context *ctx,
1571	uint32_t inst)
1572{
1573	struct dcn20_hubp *hubp2 =
1574		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1575
1576	if (!hubp2)
1577		return NULL;
1578
1579#undef REG_STRUCT
1580#define REG_STRUCT hubp_regs
1581	hubp_regs_init(0),
1582	hubp_regs_init(1),
1583	hubp_regs_init(2),
1584	hubp_regs_init(3);
1585
1586	if (hubp35_construct(hubp2, ctx, inst,
1587			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1588		return &hubp2->base;
1589
1590	BREAK_TO_DEBUGGER();
1591	kfree(hubp2);
1592	return NULL;
1593}
1594
1595static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1596{
1597	dcn35_dwbc_set_fgcg(
1598		dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1599}
1600
1601static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1602{
1603	int i;
1604	uint32_t pipe_count = pool->res_cap->num_dwb;
1605
1606	for (i = 0; i < pipe_count; i++) {
1607		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1608						    GFP_KERNEL);
1609
1610		if (!dwbc30) {
1611			dm_error("DC: failed to create dwbc30!\n");
1612			return false;
1613		}
1614
1615#undef REG_STRUCT
1616#define REG_STRUCT dwbc35_regs
1617		dwbc_regs_dcn3_init(0);
1618
1619		dcn35_dwbc_construct(dwbc30, ctx,
1620				&dwbc35_regs[i],
1621				&dwbc35_shift,
1622				&dwbc35_mask,
1623				i);
1624
1625		pool->dwbc[i] = &dwbc30->base;
1626
1627		dcn35_dwbc_init(dwbc30, ctx);
1628	}
1629	return true;
1630}
1631
1632static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1633				struct dc_context *ctx)
1634{
1635	dcn35_mmhubbub_set_fgcg(
1636		mcif_wb30,
1637		ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1638}
1639
1640static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1641{
1642	int i;
1643	uint32_t pipe_count = pool->res_cap->num_dwb;
1644
1645	for (i = 0; i < pipe_count; i++) {
1646		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1647						    GFP_KERNEL);
1648
1649		if (!mcif_wb30) {
1650			dm_error("DC: failed to create mcif_wb30!\n");
1651			return false;
1652		}
1653
1654#undef REG_STRUCT
1655#define REG_STRUCT mcif_wb35_regs
1656		mcif_wb_regs_dcn3_init(0);
1657
1658		dcn35_mmhubbub_construct(mcif_wb30, ctx,
1659				&mcif_wb35_regs[i],
1660				&mcif_wb35_shift,
1661				&mcif_wb35_mask,
1662				i);
1663
1664		dcn35_mmhubbub_init(mcif_wb30, ctx);
1665
1666		pool->mcif_wb[i] = &mcif_wb30->base;
1667	}
1668	return true;
1669}
1670
1671static struct display_stream_compressor *dcn35_dsc_create(
1672	struct dc_context *ctx, uint32_t inst)
1673{
1674	struct dcn20_dsc *dsc =
1675		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1676
1677	if (!dsc) {
1678		BREAK_TO_DEBUGGER();
1679		return NULL;
1680	}
1681
1682#undef REG_STRUCT
1683#define REG_STRUCT dsc_regs
1684	dsc_regsDCN35_init(0),
1685	dsc_regsDCN35_init(1),
1686	dsc_regsDCN35_init(2),
1687	dsc_regsDCN35_init(3);
1688
1689	dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1690	dsc35_set_fgcg(dsc,
1691		       ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1692	return &dsc->base;
1693}
1694
1695static void dcn35_destroy_resource_pool(struct resource_pool **pool)
1696{
1697	struct dcn35_resource_pool *dcn35_pool = TO_DCN35_RES_POOL(*pool);
1698
1699	dcn35_resource_destruct(dcn35_pool);
1700	kfree(dcn35_pool);
1701	*pool = NULL;
1702}
1703
1704static struct clock_source *dcn35_clock_source_create(
1705		struct dc_context *ctx,
1706		struct dc_bios *bios,
1707		enum clock_source_id id,
1708		const struct dce110_clk_src_regs *regs,
1709		bool dp_clk_src)
1710{
1711	struct dce110_clk_src *clk_src =
1712		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1713
1714	if (!clk_src)
1715		return NULL;
1716
1717	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1718			regs, &cs_shift, &cs_mask)) {
1719		clk_src->base.dp_clk_src = dp_clk_src;
1720		return &clk_src->base;
1721	}
1722
1723	kfree(clk_src);
1724	BREAK_TO_DEBUGGER();
1725	return NULL;
1726}
1727
1728static struct dc_cap_funcs cap_funcs = {
1729	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1730};
1731
1732static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1733{
1734	*panel_config = panel_config_defaults;
1735}
1736
1737
1738static enum dc_status dcn35_validate_bandwidth(struct dc *dc,
1739		struct dc_state *context,
1740		enum dc_validate_mode validate_mode)
1741{
1742	bool out = false;
1743
1744	out = dml2_validate(dc, context,
1745			context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1746			validate_mode);
1747
1748	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1749		return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1750
1751	DC_FP_START();
1752	dcn35_decide_zstate_support(dc, context);
1753	DC_FP_END();
1754
1755	return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1756}
1757
1758enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1759{
1760	plane_state->tiling_info.gfxversion = DcGfxVersion9;
1761	dcn20_patch_unknown_plane_state(plane_state);
1762	return DC_OK;
1763}
1764
1765
1766static int populate_dml_pipes_from_context_fpu(struct dc *dc,
1767					       struct dc_state *context,
1768					       display_e2e_pipe_params_st *pipes,
1769					       enum dc_validate_mode validate_mode)
1770{
1771	int ret;
1772
1773	DC_FP_START();
1774	ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1775	DC_FP_END();
1776
1777	return ret;
1778}
1779
1780static struct resource_funcs dcn35_res_pool_funcs = {
1781	.destroy = dcn35_destroy_resource_pool,
1782	.link_enc_create = dcn35_link_encoder_create,
1783	.link_enc_create_minimal = dcn31_link_enc_create_minimal,
1784	.link_encs_assign = link_enc_cfg_link_encs_assign,
1785	.link_enc_unassign = link_enc_cfg_link_enc_unassign,
1786	.panel_cntl_create = dcn31_panel_cntl_create,
1787	.validate_bandwidth = dcn35_validate_bandwidth,
1788	.calculate_wm_and_dlg = NULL,
1789	.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1790	.populate_dml_pipes = populate_dml_pipes_from_context_fpu,
1791	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1792	.release_pipe = dcn20_release_pipe,
1793	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1794	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1795	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1796	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1797	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1798	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1799	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1800	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1801	.update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,
1802	.patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
1803	.get_panel_config_defaults = dcn35_get_panel_config_defaults,
1804	.get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia,
1805	.get_det_buffer_size = dcn31_get_det_buffer_size,
1806	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1807	.update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1808	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
1809};
1810
1811static bool dcn35_resource_construct(
1812	uint8_t num_virtual_links,
1813	struct dc *dc,
1814	struct dcn35_resource_pool *pool)
1815{
1816	int i;
1817	struct dc_context *ctx = dc->ctx;
1818	struct irq_service_init_data init_data;
1819
1820#undef REG_STRUCT
1821#define REG_STRUCT bios_regs
1822	bios_regs_init();
1823
1824#undef REG_STRUCT
1825#define REG_STRUCT clk_src_regs
1826	clk_src_regs_init(0, A),
1827	clk_src_regs_init(1, B),
1828	clk_src_regs_init(2, C),
1829	clk_src_regs_init(3, D),
1830	clk_src_regs_init(4, E);
1831
1832#undef REG_STRUCT
1833#define REG_STRUCT abm_regs
1834	abm_regs_init(0),
1835	abm_regs_init(1),
1836	abm_regs_init(2),
1837	abm_regs_init(3);
1838
1839#undef REG_STRUCT
1840#define REG_STRUCT dccg_regs
1841	dccg_regs_init();
1842
1843	ctx->dc_bios->regs = &bios_regs;
1844
1845	pool->base.res_cap = &res_cap_dcn35;
1846
1847	pool->base.funcs = &dcn35_res_pool_funcs;
1848
1849	/*************************************************
1850	 *  Resource + asic cap harcoding                *
1851	 *************************************************/
1852	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1853	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1854	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1855	dc->caps.max_downscale_ratio = 600;
1856	dc->caps.i2c_speed_in_khz = 100;
1857	dc->caps.i2c_speed_in_khz_hdcp = 100;
1858	dc->caps.max_cursor_size = 256;
1859	dc->caps.min_horizontal_blanking_period = 80;
1860	dc->caps.dmdata_alloc_size = 2048;
1861	dc->caps.max_slave_planes = 3;
1862	dc->caps.max_slave_yuv_planes = 3;
1863	dc->caps.max_slave_rgb_planes = 3;
1864	dc->caps.post_blend_color_processing = true;
1865	dc->caps.force_dp_tps4_for_cp2520 = true;
1866	if (dc->config.forceHBR2CP2520)
1867		dc->caps.force_dp_tps4_for_cp2520 = false;
1868	dc->caps.dp_hpo = true;
1869	dc->caps.dp_hdmi21_pcon_support = true;
1870
1871	dc->caps.edp_dsc_support = true;
1872	dc->caps.extended_aux_timeout_support = true;
1873	dc->caps.dmcub_support = true;
1874	dc->caps.is_apu = true;
1875	dc->caps.seamless_odm = true;
1876
1877	dc->caps.zstate_support = true;
1878	dc->caps.ips_support = true;
1879	dc->caps.max_v_total = (1 << 15) - 1;
1880	dc->caps.vtotal_limited_by_fp2 = true;
1881
1882	/* Color pipeline capabilities */
1883	dc->caps.color.dpp.dcn_arch = 1;
1884	dc->caps.color.dpp.input_lut_shared = 0;
1885	dc->caps.color.dpp.icsc = 1;
1886	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1887	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1888	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1889	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1890	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1891	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1892	dc->caps.color.dpp.post_csc = 1;
1893	dc->caps.color.dpp.gamma_corr = 1;
1894	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1895
1896	dc->caps.color.dpp.hw_3d_lut = 0;
1897	dc->caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1
1898	// no OGAM ROM on DCN301
1899	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1900	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1901	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1902	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1903	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1904	dc->caps.color.dpp.ocsc = 0;
1905
1906	dc->caps.color.mpc.gamut_remap = 1;
1907	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1908	dc->caps.color.mpc.ogam_ram = 1;
1909	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1910	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1911	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1912	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1913	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1914	dc->caps.color.mpc.ocsc = 1;
1915	dc->caps.color.mpc.preblend = true;
1916
1917	dc->caps.num_of_host_routers = 2;
1918	dc->caps.num_of_dpias_per_host_router = 2;
1919
1920	/* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1921	 * to provide some margin.
1922	 * It's expected for furture ASIC to have equal or higher value, in order to
1923	 * have determinstic power improvement from generate to genration.
1924	 * (i.e., we should not expect new ASIC generation with lower vmin rate)
1925	 */
1926	dc->caps.max_disp_clock_khz_at_vmin = 650000;
1927
1928	/* Sequential ONO is based on ASIC. */
1929	if (dc->ctx->asic_id.hw_internal_rev >= 0x40)
1930		dc->caps.sequential_ono = true;
1931
1932	/* Use pipe context based otg sync logic */
1933	dc->config.use_pipe_ctx_sync_logic = true;
1934
1935
1936	dc->config.disable_hbr_audio_dp2 = true;
1937	/* read VBIOS LTTPR caps */
1938	{
1939		if (ctx->dc_bios->funcs->get_lttpr_caps) {
1940			enum bp_result bp_query_result;
1941			uint8_t is_vbios_lttpr_enable = 0;
1942
1943			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1944			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1945		}
1946
1947		/* interop bit is implicit */
1948		{
1949			dc->caps.vbios_lttpr_aware = true;
1950		}
1951	}
1952	dc->check_config = config_defaults;
1953
1954	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1955		dc->debug = debug_defaults_drv;
1956	/*HW default is to have all the FGCG enabled, SW no need to program them*/
1957	dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
1958	// Init the vm_helper
1959	if (dc->vm_helper)
1960		vm_helper_init(dc->vm_helper, 16);
1961
1962	/*************************************************
1963	 *  Create resources                             *
1964	 *************************************************/
1965
1966	/* Clock Sources for Pixel Clock*/
1967	pool->base.clock_sources[DCN35_CLK_SRC_PLL0] =
1968			dcn35_clock_source_create(ctx, ctx->dc_bios,
1969				CLOCK_SOURCE_COMBO_PHY_PLL0,
1970				&clk_src_regs[0], false);
1971	pool->base.clock_sources[DCN35_CLK_SRC_PLL1] =
1972			dcn35_clock_source_create(ctx, ctx->dc_bios,
1973				CLOCK_SOURCE_COMBO_PHY_PLL1,
1974				&clk_src_regs[1], false);
1975	pool->base.clock_sources[DCN35_CLK_SRC_PLL2] =
1976			dcn35_clock_source_create(ctx, ctx->dc_bios,
1977				CLOCK_SOURCE_COMBO_PHY_PLL2,
1978				&clk_src_regs[2], false);
1979	pool->base.clock_sources[DCN35_CLK_SRC_PLL3] =
1980			dcn35_clock_source_create(ctx, ctx->dc_bios,
1981				CLOCK_SOURCE_COMBO_PHY_PLL3,
1982				&clk_src_regs[3], false);
1983	pool->base.clock_sources[DCN35_CLK_SRC_PLL4] =
1984			dcn35_clock_source_create(ctx, ctx->dc_bios,
1985				CLOCK_SOURCE_COMBO_PHY_PLL4,
1986				&clk_src_regs[4], false);
1987
1988	pool->base.clk_src_count = DCN35_CLK_SRC_TOTAL;
1989
1990	/* todo: not reuse phy_pll registers */
1991	pool->base.dp_clock_source =
1992			dcn35_clock_source_create(ctx, ctx->dc_bios,
1993				CLOCK_SOURCE_ID_DP_DTO,
1994				&clk_src_regs[0], true);
1995
1996	for (i = 0; i < pool->base.clk_src_count; i++) {
1997		if (pool->base.clock_sources[i] == NULL) {
1998			dm_error("DC: failed to create clock sources!\n");
1999			BREAK_TO_DEBUGGER();
2000			goto create_fail;
2001		}
2002	}
2003	/*temp till dml2 fully work without dml1*/
2004	dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
2005
2006	/* TODO: DCCG */
2007	pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2008	if (pool->base.dccg == NULL) {
2009		dm_error("DC: failed to create dccg!\n");
2010		BREAK_TO_DEBUGGER();
2011		goto create_fail;
2012	}
2013
2014#undef REG_STRUCT
2015#define REG_STRUCT pg_cntl_regs
2016	pg_cntl_dcn35_regs_init();
2017
2018	pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
2019	if (pool->base.pg_cntl == NULL) {
2020		dm_error("DC: failed to create power gate control!\n");
2021		BREAK_TO_DEBUGGER();
2022		goto create_fail;
2023	}
2024
2025	/* TODO: IRQ */
2026	init_data.ctx = dc->ctx;
2027	pool->base.irqs = dal_irq_service_dcn35_create(&init_data);
2028	if (!pool->base.irqs)
2029		goto create_fail;
2030
2031	/* HUBBUB */
2032	pool->base.hubbub = dcn35_hubbub_create(ctx);
2033	if (pool->base.hubbub == NULL) {
2034		BREAK_TO_DEBUGGER();
2035		dm_error("DC: failed to create hubbub!\n");
2036		goto create_fail;
2037	}
2038
2039	/* HUBPs, DPPs, OPPs and TGs */
2040	for (i = 0; i < pool->base.pipe_count; i++) {
2041		pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
2042		if (pool->base.hubps[i] == NULL) {
2043			BREAK_TO_DEBUGGER();
2044			dm_error(
2045				"DC: failed to create hubps!\n");
2046			goto create_fail;
2047		}
2048
2049		pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
2050		if (pool->base.dpps[i] == NULL) {
2051			BREAK_TO_DEBUGGER();
2052			dm_error(
2053				"DC: failed to create dpps!\n");
2054			goto create_fail;
2055		}
2056	}
2057
2058	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2059		pool->base.opps[i] = dcn35_opp_create(ctx, i);
2060		if (pool->base.opps[i] == NULL) {
2061			BREAK_TO_DEBUGGER();
2062			dm_error(
2063				"DC: failed to create output pixel processor!\n");
2064			goto create_fail;
2065		}
2066	}
2067
2068	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2069		pool->base.timing_generators[i] = dcn35_timing_generator_create(
2070				ctx, i);
2071		if (pool->base.timing_generators[i] == NULL) {
2072			BREAK_TO_DEBUGGER();
2073			dm_error("DC: failed to create tg!\n");
2074			goto create_fail;
2075		}
2076	}
2077	pool->base.timing_generator_count = i;
2078
2079	/* PSR */
2080	pool->base.psr = dmub_psr_create(ctx);
2081	if (pool->base.psr == NULL) {
2082		dm_error("DC: failed to create psr obj!\n");
2083		BREAK_TO_DEBUGGER();
2084		goto create_fail;
2085	}
2086
2087	/* Replay */
2088	pool->base.replay = dmub_replay_create(ctx);
2089	if (pool->base.replay == NULL) {
2090		dm_error("DC: failed to create replay obj!\n");
2091		BREAK_TO_DEBUGGER();
2092		goto create_fail;
2093	}
2094
2095	/* ABM */
2096	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2097		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2098				&abm_regs[i],
2099				&abm_shift,
2100				&abm_mask);
2101		if (pool->base.multiple_abms[i] == NULL) {
2102			dm_error("DC: failed to create abm for pipe %d!\n", i);
2103			BREAK_TO_DEBUGGER();
2104			goto create_fail;
2105		}
2106	}
2107
2108	/* MPC and DSC */
2109	pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2110	if (pool->base.mpc == NULL) {
2111		BREAK_TO_DEBUGGER();
2112		dm_error("DC: failed to create mpc!\n");
2113		goto create_fail;
2114	}
2115
2116	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2117		pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2118		if (pool->base.dscs[i] == NULL) {
2119			BREAK_TO_DEBUGGER();
2120			dm_error("DC: failed to create display stream compressor %d!\n", i);
2121			goto create_fail;
2122		}
2123	}
2124
2125	/* DWB and MMHUBBUB */
2126	if (!dcn35_dwbc_create(ctx, &pool->base)) {
2127		BREAK_TO_DEBUGGER();
2128		dm_error("DC: failed to create dwbc!\n");
2129		goto create_fail;
2130	}
2131
2132	if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2133		BREAK_TO_DEBUGGER();
2134		dm_error("DC: failed to create mcif_wb!\n");
2135		goto create_fail;
2136	}
2137
2138	/* AUX and I2C */
2139	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2140		pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2141		if (pool->base.engines[i] == NULL) {
2142			BREAK_TO_DEBUGGER();
2143			dm_error(
2144				"DC:failed to create aux engine!!\n");
2145			goto create_fail;
2146		}
2147		pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2148		if (pool->base.hw_i2cs[i] == NULL) {
2149			BREAK_TO_DEBUGGER();
2150			dm_error(
2151				"DC:failed to create hw i2c!!\n");
2152			goto create_fail;
2153		}
2154		pool->base.sw_i2cs[i] = NULL;
2155	}
2156
2157	/* DCN3.5 has 6 DPIA */
2158	pool->base.usb4_dpia_count = 4;
2159	if (dc->debug.dpia_debug.bits.disable_dpia)
2160		pool->base.usb4_dpia_count = 0;
2161
2162	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2163	if (!resource_construct(num_virtual_links, dc, &pool->base,
2164			&res_create_funcs))
2165		goto create_fail;
2166
2167	/* HW Sequencer and Plane caps */
2168	dcn35_hw_sequencer_construct(dc);
2169
2170	dc->caps.max_planes =  pool->base.pipe_count;
2171
2172	for (i = 0; i < dc->caps.max_planes; ++i)
2173		dc->caps.planes[i] = plane_cap;
2174
2175	dc->caps.max_odm_combine_factor = 4;
2176
2177	dc->cap_funcs = cap_funcs;
2178
2179	dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2180
2181	dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2182	dc->dml2_options.use_native_soc_bb_construction = true;
2183	dc->dml2_options.minimize_dispclk_using_odm = false;
2184	if (dc->config.EnableMinDispClkODM)
2185		dc->dml2_options.minimize_dispclk_using_odm = true;
2186	dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2187
2188	resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2189	dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2190
2191	dc->dml2_options.max_segments_per_hubp = 24;
2192	dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2193	dc->dml2_options.override_det_buffer_size_kbytes = true;
2194
2195	if (dc->config.sdpif_request_limit_words_per_umc == 0)
2196		dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2197
2198	return true;
2199
2200create_fail:
2201
2202	dcn35_resource_destruct(pool);
2203
2204	return false;
2205}
2206
2207struct resource_pool *dcn35_create_resource_pool(
2208		const struct dc_init_data *init_data,
2209		struct dc *dc)
2210{
2211	struct dcn35_resource_pool *pool =
2212		kzalloc(sizeof(struct dcn35_resource_pool), GFP_KERNEL);
2213
2214	if (!pool)
2215		return NULL;
2216
2217	if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool))
2218		return &pool->base;
2219
2220	BREAK_TO_DEBUGGER();
2221	kfree(pool);
2222	return NULL;
2223}