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dcn321_resource.c

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linux-6.19.14/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c C 
   1// SPDX-License-Identifier: MIT
   2/*
   3 * Copyright 2019 Advanced Micro Devices, Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: AMD
  24 *
  25 */
  26
  27#include "dm_services.h"
  28#include "dc.h"
  29
  30#include "dcn32/dcn32_init.h"
  31
  32#include "resource.h"
  33#include "include/irq_service_interface.h"
  34#include "dcn32/dcn32_resource.h"
  35#include "dcn321_resource.h"
  36
  37#include "dcn20/dcn20_resource.h"
  38#include "dcn30/dcn30_resource.h"
  39
  40#include "dml/dcn321/dcn321_fpu.h"
  41
  42#include "dcn10/dcn10_ipp.h"
  43#include "dcn30/dcn30_hubbub.h"
  44#include "dcn31/dcn31_hubbub.h"
  45#include "dcn32/dcn32_hubbub.h"
  46#include "dcn32/dcn32_mpc.h"
  47#include "dcn32/dcn32_hubp.h"
  48#include "irq/dcn32/irq_service_dcn32.h"
  49#include "dcn32/dcn32_dpp.h"
  50#include "dcn32/dcn32_optc.h"
  51#include "dcn20/dcn20_hwseq.h"
  52#include "dcn30/dcn30_hwseq.h"
  53#include "dce110/dce110_hwseq.h"
  54#include "dcn30/dcn30_opp.h"
  55#include "dcn20/dcn20_dsc.h"
  56#include "dcn30/dcn30_vpg.h"
  57#include "dcn30/dcn30_afmt.h"
  58#include "dcn30/dcn30_dio_stream_encoder.h"
  59#include "dcn32/dcn32_dio_stream_encoder.h"
  60#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  61#include "dcn31/dcn31_hpo_dp_link_encoder.h"
  62#include "dcn32/dcn32_hpo_dp_link_encoder.h"
  63#include "dcn31/dcn31_apg.h"
  64#include "dcn31/dcn31_dio_link_encoder.h"
  65#include "dcn32/dcn32_dio_link_encoder.h"
  66#include "dcn321/dcn321_dio_link_encoder.h"
  67#include "dce/dce_clock_source.h"
  68#include "dce/dce_audio.h"
  69#include "dce/dce_hwseq.h"
  70#include "clk_mgr.h"
  71#include "virtual/virtual_stream_encoder.h"
  72#include "dml/display_mode_vba.h"
  73#include "dcn32/dcn32_dccg.h"
  74#include "dcn10/dcn10_resource.h"
  75#include "link_service.h"
  76#include "dcn31/dcn31_panel_cntl.h"
  77
  78#include "dcn30/dcn30_dwb.h"
  79#include "dcn32/dcn32_mmhubbub.h"
  80
  81#include "dcn/dcn_3_2_1_offset.h"
  82#include "dcn/dcn_3_2_1_sh_mask.h"
  83#include "nbio/nbio_4_3_0_offset.h"
  84
  85#include "reg_helper.h"
  86#include "dce/dmub_abm.h"
  87#include "dce/dmub_psr.h"
  88#include "dce/dce_aux.h"
  89#include "dce/dce_i2c.h"
  90
  91#include "dml/dcn30/display_mode_vba_30.h"
  92#include "vm_helper.h"
  93#include "dcn20/dcn20_vmid.h"
  94
  95#include "dc_state_priv.h"
  96
  97#define DC_LOGGER_INIT(logger)
  98
  99enum dcn321_clk_src_array_id {
 100	DCN321_CLK_SRC_PLL0,
 101	DCN321_CLK_SRC_PLL1,
 102	DCN321_CLK_SRC_PLL2,
 103	DCN321_CLK_SRC_PLL3,
 104	DCN321_CLK_SRC_PLL4,
 105	DCN321_CLK_SRC_TOTAL
 106};
 107
 108/* begin *********************
 109 * macros to expend register list macro defined in HW object header file
 110 */
 111
 112/* DCN */
 113#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
 114
 115#define BASE(seg) BASE_INNER(seg)
 116
 117#define SR(reg_name)\
 118	REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 119		reg ## reg_name
 120#define SR_ARR(reg_name, id)\
 121	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 122		reg ## reg_name
 123#define SR_ARR_INIT(reg_name, id, value)\
 124	REG_STRUCT[id].reg_name =  value
 125
 126#define SRI(reg_name, block, id)\
 127	REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 128		reg ## block ## id ## _ ## reg_name
 129
 130#define SRI_ARR(reg_name, block, id)\
 131	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 132		reg ## block ## id ## _ ## reg_name
 133
 134#define SR_ARR_I2C(reg_name, id) \
 135	REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 136
 137#define SRI_ARR_I2C(reg_name, block, id)\
 138	REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 139		reg ## block ## id ## _ ## reg_name
 140
 141#define SRI_ARR_ALPHABET(reg_name, block, index, id)\
 142	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 143		reg ## block ## id ## _ ## reg_name
 144
 145#define SRI2(reg_name, block, id)\
 146	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 147		reg ## reg_name
 148#define SRI2_ARR(reg_name, block, id)\
 149	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 150		reg ## reg_name
 151
 152#define SRIR(var_name, reg_name, block, id)\
 153	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 154		reg ## block ## id ## _ ## reg_name
 155
 156#define SRII(reg_name, block, id)\
 157	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 158		reg ## block ## id ## _ ## reg_name
 159
 160#define SRII_ARR_2(reg_name, block, id, inst)\
 161	REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 162		reg ## block ## id ## _ ## reg_name
 163
 164#define SRII_MPC_RMU(reg_name, block, id)\
 165	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 166		reg ## block ## id ## _ ## reg_name
 167
 168#define SRII_DWB(reg_name, temp_name, block, id)\
 169	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 170		reg ## block ## id ## _ ## temp_name
 171
 172#define DCCG_SRII(reg_name, block, id)\
 173	REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 174		reg ## block ## id ## _ ## reg_name
 175
 176#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
 177	.field_name = reg_name ## __ ## field_name ## post_fix
 178
 179#define VUPDATE_SRII(reg_name, block, id)\
 180	REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 181		reg ## reg_name ## _ ## block ## id
 182
 183/* NBIO */
 184#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
 185
 186#define NBIO_BASE(seg) \
 187	NBIO_BASE_INNER(seg)
 188
 189#define NBIO_SR(reg_name)\
 190	REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
 191		regBIF_BX0_ ## reg_name
 192#define NBIO_SR_ARR(reg_name, id)\
 193	REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
 194		regBIF_BX0_ ## reg_name
 195
 196#define CTX ctx
 197#define REG(reg_name) \
 198	(ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
 199
 200static struct bios_registers bios_regs;
 201
 202#define bios_regs_init() \
 203		( \
 204		NBIO_SR(BIOS_SCRATCH_3),\
 205		NBIO_SR(BIOS_SCRATCH_6)\
 206		)
 207
 208#define clk_src_regs_init(index, pllid)\
 209	CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
 210
 211static struct dce110_clk_src_regs clk_src_regs[5];
 212
 213static const struct dce110_clk_src_shift cs_shift = {
 214		CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
 215};
 216
 217static const struct dce110_clk_src_mask cs_mask = {
 218		CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
 219};
 220
 221#define abm_regs_init(id)\
 222		ABM_DCN32_REG_LIST_RI(id)
 223
 224static struct dce_abm_registers abm_regs[4];
 225
 226static const struct dce_abm_shift abm_shift = {
 227		ABM_MASK_SH_LIST_DCN32(__SHIFT)
 228};
 229
 230static const struct dce_abm_mask abm_mask = {
 231		ABM_MASK_SH_LIST_DCN32(_MASK)
 232};
 233
 234#define audio_regs_init(id)\
 235		AUD_COMMON_REG_LIST_RI(id)
 236
 237static struct dce_audio_registers audio_regs[5];
 238
 239#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 240		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 241		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 242		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 243
 244static const struct dce_audio_shift audio_shift = {
 245		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 246};
 247
 248static const struct dce_audio_mask audio_mask = {
 249		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 250};
 251
 252#define vpg_regs_init(id)\
 253	VPG_DCN3_REG_LIST_RI(id)
 254
 255static struct dcn30_vpg_registers vpg_regs[10];
 256
 257static const struct dcn30_vpg_shift vpg_shift = {
 258	DCN3_VPG_MASK_SH_LIST(__SHIFT)
 259};
 260
 261static const struct dcn30_vpg_mask vpg_mask = {
 262	DCN3_VPG_MASK_SH_LIST(_MASK)
 263};
 264
 265#define afmt_regs_init(id)\
 266	AFMT_DCN3_REG_LIST_RI(id)
 267
 268static struct dcn30_afmt_registers afmt_regs[6];
 269
 270static const struct dcn30_afmt_shift afmt_shift = {
 271	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 272};
 273
 274static const struct dcn30_afmt_mask afmt_mask = {
 275	DCN3_AFMT_MASK_SH_LIST(_MASK)
 276};
 277
 278#define apg_regs_init(id)\
 279	APG_DCN31_REG_LIST_RI(id)
 280
 281static struct dcn31_apg_registers apg_regs[4];
 282
 283static const struct dcn31_apg_shift apg_shift = {
 284	DCN31_APG_MASK_SH_LIST(__SHIFT)
 285};
 286
 287static const struct dcn31_apg_mask apg_mask = {
 288		DCN31_APG_MASK_SH_LIST(_MASK)
 289};
 290
 291#define stream_enc_regs_init(id)\
 292	SE_DCN32_REG_LIST_RI(id)
 293
 294static struct dcn10_stream_enc_registers stream_enc_regs[5];
 295
 296static const struct dcn10_stream_encoder_shift se_shift = {
 297		SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 298};
 299
 300static const struct dcn10_stream_encoder_mask se_mask = {
 301		SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
 302};
 303
 304
 305#define aux_regs_init(id)\
 306	DCN2_AUX_REG_LIST_RI(id)
 307
 308static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
 309
 310#define hpd_regs_init(id)\
 311	HPD_REG_LIST_RI(id)
 312
 313static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
 314
 315#define link_regs_init(id, phyid)\
 316	( \
 317	LE_DCN31_REG_LIST_RI(id), \
 318	UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
 319	)
 320	/*DPCS_DCN31_REG_LIST(id),*/ \
 321
 322static struct dcn10_link_enc_registers link_enc_regs[5];
 323
 324static const struct dcn10_link_enc_shift le_shift = {
 325	LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 326//	DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 327};
 328
 329static const struct dcn10_link_enc_mask le_mask = {
 330	LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 331//	DPCS_DCN31_MASK_SH_LIST(_MASK)
 332};
 333
 334#define hpo_dp_stream_encoder_reg_init(id)\
 335	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
 336
 337static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
 338
 339static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 340	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 341};
 342
 343static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 344	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 345};
 346
 347
 348#define hpo_dp_link_encoder_reg_init(id)\
 349	DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
 350	/*DCN3_1_RDPCSTX_REG_LIST(0),*/
 351	/*DCN3_1_RDPCSTX_REG_LIST(1),*/
 352	/*DCN3_1_RDPCSTX_REG_LIST(2),*/
 353	/*DCN3_1_RDPCSTX_REG_LIST(3),*/
 354
 355static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
 356
 357static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 358	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 359};
 360
 361static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 362	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 363};
 364
 365#define dpp_regs_init(id)\
 366	DPP_REG_LIST_DCN30_COMMON_RI(id)
 367
 368static struct dcn3_dpp_registers dpp_regs[4];
 369
 370static const struct dcn3_dpp_shift tf_shift = {
 371		DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
 372};
 373
 374static const struct dcn3_dpp_mask tf_mask = {
 375		DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
 376};
 377
 378
 379#define opp_regs_init(id)\
 380	OPP_REG_LIST_DCN30_RI(id)
 381
 382static struct dcn20_opp_registers opp_regs[4];
 383
 384static const struct dcn20_opp_shift opp_shift = {
 385	OPP_MASK_SH_LIST_DCN20(__SHIFT)
 386};
 387
 388static const struct dcn20_opp_mask opp_mask = {
 389	OPP_MASK_SH_LIST_DCN20(_MASK)
 390};
 391
 392#define aux_engine_regs_init(id) \
 393	( \
 394	AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
 395	SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
 396	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
 397	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\
 398	)
 399
 400static struct dce110_aux_registers aux_engine_regs[5];
 401
 402static const struct dce110_aux_registers_shift aux_shift = {
 403	DCN_AUX_MASK_SH_LIST(__SHIFT)
 404};
 405
 406static const struct dce110_aux_registers_mask aux_mask = {
 407	DCN_AUX_MASK_SH_LIST(_MASK)
 408};
 409
 410#define dwbc_regs_dcn3_init(id)\
 411	DWBC_COMMON_REG_LIST_DCN30_RI(id)
 412
 413static struct dcn30_dwbc_registers dwbc30_regs[1];
 414
 415static const struct dcn30_dwbc_shift dwbc30_shift = {
 416	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 417};
 418
 419static const struct dcn30_dwbc_mask dwbc30_mask = {
 420	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 421};
 422
 423#define mcif_wb_regs_dcn3_init(id)\
 424	MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
 425
 426static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
 427
 428static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 429	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 430};
 431
 432static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 433	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
 434};
 435
 436#define dsc_regsDCN20_init(id)\
 437	DSC_REG_LIST_DCN20_RI(id)
 438
 439static struct dcn20_dsc_registers dsc_regs[4];
 440
 441static const struct dcn20_dsc_shift dsc_shift = {
 442	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 443};
 444
 445static const struct dcn20_dsc_mask dsc_mask = {
 446	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 447};
 448
 449static struct dcn30_mpc_registers mpc_regs;
 450#define dcn_mpc_regs_init()\
 451	MPC_REG_LIST_DCN3_2_RI(0),\
 452	MPC_REG_LIST_DCN3_2_RI(1),\
 453	MPC_REG_LIST_DCN3_2_RI(2),\
 454	MPC_REG_LIST_DCN3_2_RI(3),\
 455	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
 456	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
 457	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
 458	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
 459	MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
 460
 461static const struct dcn30_mpc_shift mpc_shift = {
 462	MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 463};
 464
 465static const struct dcn30_mpc_mask mpc_mask = {
 466	MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
 467};
 468
 469#define optc_regs_init(id)\
 470	OPTC_COMMON_REG_LIST_DCN3_2_RI(id)
 471
 472static struct dcn_optc_registers optc_regs[4];
 473
 474static const struct dcn_optc_shift optc_shift = {
 475	OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
 476};
 477
 478static const struct dcn_optc_mask optc_mask = {
 479	OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
 480};
 481
 482#define hubp_regs_init(id) \
 483	HUBP_REG_LIST_DCN32_RI(id)
 484
 485static struct dcn_hubp2_registers hubp_regs[4];
 486
 487static const struct dcn_hubp2_shift hubp_shift = {
 488		HUBP_MASK_SH_LIST_DCN32(__SHIFT)
 489};
 490
 491static const struct dcn_hubp2_mask hubp_mask = {
 492		HUBP_MASK_SH_LIST_DCN32(_MASK)
 493};
 494
 495static struct dcn_hubbub_registers hubbub_reg;
 496#define hubbub_reg_init()\
 497		HUBBUB_REG_LIST_DCN32_RI(0)
 498
 499static const struct dcn_hubbub_shift hubbub_shift = {
 500		HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
 501};
 502
 503static const struct dcn_hubbub_mask hubbub_mask = {
 504		HUBBUB_MASK_SH_LIST_DCN32(_MASK)
 505};
 506
 507static struct dccg_registers dccg_regs;
 508
 509#define dccg_regs_init()\
 510	DCCG_REG_LIST_DCN32_RI()
 511
 512static const struct dccg_shift dccg_shift = {
 513		DCCG_MASK_SH_LIST_DCN32(__SHIFT)
 514};
 515
 516static const struct dccg_mask dccg_mask = {
 517		DCCG_MASK_SH_LIST_DCN32(_MASK)
 518};
 519
 520
 521#define SRII2(reg_name_pre, reg_name_post, id)\
 522	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 523			## id ## _ ## reg_name_post ## _BASE_IDX) + \
 524			reg ## reg_name_pre ## id ## _ ## reg_name_post
 525
 526
 527#define HWSEQ_DCN32_REG_LIST()\
 528	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 529	SR(DIO_MEM_PWR_CTRL), \
 530	SR(ODM_MEM_PWR_CTRL3), \
 531	SR(MMHUBBUB_MEM_PWR_CNTL), \
 532	SR(DCCG_GATE_DISABLE_CNTL), \
 533	SR(DCCG_GATE_DISABLE_CNTL2), \
 534	SR(DCFCLK_CNTL),\
 535	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 536	SRII(PIXEL_RATE_CNTL, OTG, 0), \
 537	SRII(PIXEL_RATE_CNTL, OTG, 1),\
 538	SRII(PIXEL_RATE_CNTL, OTG, 2),\
 539	SRII(PIXEL_RATE_CNTL, OTG, 3),\
 540	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 541	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 542	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 543	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 544	SR(MICROSECOND_TIME_BASE_DIV), \
 545	SR(MILLISECOND_TIME_BASE_DIV), \
 546	SR(DISPCLK_FREQ_CHANGE_CNTL), \
 547	SR(RBBMIF_TIMEOUT_DIS), \
 548	SR(RBBMIF_TIMEOUT_DIS_2), \
 549	SR(DCHUBBUB_CRC_CTRL), \
 550	SR(DPP_TOP0_DPP_CRC_CTRL), \
 551	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 552	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 553	SR(MPC_CRC_CTRL), \
 554	SR(MPC_CRC_RESULT_GB), \
 555	SR(MPC_CRC_RESULT_C), \
 556	SR(MPC_CRC_RESULT_AR), \
 557	SR(DOMAIN0_PG_CONFIG), \
 558	SR(DOMAIN1_PG_CONFIG), \
 559	SR(DOMAIN2_PG_CONFIG), \
 560	SR(DOMAIN3_PG_CONFIG), \
 561	SR(DOMAIN16_PG_CONFIG), \
 562	SR(DOMAIN17_PG_CONFIG), \
 563	SR(DOMAIN18_PG_CONFIG), \
 564	SR(DOMAIN19_PG_CONFIG), \
 565	SR(DOMAIN0_PG_STATUS), \
 566	SR(DOMAIN1_PG_STATUS), \
 567	SR(DOMAIN2_PG_STATUS), \
 568	SR(DOMAIN3_PG_STATUS), \
 569	SR(DOMAIN16_PG_STATUS), \
 570	SR(DOMAIN17_PG_STATUS), \
 571	SR(DOMAIN18_PG_STATUS), \
 572	SR(DOMAIN19_PG_STATUS), \
 573	SR(D1VGA_CONTROL), \
 574	SR(D2VGA_CONTROL), \
 575	SR(D3VGA_CONTROL), \
 576	SR(D4VGA_CONTROL), \
 577	SR(D5VGA_CONTROL), \
 578	SR(D6VGA_CONTROL), \
 579	SR(DC_IP_REQUEST_CNTL), \
 580	SR(AZALIA_AUDIO_DTO), \
 581	SR(AZALIA_CONTROLLER_CLOCK_GATING)
 582
 583static struct dce_hwseq_registers hwseq_reg;
 584
 585#define hwseq_reg_init()\
 586	HWSEQ_DCN32_REG_LIST()
 587
 588#define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
 589	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 590	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 591	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 592	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 593	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 594	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 595	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 596	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 597	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 598	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 599	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 600	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 601	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 602	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 603	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 604	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 605	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 606	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 607	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 608	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 609	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 610	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 611	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 612	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 613	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 614	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 615	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 616	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 617	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 618	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 619	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 620	HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
 621
 622static const struct dce_hwseq_shift hwseq_shift = {
 623		HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
 624};
 625
 626static const struct dce_hwseq_mask hwseq_mask = {
 627		HWSEQ_DCN32_MASK_SH_LIST(_MASK)
 628};
 629#define vmid_regs_init(id)\
 630		DCN20_VMID_REG_LIST_RI(id)
 631
 632static struct dcn_vmid_registers vmid_regs[16];
 633
 634static const struct dcn20_vmid_shift vmid_shifts = {
 635		DCN20_VMID_MASK_SH_LIST(__SHIFT)
 636};
 637
 638static const struct dcn20_vmid_mask vmid_masks = {
 639		DCN20_VMID_MASK_SH_LIST(_MASK)
 640};
 641
 642static const struct resource_caps res_cap_dcn321 = {
 643	.num_timing_generator = 4,
 644	.num_opp = 4,
 645	.num_video_plane = 4,
 646	.num_audio = 5,
 647	.num_stream_encoder = 5,
 648	.num_hpo_dp_stream_encoder = 4,
 649	.num_hpo_dp_link_encoder = 2,
 650	.num_pll = 5,
 651	.num_dwb = 1,
 652	.num_ddc = 5,
 653	.num_vmid = 16,
 654	.num_mpc_3dlut = 4,
 655	.num_dsc = 4,
 656};
 657
 658static const struct dc_plane_cap plane_cap = {
 659	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 660	.per_pixel_alpha = true,
 661
 662	.pixel_format_support = {
 663			.argb8888 = true,
 664			.nv12 = true,
 665			.fp16 = true,
 666			.p010 = true,
 667			.ayuv = false,
 668	},
 669
 670	.max_upscale_factor = {
 671			.argb8888 = 16000,
 672			.nv12 = 16000,
 673			.fp16 = 16000
 674	},
 675
 676	// 6:1 downscaling ratio: 1000/6 = 166.666
 677	.max_downscale_factor = {
 678			.argb8888 = 167,
 679			.nv12 = 167,
 680			.fp16 = 167
 681	},
 682	64,
 683	64
 684};
 685
 686static const struct dc_debug_options debug_defaults_drv = {
 687	.disable_dmcu = true,
 688	.force_abm_enable = false,
 689	.clock_trace = true,
 690	.disable_pplib_clock_request = false,
 691	.pipe_split_policy = MPC_SPLIT_AVOID,
 692	.force_single_disp_pipe_split = false,
 693	.disable_dcc = DCC_ENABLE,
 694	.vsr_support = true,
 695	.performance_trace = false,
 696	.max_downscale_src_width = 7680,/*upto 8K*/
 697	.disable_pplib_wm_range = false,
 698	.scl_reset_length10 = true,
 699	.sanity_checks = false,
 700	.underflow_assert_delay_us = 0xFFFFFFFF,
 701	.dwb_fi_phase = -1, // -1 = disable,
 702	.dmub_command_table = true,
 703	.enable_mem_low_power = {
 704		.bits = {
 705			.vga = false,
 706			.i2c = false,
 707			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 708			.dscl = false,
 709			.cm = false,
 710			.mpc = false,
 711			.optc = true,
 712		}
 713	},
 714	.use_max_lb = true,
 715	.force_disable_subvp = false,
 716	.exit_idle_opt_for_cursor_updates = true,
 717	.enable_single_display_2to1_odm_policy = true,
 718
 719	/*must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/
 720	.enable_double_buffered_dsc_pg_support = true,
 721	.enable_dp_dig_pixel_rate_div_policy = 1,
 722	.allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
 723	.alloc_extra_way_for_cursor = true,
 724	.min_prefetch_in_strobe_ns = 60000, // 60us
 725	.disable_unbounded_requesting = false,
 726	.override_dispclk_programming = true,
 727	.disable_fpo_optimizations = false,
 728	.fpo_vactive_margin_us = 2000, // 2000us
 729	.disable_fpo_vactive = false,
 730	.disable_boot_optimizations = false,
 731	.disable_subvp_high_refresh = false,
 732	.fpo_vactive_min_active_margin_us = 200,
 733	.fpo_vactive_max_blank_us = 1000,
 734	.disable_dc_mode_overwrite = true,
 735	.using_dml2 = false,
 736};
 737
 738static const struct dc_check_config config_defaults = {
 739	.enable_legacy_fast_update = false,
 740};
 741
 742static struct dce_aux *dcn321_aux_engine_create(
 743	struct dc_context *ctx,
 744	uint32_t inst)
 745{
 746	struct aux_engine_dce110 *aux_engine =
 747		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 748
 749	if (!aux_engine)
 750		return NULL;
 751
 752#undef REG_STRUCT
 753#define REG_STRUCT aux_engine_regs
 754	aux_engine_regs_init(0),
 755	aux_engine_regs_init(1),
 756	aux_engine_regs_init(2),
 757	aux_engine_regs_init(3),
 758	aux_engine_regs_init(4);
 759
 760	dce110_aux_engine_construct(aux_engine, ctx, inst,
 761				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 762				    &aux_engine_regs[inst],
 763					&aux_mask,
 764					&aux_shift,
 765					ctx->dc->caps.extended_aux_timeout_support);
 766
 767	return &aux_engine->base;
 768}
 769#define i2c_inst_regs_init(id)\
 770	I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
 771
 772static struct dce_i2c_registers i2c_hw_regs[5];
 773
 774static const struct dce_i2c_shift i2c_shifts = {
 775		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 776};
 777
 778static const struct dce_i2c_mask i2c_masks = {
 779		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
 780};
 781
 782static struct dce_i2c_hw *dcn321_i2c_hw_create(
 783	struct dc_context *ctx,
 784	uint32_t inst)
 785{
 786	struct dce_i2c_hw *dce_i2c_hw =
 787		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 788
 789	if (!dce_i2c_hw)
 790		return NULL;
 791
 792#undef REG_STRUCT
 793#define REG_STRUCT i2c_hw_regs
 794	i2c_inst_regs_init(1),
 795	i2c_inst_regs_init(2),
 796	i2c_inst_regs_init(3),
 797	i2c_inst_regs_init(4),
 798	i2c_inst_regs_init(5);
 799
 800	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 801				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 802
 803	return dce_i2c_hw;
 804}
 805
 806static struct clock_source *dcn321_clock_source_create(
 807		struct dc_context *ctx,
 808		struct dc_bios *bios,
 809		enum clock_source_id id,
 810		const struct dce110_clk_src_regs *regs,
 811		bool dp_clk_src)
 812{
 813	struct dce110_clk_src *clk_src =
 814		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 815
 816	if (!clk_src)
 817		return NULL;
 818
 819	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
 820			regs, &cs_shift, &cs_mask)) {
 821		clk_src->base.dp_clk_src = dp_clk_src;
 822		return &clk_src->base;
 823	}
 824
 825	kfree(clk_src);
 826	BREAK_TO_DEBUGGER();
 827	return NULL;
 828}
 829
 830static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx)
 831{
 832	int i;
 833
 834	struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
 835					  GFP_KERNEL);
 836
 837	if (!hubbub2)
 838		return NULL;
 839
 840#undef REG_STRUCT
 841#define REG_STRUCT hubbub_reg
 842	hubbub_reg_init();
 843
 844#undef REG_STRUCT
 845#define REG_STRUCT vmid_regs
 846	vmid_regs_init(0),
 847	vmid_regs_init(1),
 848	vmid_regs_init(2),
 849	vmid_regs_init(3),
 850	vmid_regs_init(4),
 851	vmid_regs_init(5),
 852	vmid_regs_init(6),
 853	vmid_regs_init(7),
 854	vmid_regs_init(8),
 855	vmid_regs_init(9),
 856	vmid_regs_init(10),
 857	vmid_regs_init(11),
 858	vmid_regs_init(12),
 859	vmid_regs_init(13),
 860	vmid_regs_init(14),
 861	vmid_regs_init(15);
 862
 863	hubbub32_construct(hubbub2, ctx,
 864			&hubbub_reg,
 865			&hubbub_shift,
 866			&hubbub_mask,
 867			ctx->dc->dml.ip.det_buffer_size_kbytes,
 868			ctx->dc->dml.ip.pixel_chunk_size_kbytes,
 869			ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
 870
 871
 872	for (i = 0; i < res_cap_dcn321.num_vmid; i++) {
 873		struct dcn20_vmid *vmid = &hubbub2->vmid[i];
 874
 875		vmid->ctx = ctx;
 876
 877		vmid->regs = &vmid_regs[i];
 878		vmid->shifts = &vmid_shifts;
 879		vmid->masks = &vmid_masks;
 880	}
 881
 882	return &hubbub2->base;
 883}
 884
 885static struct hubp *dcn321_hubp_create(
 886	struct dc_context *ctx,
 887	uint32_t inst)
 888{
 889	struct dcn20_hubp *hubp2 =
 890		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
 891
 892	if (!hubp2)
 893		return NULL;
 894
 895#undef REG_STRUCT
 896#define REG_STRUCT hubp_regs
 897	hubp_regs_init(0),
 898	hubp_regs_init(1),
 899	hubp_regs_init(2),
 900	hubp_regs_init(3);
 901
 902	if (hubp32_construct(hubp2, ctx, inst,
 903			&hubp_regs[inst], &hubp_shift, &hubp_mask))
 904		return &hubp2->base;
 905
 906	BREAK_TO_DEBUGGER();
 907	kfree(hubp2);
 908	return NULL;
 909}
 910
 911static void dcn321_dpp_destroy(struct dpp **dpp)
 912{
 913	kfree(TO_DCN30_DPP(*dpp));
 914	*dpp = NULL;
 915}
 916
 917static struct dpp *dcn321_dpp_create(
 918	struct dc_context *ctx,
 919	uint32_t inst)
 920{
 921	struct dcn3_dpp *dpp3 =
 922		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 923
 924	if (!dpp3)
 925		return NULL;
 926
 927#undef REG_STRUCT
 928#define REG_STRUCT dpp_regs
 929	dpp_regs_init(0),
 930	dpp_regs_init(1),
 931	dpp_regs_init(2),
 932	dpp_regs_init(3);
 933
 934	if (dpp32_construct(dpp3, ctx, inst,
 935			&dpp_regs[inst], &tf_shift, &tf_mask))
 936		return &dpp3->base;
 937
 938	BREAK_TO_DEBUGGER();
 939	kfree(dpp3);
 940	return NULL;
 941}
 942
 943static struct mpc *dcn321_mpc_create(
 944		struct dc_context *ctx,
 945		int num_mpcc,
 946		int num_rmu)
 947{
 948	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
 949					  GFP_KERNEL);
 950
 951	if (!mpc30)
 952		return NULL;
 953
 954#undef REG_STRUCT
 955#define REG_STRUCT mpc_regs
 956	dcn_mpc_regs_init();
 957
 958	dcn32_mpc_construct(mpc30, ctx,
 959			&mpc_regs,
 960			&mpc_shift,
 961			&mpc_mask,
 962			num_mpcc,
 963			num_rmu);
 964
 965	return &mpc30->base;
 966}
 967
 968static struct output_pixel_processor *dcn321_opp_create(
 969	struct dc_context *ctx, uint32_t inst)
 970{
 971	struct dcn20_opp *opp2 =
 972		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 973
 974	if (!opp2) {
 975		BREAK_TO_DEBUGGER();
 976		return NULL;
 977	}
 978
 979#undef REG_STRUCT
 980#define REG_STRUCT opp_regs
 981	opp_regs_init(0),
 982	opp_regs_init(1),
 983	opp_regs_init(2),
 984	opp_regs_init(3);
 985
 986	dcn20_opp_construct(opp2, ctx, inst,
 987			&opp_regs[inst], &opp_shift, &opp_mask);
 988	return &opp2->base;
 989}
 990
 991
 992static struct timing_generator *dcn321_timing_generator_create(
 993		struct dc_context *ctx,
 994		uint32_t instance)
 995{
 996	struct optc *tgn10 =
 997		kzalloc(sizeof(struct optc), GFP_KERNEL);
 998
 999	if (!tgn10)
1000		return NULL;
1001
1002#undef REG_STRUCT
1003#define REG_STRUCT optc_regs
1004	optc_regs_init(0),
1005	optc_regs_init(1),
1006	optc_regs_init(2),
1007	optc_regs_init(3);
1008
1009	tgn10->base.inst = instance;
1010	tgn10->base.ctx = ctx;
1011
1012	tgn10->tg_regs = &optc_regs[instance];
1013	tgn10->tg_shift = &optc_shift;
1014	tgn10->tg_mask = &optc_mask;
1015
1016	dcn32_timing_generator_init(tgn10);
1017
1018	return &tgn10->base;
1019}
1020
1021static const struct encoder_feature_support link_enc_feature = {
1022		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1023		.max_hdmi_pixel_clock = 600000,
1024		.hdmi_ycbcr420_supported = true,
1025		.dp_ycbcr420_supported = true,
1026		.fec_supported = true,
1027		.flags.bits.IS_HBR2_CAPABLE = true,
1028		.flags.bits.IS_HBR3_CAPABLE = true,
1029		.flags.bits.IS_TPS3_CAPABLE = true,
1030		.flags.bits.IS_TPS4_CAPABLE = true
1031};
1032
1033static struct link_encoder *dcn321_link_encoder_create(
1034	struct dc_context *ctx,
1035	const struct encoder_init_data *enc_init_data)
1036{
1037	struct dcn20_link_encoder *enc20 =
1038		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1039
1040	if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1041		return NULL;
1042
1043#undef REG_STRUCT
1044#define REG_STRUCT link_enc_aux_regs
1045	aux_regs_init(0),
1046	aux_regs_init(1),
1047	aux_regs_init(2),
1048	aux_regs_init(3),
1049	aux_regs_init(4);
1050
1051#undef REG_STRUCT
1052#define REG_STRUCT link_enc_hpd_regs
1053	hpd_regs_init(0),
1054	hpd_regs_init(1),
1055	hpd_regs_init(2),
1056	hpd_regs_init(3),
1057	hpd_regs_init(4);
1058
1059#undef REG_STRUCT
1060#define REG_STRUCT link_enc_regs
1061	link_regs_init(0, A),
1062	link_regs_init(1, B),
1063	link_regs_init(2, C),
1064	link_regs_init(3, D),
1065	link_regs_init(4, E);
1066
1067	dcn321_link_encoder_construct(enc20,
1068			enc_init_data,
1069			&link_enc_feature,
1070			&link_enc_regs[enc_init_data->transmitter],
1071			&link_enc_aux_regs[enc_init_data->channel - 1],
1072			&link_enc_hpd_regs[enc_init_data->hpd_source],
1073			&le_shift,
1074			&le_mask);
1075
1076	return &enc20->enc10.base;
1077}
1078
1079static void read_dce_straps(
1080	struct dc_context *ctx,
1081	struct resource_straps *straps)
1082{
1083	generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1084		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1085
1086}
1087
1088static struct audio *dcn321_create_audio(
1089		struct dc_context *ctx, unsigned int inst)
1090{
1091
1092#undef REG_STRUCT
1093#define REG_STRUCT audio_regs
1094	audio_regs_init(0),
1095	audio_regs_init(1),
1096	audio_regs_init(2),
1097	audio_regs_init(3),
1098	audio_regs_init(4);
1099
1100	return dce_audio_create(ctx, inst,
1101			&audio_regs[inst], &audio_shift, &audio_mask);
1102}
1103
1104static struct vpg *dcn321_vpg_create(
1105	struct dc_context *ctx,
1106	uint32_t inst)
1107{
1108	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1109
1110	if (!vpg3)
1111		return NULL;
1112
1113#undef REG_STRUCT
1114#define REG_STRUCT vpg_regs
1115	vpg_regs_init(0),
1116	vpg_regs_init(1),
1117	vpg_regs_init(2),
1118	vpg_regs_init(3),
1119	vpg_regs_init(4),
1120	vpg_regs_init(5),
1121	vpg_regs_init(6),
1122	vpg_regs_init(7),
1123	vpg_regs_init(8),
1124	vpg_regs_init(9);
1125
1126	vpg3_construct(vpg3, ctx, inst,
1127			&vpg_regs[inst],
1128			&vpg_shift,
1129			&vpg_mask);
1130
1131	return &vpg3->base;
1132}
1133
1134static struct afmt *dcn321_afmt_create(
1135	struct dc_context *ctx,
1136	uint32_t inst)
1137{
1138	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1139
1140	if (!afmt3)
1141		return NULL;
1142
1143#undef REG_STRUCT
1144#define REG_STRUCT afmt_regs
1145	afmt_regs_init(0),
1146	afmt_regs_init(1),
1147	afmt_regs_init(2),
1148	afmt_regs_init(3),
1149	afmt_regs_init(4),
1150	afmt_regs_init(5);
1151
1152	afmt3_construct(afmt3, ctx, inst,
1153			&afmt_regs[inst],
1154			&afmt_shift,
1155			&afmt_mask);
1156
1157	return &afmt3->base;
1158}
1159
1160static struct apg *dcn321_apg_create(
1161	struct dc_context *ctx,
1162	uint32_t inst)
1163{
1164	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1165
1166	if (!apg31)
1167		return NULL;
1168
1169#undef REG_STRUCT
1170#define REG_STRUCT apg_regs
1171	apg_regs_init(0),
1172	apg_regs_init(1),
1173	apg_regs_init(2),
1174	apg_regs_init(3);
1175
1176	apg31_construct(apg31, ctx, inst,
1177			&apg_regs[inst],
1178			&apg_shift,
1179			&apg_mask);
1180
1181	return &apg31->base;
1182}
1183
1184static struct stream_encoder *dcn321_stream_encoder_create(
1185	enum engine_id eng_id,
1186	struct dc_context *ctx)
1187{
1188	struct dcn10_stream_encoder *enc1;
1189	struct vpg *vpg;
1190	struct afmt *afmt;
1191	int vpg_inst;
1192	int afmt_inst;
1193
1194	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1195	if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1196		return NULL;
1197
1198	vpg_inst = eng_id;
1199	afmt_inst = eng_id;
1200
1201	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1202	vpg = dcn321_vpg_create(ctx, vpg_inst);
1203	afmt = dcn321_afmt_create(ctx, afmt_inst);
1204
1205	if (!enc1 || !vpg || !afmt) {
1206		kfree(enc1);
1207		kfree(vpg);
1208		kfree(afmt);
1209		return NULL;
1210	}
1211
1212#undef REG_STRUCT
1213#define REG_STRUCT stream_enc_regs
1214	stream_enc_regs_init(0),
1215	stream_enc_regs_init(1),
1216	stream_enc_regs_init(2),
1217	stream_enc_regs_init(3),
1218	stream_enc_regs_init(4);
1219
1220	dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1221					eng_id, vpg, afmt,
1222					&stream_enc_regs[eng_id],
1223					&se_shift, &se_mask);
1224
1225	return &enc1->base;
1226}
1227
1228static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create(
1229	enum engine_id eng_id,
1230	struct dc_context *ctx)
1231{
1232	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1233	struct vpg *vpg;
1234	struct apg *apg;
1235	uint32_t hpo_dp_inst;
1236	uint32_t vpg_inst;
1237	uint32_t apg_inst;
1238
1239	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1240	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1241
1242	/* Mapping of VPG register blocks to HPO DP block instance:
1243	 * VPG[6] -> HPO_DP[0]
1244	 * VPG[7] -> HPO_DP[1]
1245	 * VPG[8] -> HPO_DP[2]
1246	 * VPG[9] -> HPO_DP[3]
1247	 */
1248	vpg_inst = hpo_dp_inst + 6;
1249
1250	/* Mapping of APG register blocks to HPO DP block instance:
1251	 * APG[0] -> HPO_DP[0]
1252	 * APG[1] -> HPO_DP[1]
1253	 * APG[2] -> HPO_DP[2]
1254	 * APG[3] -> HPO_DP[3]
1255	 */
1256	apg_inst = hpo_dp_inst;
1257
1258	/* allocate HPO stream encoder and create VPG sub-block */
1259	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1260	vpg = dcn321_vpg_create(ctx, vpg_inst);
1261	apg = dcn321_apg_create(ctx, apg_inst);
1262
1263	if (!hpo_dp_enc31 || !vpg || !apg) {
1264		kfree(hpo_dp_enc31);
1265		kfree(vpg);
1266		kfree(apg);
1267		return NULL;
1268	}
1269
1270#undef REG_STRUCT
1271#define REG_STRUCT hpo_dp_stream_enc_regs
1272	hpo_dp_stream_encoder_reg_init(0),
1273	hpo_dp_stream_encoder_reg_init(1),
1274	hpo_dp_stream_encoder_reg_init(2),
1275	hpo_dp_stream_encoder_reg_init(3);
1276
1277	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1278					hpo_dp_inst, eng_id, vpg, apg,
1279					&hpo_dp_stream_enc_regs[hpo_dp_inst],
1280					&hpo_dp_se_shift, &hpo_dp_se_mask);
1281
1282	return &hpo_dp_enc31->base;
1283}
1284
1285static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create(
1286	uint8_t inst,
1287	struct dc_context *ctx)
1288{
1289	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1290
1291	/* allocate HPO link encoder */
1292	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1293	if (!hpo_dp_enc31)
1294		return NULL; /* out of memory */
1295
1296#undef REG_STRUCT
1297#define REG_STRUCT hpo_dp_link_enc_regs
1298	hpo_dp_link_encoder_reg_init(0),
1299	hpo_dp_link_encoder_reg_init(1);
1300
1301	hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1302					&hpo_dp_link_enc_regs[inst],
1303					&hpo_dp_le_shift, &hpo_dp_le_mask);
1304
1305	return &hpo_dp_enc31->base;
1306}
1307
1308static struct dce_hwseq *dcn321_hwseq_create(
1309	struct dc_context *ctx)
1310{
1311	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1312
1313#undef REG_STRUCT
1314#define REG_STRUCT hwseq_reg
1315	hwseq_reg_init();
1316
1317	if (hws) {
1318		hws->ctx = ctx;
1319		hws->regs = &hwseq_reg;
1320		hws->shifts = &hwseq_shift;
1321		hws->masks = &hwseq_mask;
1322	}
1323	return hws;
1324}
1325static const struct resource_create_funcs res_create_funcs = {
1326	.read_dce_straps = read_dce_straps,
1327	.create_audio = dcn321_create_audio,
1328	.create_stream_encoder = dcn321_stream_encoder_create,
1329	.create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
1330	.create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
1331	.create_hwseq = dcn321_hwseq_create,
1332};
1333
1334static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
1335{
1336	unsigned int i;
1337
1338	for (i = 0; i < pool->base.stream_enc_count; i++) {
1339		if (pool->base.stream_enc[i] != NULL) {
1340			if (pool->base.stream_enc[i]->vpg != NULL) {
1341				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1342				pool->base.stream_enc[i]->vpg = NULL;
1343			}
1344			if (pool->base.stream_enc[i]->afmt != NULL) {
1345				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1346				pool->base.stream_enc[i]->afmt = NULL;
1347			}
1348			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1349			pool->base.stream_enc[i] = NULL;
1350		}
1351	}
1352
1353	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1354		if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1355			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1356				kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1357				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1358			}
1359			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1360				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1361				pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1362			}
1363			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1364			pool->base.hpo_dp_stream_enc[i] = NULL;
1365		}
1366	}
1367
1368	for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1369		if (pool->base.hpo_dp_link_enc[i] != NULL) {
1370			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1371			pool->base.hpo_dp_link_enc[i] = NULL;
1372		}
1373	}
1374
1375	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1376		if (pool->base.dscs[i] != NULL)
1377			dcn20_dsc_destroy(&pool->base.dscs[i]);
1378	}
1379
1380	if (pool->base.mpc != NULL) {
1381		kfree(TO_DCN20_MPC(pool->base.mpc));
1382		pool->base.mpc = NULL;
1383	}
1384	if (pool->base.hubbub != NULL) {
1385		kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1386		pool->base.hubbub = NULL;
1387	}
1388	for (i = 0; i < pool->base.pipe_count; i++) {
1389		if (pool->base.dpps[i] != NULL)
1390			dcn321_dpp_destroy(&pool->base.dpps[i]);
1391
1392		if (pool->base.ipps[i] != NULL)
1393			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1394
1395		if (pool->base.hubps[i] != NULL) {
1396			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1397			pool->base.hubps[i] = NULL;
1398		}
1399
1400		if (pool->base.irqs != NULL)
1401			dal_irq_service_destroy(&pool->base.irqs);
1402	}
1403
1404	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1405		if (pool->base.engines[i] != NULL)
1406			dce110_engine_destroy(&pool->base.engines[i]);
1407		if (pool->base.hw_i2cs[i] != NULL) {
1408			kfree(pool->base.hw_i2cs[i]);
1409			pool->base.hw_i2cs[i] = NULL;
1410		}
1411		if (pool->base.sw_i2cs[i] != NULL) {
1412			kfree(pool->base.sw_i2cs[i]);
1413			pool->base.sw_i2cs[i] = NULL;
1414		}
1415	}
1416
1417	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1418		if (pool->base.opps[i] != NULL)
1419			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1420	}
1421
1422	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1423		if (pool->base.timing_generators[i] != NULL)	{
1424			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1425			pool->base.timing_generators[i] = NULL;
1426		}
1427	}
1428
1429	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1430		if (pool->base.dwbc[i] != NULL) {
1431			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1432			pool->base.dwbc[i] = NULL;
1433		}
1434		if (pool->base.mcif_wb[i] != NULL) {
1435			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1436			pool->base.mcif_wb[i] = NULL;
1437		}
1438	}
1439
1440	for (i = 0; i < pool->base.audio_count; i++) {
1441		if (pool->base.audios[i])
1442			dce_aud_destroy(&pool->base.audios[i]);
1443	}
1444
1445	for (i = 0; i < pool->base.clk_src_count; i++) {
1446		if (pool->base.clock_sources[i] != NULL) {
1447			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1448			pool->base.clock_sources[i] = NULL;
1449		}
1450	}
1451
1452	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1453		if (pool->base.mpc_lut[i] != NULL) {
1454			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1455			pool->base.mpc_lut[i] = NULL;
1456		}
1457		if (pool->base.mpc_shaper[i] != NULL) {
1458			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1459			pool->base.mpc_shaper[i] = NULL;
1460		}
1461	}
1462
1463	if (pool->base.dp_clock_source != NULL) {
1464		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1465		pool->base.dp_clock_source = NULL;
1466	}
1467
1468	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1469		if (pool->base.multiple_abms[i] != NULL)
1470			dce_abm_destroy(&pool->base.multiple_abms[i]);
1471	}
1472
1473	if (pool->base.psr != NULL)
1474		dmub_psr_destroy(&pool->base.psr);
1475
1476	if (pool->base.dccg != NULL)
1477		dcn_dccg_destroy(&pool->base.dccg);
1478
1479	if (pool->base.oem_device != NULL) {
1480		struct dc *dc = pool->base.oem_device->ctx->dc;
1481
1482		dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1483	}
1484}
1485
1486
1487static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1488{
1489	int i;
1490	uint32_t dwb_count = pool->res_cap->num_dwb;
1491
1492	for (i = 0; i < dwb_count; i++) {
1493		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1494						    GFP_KERNEL);
1495
1496		if (!dwbc30) {
1497			dm_error("DC: failed to create dwbc30!\n");
1498			return false;
1499		}
1500
1501#undef REG_STRUCT
1502#define REG_STRUCT dwbc30_regs
1503		dwbc_regs_dcn3_init(0);
1504
1505		dcn30_dwbc_construct(dwbc30, ctx,
1506				&dwbc30_regs[i],
1507				&dwbc30_shift,
1508				&dwbc30_mask,
1509				i);
1510
1511		pool->dwbc[i] = &dwbc30->base;
1512	}
1513	return true;
1514}
1515
1516static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1517{
1518	int i;
1519	uint32_t dwb_count = pool->res_cap->num_dwb;
1520
1521	for (i = 0; i < dwb_count; i++) {
1522		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1523						    GFP_KERNEL);
1524
1525		if (!mcif_wb30) {
1526			dm_error("DC: failed to create mcif_wb30!\n");
1527			return false;
1528		}
1529
1530#undef REG_STRUCT
1531#define REG_STRUCT mcif_wb30_regs
1532		mcif_wb_regs_dcn3_init(0);
1533
1534		dcn32_mmhubbub_construct(mcif_wb30, ctx,
1535				&mcif_wb30_regs[i],
1536				&mcif_wb30_shift,
1537				&mcif_wb30_mask,
1538				i);
1539
1540		pool->mcif_wb[i] = &mcif_wb30->base;
1541	}
1542	return true;
1543}
1544
1545static struct display_stream_compressor *dcn321_dsc_create(
1546	struct dc_context *ctx, uint32_t inst)
1547{
1548	struct dcn20_dsc *dsc =
1549		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1550
1551	if (!dsc) {
1552		BREAK_TO_DEBUGGER();
1553		return NULL;
1554	}
1555
1556#undef REG_STRUCT
1557#define REG_STRUCT dsc_regs
1558	dsc_regsDCN20_init(0),
1559	dsc_regsDCN20_init(1),
1560	dsc_regsDCN20_init(2),
1561	dsc_regsDCN20_init(3);
1562
1563	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1564
1565	dsc->max_image_width = 6016;
1566
1567	return &dsc->base;
1568}
1569
1570static void dcn321_destroy_resource_pool(struct resource_pool **pool)
1571{
1572	struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool);
1573
1574	dcn321_resource_destruct(dcn321_pool);
1575	kfree(dcn321_pool);
1576	*pool = NULL;
1577}
1578
1579static struct dc_cap_funcs cap_funcs = {
1580	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
1581	.get_subvp_en = dcn32_subvp_in_use,
1582};
1583
1584static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1585{
1586	DC_FP_START();
1587
1588	dcn321_update_bw_bounding_box_fpu(dc, bw_params);
1589
1590	if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
1591		dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1592
1593	if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
1594		dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
1595
1596	DC_FP_END();
1597}
1598
1599static struct resource_funcs dcn321_res_pool_funcs = {
1600	.destroy = dcn321_destroy_resource_pool,
1601	.link_enc_create = dcn321_link_encoder_create,
1602	.link_enc_create_minimal = NULL,
1603	.panel_cntl_create = dcn32_panel_cntl_create,
1604	.validate_bandwidth = dcn32_validate_bandwidth,
1605	.calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
1606	.populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
1607	.acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1608	.acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1609	.release_pipe = dcn20_release_pipe,
1610	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1611	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1612	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1613	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1614	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1615	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1616	.acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1617	.release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1618	.update_bw_bounding_box = dcn321_update_bw_bounding_box,
1619	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1620	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1621	.add_phantom_pipes = dcn32_add_phantom_pipes,
1622	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
1623	.calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
1624	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1625	.get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size,
1626};
1627
1628static uint32_t read_pipe_fuses(struct dc_context *ctx)
1629{
1630	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1631	/* DCN321 support max 4 pipes */
1632	value = value & 0xf;
1633	return value;
1634}
1635
1636
1637static bool dcn321_resource_construct(
1638	uint8_t num_virtual_links,
1639	struct dc *dc,
1640	struct dcn321_resource_pool *pool)
1641{
1642	int i, j;
1643	struct dc_context *ctx = dc->ctx;
1644	struct irq_service_init_data init_data;
1645	struct ddc_service_init_data ddc_init_data = {0};
1646	uint32_t pipe_fuses = 0;
1647	uint32_t num_pipes  = 4;
1648
1649#undef REG_STRUCT
1650#define REG_STRUCT bios_regs
1651	bios_regs_init();
1652
1653#undef REG_STRUCT
1654#define REG_STRUCT clk_src_regs
1655	clk_src_regs_init(0, A),
1656	clk_src_regs_init(1, B),
1657	clk_src_regs_init(2, C),
1658	clk_src_regs_init(3, D),
1659	clk_src_regs_init(4, E);
1660
1661#undef REG_STRUCT
1662#define REG_STRUCT abm_regs
1663	abm_regs_init(0),
1664	abm_regs_init(1),
1665	abm_regs_init(2),
1666	abm_regs_init(3);
1667
1668#undef REG_STRUCT
1669#define REG_STRUCT dccg_regs
1670	dccg_regs_init();
1671
1672
1673	ctx->dc_bios->regs = &bios_regs;
1674
1675	pool->base.res_cap = &res_cap_dcn321;
1676	/* max number of pipes for ASIC before checking for pipe fuses */
1677	num_pipes  = pool->base.res_cap->num_timing_generator;
1678	pipe_fuses = read_pipe_fuses(ctx);
1679
1680	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1681		if (pipe_fuses & 1 << i)
1682			num_pipes--;
1683
1684	if (pipe_fuses & 1)
1685		ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
1686
1687	if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
1688		ASSERT(0); //Entire DCN is harvested!
1689
1690	/* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
1691	 * value will be changed, update max_num_dpp and max_num_otg for dml.
1692	 */
1693	dcn3_21_ip.max_num_dpp = num_pipes;
1694	dcn3_21_ip.max_num_otg = num_pipes;
1695
1696	pool->base.funcs = &dcn321_res_pool_funcs;
1697
1698	/*************************************************
1699	 *  Resource + asic cap harcoding                *
1700	 *************************************************/
1701	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1702	pool->base.timing_generator_count = num_pipes;
1703	pool->base.pipe_count = num_pipes;
1704	pool->base.mpcc_count = num_pipes;
1705	dc->caps.max_downscale_ratio = 600;
1706	dc->caps.i2c_speed_in_khz = 100;
1707	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
1708	/* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/
1709	dc->caps.max_cursor_size = 64;
1710	dc->caps.max_buffered_cursor_size = 64; // sqrt(16 * 1024 / 4)
1711	dc->caps.min_horizontal_blanking_period = 80;
1712	dc->caps.dmdata_alloc_size = 2048;
1713	dc->caps.mall_size_per_mem_channel = 4;
1714	/* total size = mall per channel * num channels * 1024 * 1024 */
1715	dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1716
1717	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1718	dc->caps.cache_line_size = 64;
1719	dc->caps.cache_num_ways = 16;
1720
1721	/* Calculate the available MALL space */
1722	dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(
1723		dc, dc->ctx->dc_bios->vram_info.num_chans) *
1724		dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1725	dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1726
1727	dc->caps.subvp_fw_processing_delay_us = 15;
1728	dc->caps.subvp_drr_max_vblank_margin_us = 40;
1729	dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
1730	dc->caps.subvp_swath_height_margin_lines = 16;
1731	dc->caps.subvp_pstate_allow_width_us = 20;
1732	dc->caps.subvp_vertical_int_margin_us = 30;
1733	dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
1734	dc->caps.max_slave_planes = 2;
1735	dc->caps.max_slave_yuv_planes = 2;
1736	dc->caps.max_slave_rgb_planes = 2;
1737	dc->caps.post_blend_color_processing = true;
1738	dc->caps.force_dp_tps4_for_cp2520 = true;
1739	dc->caps.dp_hpo = true;
1740	dc->caps.dp_hdmi21_pcon_support = true;
1741	dc->caps.edp_dsc_support = true;
1742	dc->caps.extended_aux_timeout_support = true;
1743	dc->caps.dmcub_support = true;
1744	dc->caps.max_v_total = (1 << 15) - 1;
1745	dc->caps.vtotal_limited_by_fp2 = true;
1746
1747	/* Color pipeline capabilities */
1748	dc->caps.color.dpp.dcn_arch = 1;
1749	dc->caps.color.dpp.input_lut_shared = 0;
1750	dc->caps.color.dpp.icsc = 1;
1751	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1752	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1753	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1754	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1755	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1756	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1757	dc->caps.color.dpp.post_csc = 1;
1758	dc->caps.color.dpp.gamma_corr = 1;
1759	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1760
1761	dc->caps.color.dpp.hw_3d_lut = 0;
1762	dc->caps.color.dpp.ogam_ram = 0;
1763	// no OGAM ROM on DCN2 and later ASICs
1764	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1765	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1766	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1767	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1768	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1769	dc->caps.color.dpp.ocsc = 0;
1770
1771	dc->caps.color.mpc.gamut_remap = 1;
1772	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
1773	dc->caps.color.mpc.ogam_ram = 1;
1774	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1775	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1776	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1777	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1778	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1779	dc->caps.color.mpc.ocsc = 1;
1780	dc->caps.color.mpc.preblend = true;
1781
1782	/* Use pipe context based otg sync logic */
1783	dc->config.use_pipe_ctx_sync_logic = true;
1784
1785	dc->config.dc_mode_clk_limit_support = true;
1786	dc->config.enable_windowed_mpo_odm = true;
1787	dc->config.disable_hbr_audio_dp2 = true;
1788	/* read VBIOS LTTPR caps */
1789	{
1790		if (ctx->dc_bios->funcs->get_lttpr_caps) {
1791			enum bp_result bp_query_result;
1792			uint8_t is_vbios_lttpr_enable = 0;
1793
1794			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1795			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1796		}
1797
1798		/* interop bit is implicit */
1799		{
1800			dc->caps.vbios_lttpr_aware = true;
1801		}
1802	}
1803	dc->check_config = config_defaults;
1804
1805	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1806		dc->debug = debug_defaults_drv;
1807
1808	// Init the vm_helper
1809	if (dc->vm_helper)
1810		vm_helper_init(dc->vm_helper, 16);
1811
1812	/*************************************************
1813	 *  Create resources                             *
1814	 *************************************************/
1815
1816	/* Clock Sources for Pixel Clock*/
1817	pool->base.clock_sources[DCN321_CLK_SRC_PLL0] =
1818			dcn321_clock_source_create(ctx, ctx->dc_bios,
1819				CLOCK_SOURCE_COMBO_PHY_PLL0,
1820				&clk_src_regs[0], false);
1821	pool->base.clock_sources[DCN321_CLK_SRC_PLL1] =
1822			dcn321_clock_source_create(ctx, ctx->dc_bios,
1823				CLOCK_SOURCE_COMBO_PHY_PLL1,
1824				&clk_src_regs[1], false);
1825	pool->base.clock_sources[DCN321_CLK_SRC_PLL2] =
1826			dcn321_clock_source_create(ctx, ctx->dc_bios,
1827				CLOCK_SOURCE_COMBO_PHY_PLL2,
1828				&clk_src_regs[2], false);
1829	pool->base.clock_sources[DCN321_CLK_SRC_PLL3] =
1830			dcn321_clock_source_create(ctx, ctx->dc_bios,
1831				CLOCK_SOURCE_COMBO_PHY_PLL3,
1832				&clk_src_regs[3], false);
1833	pool->base.clock_sources[DCN321_CLK_SRC_PLL4] =
1834			dcn321_clock_source_create(ctx, ctx->dc_bios,
1835				CLOCK_SOURCE_COMBO_PHY_PLL4,
1836				&clk_src_regs[4], false);
1837
1838	pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL;
1839
1840	/* todo: not reuse phy_pll registers */
1841	pool->base.dp_clock_source =
1842			dcn321_clock_source_create(ctx, ctx->dc_bios,
1843				CLOCK_SOURCE_ID_DP_DTO,
1844				&clk_src_regs[0], true);
1845
1846	for (i = 0; i < pool->base.clk_src_count; i++) {
1847		if (pool->base.clock_sources[i] == NULL) {
1848			dm_error("DC: failed to create clock sources!\n");
1849			BREAK_TO_DEBUGGER();
1850			goto create_fail;
1851		}
1852	}
1853
1854	/* DCCG */
1855	pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1856	if (pool->base.dccg == NULL) {
1857		dm_error("DC: failed to create dccg!\n");
1858		BREAK_TO_DEBUGGER();
1859		goto create_fail;
1860	}
1861
1862	/* DML */
1863	dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
1864
1865	/* IRQ Service */
1866	init_data.ctx = dc->ctx;
1867	pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
1868	if (!pool->base.irqs)
1869		goto create_fail;
1870
1871	/* HUBBUB */
1872	pool->base.hubbub = dcn321_hubbub_create(ctx);
1873	if (pool->base.hubbub == NULL) {
1874		BREAK_TO_DEBUGGER();
1875		dm_error("DC: failed to create hubbub!\n");
1876		goto create_fail;
1877	}
1878
1879	/* HUBPs, DPPs, OPPs, TGs, ABMs */
1880	for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1881
1882		/* if pipe is disabled, skip instance of HW pipe,
1883		 * i.e, skip ASIC register instance
1884		 */
1885		if (pipe_fuses & 1 << i)
1886			continue;
1887
1888		pool->base.hubps[j] = dcn321_hubp_create(ctx, i);
1889		if (pool->base.hubps[j] == NULL) {
1890			BREAK_TO_DEBUGGER();
1891			dm_error(
1892				"DC: failed to create hubps!\n");
1893			goto create_fail;
1894		}
1895
1896		pool->base.dpps[j] = dcn321_dpp_create(ctx, i);
1897		if (pool->base.dpps[j] == NULL) {
1898			BREAK_TO_DEBUGGER();
1899			dm_error(
1900				"DC: failed to create dpps!\n");
1901			goto create_fail;
1902		}
1903
1904		pool->base.opps[j] = dcn321_opp_create(ctx, i);
1905		if (pool->base.opps[j] == NULL) {
1906			BREAK_TO_DEBUGGER();
1907			dm_error(
1908				"DC: failed to create output pixel processor!\n");
1909			goto create_fail;
1910		}
1911
1912		pool->base.timing_generators[j] = dcn321_timing_generator_create(
1913				ctx, i);
1914		if (pool->base.timing_generators[j] == NULL) {
1915			BREAK_TO_DEBUGGER();
1916			dm_error("DC: failed to create tg!\n");
1917			goto create_fail;
1918		}
1919
1920		pool->base.multiple_abms[j] = dmub_abm_create(ctx,
1921				&abm_regs[i],
1922				&abm_shift,
1923				&abm_mask);
1924		if (pool->base.multiple_abms[j] == NULL) {
1925			dm_error("DC: failed to create abm for pipe %d!\n", i);
1926			BREAK_TO_DEBUGGER();
1927			goto create_fail;
1928		}
1929
1930		/* index for resource pool arrays for next valid pipe */
1931		j++;
1932	}
1933
1934	/* PSR */
1935	pool->base.psr = dmub_psr_create(ctx);
1936	if (pool->base.psr == NULL) {
1937		dm_error("DC: failed to create psr obj!\n");
1938		BREAK_TO_DEBUGGER();
1939		goto create_fail;
1940	}
1941
1942	/* MPCCs */
1943	pool->base.mpc = dcn321_mpc_create(ctx,  pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
1944	if (pool->base.mpc == NULL) {
1945		BREAK_TO_DEBUGGER();
1946		dm_error("DC: failed to create mpc!\n");
1947		goto create_fail;
1948	}
1949
1950	/* DSCs */
1951	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1952		pool->base.dscs[i] = dcn321_dsc_create(ctx, i);
1953		if (pool->base.dscs[i] == NULL) {
1954			BREAK_TO_DEBUGGER();
1955			dm_error("DC: failed to create display stream compressor %d!\n", i);
1956			goto create_fail;
1957		}
1958	}
1959
1960	/* DWB */
1961	if (!dcn321_dwbc_create(ctx, &pool->base)) {
1962		BREAK_TO_DEBUGGER();
1963		dm_error("DC: failed to create dwbc!\n");
1964		goto create_fail;
1965	}
1966
1967	/* MMHUBBUB */
1968	if (!dcn321_mmhubbub_create(ctx, &pool->base)) {
1969		BREAK_TO_DEBUGGER();
1970		dm_error("DC: failed to create mcif_wb!\n");
1971		goto create_fail;
1972	}
1973
1974	/* AUX and I2C */
1975	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1976		pool->base.engines[i] = dcn321_aux_engine_create(ctx, i);
1977		if (pool->base.engines[i] == NULL) {
1978			BREAK_TO_DEBUGGER();
1979			dm_error(
1980				"DC:failed to create aux engine!!\n");
1981			goto create_fail;
1982		}
1983		pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i);
1984		if (pool->base.hw_i2cs[i] == NULL) {
1985			BREAK_TO_DEBUGGER();
1986			dm_error(
1987				"DC:failed to create hw i2c!!\n");
1988			goto create_fail;
1989		}
1990		pool->base.sw_i2cs[i] = NULL;
1991	}
1992
1993	/* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1994	if (!resource_construct(num_virtual_links, dc, &pool->base,
1995			&res_create_funcs))
1996		goto create_fail;
1997
1998	/* HW Sequencer init functions and Plane caps */
1999	dcn32_hw_sequencer_init_functions(dc);
2000
2001	dc->caps.max_planes =  pool->base.pipe_count;
2002
2003	for (i = 0; i < dc->caps.max_planes; ++i)
2004		dc->caps.planes[i] = plane_cap;
2005
2006	dc->caps.max_odm_combine_factor = 4;
2007
2008	dc->cap_funcs = cap_funcs;
2009
2010	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2011		ddc_init_data.ctx = dc->ctx;
2012		ddc_init_data.link = NULL;
2013		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2014		ddc_init_data.id.enum_id = 0;
2015		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2016		pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2017	} else {
2018		pool->base.oem_device = NULL;
2019	}
2020
2021	dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2022	dc->dml2_options.use_native_soc_bb_construction = true;
2023	dc->dml2_options.minimize_dispclk_using_odm = true;
2024
2025	resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2026	dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2027	dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2028	dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2029
2030	dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2031	dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2032	dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2033	dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2034
2035	dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2036	dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2037
2038	dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2039	dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2040	dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2041	dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2042	dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2043	dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2044	dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2045
2046	dc->dml2_options.max_segments_per_hubp = 18;
2047	dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
2048
2049	/* init DC limited DML2 options */
2050	memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
2051	dc->dml2_dc_power_options.use_clock_dc_limits = true;
2052
2053	return true;
2054
2055create_fail:
2056
2057	dcn321_resource_destruct(pool);
2058
2059	return false;
2060}
2061
2062struct resource_pool *dcn321_create_resource_pool(
2063		const struct dc_init_data *init_data,
2064		struct dc *dc)
2065{
2066	struct dcn321_resource_pool *pool =
2067		kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL);
2068
2069	if (!pool)
2070		return NULL;
2071
2072	if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))
2073		return &pool->base;
2074
2075	BREAK_TO_DEBUGGER();
2076	kfree(pool);
2077	return NULL;
2078}
~/ Read-only file preview.