FILE
dcn32_resource.c
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1// SPDX-License-Identifier: MIT 2/* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27#include "dc_types.h" 28#include "dm_services.h" 29#include "dc.h" 30 31#include "dcn32/dcn32_init.h" 32 33#include "resource.h" 34#include "include/irq_service_interface.h" 35#include "dcn32_resource.h" 36 37#include "dcn20/dcn20_resource.h" 38#include "dcn30/dcn30_resource.h" 39 40#include "dcn10/dcn10_ipp.h" 41#include "dcn30/dcn30_hubbub.h" 42#include "dcn31/dcn31_hubbub.h" 43#include "dcn32/dcn32_hubbub.h" 44#include "dcn32/dcn32_mpc.h" 45#include "dcn32/dcn32_hubp.h" 46#include "irq/dcn32/irq_service_dcn32.h" 47#include "dcn32/dcn32_dpp.h" 48#include "dcn32/dcn32_optc.h" 49#include "dcn20/dcn20_hwseq.h" 50#include "dcn30/dcn30_hwseq.h" 51#include "dce110/dce110_hwseq.h" 52#include "dcn30/dcn30_opp.h" 53#include "dcn20/dcn20_dsc.h" 54#include "dcn30/dcn30_vpg.h" 55#include "dcn30/dcn30_afmt.h" 56#include "dcn30/dcn30_dio_stream_encoder.h" 57#include "dcn32/dcn32_dio_stream_encoder.h" 58#include "dcn31/dcn31_hpo_dp_stream_encoder.h" 59#include "dcn31/dcn31_hpo_dp_link_encoder.h" 60#include "dcn32/dcn32_hpo_dp_link_encoder.h" 61#include "dcn31/dcn31_apg.h" 62#include "dcn31/dcn31_dio_link_encoder.h" 63#include "dcn32/dcn32_dio_link_encoder.h" 64#include "dce/dce_clock_source.h" 65#include "dce/dce_audio.h" 66#include "dce/dce_hwseq.h" 67#include "clk_mgr.h" 68#include "virtual/virtual_stream_encoder.h" 69#include "dml/display_mode_vba.h" 70#include "dcn32/dcn32_dccg.h" 71#include "dcn10/dcn10_resource.h" 72#include "link_service.h" 73#include "dcn31/dcn31_panel_cntl.h" 74 75#include "dcn30/dcn30_dwb.h" 76#include "dcn32/dcn32_mmhubbub.h" 77 78#include "dcn/dcn_3_2_0_offset.h" 79#include "dcn/dcn_3_2_0_sh_mask.h" 80#include "nbio/nbio_4_3_0_offset.h" 81 82#include "reg_helper.h" 83#include "dce/dmub_abm.h" 84#include "dce/dmub_psr.h" 85#include "dce/dce_aux.h" 86#include "dce/dce_i2c.h" 87 88#include "dml/dcn30/display_mode_vba_30.h" 89#include "vm_helper.h" 90#include "dcn20/dcn20_vmid.h" 91#include "dml/dcn32/dcn32_fpu.h" 92 93#include "dc_state_priv.h" 94 95#include "dml2_0/dml2_wrapper.h" 96 97#define DC_LOGGER_INIT(logger) 98 99enum dcn32_clk_src_array_id { 100 DCN32_CLK_SRC_PLL0, 101 DCN32_CLK_SRC_PLL1, 102 DCN32_CLK_SRC_PLL2, 103 DCN32_CLK_SRC_PLL3, 104 DCN32_CLK_SRC_PLL4, 105 DCN32_CLK_SRC_TOTAL 106}; 107 108/* begin ********************* 109 * macros to expend register list macro defined in HW object header file 110 */ 111 112/* DCN */ 113#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 114 115#define BASE(seg) BASE_INNER(seg) 116 117#define SR(reg_name)\ 118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 119 reg ## reg_name 120#define SR_ARR(reg_name, id) \ 121 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 122 123#define SR_ARR_INIT(reg_name, id, value) \ 124 REG_STRUCT[id].reg_name = value 125 126#define SRI(reg_name, block, id)\ 127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 128 reg ## block ## id ## _ ## reg_name 129 130#define SRI_ARR(reg_name, block, id)\ 131 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 132 reg ## block ## id ## _ ## reg_name 133 134#define SR_ARR_I2C(reg_name, id) \ 135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 136 137#define SRI_ARR_I2C(reg_name, block, id)\ 138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 139 reg ## block ## id ## _ ## reg_name 140 141#define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 142 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 143 reg ## block ## id ## _ ## reg_name 144 145#define SRI2(reg_name, block, id)\ 146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 147 reg ## reg_name 148#define SRI2_ARR(reg_name, block, id)\ 149 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 150 reg ## reg_name 151 152#define SRIR(var_name, reg_name, block, id)\ 153 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 154 reg ## block ## id ## _ ## reg_name 155 156#define SRII(reg_name, block, id)\ 157 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 158 reg ## block ## id ## _ ## reg_name 159 160#define SRII_ARR_2(reg_name, block, id, inst)\ 161 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 162 reg ## block ## id ## _ ## reg_name 163 164#define SRII_MPC_RMU(reg_name, block, id)\ 165 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 166 reg ## block ## id ## _ ## reg_name 167 168#define SRII_DWB(reg_name, temp_name, block, id)\ 169 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 170 reg ## block ## id ## _ ## temp_name 171 172#define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 173 .field_name = reg_name ## __ ## field_name ## post_fix 174 175#define DCCG_SRII(reg_name, block, id)\ 176 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 reg ## block ## id ## _ ## reg_name 178 179#define VUPDATE_SRII(reg_name, block, id)\ 180 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 181 reg ## reg_name ## _ ## block ## id 182 183/* NBIO */ 184#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 185 186#define NBIO_BASE(seg) \ 187 NBIO_BASE_INNER(seg) 188 189#define NBIO_SR(reg_name)\ 190 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 191 regBIF_BX0_ ## reg_name 192#define NBIO_SR_ARR(reg_name, id)\ 193 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 194 regBIF_BX0_ ## reg_name 195 196#undef CTX 197#define CTX ctx 198#define REG(reg_name) \ 199 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 200 201static struct bios_registers bios_regs; 202 203#define bios_regs_init() \ 204 ( \ 205 NBIO_SR(BIOS_SCRATCH_3),\ 206 NBIO_SR(BIOS_SCRATCH_6)\ 207 ) 208 209#define clk_src_regs_init(index, pllid)\ 210 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 211 212static struct dce110_clk_src_regs clk_src_regs[5]; 213 214static const struct dce110_clk_src_shift cs_shift = { 215 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 216}; 217 218static const struct dce110_clk_src_mask cs_mask = { 219 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 220}; 221 222#define abm_regs_init(id)\ 223 ABM_DCN32_REG_LIST_RI(id) 224 225static struct dce_abm_registers abm_regs[4]; 226 227static const struct dce_abm_shift abm_shift = { 228 ABM_MASK_SH_LIST_DCN32(__SHIFT) 229}; 230 231static const struct dce_abm_mask abm_mask = { 232 ABM_MASK_SH_LIST_DCN32(_MASK) 233}; 234 235#define audio_regs_init(id)\ 236 AUD_COMMON_REG_LIST_RI(id) 237 238static struct dce_audio_registers audio_regs[5]; 239 240#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 241 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 242 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 243 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 244 245static const struct dce_audio_shift audio_shift = { 246 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 247}; 248 249static const struct dce_audio_mask audio_mask = { 250 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 251}; 252 253#define vpg_regs_init(id)\ 254 VPG_DCN3_REG_LIST_RI(id) 255 256static struct dcn30_vpg_registers vpg_regs[10]; 257 258static const struct dcn30_vpg_shift vpg_shift = { 259 DCN3_VPG_MASK_SH_LIST(__SHIFT) 260}; 261 262static const struct dcn30_vpg_mask vpg_mask = { 263 DCN3_VPG_MASK_SH_LIST(_MASK) 264}; 265 266#define afmt_regs_init(id)\ 267 AFMT_DCN3_REG_LIST_RI(id) 268 269static struct dcn30_afmt_registers afmt_regs[6]; 270 271static const struct dcn30_afmt_shift afmt_shift = { 272 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 273}; 274 275static const struct dcn30_afmt_mask afmt_mask = { 276 DCN3_AFMT_MASK_SH_LIST(_MASK) 277}; 278 279#define apg_regs_init(id)\ 280 APG_DCN31_REG_LIST_RI(id) 281 282static struct dcn31_apg_registers apg_regs[4]; 283 284static const struct dcn31_apg_shift apg_shift = { 285 DCN31_APG_MASK_SH_LIST(__SHIFT) 286}; 287 288static const struct dcn31_apg_mask apg_mask = { 289 DCN31_APG_MASK_SH_LIST(_MASK) 290}; 291 292#define stream_enc_regs_init(id)\ 293 SE_DCN32_REG_LIST_RI(id) 294 295static struct dcn10_stream_enc_registers stream_enc_regs[5]; 296 297static const struct dcn10_stream_encoder_shift se_shift = { 298 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 299}; 300 301static const struct dcn10_stream_encoder_mask se_mask = { 302 SE_COMMON_MASK_SH_LIST_DCN32(_MASK) 303}; 304 305 306#define aux_regs_init(id)\ 307 DCN2_AUX_REG_LIST_RI(id) 308 309static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 310 311#define hpd_regs_init(id)\ 312 HPD_REG_LIST_RI(id) 313 314static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 315 316#define link_regs_init(id, phyid)\ 317 ( \ 318 LE_DCN31_REG_LIST_RI(id), \ 319 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 320 ) 321 /*DPCS_DCN31_REG_LIST(id),*/ \ 322 323static struct dcn10_link_enc_registers link_enc_regs[5]; 324 325static const struct dcn10_link_enc_shift le_shift = { 326 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 327 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 328}; 329 330static const struct dcn10_link_enc_mask le_mask = { 331 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 332 //DPCS_DCN31_MASK_SH_LIST(_MASK) 333}; 334 335#define hpo_dp_stream_encoder_reg_init(id)\ 336 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 337 338static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 339 340static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 341 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 342}; 343 344static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 345 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 346}; 347 348 349#define hpo_dp_link_encoder_reg_init(id)\ 350 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 351 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 352 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 353 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 354 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 355 356static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 357 358static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 359 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 360}; 361 362static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 363 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 364}; 365 366#define dpp_regs_init(id)\ 367 DPP_REG_LIST_DCN30_COMMON_RI(id) 368 369static struct dcn3_dpp_registers dpp_regs[4]; 370 371static const struct dcn3_dpp_shift tf_shift = { 372 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT) 373}; 374 375static const struct dcn3_dpp_mask tf_mask = { 376 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK) 377}; 378 379 380#define opp_regs_init(id)\ 381 OPP_REG_LIST_DCN30_RI(id) 382 383static struct dcn20_opp_registers opp_regs[4]; 384 385static const struct dcn20_opp_shift opp_shift = { 386 OPP_MASK_SH_LIST_DCN20(__SHIFT) 387}; 388 389static const struct dcn20_opp_mask opp_mask = { 390 OPP_MASK_SH_LIST_DCN20(_MASK) 391}; 392 393#define aux_engine_regs_init(id)\ 394 ( \ 395 AUX_COMMON_REG_LIST0_RI(id), \ 396 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 397 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 398 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 399 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\ 400 ) 401 402static struct dce110_aux_registers aux_engine_regs[5]; 403 404static const struct dce110_aux_registers_shift aux_shift = { 405 DCN_AUX_MASK_SH_LIST(__SHIFT) 406}; 407 408static const struct dce110_aux_registers_mask aux_mask = { 409 DCN_AUX_MASK_SH_LIST(_MASK) 410}; 411 412#define dwbc_regs_dcn3_init(id)\ 413 DWBC_COMMON_REG_LIST_DCN30_RI(id) 414 415static struct dcn30_dwbc_registers dwbc30_regs[1]; 416 417static const struct dcn30_dwbc_shift dwbc30_shift = { 418 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 419}; 420 421static const struct dcn30_dwbc_mask dwbc30_mask = { 422 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 423}; 424 425#define mcif_wb_regs_dcn3_init(id)\ 426 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id) 427 428static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; 429 430static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 432}; 433 434static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 435 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK) 436}; 437 438#define dsc_regsDCN20_init(id)\ 439 DSC_REG_LIST_DCN20_RI(id) 440 441static struct dcn20_dsc_registers dsc_regs[4]; 442 443static const struct dcn20_dsc_shift dsc_shift = { 444 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 445}; 446 447static const struct dcn20_dsc_mask dsc_mask = { 448 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 449}; 450 451static struct dcn30_mpc_registers mpc_regs; 452 453#define dcn_mpc_regs_init() \ 454 MPC_REG_LIST_DCN3_2_RI(0),\ 455 MPC_REG_LIST_DCN3_2_RI(1),\ 456 MPC_REG_LIST_DCN3_2_RI(2),\ 457 MPC_REG_LIST_DCN3_2_RI(3),\ 458 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 459 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 460 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 461 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 462 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 463 464static const struct dcn30_mpc_shift mpc_shift = { 465 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 466}; 467 468static const struct dcn30_mpc_mask mpc_mask = { 469 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 470}; 471 472#define optc_regs_init(id)\ 473 OPTC_COMMON_REG_LIST_DCN3_2_RI(id) 474 475static struct dcn_optc_registers optc_regs[4]; 476 477static const struct dcn_optc_shift optc_shift = { 478 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 479}; 480 481static const struct dcn_optc_mask optc_mask = { 482 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 483}; 484 485#define hubp_regs_init(id)\ 486 HUBP_REG_LIST_DCN32_RI(id) 487 488static struct dcn_hubp2_registers hubp_regs[4]; 489 490 491static const struct dcn_hubp2_shift hubp_shift = { 492 HUBP_MASK_SH_LIST_DCN32(__SHIFT) 493}; 494 495static const struct dcn_hubp2_mask hubp_mask = { 496 HUBP_MASK_SH_LIST_DCN32(_MASK) 497}; 498 499static struct dcn_hubbub_registers hubbub_reg; 500#define hubbub_reg_init()\ 501 HUBBUB_REG_LIST_DCN32_RI(0) 502 503static const struct dcn_hubbub_shift hubbub_shift = { 504 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT) 505}; 506 507static const struct dcn_hubbub_mask hubbub_mask = { 508 HUBBUB_MASK_SH_LIST_DCN32(_MASK) 509}; 510 511static struct dccg_registers dccg_regs; 512 513#define dccg_regs_init()\ 514 DCCG_REG_LIST_DCN32_RI() 515 516static const struct dccg_shift dccg_shift = { 517 DCCG_MASK_SH_LIST_DCN32(__SHIFT) 518}; 519 520static const struct dccg_mask dccg_mask = { 521 DCCG_MASK_SH_LIST_DCN32(_MASK) 522}; 523 524 525#define SRII2(reg_name_pre, reg_name_post, id)\ 526 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 527 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 528 reg ## reg_name_pre ## id ## _ ## reg_name_post 529 530 531#define HWSEQ_DCN32_REG_LIST()\ 532 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 533 SR(DIO_MEM_PWR_CTRL), \ 534 SR(ODM_MEM_PWR_CTRL3), \ 535 SR(MMHUBBUB_MEM_PWR_CNTL), \ 536 SR(DCCG_GATE_DISABLE_CNTL), \ 537 SR(DCCG_GATE_DISABLE_CNTL2), \ 538 SR(DCFCLK_CNTL),\ 539 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 540 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 541 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 542 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 543 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 544 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 545 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 546 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 547 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 548 SR(MICROSECOND_TIME_BASE_DIV), \ 549 SR(MILLISECOND_TIME_BASE_DIV), \ 550 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 551 SR(RBBMIF_TIMEOUT_DIS), \ 552 SR(RBBMIF_TIMEOUT_DIS_2), \ 553 SR(DCHUBBUB_CRC_CTRL), \ 554 SR(DPP_TOP0_DPP_CRC_CTRL), \ 555 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 556 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 557 SR(MPC_CRC_CTRL), \ 558 SR(MPC_CRC_RESULT_GB), \ 559 SR(MPC_CRC_RESULT_C), \ 560 SR(MPC_CRC_RESULT_AR), \ 561 SR(DOMAIN0_PG_CONFIG), \ 562 SR(DOMAIN1_PG_CONFIG), \ 563 SR(DOMAIN2_PG_CONFIG), \ 564 SR(DOMAIN3_PG_CONFIG), \ 565 SR(DOMAIN16_PG_CONFIG), \ 566 SR(DOMAIN17_PG_CONFIG), \ 567 SR(DOMAIN18_PG_CONFIG), \ 568 SR(DOMAIN19_PG_CONFIG), \ 569 SR(DOMAIN0_PG_STATUS), \ 570 SR(DOMAIN1_PG_STATUS), \ 571 SR(DOMAIN2_PG_STATUS), \ 572 SR(DOMAIN3_PG_STATUS), \ 573 SR(DOMAIN16_PG_STATUS), \ 574 SR(DOMAIN17_PG_STATUS), \ 575 SR(DOMAIN18_PG_STATUS), \ 576 SR(DOMAIN19_PG_STATUS), \ 577 SR(D1VGA_CONTROL), \ 578 SR(D2VGA_CONTROL), \ 579 SR(D3VGA_CONTROL), \ 580 SR(D4VGA_CONTROL), \ 581 SR(D5VGA_CONTROL), \ 582 SR(D6VGA_CONTROL), \ 583 SR(DC_IP_REQUEST_CNTL), \ 584 SR(AZALIA_AUDIO_DTO), \ 585 SR(AZALIA_CONTROLLER_CLOCK_GATING) 586 587static struct dce_hwseq_registers hwseq_reg; 588 589#define hwseq_reg_init()\ 590 HWSEQ_DCN32_REG_LIST() 591 592#define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\ 593 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 594 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 595 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 596 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 597 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 606 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 607 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 608 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 609 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 610 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 611 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 615 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 616 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 617 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 618 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 619 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 620 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 621 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 622 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 623 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 624 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) 625 626static const struct dce_hwseq_shift hwseq_shift = { 627 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT) 628}; 629 630static const struct dce_hwseq_mask hwseq_mask = { 631 HWSEQ_DCN32_MASK_SH_LIST(_MASK) 632}; 633#define vmid_regs_init(id)\ 634 DCN20_VMID_REG_LIST_RI(id) 635 636static struct dcn_vmid_registers vmid_regs[16]; 637 638static const struct dcn20_vmid_shift vmid_shifts = { 639 DCN20_VMID_MASK_SH_LIST(__SHIFT) 640}; 641 642static const struct dcn20_vmid_mask vmid_masks = { 643 DCN20_VMID_MASK_SH_LIST(_MASK) 644}; 645 646static const struct resource_caps res_cap_dcn32 = { 647 .num_timing_generator = 4, 648 .num_opp = 4, 649 .num_video_plane = 4, 650 .num_audio = 5, 651 .num_stream_encoder = 5, 652 .num_hpo_dp_stream_encoder = 4, 653 .num_hpo_dp_link_encoder = 2, 654 .num_pll = 5, 655 .num_dwb = 1, 656 .num_ddc = 5, 657 .num_vmid = 16, 658 .num_mpc_3dlut = 4, 659 .num_dsc = 4, 660}; 661 662static const struct dc_plane_cap plane_cap = { 663 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 664 .per_pixel_alpha = true, 665 666 .pixel_format_support = { 667 .argb8888 = true, 668 .nv12 = true, 669 .fp16 = true, 670 .p010 = true, 671 .ayuv = false, 672 }, 673 674 .max_upscale_factor = { 675 .argb8888 = 16000, 676 .nv12 = 16000, 677 .fp16 = 16000 678 }, 679 680 // 6:1 downscaling ratio: 1000/6 = 166.666 681 .max_downscale_factor = { 682 .argb8888 = 167, 683 .nv12 = 167, 684 .fp16 = 167 685 }, 686 64, 687 64 688}; 689 690static const struct dc_debug_options debug_defaults_drv = { 691 .disable_dmcu = true, 692 .force_abm_enable = false, 693 .clock_trace = true, 694 .disable_pplib_clock_request = false, 695 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore 696 .force_single_disp_pipe_split = false, 697 .disable_dcc = DCC_ENABLE, 698 .vsr_support = true, 699 .performance_trace = false, 700 .max_downscale_src_width = 7680,/*upto 8K*/ 701 .disable_pplib_wm_range = false, 702 .scl_reset_length10 = true, 703 .sanity_checks = false, 704 .underflow_assert_delay_us = 0xFFFFFFFF, 705 .dwb_fi_phase = -1, // -1 = disable, 706 .dmub_command_table = true, 707 .enable_mem_low_power = { 708 .bits = { 709 .vga = false, 710 .i2c = false, 711 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 712 .dscl = false, 713 .cm = false, 714 .mpc = false, 715 .optc = true, 716 } 717 }, 718 .use_max_lb = true, 719 .force_disable_subvp = false, 720 .exit_idle_opt_for_cursor_updates = true, 721 .using_dml2 = false, 722 .using_dml21 = false, // TODO : Temporary for N-1 validation. Remove after N-1 is done. 723 .enable_single_display_2to1_odm_policy = true, 724 725 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ 726 .enable_double_buffered_dsc_pg_support = true, 727 .enable_dp_dig_pixel_rate_div_policy = 1, 728 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback" 729 .alloc_extra_way_for_cursor = true, 730 .min_prefetch_in_strobe_ns = 60000, // 60us 731 .disable_unbounded_requesting = false, 732 .override_dispclk_programming = true, 733 .disable_fpo_optimizations = false, 734 .fpo_vactive_margin_us = 2000, // 2000us 735 .disable_fpo_vactive = false, 736 .disable_boot_optimizations = false, 737 .disable_subvp_high_refresh = false, 738 .disable_dp_plus_plus_wa = true, 739 .fpo_vactive_min_active_margin_us = 200, 740 .fpo_vactive_max_blank_us = 1000, 741 .disable_stutter_for_wm_program = true 742}; 743 744static const struct dc_check_config config_defaults = { 745 .enable_legacy_fast_update = false, 746}; 747 748static struct dce_aux *dcn32_aux_engine_create( 749 struct dc_context *ctx, 750 uint32_t inst) 751{ 752 struct aux_engine_dce110 *aux_engine = 753 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 754 755 if (!aux_engine) 756 return NULL; 757 758#undef REG_STRUCT 759#define REG_STRUCT aux_engine_regs 760 aux_engine_regs_init(0), 761 aux_engine_regs_init(1), 762 aux_engine_regs_init(2), 763 aux_engine_regs_init(3), 764 aux_engine_regs_init(4); 765 766 dce110_aux_engine_construct(aux_engine, ctx, inst, 767 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 768 &aux_engine_regs[inst], 769 &aux_mask, 770 &aux_shift, 771 ctx->dc->caps.extended_aux_timeout_support); 772 773 return &aux_engine->base; 774} 775#define i2c_inst_regs_init(id)\ 776 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 777 778static struct dce_i2c_registers i2c_hw_regs[5]; 779 780static const struct dce_i2c_shift i2c_shifts = { 781 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 782}; 783 784static const struct dce_i2c_mask i2c_masks = { 785 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 786}; 787 788static struct dce_i2c_hw *dcn32_i2c_hw_create( 789 struct dc_context *ctx, 790 uint32_t inst) 791{ 792 struct dce_i2c_hw *dce_i2c_hw = 793 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 794 795 if (!dce_i2c_hw) 796 return NULL; 797 798#undef REG_STRUCT 799#define REG_STRUCT i2c_hw_regs 800 i2c_inst_regs_init(1), 801 i2c_inst_regs_init(2), 802 i2c_inst_regs_init(3), 803 i2c_inst_regs_init(4), 804 i2c_inst_regs_init(5); 805 806 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 807 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 808 809 return dce_i2c_hw; 810} 811 812static struct clock_source *dcn32_clock_source_create( 813 struct dc_context *ctx, 814 struct dc_bios *bios, 815 enum clock_source_id id, 816 const struct dce110_clk_src_regs *regs, 817 bool dp_clk_src) 818{ 819 struct dce110_clk_src *clk_src = 820 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 821 822 if (!clk_src) 823 return NULL; 824 825 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 826 regs, &cs_shift, &cs_mask)) { 827 clk_src->base.dp_clk_src = dp_clk_src; 828 return &clk_src->base; 829 } 830 831 kfree(clk_src); 832 BREAK_TO_DEBUGGER(); 833 return NULL; 834} 835 836static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 837{ 838 int i; 839 840 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), 841 GFP_KERNEL); 842 843 if (!hubbub2) 844 return NULL; 845 846#undef REG_STRUCT 847#define REG_STRUCT hubbub_reg 848 hubbub_reg_init(); 849 850#undef REG_STRUCT 851#define REG_STRUCT vmid_regs 852 vmid_regs_init(0), 853 vmid_regs_init(1), 854 vmid_regs_init(2), 855 vmid_regs_init(3), 856 vmid_regs_init(4), 857 vmid_regs_init(5), 858 vmid_regs_init(6), 859 vmid_regs_init(7), 860 vmid_regs_init(8), 861 vmid_regs_init(9), 862 vmid_regs_init(10), 863 vmid_regs_init(11), 864 vmid_regs_init(12), 865 vmid_regs_init(13), 866 vmid_regs_init(14), 867 vmid_regs_init(15); 868 869 hubbub32_construct(hubbub2, ctx, 870 &hubbub_reg, 871 &hubbub_shift, 872 &hubbub_mask, 873 ctx->dc->dml.ip.det_buffer_size_kbytes, 874 ctx->dc->dml.ip.pixel_chunk_size_kbytes, 875 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); 876 877 878 for (i = 0; i < res_cap_dcn32.num_vmid; i++) { 879 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 880 881 vmid->ctx = ctx; 882 883 vmid->regs = &vmid_regs[i]; 884 vmid->shifts = &vmid_shifts; 885 vmid->masks = &vmid_masks; 886 } 887 888 return &hubbub2->base; 889} 890 891static struct hubp *dcn32_hubp_create( 892 struct dc_context *ctx, 893 uint32_t inst) 894{ 895 struct dcn20_hubp *hubp2 = 896 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 897 898 if (!hubp2) 899 return NULL; 900 901#undef REG_STRUCT 902#define REG_STRUCT hubp_regs 903 hubp_regs_init(0), 904 hubp_regs_init(1), 905 hubp_regs_init(2), 906 hubp_regs_init(3); 907 908 if (hubp32_construct(hubp2, ctx, inst, 909 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 910 return &hubp2->base; 911 912 BREAK_TO_DEBUGGER(); 913 kfree(hubp2); 914 return NULL; 915} 916 917static void dcn32_dpp_destroy(struct dpp **dpp) 918{ 919 kfree(TO_DCN30_DPP(*dpp)); 920 *dpp = NULL; 921} 922 923static struct dpp *dcn32_dpp_create( 924 struct dc_context *ctx, 925 uint32_t inst) 926{ 927 struct dcn3_dpp *dpp3 = 928 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 929 930 if (!dpp3) 931 return NULL; 932 933#undef REG_STRUCT 934#define REG_STRUCT dpp_regs 935 dpp_regs_init(0), 936 dpp_regs_init(1), 937 dpp_regs_init(2), 938 dpp_regs_init(3); 939 940 if (dpp32_construct(dpp3, ctx, inst, 941 &dpp_regs[inst], &tf_shift, &tf_mask)) 942 return &dpp3->base; 943 944 BREAK_TO_DEBUGGER(); 945 kfree(dpp3); 946 return NULL; 947} 948 949static struct mpc *dcn32_mpc_create( 950 struct dc_context *ctx, 951 int num_mpcc, 952 int num_rmu) 953{ 954 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 955 GFP_KERNEL); 956 957 if (!mpc30) 958 return NULL; 959 960#undef REG_STRUCT 961#define REG_STRUCT mpc_regs 962 dcn_mpc_regs_init(); 963 964 dcn32_mpc_construct(mpc30, ctx, 965 &mpc_regs, 966 &mpc_shift, 967 &mpc_mask, 968 num_mpcc, 969 num_rmu); 970 971 return &mpc30->base; 972} 973 974static struct output_pixel_processor *dcn32_opp_create( 975 struct dc_context *ctx, uint32_t inst) 976{ 977 struct dcn20_opp *opp2 = 978 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 979 980 if (!opp2) { 981 BREAK_TO_DEBUGGER(); 982 return NULL; 983 } 984 985#undef REG_STRUCT 986#define REG_STRUCT opp_regs 987 opp_regs_init(0), 988 opp_regs_init(1), 989 opp_regs_init(2), 990 opp_regs_init(3); 991 992 dcn20_opp_construct(opp2, ctx, inst, 993 &opp_regs[inst], &opp_shift, &opp_mask); 994 return &opp2->base; 995} 996 997 998static struct timing_generator *dcn32_timing_generator_create( 999 struct dc_context *ctx, 1000 uint32_t instance) 1001{ 1002 struct optc *tgn10 = 1003 kzalloc(sizeof(struct optc), GFP_KERNEL); 1004 1005 if (!tgn10) 1006 return NULL; 1007 1008#undef REG_STRUCT 1009#define REG_STRUCT optc_regs 1010 optc_regs_init(0), 1011 optc_regs_init(1), 1012 optc_regs_init(2), 1013 optc_regs_init(3); 1014 1015 tgn10->base.inst = instance; 1016 tgn10->base.ctx = ctx; 1017 1018 tgn10->tg_regs = &optc_regs[instance]; 1019 tgn10->tg_shift = &optc_shift; 1020 tgn10->tg_mask = &optc_mask; 1021 1022 dcn32_timing_generator_init(tgn10); 1023 1024 return &tgn10->base; 1025} 1026 1027static const struct encoder_feature_support link_enc_feature = { 1028 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1029 .max_hdmi_pixel_clock = 600000, 1030 .hdmi_ycbcr420_supported = true, 1031 .dp_ycbcr420_supported = true, 1032 .fec_supported = true, 1033 .flags.bits.IS_HBR2_CAPABLE = true, 1034 .flags.bits.IS_HBR3_CAPABLE = true, 1035 .flags.bits.IS_TPS3_CAPABLE = true, 1036 .flags.bits.IS_TPS4_CAPABLE = true 1037}; 1038 1039static struct link_encoder *dcn32_link_encoder_create( 1040 struct dc_context *ctx, 1041 const struct encoder_init_data *enc_init_data) 1042{ 1043 struct dcn20_link_encoder *enc20 = 1044 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1045 1046 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 1047 return NULL; 1048 1049#undef REG_STRUCT 1050#define REG_STRUCT link_enc_aux_regs 1051 aux_regs_init(0), 1052 aux_regs_init(1), 1053 aux_regs_init(2), 1054 aux_regs_init(3), 1055 aux_regs_init(4); 1056 1057#undef REG_STRUCT 1058#define REG_STRUCT link_enc_hpd_regs 1059 hpd_regs_init(0), 1060 hpd_regs_init(1), 1061 hpd_regs_init(2), 1062 hpd_regs_init(3), 1063 hpd_regs_init(4); 1064 1065#undef REG_STRUCT 1066#define REG_STRUCT link_enc_regs 1067 link_regs_init(0, A), 1068 link_regs_init(1, B), 1069 link_regs_init(2, C), 1070 link_regs_init(3, D), 1071 link_regs_init(4, E); 1072 1073 dcn32_link_encoder_construct(enc20, 1074 enc_init_data, 1075 &link_enc_feature, 1076 &link_enc_regs[enc_init_data->transmitter], 1077 &link_enc_aux_regs[enc_init_data->channel - 1], 1078 &link_enc_hpd_regs[enc_init_data->hpd_source], 1079 &le_shift, 1080 &le_mask); 1081 1082 return &enc20->enc10.base; 1083} 1084 1085struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1086{ 1087 struct dcn31_panel_cntl *panel_cntl = 1088 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1089 1090 if (!panel_cntl) 1091 return NULL; 1092 1093 dcn31_panel_cntl_construct(panel_cntl, init_data); 1094 1095 return &panel_cntl->base; 1096} 1097 1098static void read_dce_straps( 1099 struct dc_context *ctx, 1100 struct resource_straps *straps) 1101{ 1102 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, 1103 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1104 1105} 1106 1107static struct audio *dcn32_create_audio( 1108 struct dc_context *ctx, unsigned int inst) 1109{ 1110 1111#undef REG_STRUCT 1112#define REG_STRUCT audio_regs 1113 audio_regs_init(0), 1114 audio_regs_init(1), 1115 audio_regs_init(2), 1116 audio_regs_init(3), 1117 audio_regs_init(4); 1118 1119 return dce_audio_create(ctx, inst, 1120 &audio_regs[inst], &audio_shift, &audio_mask); 1121} 1122 1123static struct vpg *dcn32_vpg_create( 1124 struct dc_context *ctx, 1125 uint32_t inst) 1126{ 1127 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1128 1129 if (!vpg3) 1130 return NULL; 1131 1132#undef REG_STRUCT 1133#define REG_STRUCT vpg_regs 1134 vpg_regs_init(0), 1135 vpg_regs_init(1), 1136 vpg_regs_init(2), 1137 vpg_regs_init(3), 1138 vpg_regs_init(4), 1139 vpg_regs_init(5), 1140 vpg_regs_init(6), 1141 vpg_regs_init(7), 1142 vpg_regs_init(8), 1143 vpg_regs_init(9); 1144 1145 vpg3_construct(vpg3, ctx, inst, 1146 &vpg_regs[inst], 1147 &vpg_shift, 1148 &vpg_mask); 1149 1150 return &vpg3->base; 1151} 1152 1153static struct afmt *dcn32_afmt_create( 1154 struct dc_context *ctx, 1155 uint32_t inst) 1156{ 1157 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1158 1159 if (!afmt3) 1160 return NULL; 1161 1162#undef REG_STRUCT 1163#define REG_STRUCT afmt_regs 1164 afmt_regs_init(0), 1165 afmt_regs_init(1), 1166 afmt_regs_init(2), 1167 afmt_regs_init(3), 1168 afmt_regs_init(4), 1169 afmt_regs_init(5); 1170 1171 afmt3_construct(afmt3, ctx, inst, 1172 &afmt_regs[inst], 1173 &afmt_shift, 1174 &afmt_mask); 1175 1176 return &afmt3->base; 1177} 1178 1179static struct apg *dcn31_apg_create( 1180 struct dc_context *ctx, 1181 uint32_t inst) 1182{ 1183 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1184 1185 if (!apg31) 1186 return NULL; 1187 1188#undef REG_STRUCT 1189#define REG_STRUCT apg_regs 1190 apg_regs_init(0), 1191 apg_regs_init(1), 1192 apg_regs_init(2), 1193 apg_regs_init(3); 1194 1195 apg31_construct(apg31, ctx, inst, 1196 &apg_regs[inst], 1197 &apg_shift, 1198 &apg_mask); 1199 1200 return &apg31->base; 1201} 1202 1203static struct stream_encoder *dcn32_stream_encoder_create( 1204 enum engine_id eng_id, 1205 struct dc_context *ctx) 1206{ 1207 struct dcn10_stream_encoder *enc1; 1208 struct vpg *vpg; 1209 struct afmt *afmt; 1210 int vpg_inst; 1211 int afmt_inst; 1212 1213 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1214 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) 1215 return NULL; 1216 1217 vpg_inst = eng_id; 1218 afmt_inst = eng_id; 1219 1220 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1221 vpg = dcn32_vpg_create(ctx, vpg_inst); 1222 afmt = dcn32_afmt_create(ctx, afmt_inst); 1223 1224 if (!enc1 || !vpg || !afmt) { 1225 kfree(enc1); 1226 kfree(vpg); 1227 kfree(afmt); 1228 return NULL; 1229 } 1230 1231#undef REG_STRUCT 1232#define REG_STRUCT stream_enc_regs 1233 stream_enc_regs_init(0), 1234 stream_enc_regs_init(1), 1235 stream_enc_regs_init(2), 1236 stream_enc_regs_init(3), 1237 stream_enc_regs_init(4); 1238 1239 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1240 eng_id, vpg, afmt, 1241 &stream_enc_regs[eng_id], 1242 &se_shift, &se_mask); 1243 1244 return &enc1->base; 1245} 1246 1247static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 1248 enum engine_id eng_id, 1249 struct dc_context *ctx) 1250{ 1251 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1252 struct vpg *vpg; 1253 struct apg *apg; 1254 uint32_t hpo_dp_inst; 1255 uint32_t vpg_inst; 1256 uint32_t apg_inst; 1257 1258 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1259 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1260 1261 /* Mapping of VPG register blocks to HPO DP block instance: 1262 * VPG[6] -> HPO_DP[0] 1263 * VPG[7] -> HPO_DP[1] 1264 * VPG[8] -> HPO_DP[2] 1265 * VPG[9] -> HPO_DP[3] 1266 */ 1267 vpg_inst = hpo_dp_inst + 6; 1268 1269 /* Mapping of APG register blocks to HPO DP block instance: 1270 * APG[0] -> HPO_DP[0] 1271 * APG[1] -> HPO_DP[1] 1272 * APG[2] -> HPO_DP[2] 1273 * APG[3] -> HPO_DP[3] 1274 */ 1275 apg_inst = hpo_dp_inst; 1276 1277 /* allocate HPO stream encoder and create VPG sub-block */ 1278 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1279 vpg = dcn32_vpg_create(ctx, vpg_inst); 1280 apg = dcn31_apg_create(ctx, apg_inst); 1281 1282 if (!hpo_dp_enc31 || !vpg || !apg) { 1283 kfree(hpo_dp_enc31); 1284 kfree(vpg); 1285 kfree(apg); 1286 return NULL; 1287 } 1288 1289#undef REG_STRUCT 1290#define REG_STRUCT hpo_dp_stream_enc_regs 1291 hpo_dp_stream_encoder_reg_init(0), 1292 hpo_dp_stream_encoder_reg_init(1), 1293 hpo_dp_stream_encoder_reg_init(2), 1294 hpo_dp_stream_encoder_reg_init(3); 1295 1296 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1297 hpo_dp_inst, eng_id, vpg, apg, 1298 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1299 &hpo_dp_se_shift, &hpo_dp_se_mask); 1300 1301 return &hpo_dp_enc31->base; 1302} 1303 1304static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 1305 uint8_t inst, 1306 struct dc_context *ctx) 1307{ 1308 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1309 1310 /* allocate HPO link encoder */ 1311 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1312 if (!hpo_dp_enc31) 1313 return NULL; /* out of memory */ 1314 1315#undef REG_STRUCT 1316#define REG_STRUCT hpo_dp_link_enc_regs 1317 hpo_dp_link_encoder_reg_init(0), 1318 hpo_dp_link_encoder_reg_init(1); 1319 1320 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, 1321 &hpo_dp_link_enc_regs[inst], 1322 &hpo_dp_le_shift, &hpo_dp_le_mask); 1323 1324 return &hpo_dp_enc31->base; 1325} 1326 1327static struct dce_hwseq *dcn32_hwseq_create( 1328 struct dc_context *ctx) 1329{ 1330 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1331 1332#undef REG_STRUCT 1333#define REG_STRUCT hwseq_reg 1334 hwseq_reg_init(); 1335 1336 if (hws) { 1337 hws->ctx = ctx; 1338 hws->regs = &hwseq_reg; 1339 hws->shifts = &hwseq_shift; 1340 hws->masks = &hwseq_mask; 1341 } 1342 return hws; 1343} 1344static const struct resource_create_funcs res_create_funcs = { 1345 .read_dce_straps = read_dce_straps, 1346 .create_audio = dcn32_create_audio, 1347 .create_stream_encoder = dcn32_stream_encoder_create, 1348 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, 1349 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, 1350 .create_hwseq = dcn32_hwseq_create, 1351}; 1352 1353static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) 1354{ 1355 unsigned int i; 1356 1357 for (i = 0; i < pool->base.stream_enc_count; i++) { 1358 if (pool->base.stream_enc[i] != NULL) { 1359 if (pool->base.stream_enc[i]->vpg != NULL) { 1360 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1361 pool->base.stream_enc[i]->vpg = NULL; 1362 } 1363 if (pool->base.stream_enc[i]->afmt != NULL) { 1364 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1365 pool->base.stream_enc[i]->afmt = NULL; 1366 } 1367 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1368 pool->base.stream_enc[i] = NULL; 1369 } 1370 } 1371 1372 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1373 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1374 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1375 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1376 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1377 } 1378 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1379 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1380 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1381 } 1382 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1383 pool->base.hpo_dp_stream_enc[i] = NULL; 1384 } 1385 } 1386 1387 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1388 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1389 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1390 pool->base.hpo_dp_link_enc[i] = NULL; 1391 } 1392 } 1393 1394 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1395 if (pool->base.dscs[i] != NULL) 1396 dcn20_dsc_destroy(&pool->base.dscs[i]); 1397 } 1398 1399 if (pool->base.mpc != NULL) { 1400 kfree(TO_DCN20_MPC(pool->base.mpc)); 1401 pool->base.mpc = NULL; 1402 } 1403 if (pool->base.hubbub != NULL) { 1404 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1405 pool->base.hubbub = NULL; 1406 } 1407 for (i = 0; i < pool->base.pipe_count; i++) { 1408 if (pool->base.dpps[i] != NULL) 1409 dcn32_dpp_destroy(&pool->base.dpps[i]); 1410 1411 if (pool->base.ipps[i] != NULL) 1412 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1413 1414 if (pool->base.hubps[i] != NULL) { 1415 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1416 pool->base.hubps[i] = NULL; 1417 } 1418 1419 if (pool->base.irqs != NULL) { 1420 dal_irq_service_destroy(&pool->base.irqs); 1421 } 1422 } 1423 1424 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1425 if (pool->base.engines[i] != NULL) 1426 dce110_engine_destroy(&pool->base.engines[i]); 1427 if (pool->base.hw_i2cs[i] != NULL) { 1428 kfree(pool->base.hw_i2cs[i]); 1429 pool->base.hw_i2cs[i] = NULL; 1430 } 1431 if (pool->base.sw_i2cs[i] != NULL) { 1432 kfree(pool->base.sw_i2cs[i]); 1433 pool->base.sw_i2cs[i] = NULL; 1434 } 1435 } 1436 1437 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1438 if (pool->base.opps[i] != NULL) 1439 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1440 } 1441 1442 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1443 if (pool->base.timing_generators[i] != NULL) { 1444 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1445 pool->base.timing_generators[i] = NULL; 1446 } 1447 } 1448 1449 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1450 if (pool->base.dwbc[i] != NULL) { 1451 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1452 pool->base.dwbc[i] = NULL; 1453 } 1454 if (pool->base.mcif_wb[i] != NULL) { 1455 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1456 pool->base.mcif_wb[i] = NULL; 1457 } 1458 } 1459 1460 for (i = 0; i < pool->base.audio_count; i++) { 1461 if (pool->base.audios[i]) 1462 dce_aud_destroy(&pool->base.audios[i]); 1463 } 1464 1465 for (i = 0; i < pool->base.clk_src_count; i++) { 1466 if (pool->base.clock_sources[i] != NULL) { 1467 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1468 pool->base.clock_sources[i] = NULL; 1469 } 1470 } 1471 1472 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1473 if (pool->base.mpc_lut[i] != NULL) { 1474 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1475 pool->base.mpc_lut[i] = NULL; 1476 } 1477 if (pool->base.mpc_shaper[i] != NULL) { 1478 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1479 pool->base.mpc_shaper[i] = NULL; 1480 } 1481 } 1482 1483 if (pool->base.dp_clock_source != NULL) { 1484 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1485 pool->base.dp_clock_source = NULL; 1486 } 1487 1488 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1489 if (pool->base.multiple_abms[i] != NULL) 1490 dce_abm_destroy(&pool->base.multiple_abms[i]); 1491 } 1492 1493 if (pool->base.psr != NULL) 1494 dmub_psr_destroy(&pool->base.psr); 1495 1496 if (pool->base.dccg != NULL) 1497 dcn_dccg_destroy(&pool->base.dccg); 1498 1499 if (pool->base.oem_device != NULL) { 1500 struct dc *dc = pool->base.oem_device->ctx->dc; 1501 1502 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); 1503 } 1504} 1505 1506 1507static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1508{ 1509 int i; 1510 uint32_t dwb_count = pool->res_cap->num_dwb; 1511 1512 for (i = 0; i < dwb_count; i++) { 1513 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1514 GFP_KERNEL); 1515 1516 if (!dwbc30) { 1517 dm_error("DC: failed to create dwbc30!\n"); 1518 return false; 1519 } 1520 1521#undef REG_STRUCT 1522#define REG_STRUCT dwbc30_regs 1523 dwbc_regs_dcn3_init(0); 1524 1525 dcn30_dwbc_construct(dwbc30, ctx, 1526 &dwbc30_regs[i], 1527 &dwbc30_shift, 1528 &dwbc30_mask, 1529 i); 1530 1531 pool->dwbc[i] = &dwbc30->base; 1532 } 1533 return true; 1534} 1535 1536static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1537{ 1538 int i; 1539 uint32_t dwb_count = pool->res_cap->num_dwb; 1540 1541 for (i = 0; i < dwb_count; i++) { 1542 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1543 GFP_KERNEL); 1544 1545 if (!mcif_wb30) { 1546 dm_error("DC: failed to create mcif_wb30!\n"); 1547 return false; 1548 } 1549 1550#undef REG_STRUCT 1551#define REG_STRUCT mcif_wb30_regs 1552 mcif_wb_regs_dcn3_init(0); 1553 1554 dcn32_mmhubbub_construct(mcif_wb30, ctx, 1555 &mcif_wb30_regs[i], 1556 &mcif_wb30_shift, 1557 &mcif_wb30_mask, 1558 i); 1559 1560 pool->mcif_wb[i] = &mcif_wb30->base; 1561 } 1562 return true; 1563} 1564 1565static struct display_stream_compressor *dcn32_dsc_create( 1566 struct dc_context *ctx, uint32_t inst) 1567{ 1568 struct dcn20_dsc *dsc = 1569 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1570 1571 if (!dsc) { 1572 BREAK_TO_DEBUGGER(); 1573 return NULL; 1574 } 1575 1576#undef REG_STRUCT 1577#define REG_STRUCT dsc_regs 1578 dsc_regsDCN20_init(0), 1579 dsc_regsDCN20_init(1), 1580 dsc_regsDCN20_init(2), 1581 dsc_regsDCN20_init(3); 1582 1583 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1584 1585 dsc->max_image_width = 6016; 1586 1587 return &dsc->base; 1588} 1589 1590static void dcn32_destroy_resource_pool(struct resource_pool **pool) 1591{ 1592 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool); 1593 1594 dcn32_resource_destruct(dcn32_pool); 1595 kfree(dcn32_pool); 1596 *pool = NULL; 1597} 1598 1599bool dcn32_acquire_post_bldn_3dlut( 1600 struct resource_context *res_ctx, 1601 const struct resource_pool *pool, 1602 int mpcc_id, 1603 struct dc_3dlut **lut, 1604 struct dc_transfer_func **shaper) 1605{ 1606 bool ret = false; 1607 1608 ASSERT(*lut == NULL && *shaper == NULL); 1609 *lut = NULL; 1610 *shaper = NULL; 1611 1612 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { 1613 *lut = pool->mpc_lut[mpcc_id]; 1614 *shaper = pool->mpc_shaper[mpcc_id]; 1615 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; 1616 ret = true; 1617 } 1618 return ret; 1619} 1620 1621bool dcn32_release_post_bldn_3dlut( 1622 struct resource_context *res_ctx, 1623 const struct resource_pool *pool, 1624 struct dc_3dlut **lut, 1625 struct dc_transfer_func **shaper) 1626{ 1627 int i; 1628 bool ret = false; 1629 1630 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1631 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1632 res_ctx->is_mpc_3dlut_acquired[i] = false; 1633 pool->mpc_lut[i]->state.raw = 0; 1634 *lut = NULL; 1635 *shaper = NULL; 1636 ret = true; 1637 break; 1638 } 1639 } 1640 return ret; 1641} 1642 1643static void dcn32_enable_phantom_plane(struct dc *dc, 1644 struct dc_state *context, 1645 struct dc_stream_state *phantom_stream, 1646 unsigned int dc_pipe_idx) 1647{ 1648 struct dc_plane_state *phantom_plane = NULL; 1649 struct dc_plane_state *prev_phantom_plane = NULL; 1650 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1651 1652 while (curr_pipe) { 1653 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) 1654 phantom_plane = prev_phantom_plane; 1655 else 1656 phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state); 1657 1658 if (!phantom_plane) 1659 continue; 1660 1661 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); 1662 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, 1663 sizeof(phantom_plane->scaling_quality)); 1664 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect)); 1665 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect)); 1666 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect)); 1667 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size, 1668 sizeof(phantom_plane->plane_size)); 1669 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, 1670 sizeof(phantom_plane->tiling_info)); 1671 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc)); 1672 phantom_plane->format = curr_pipe->plane_state->format; 1673 phantom_plane->rotation = curr_pipe->plane_state->rotation; 1674 phantom_plane->visible = curr_pipe->plane_state->visible; 1675 1676 /* Shadow pipe has small viewport. */ 1677 phantom_plane->clip_rect.y = 0; 1678 phantom_plane->clip_rect.height = phantom_stream->src.height; 1679 1680 dc_state_add_phantom_plane(dc, phantom_stream, phantom_plane, context); 1681 1682 curr_pipe = curr_pipe->bottom_pipe; 1683 prev_phantom_plane = phantom_plane; 1684 } 1685} 1686 1687static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, 1688 struct dc_state *context, 1689 display_e2e_pipe_params_st *pipes, 1690 unsigned int pipe_cnt, 1691 unsigned int dc_pipe_idx) 1692{ 1693 struct dc_stream_state *phantom_stream = NULL; 1694 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; 1695 1696 phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe->stream); 1697 if (!phantom_stream) 1698 return phantom_stream; 1699 1700 /* stream has limited viewport and small timing */ 1701 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing)); 1702 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src)); 1703 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst)); 1704 DC_FP_START(); 1705 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1706 DC_FP_END(); 1707 1708 dc_state_add_phantom_stream(dc, context, phantom_stream, ref_pipe->stream); 1709 return phantom_stream; 1710} 1711 1712/* TODO: Input to this function should indicate which pipe indexes (or streams) 1713 * require a phantom pipe / stream 1714 */ 1715void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, 1716 display_e2e_pipe_params_st *pipes, 1717 unsigned int pipe_cnt, 1718 unsigned int index) 1719{ 1720 struct dc_stream_state *phantom_stream = NULL; 1721 unsigned int i; 1722 1723 // The index of the DC pipe passed into this function is guarenteed to 1724 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't 1725 // already have phantom pipe assigned, etc.) by previous checks. 1726 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1727 if (!phantom_stream) 1728 return; 1729 1730 dcn32_enable_phantom_plane(dc, context, phantom_stream, index); 1731 1732 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1733 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1734 1735 // Build scaling params for phantom pipes which were newly added. 1736 // We determine which phantom pipes were added by comparing with 1737 // the phantom stream. 1738 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && 1739 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { 1740 pipe->stream->use_dynamic_meta = false; 1741 pipe->plane_state->flip_immediate = false; 1742 if (!resource_build_scaling_params(pipe)) { 1743 // Log / remove phantom pipes since failed to build scaling params 1744 } 1745 } 1746 } 1747} 1748 1749static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode) 1750{ 1751 bool out = false; 1752 1753 BW_VAL_TRACE_SETUP(); 1754 1755 int vlevel = 0; 1756 int pipe_cnt = 0; 1757 display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count, 1758 sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1759 1760 /* To handle Freesync properly, setting FreeSync DML parameters 1761 * to its default state for the first stage of validation 1762 */ 1763 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 1764 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 1765 1766 DC_LOGGER_INIT(dc->ctx->logger); 1767 1768 BW_VAL_TRACE_COUNT(); 1769 1770 if (!pipes) 1771 goto validate_fail; 1772 1773 DC_FP_START(); 1774 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode); 1775 DC_FP_END(); 1776 1777 if (pipe_cnt == 0) 1778 goto validate_out; 1779 1780 if (!out) 1781 goto validate_fail; 1782 1783 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1784 1785 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) { 1786 BW_VAL_TRACE_SKIP(fast); 1787 goto validate_out; 1788 } 1789 1790 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1791 1792 DC_FP_START(); 1793 dcn32_override_min_req_memclk(dc, context); 1794 DC_FP_END(); 1795 1796 dcn32_override_min_req_dcfclk(dc, context); 1797 1798 BW_VAL_TRACE_END_WATERMARKS(); 1799 1800 goto validate_out; 1801 1802validate_fail: 1803 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1804 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1805 1806 BW_VAL_TRACE_SKIP(fail); 1807 out = false; 1808 1809validate_out: 1810 kfree(pipes); 1811 1812 BW_VAL_TRACE_FINISH(); 1813 1814 return out; 1815} 1816 1817enum dc_status dcn32_validate_bandwidth(struct dc *dc, 1818 struct dc_state *context, 1819 enum dc_validate_mode validate_mode) 1820{ 1821 unsigned int i; 1822 enum dc_status status; 1823 const struct dc_stream_state *stream; 1824 1825 /* reset cursor limitations on subvp */ 1826 for (i = 0; i < context->stream_count; i++) { 1827 stream = context->streams[i]; 1828 1829 if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) { 1830 dc_state_set_stream_cursor_subvp_limit(stream, context, false); 1831 } 1832 } 1833 1834 if (dc->debug.using_dml2) 1835 status = dml2_validate(dc, context, 1836 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, 1837 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1838 else 1839 status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1840 1841 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) { 1842 /* check new stream configuration still supports cursor if subvp used */ 1843 for (i = 0; i < context->stream_count; i++) { 1844 stream = context->streams[i]; 1845 1846 if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM && 1847 stream->cursor_position.enable && 1848 !dc_stream_check_cursor_attributes(stream, context, &stream->cursor_attributes)) { 1849 /* hw cursor cannot be supported with subvp active, so disable subvp for now */ 1850 dc_state_set_stream_cursor_subvp_limit(stream, context, true); 1851 status = DC_FAIL_HW_CURSOR_SUPPORT; 1852 } 1853 } 1854 } 1855 1856 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) { 1857 /* attempt to validate again with subvp disabled due to cursor */ 1858 if (dc->debug.using_dml2) 1859 status = dml2_validate(dc, context, 1860 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, 1861 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1862 else 1863 status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1864 } 1865 1866 return status; 1867} 1868 1869int dcn32_populate_dml_pipes_from_context( 1870 struct dc *dc, struct dc_state *context, 1871 display_e2e_pipe_params_st *pipes, 1872 enum dc_validate_mode validate_mode) 1873{ 1874 int i, pipe_cnt; 1875 struct resource_context *res_ctx = &context->res_ctx; 1876 struct pipe_ctx *pipe = NULL; 1877 bool subvp_in_use = false; 1878 struct dc_crtc_timing *timing; 1879 int subvp_main_pipe_index = -1; 1880 enum mall_stream_type mall_type; 1881 bool single_display_subvp = false; 1882 struct dc_stream_state *stream = NULL; 1883 int num_subvp_main = 0; 1884 int num_subvp_phantom = 0; 1885 int num_subvp_none = 0; 1886 int odm_slice_count; 1887 1888 dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); 1889 1890 /* For single display subvp, look for subvp main so if we have phantom 1891 * pipe, we can set odm policy to match main pipe 1892 */ 1893 for (i = 0; i < context->stream_count; i++) { 1894 stream = context->streams[i]; 1895 mall_type = dc_state_get_stream_subvp_type(context, stream); 1896 if (mall_type == SUBVP_MAIN) 1897 num_subvp_main++; 1898 else if (mall_type == SUBVP_PHANTOM) 1899 num_subvp_phantom++; 1900 else 1901 num_subvp_none++; 1902 } 1903 if (num_subvp_main == 1 && num_subvp_phantom == 1 && num_subvp_none == 0) 1904 single_display_subvp = true; 1905 1906 if (single_display_subvp) { 1907 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1908 pipe = &res_ctx->pipe_ctx[i]; 1909 if (!res_ctx->pipe_ctx[i].stream) 1910 continue; 1911 1912 mall_type = dc_state_get_pipe_subvp_type(context, pipe); 1913 if (mall_type == SUBVP_MAIN) { 1914 if (resource_is_pipe_type(pipe, OTG_MASTER)) 1915 subvp_main_pipe_index = i; 1916 } 1917 pipe_cnt++; 1918 } 1919 } 1920 1921 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1922 1923 if (!res_ctx->pipe_ctx[i].stream) 1924 continue; 1925 pipe = &res_ctx->pipe_ctx[i]; 1926 timing = &pipe->stream->timing; 1927 1928 pipes[pipe_cnt].pipe.src.gpuvm = true; 1929 DC_FP_START(); 1930 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1931 DC_FP_END(); 1932 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1933 if (dc->config.enable_windowed_mpo_odm && 1934 dc->debug.enable_single_display_2to1_odm_policy) { 1935 /* For single display subvp, if pipe is phantom pipe, 1936 * then copy odm policy from subvp main pipe 1937 */ 1938 mall_type = dc_state_get_pipe_subvp_type(context, pipe); 1939 if (single_display_subvp && (mall_type == SUBVP_PHANTOM)) { 1940 if (subvp_main_pipe_index < 0) { 1941 odm_slice_count = -1; 1942 ASSERT(0); 1943 } else { 1944 odm_slice_count = resource_get_odm_slice_count(&res_ctx->pipe_ctx[subvp_main_pipe_index]); 1945 } 1946 } else { 1947 odm_slice_count = resource_get_odm_slice_count(pipe); 1948 } 1949 switch (odm_slice_count) { 1950 case 2: 1951 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; 1952 break; 1953 case 4: 1954 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1; 1955 break; 1956 default: 1957 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1958 } 1959 } else { 1960 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; 1961 } 1962 1963 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet 1964 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1965 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; 1966 1967 /* Only populate DML input with subvp info for full updates. 1968 * This is just a workaround -- needs a proper fix. 1969 */ 1970 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { 1971 switch (dc_state_get_pipe_subvp_type(context, pipe)) { 1972 case SUBVP_MAIN: 1973 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; 1974 subvp_in_use = true; 1975 break; 1976 case SUBVP_PHANTOM: 1977 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; 1978 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1979 // Disallow unbounded req for SubVP according to DCHUB programming guide 1980 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1981 break; 1982 case SUBVP_NONE: 1983 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; 1984 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; 1985 break; 1986 default: 1987 break; 1988 } 1989 } 1990 1991 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1992 if (pipes[pipe_cnt].dout.dsc_enable) { 1993 switch (timing->display_color_depth) { 1994 case COLOR_DEPTH_888: 1995 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1996 break; 1997 case COLOR_DEPTH_101010: 1998 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1999 break; 2000 case COLOR_DEPTH_121212: 2001 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 2002 break; 2003 default: 2004 ASSERT(0); 2005 break; 2006 } 2007 } 2008 2009 2010 pipe_cnt++; 2011 } 2012 2013 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all 2014 * the DET available for each pipe). Use the DET override input to maintain our driver 2015 * policy. 2016 */ 2017 dcn32_set_det_allocations(dc, context, pipes); 2018 2019 // In general cases we want to keep the dram clock change requirement 2020 // (prefer configs that support MCLK switch). Only override to false 2021 // for SubVP 2022 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use) 2023 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 2024 else 2025 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; 2026 2027 return pipe_cnt; 2028} 2029 2030unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes) 2031{ 2032 uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways; 2033 2034 if (total_size_in_mall_bytes == 0) { 2035 return 0; 2036 } 2037 2038 if (dc->caps.max_cab_allocation_bytes == 0) { 2039 return 0xffffffff; 2040 } 2041 2042 /* add 2 lines for worst case alignment */ 2043 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2; 2044 2045 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; 2046 lines_per_way = total_cache_lines / dc->caps.cache_num_ways; 2047 num_ways = cache_lines_used / lines_per_way; 2048 if (cache_lines_used % lines_per_way > 0) 2049 num_ways++; 2050 2051 return num_ways; 2052} 2053 2054static struct dc_cap_funcs cap_funcs = { 2055 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap, 2056 .get_subvp_en = dcn32_subvp_in_use, 2057}; 2058 2059void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 2060 display_e2e_pipe_params_st *pipes, 2061 int pipe_cnt, 2062 int vlevel) 2063{ 2064 DC_FP_START(); 2065 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); 2066 DC_FP_END(); 2067} 2068 2069static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2070{ 2071 DC_FP_START(); 2072 2073 dcn32_update_bw_bounding_box_fpu(dc, bw_params); 2074 2075 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2) 2076 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); 2077 2078 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source) 2079 dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source); 2080 2081 DC_FP_END(); 2082} 2083 2084unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc, 2085 struct dc_state *state, 2086 const struct dc_stream_state *stream) 2087{ 2088 bool limit_cur_to_buf; 2089 2090 limit_cur_to_buf = dc_state_get_stream_subvp_cursor_limit(stream, state) && 2091 !stream->hw_cursor_req; 2092 2093 return limit_cur_to_buf ? dc->caps.max_buffered_cursor_size : dc->caps.max_cursor_size; 2094} 2095 2096static struct resource_funcs dcn32_res_pool_funcs = { 2097 .destroy = dcn32_destroy_resource_pool, 2098 .link_enc_create = dcn32_link_encoder_create, 2099 .link_enc_create_minimal = NULL, 2100 .panel_cntl_create = dcn32_panel_cntl_create, 2101 .validate_bandwidth = dcn32_validate_bandwidth, 2102 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, 2103 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, 2104 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe, 2105 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, 2106 .release_pipe = dcn20_release_pipe, 2107 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2108 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2109 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2110 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2111 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2112 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2113 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 2114 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 2115 .update_bw_bounding_box = dcn32_update_bw_bounding_box, 2116 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2117 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 2118 .add_phantom_pipes = dcn32_add_phantom_pipes, 2119 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, 2120 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, 2121 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, 2122 .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size, 2123}; 2124 2125static uint32_t read_pipe_fuses(struct dc_context *ctx) 2126{ 2127 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 2128 /* DCN32 support max 4 pipes */ 2129 value = value & 0xf; 2130 return value; 2131} 2132 2133 2134static bool dcn32_resource_construct( 2135 uint8_t num_virtual_links, 2136 struct dc *dc, 2137 struct dcn32_resource_pool *pool) 2138{ 2139 int i, j; 2140 struct dc_context *ctx = dc->ctx; 2141 struct irq_service_init_data init_data; 2142 struct ddc_service_init_data ddc_init_data = {0}; 2143 uint32_t pipe_fuses = 0; 2144 uint32_t num_pipes = 4; 2145 2146#undef REG_STRUCT 2147#define REG_STRUCT bios_regs 2148 bios_regs_init(); 2149 2150#undef REG_STRUCT 2151#define REG_STRUCT clk_src_regs 2152 clk_src_regs_init(0, A), 2153 clk_src_regs_init(1, B), 2154 clk_src_regs_init(2, C), 2155 clk_src_regs_init(3, D), 2156 clk_src_regs_init(4, E); 2157 2158#undef REG_STRUCT 2159#define REG_STRUCT abm_regs 2160 abm_regs_init(0), 2161 abm_regs_init(1), 2162 abm_regs_init(2), 2163 abm_regs_init(3); 2164 2165#undef REG_STRUCT 2166#define REG_STRUCT dccg_regs 2167 dccg_regs_init(); 2168 2169 ctx->dc_bios->regs = &bios_regs; 2170 2171 pool->base.res_cap = &res_cap_dcn32; 2172 /* max number of pipes for ASIC before checking for pipe fuses */ 2173 num_pipes = pool->base.res_cap->num_timing_generator; 2174 pipe_fuses = read_pipe_fuses(ctx); 2175 2176 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2177 if (pipe_fuses & 1 << i) 2178 num_pipes--; 2179 2180 if (pipe_fuses & 1) 2181 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2182 2183 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2184 ASSERT(0); //Entire DCN is harvested! 2185 2186 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the 2187 * value will be changed, update max_num_dpp and max_num_otg for dml. 2188 */ 2189 dcn3_2_ip.max_num_dpp = num_pipes; 2190 dcn3_2_ip.max_num_otg = num_pipes; 2191 2192 pool->base.funcs = &dcn32_res_pool_funcs; 2193 2194 /************************************************* 2195 * Resource + asic cap harcoding * 2196 *************************************************/ 2197 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2198 pool->base.timing_generator_count = num_pipes; 2199 pool->base.pipe_count = num_pipes; 2200 pool->base.mpcc_count = num_pipes; 2201 dc->caps.max_downscale_ratio = 600; 2202 dc->caps.i2c_speed_in_khz = 100; 2203 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2204 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2205 dc->caps.max_cursor_size = 64; 2206 /* floor(sqrt(buf_size_bytes / bpp ) * bpp, fixed_req_size) / bpp = max_width */ 2207 dc->caps.max_buffered_cursor_size = 64; // floor(sqrt(16 * 1024 / 4) * 4, 256) / 4 = 64 2208 dc->caps.min_horizontal_blanking_period = 80; 2209 dc->caps.dmdata_alloc_size = 2048; 2210 dc->caps.mall_size_per_mem_channel = 4; 2211 /* total size = mall per channel * num channels * 1024 * 1024 */ 2212 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 2213 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2214 2215 dc->caps.cache_line_size = 64; 2216 dc->caps.cache_num_ways = 16; 2217 2218 /* Calculate the available MALL space */ 2219 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( 2220 dc, dc->ctx->dc_bios->vram_info.num_chans) * 2221 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 2222 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 2223 2224 dc->caps.subvp_fw_processing_delay_us = 15; 2225 dc->caps.subvp_drr_max_vblank_margin_us = 40; 2226 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 2227 dc->caps.subvp_swath_height_margin_lines = 16; 2228 dc->caps.subvp_pstate_allow_width_us = 20; 2229 dc->caps.subvp_vertical_int_margin_us = 30; 2230 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 2231 2232 dc->caps.max_slave_planes = 2; 2233 dc->caps.max_slave_yuv_planes = 2; 2234 dc->caps.max_slave_rgb_planes = 2; 2235 dc->caps.post_blend_color_processing = true; 2236 dc->caps.force_dp_tps4_for_cp2520 = true; 2237 if (dc->config.forceHBR2CP2520) 2238 dc->caps.force_dp_tps4_for_cp2520 = false; 2239 dc->caps.dp_hpo = true; 2240 dc->caps.dp_hdmi21_pcon_support = true; 2241 dc->caps.edp_dsc_support = true; 2242 dc->caps.extended_aux_timeout_support = true; 2243 dc->caps.dmcub_support = true; 2244 dc->caps.seamless_odm = true; 2245 dc->caps.max_v_total = (1 << 15) - 1; 2246 dc->caps.vtotal_limited_by_fp2 = true; 2247 2248 /* Color pipeline capabilities */ 2249 dc->caps.color.dpp.dcn_arch = 1; 2250 dc->caps.color.dpp.input_lut_shared = 0; 2251 dc->caps.color.dpp.icsc = 1; 2252 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2253 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2254 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2255 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2256 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2257 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2258 dc->caps.color.dpp.post_csc = 1; 2259 dc->caps.color.dpp.gamma_corr = 1; 2260 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2261 2262 dc->caps.color.dpp.hw_3d_lut = 0; 2263 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2264 // no OGAM ROM on DCN2 and later ASICs 2265 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2266 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2267 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2268 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2269 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2270 dc->caps.color.dpp.ocsc = 0; 2271 2272 dc->caps.color.mpc.gamut_remap = 1; 2273 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2274 dc->caps.color.mpc.ogam_ram = 1; 2275 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2276 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2277 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2278 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2279 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2280 dc->caps.color.mpc.ocsc = 1; 2281 dc->caps.color.mpc.preblend = true; 2282 2283 /* Use pipe context based otg sync logic */ 2284 dc->config.use_pipe_ctx_sync_logic = true; 2285 2286 dc->config.dc_mode_clk_limit_support = true; 2287 dc->config.enable_windowed_mpo_odm = true; 2288 dc->config.disable_hbr_audio_dp2 = true; 2289 /* read VBIOS LTTPR caps */ 2290 { 2291 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2292 enum bp_result bp_query_result; 2293 uint8_t is_vbios_lttpr_enable = 0; 2294 2295 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2296 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2297 } 2298 2299 /* interop bit is implicit */ 2300 { 2301 dc->caps.vbios_lttpr_aware = true; 2302 } 2303 } 2304 dc->check_config = config_defaults; 2305 2306 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2307 dc->debug = debug_defaults_drv; 2308 2309 // Init the vm_helper 2310 if (dc->vm_helper) 2311 vm_helper_init(dc->vm_helper, 16); 2312 2313 /************************************************* 2314 * Create resources * 2315 *************************************************/ 2316 2317 /* Clock Sources for Pixel Clock*/ 2318 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = 2319 dcn32_clock_source_create(ctx, ctx->dc_bios, 2320 CLOCK_SOURCE_COMBO_PHY_PLL0, 2321 &clk_src_regs[0], false); 2322 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = 2323 dcn32_clock_source_create(ctx, ctx->dc_bios, 2324 CLOCK_SOURCE_COMBO_PHY_PLL1, 2325 &clk_src_regs[1], false); 2326 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = 2327 dcn32_clock_source_create(ctx, ctx->dc_bios, 2328 CLOCK_SOURCE_COMBO_PHY_PLL2, 2329 &clk_src_regs[2], false); 2330 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = 2331 dcn32_clock_source_create(ctx, ctx->dc_bios, 2332 CLOCK_SOURCE_COMBO_PHY_PLL3, 2333 &clk_src_regs[3], false); 2334 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = 2335 dcn32_clock_source_create(ctx, ctx->dc_bios, 2336 CLOCK_SOURCE_COMBO_PHY_PLL4, 2337 &clk_src_regs[4], false); 2338 2339 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; 2340 2341 /* todo: not reuse phy_pll registers */ 2342 pool->base.dp_clock_source = 2343 dcn32_clock_source_create(ctx, ctx->dc_bios, 2344 CLOCK_SOURCE_ID_DP_DTO, 2345 &clk_src_regs[0], true); 2346 2347 for (i = 0; i < pool->base.clk_src_count; i++) { 2348 if (pool->base.clock_sources[i] == NULL) { 2349 dm_error("DC: failed to create clock sources!\n"); 2350 BREAK_TO_DEBUGGER(); 2351 goto create_fail; 2352 } 2353 } 2354 2355 /* DCCG */ 2356 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2357 if (pool->base.dccg == NULL) { 2358 dm_error("DC: failed to create dccg!\n"); 2359 BREAK_TO_DEBUGGER(); 2360 goto create_fail; 2361 } 2362 2363 /* DML */ 2364 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); 2365 2366 /* IRQ Service */ 2367 init_data.ctx = dc->ctx; 2368 pool->base.irqs = dal_irq_service_dcn32_create(&init_data); 2369 if (!pool->base.irqs) 2370 goto create_fail; 2371 2372 /* HUBBUB */ 2373 pool->base.hubbub = dcn32_hubbub_create(ctx); 2374 if (pool->base.hubbub == NULL) { 2375 BREAK_TO_DEBUGGER(); 2376 dm_error("DC: failed to create hubbub!\n"); 2377 goto create_fail; 2378 } 2379 2380 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2381 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2382 2383 /* if pipe is disabled, skip instance of HW pipe, 2384 * i.e, skip ASIC register instance 2385 */ 2386 if (pipe_fuses & 1 << i) 2387 continue; 2388 2389 /* HUBPs */ 2390 pool->base.hubps[j] = dcn32_hubp_create(ctx, i); 2391 if (pool->base.hubps[j] == NULL) { 2392 BREAK_TO_DEBUGGER(); 2393 dm_error( 2394 "DC: failed to create hubps!\n"); 2395 goto create_fail; 2396 } 2397 2398 /* DPPs */ 2399 pool->base.dpps[j] = dcn32_dpp_create(ctx, i); 2400 if (pool->base.dpps[j] == NULL) { 2401 BREAK_TO_DEBUGGER(); 2402 dm_error( 2403 "DC: failed to create dpps!\n"); 2404 goto create_fail; 2405 } 2406 2407 /* OPPs */ 2408 pool->base.opps[j] = dcn32_opp_create(ctx, i); 2409 if (pool->base.opps[j] == NULL) { 2410 BREAK_TO_DEBUGGER(); 2411 dm_error( 2412 "DC: failed to create output pixel processor!\n"); 2413 goto create_fail; 2414 } 2415 2416 /* TGs */ 2417 pool->base.timing_generators[j] = dcn32_timing_generator_create( 2418 ctx, i); 2419 if (pool->base.timing_generators[j] == NULL) { 2420 BREAK_TO_DEBUGGER(); 2421 dm_error("DC: failed to create tg!\n"); 2422 goto create_fail; 2423 } 2424 2425 /* ABMs */ 2426 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2427 &abm_regs[i], 2428 &abm_shift, 2429 &abm_mask); 2430 if (pool->base.multiple_abms[j] == NULL) { 2431 dm_error("DC: failed to create abm for pipe %d!\n", i); 2432 BREAK_TO_DEBUGGER(); 2433 goto create_fail; 2434 } 2435 2436 /* index for resource pool arrays for next valid pipe */ 2437 j++; 2438 } 2439 2440 /* PSR */ 2441 pool->base.psr = dmub_psr_create(ctx); 2442 if (pool->base.psr == NULL) { 2443 dm_error("DC: failed to create psr obj!\n"); 2444 BREAK_TO_DEBUGGER(); 2445 goto create_fail; 2446 } 2447 2448 /* MPCCs */ 2449 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); 2450 if (pool->base.mpc == NULL) { 2451 BREAK_TO_DEBUGGER(); 2452 dm_error("DC: failed to create mpc!\n"); 2453 goto create_fail; 2454 } 2455 2456 /* DSCs */ 2457 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2458 pool->base.dscs[i] = dcn32_dsc_create(ctx, i); 2459 if (pool->base.dscs[i] == NULL) { 2460 BREAK_TO_DEBUGGER(); 2461 dm_error("DC: failed to create display stream compressor %d!\n", i); 2462 goto create_fail; 2463 } 2464 } 2465 2466 /* DWB */ 2467 if (!dcn32_dwbc_create(ctx, &pool->base)) { 2468 BREAK_TO_DEBUGGER(); 2469 dm_error("DC: failed to create dwbc!\n"); 2470 goto create_fail; 2471 } 2472 2473 /* MMHUBBUB */ 2474 if (!dcn32_mmhubbub_create(ctx, &pool->base)) { 2475 BREAK_TO_DEBUGGER(); 2476 dm_error("DC: failed to create mcif_wb!\n"); 2477 goto create_fail; 2478 } 2479 2480 /* AUX and I2C */ 2481 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2482 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); 2483 if (pool->base.engines[i] == NULL) { 2484 BREAK_TO_DEBUGGER(); 2485 dm_error( 2486 "DC:failed to create aux engine!!\n"); 2487 goto create_fail; 2488 } 2489 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); 2490 if (pool->base.hw_i2cs[i] == NULL) { 2491 BREAK_TO_DEBUGGER(); 2492 dm_error( 2493 "DC:failed to create hw i2c!!\n"); 2494 goto create_fail; 2495 } 2496 pool->base.sw_i2cs[i] = NULL; 2497 } 2498 2499 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2500 if (!resource_construct(num_virtual_links, dc, &pool->base, 2501 &res_create_funcs)) 2502 goto create_fail; 2503 2504 /* HW Sequencer init functions and Plane caps */ 2505 dcn32_hw_sequencer_init_functions(dc); 2506 2507 dc->caps.max_planes = pool->base.pipe_count; 2508 2509 for (i = 0; i < dc->caps.max_planes; ++i) 2510 dc->caps.planes[i] = plane_cap; 2511 2512 dc->caps.max_odm_combine_factor = 4; 2513 2514 dc->cap_funcs = cap_funcs; 2515 2516 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2517 ddc_init_data.ctx = dc->ctx; 2518 ddc_init_data.link = NULL; 2519 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2520 ddc_init_data.id.enum_id = 0; 2521 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2522 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 2523 } else { 2524 pool->base.oem_device = NULL; 2525 } 2526 2527 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; 2528 dc->dml2_options.use_native_soc_bb_construction = true; 2529 dc->dml2_options.minimize_dispclk_using_odm = true; 2530 2531 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); 2532 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; 2533 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; 2534 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes; 2535 2536 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; 2537 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us; 2538 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 2539 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines; 2540 2541 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp; 2542 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch; 2543 2544 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; 2545 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; 2546 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes; 2547 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE; 2548 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE; 2549 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES; 2550 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; 2551 2552 dc->dml2_options.max_segments_per_hubp = 18; 2553 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE; 2554 dc->dml2_options.map_dc_pipes_with_callbacks = true; 2555 2556 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0)) 2557 dc->config.sdpif_request_limit_words_per_umc = 16; 2558 2559 /* init DC limited DML2 options */ 2560 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options)); 2561 dc->dml2_dc_power_options.use_clock_dc_limits = true; 2562 2563 return true; 2564 2565create_fail: 2566 2567 dcn32_resource_destruct(pool); 2568 2569 return false; 2570} 2571 2572struct resource_pool *dcn32_create_resource_pool( 2573 const struct dc_init_data *init_data, 2574 struct dc *dc) 2575{ 2576 struct dcn32_resource_pool *pool = 2577 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL); 2578 2579 if (!pool) 2580 return NULL; 2581 2582 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) 2583 return &pool->base; 2584 2585 BREAK_TO_DEBUGGER(); 2586 kfree(pool); 2587 return NULL; 2588} 2589 2590/* 2591 * Find the most optimal free pipe from res_ctx, which could be used as a 2592 * secondary dpp pipe for input opp head pipe. 2593 * 2594 * a free pipe - a pipe in input res_ctx not yet used for any streams or 2595 * planes. 2596 * secondary dpp pipe - a pipe gets inserted to a head OPP pipe's MPC blending 2597 * tree. This is typical used for rendering MPO planes or additional offset 2598 * areas in MPCC combine. 2599 * 2600 * Hardware Transition Minimization Algorithm for Finding a Secondary DPP Pipe 2601 * ------------------------------------------------------------------------- 2602 * 2603 * PROBLEM: 2604 * 2605 * 1. There is a hardware limitation that a secondary DPP pipe cannot be 2606 * transferred from one MPC blending tree to the other in a single frame. 2607 * Otherwise it could cause glitches on the screen. 2608 * 2609 * For instance, we cannot transition from state 1 to state 2 in one frame. This 2610 * is because PIPE1 is transferred from PIPE0's MPC blending tree over to 2611 * PIPE2's MPC blending tree, which is not supported by hardware. 2612 * To support this transition we need to first remove PIPE1 from PIPE0's MPC 2613 * blending tree in one frame and then insert PIPE1 to PIPE2's MPC blending tree 2614 * in the next frame. This is not optimal as it will delay the flip for two 2615 * frames. 2616 * 2617 * State 1: 2618 * PIPE0 -- secondary DPP pipe --> (PIPE1) 2619 * PIPE2 -- secondary DPP pipe --> NONE 2620 * 2621 * State 2: 2622 * PIPE0 -- secondary DPP pipe --> NONE 2623 * PIPE2 -- secondary DPP pipe --> (PIPE1) 2624 * 2625 * 2. We want to in general minimize the unnecessary changes in pipe topology. 2626 * If a pipe is already added in current blending tree and there are no changes 2627 * to plane topology, we don't want to swap it with another free pipe 2628 * unnecessarily in every update. Powering up and down a pipe would require a 2629 * full update which delays the flip for 1 frame. If we use the original pipe 2630 * we don't have to toggle its power. So we can flip faster. 2631 */ 2632int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe( 2633 const struct resource_context *cur_res_ctx, 2634 struct resource_context *new_res_ctx, 2635 const struct resource_pool *pool, 2636 const struct pipe_ctx *new_opp_head) 2637{ 2638 const struct pipe_ctx *cur_opp_head; 2639 int free_pipe_idx; 2640 2641 cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx]; 2642 free_pipe_idx = resource_find_free_pipe_used_in_cur_mpc_blending_tree( 2643 cur_res_ctx, new_res_ctx, cur_opp_head); 2644 2645 /* Up until here if we have not found a free secondary pipe, we will 2646 * need to wait for at least one frame to complete the transition 2647 * sequence. 2648 */ 2649 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND) 2650 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx( 2651 cur_res_ctx, new_res_ctx, pool); 2652 2653 /* Up until here if we have not found a free secondary pipe, we will 2654 * need to wait for at least two frames to complete the transition 2655 * sequence. It really doesn't matter which pipe we decide take from 2656 * current enabled pipes. It won't save our frame time when we swap only 2657 * one pipe or more pipes. 2658 */ 2659 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND) 2660 free_pipe_idx = resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine( 2661 cur_res_ctx, new_res_ctx, pool); 2662 2663 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND) 2664 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool); 2665 2666 return free_pipe_idx; 2667} 2668 2669static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( 2670 struct resource_context *res_ctx, 2671 const struct resource_pool *pool, 2672 const struct pipe_ctx *primary_pipe) 2673{ 2674 int i; 2675 struct pipe_ctx *secondary_pipe = NULL; 2676 struct pipe_ctx *next_odm_mpo_pipe = NULL; 2677 int primary_index, preferred_pipe_idx; 2678 struct pipe_ctx *old_primary_pipe = NULL; 2679 2680 /* 2681 * Modified from find_idle_secondary_pipe 2682 * With windowed MPO and ODM, we want to avoid the case where we want a 2683 * free pipe for the left side but the free pipe is being used on the 2684 * right side. 2685 * Add check on current_state if the primary_pipe is the left side, 2686 * to check the right side ( primary_pipe->next_odm_pipe ) to see if 2687 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) 2688 * - If so, then don't use this pipe 2689 * EXCEPTION - 3 plane ( 2 MPO plane ) case 2690 * - in this case, the primary pipe has already gotten a free pipe for the 2691 * MPO window in the left 2692 * - when it tries to get a free pipe for the MPO window on the right, 2693 * it will see that it is already assigned to the right side 2694 * ( primary_pipe->next_odm_pipe ). But in this case, we want this 2695 * free pipe, since it will be for the right side. So add an 2696 * additional condition, that skipping the free pipe on the right only 2697 * applies if the primary pipe has no bottom pipe currently assigned 2698 */ 2699 if (primary_pipe) { 2700 primary_index = primary_pipe->pipe_idx; 2701 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; 2702 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) 2703 && (!primary_pipe->bottom_pipe)) 2704 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; 2705 2706 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 2707 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && 2708 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { 2709 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 2710 secondary_pipe->pipe_idx = preferred_pipe_idx; 2711 } 2712 } 2713 2714 /* 2715 * search backwards for the second pipe to keep pipe 2716 * assignment more consistent 2717 */ 2718 if (!secondary_pipe) 2719 for (i = pool->pipe_count - 1; i >= 0; i--) { 2720 if ((res_ctx->pipe_ctx[i].stream == NULL) && 2721 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { 2722 secondary_pipe = &res_ctx->pipe_ctx[i]; 2723 secondary_pipe->pipe_idx = i; 2724 break; 2725 } 2726 } 2727 2728 return secondary_pipe; 2729} 2730 2731static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2732 struct dc_state *state, 2733 const struct resource_pool *pool, 2734 struct dc_stream_state *stream, 2735 const struct pipe_ctx *head_pipe) 2736{ 2737 struct resource_context *res_ctx = &state->res_ctx; 2738 struct pipe_ctx *idle_pipe, *pipe; 2739 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; 2740 int head_index; 2741 2742 if (!head_pipe) { 2743 ASSERT(0); 2744 return NULL; 2745 } 2746 2747 /* 2748 * Modified from dcn20_acquire_idle_pipe_for_layer 2749 * Check if head_pipe in old_context already has bottom_pipe allocated. 2750 * - If so, check if that pipe is available in the current context. 2751 * -- If so, reuse pipe from old_context 2752 */ 2753 head_index = head_pipe->pipe_idx; 2754 pipe = &old_ctx->pipe_ctx[head_index]; 2755 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { 2756 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; 2757 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; 2758 } else { 2759 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); 2760 if (!idle_pipe) 2761 return NULL; 2762 } 2763 2764 idle_pipe->stream = head_pipe->stream; 2765 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 2766 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 2767 2768 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 2769 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 2770 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 2771 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 2772 2773 return idle_pipe; 2774} 2775 2776static int find_optimal_free_pipe_as_secondary_opp_head( 2777 const struct resource_context *cur_res_ctx, 2778 struct resource_context *new_res_ctx, 2779 const struct resource_pool *pool, 2780 const struct pipe_ctx *new_otg_master) 2781{ 2782 const struct pipe_ctx *cur_otg_master; 2783 int free_pipe_idx; 2784 2785 cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx]; 2786 free_pipe_idx = resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master( 2787 cur_res_ctx, new_res_ctx, cur_otg_master); 2788 2789 /* Up until here if we have not found a free secondary pipe, we will 2790 * need to wait for at least one frame to complete the transition 2791 * sequence. 2792 */ 2793 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND) 2794 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx( 2795 cur_res_ctx, new_res_ctx, pool); 2796 2797 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND) 2798 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool); 2799 2800 return free_pipe_idx; 2801} 2802 2803struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe( 2804 const struct dc_state *cur_ctx, 2805 struct dc_state *new_ctx, 2806 const struct resource_pool *pool, 2807 const struct pipe_ctx *opp_head_pipe) 2808{ 2809 2810 int free_pipe_idx; 2811 struct pipe_ctx *free_pipe; 2812 2813 if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm) 2814 return dcn32_acquire_idle_pipe_for_head_pipe_in_layer( 2815 new_ctx, pool, opp_head_pipe->stream, opp_head_pipe); 2816 2817 free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe( 2818 &cur_ctx->res_ctx, &new_ctx->res_ctx, 2819 pool, opp_head_pipe); 2820 if (free_pipe_idx >= 0) { 2821 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx]; 2822 free_pipe->pipe_idx = free_pipe_idx; 2823 free_pipe->stream = opp_head_pipe->stream; 2824 free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg; 2825 free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp; 2826 2827 free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx]; 2828 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx]; 2829 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx]; 2830 free_pipe->plane_res.mpcc_inst = 2831 pool->dpps[free_pipe->pipe_idx]->inst; 2832 } else { 2833 ASSERT(opp_head_pipe); 2834 free_pipe = NULL; 2835 } 2836 2837 return free_pipe; 2838} 2839 2840struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head( 2841 const struct dc_state *cur_ctx, 2842 struct dc_state *new_ctx, 2843 const struct resource_pool *pool, 2844 const struct pipe_ctx *otg_master) 2845{ 2846 int free_pipe_idx = find_optimal_free_pipe_as_secondary_opp_head( 2847 &cur_ctx->res_ctx, &new_ctx->res_ctx, 2848 pool, otg_master); 2849 struct pipe_ctx *free_pipe; 2850 2851 if (free_pipe_idx >= 0) { 2852 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx]; 2853 free_pipe->pipe_idx = free_pipe_idx; 2854 free_pipe->stream = otg_master->stream; 2855 free_pipe->stream_res.tg = otg_master->stream_res.tg; 2856 free_pipe->stream_res.dsc = NULL; 2857 free_pipe->stream_res.opp = pool->opps[free_pipe_idx]; 2858 free_pipe->plane_res.mi = pool->mis[free_pipe_idx]; 2859 free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx]; 2860 free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx]; 2861 free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx]; 2862 free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx]; 2863 free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst; 2864 free_pipe->dsc_padding_params = otg_master->dsc_padding_params; 2865 if (free_pipe->stream->timing.flags.DSC == 1) { 2866 dcn20_acquire_dsc(free_pipe->stream->ctx->dc, 2867 &new_ctx->res_ctx, 2868 &free_pipe->stream_res.dsc, 2869 free_pipe_idx); 2870 ASSERT(free_pipe->stream_res.dsc); 2871 if (free_pipe->stream_res.dsc == NULL) { 2872 memset(free_pipe, 0, sizeof(*free_pipe)); 2873 free_pipe = NULL; 2874 } 2875 } 2876 } else { 2877 ASSERT(otg_master); 2878 free_pipe = NULL; 2879 } 2880 2881 return free_pipe; 2882} 2883 2884unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans) 2885{ 2886 /* 2887 * DCN32 and DCN321 SKUs may have different sizes for MALL 2888 * but we may not be able to access all the MALL space. 2889 * If the num_chans is power of 2, then we can access all 2890 * of the available MALL space. Otherwise, we can only 2891 * access: 2892 * 2893 * max_cab_size_in_bytes = total_cache_size_in_bytes * 2894 * ((2^floor(log2(num_chans)))/num_chans) 2895 * 2896 * Calculating the MALL sizes for all available SKUs, we 2897 * have come up with the follow simplified check. 2898 * - we have max_chans which provides the max MALL size. 2899 * Each chans supports 4MB of MALL so: 2900 * 2901 * total_cache_size_in_bytes = max_chans * 4 MB 2902 * 2903 * - we have avail_chans which shows the number of channels 2904 * we can use if we can't access the entire MALL space. 2905 * It is generally half of max_chans 2906 * - so we use the following checks: 2907 * 2908 * if (num_chans == max_chans), return max_chans 2909 * if (num_chans < max_chans), return avail_chans 2910 * 2911 * - exception is GC_11_0_0 where we can't access max_chans, 2912 * so we define max_avail_chans as the maximum available 2913 * MALL space 2914 * 2915 */ 2916 int gc_11_0_0_max_chans = 48; 2917 int gc_11_0_0_max_avail_chans = 32; 2918 int gc_11_0_0_avail_chans = 16; 2919 int gc_11_0_3_max_chans = 16; 2920 int gc_11_0_3_avail_chans = 8; 2921 int gc_11_0_2_max_chans = 8; 2922 int gc_11_0_2_avail_chans = 4; 2923 2924 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) { 2925 return (num_chans == gc_11_0_0_max_chans) ? 2926 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans; 2927 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) { 2928 return (num_chans == gc_11_0_2_max_chans) ? 2929 gc_11_0_2_max_chans : gc_11_0_2_avail_chans; 2930 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) { 2931 return (num_chans == gc_11_0_3_max_chans) ? 2932 gc_11_0_3_max_chans : gc_11_0_3_avail_chans; 2933 } 2934}
~/
Read-only file preview.