dcn316_resource.c

   1/*
   2 * Copyright 2021 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26
  27#include "dm_services.h"
  28#include "dc.h"
  29
  30#include "dcn31/dcn31_init.h"
  31
  32#include "resource.h"
  33#include "include/irq_service_interface.h"
  34#include "dcn316_resource.h"
  35
  36#include "dcn20/dcn20_resource.h"
  37#include "dcn30/dcn30_resource.h"
  38#include "dcn31/dcn31_resource.h"
  39
  40#include "dcn10/dcn10_ipp.h"
  41#include "dcn30/dcn30_hubbub.h"
  42#include "dcn31/dcn31_hubbub.h"
  43#include "dcn30/dcn30_mpc.h"
  44#include "dcn31/dcn31_hubp.h"
  45#include "irq/dcn31/irq_service_dcn31.h"
  46#include "dcn30/dcn30_dpp.h"
  47#include "dcn31/dcn31_optc.h"
  48#include "dcn20/dcn20_hwseq.h"
  49#include "dcn30/dcn30_hwseq.h"
  50#include "dce110/dce110_hwseq.h"
  51#include "dcn30/dcn30_opp.h"
  52#include "dcn20/dcn20_dsc.h"
  53#include "dcn30/dcn30_vpg.h"
  54#include "dcn30/dcn30_afmt.h"
  55#include "dcn30/dcn30_dio_stream_encoder.h"
  56#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  57#include "dcn31/dcn31_hpo_dp_link_encoder.h"
  58#include "dcn31/dcn31_apg.h"
  59#include "dcn31/dcn31_dio_link_encoder.h"
  60#include "dcn31/dcn31_vpg.h"
  61#include "dcn31/dcn31_afmt.h"
  62#include "dce/dce_clock_source.h"
  63#include "dce/dce_audio.h"
  64#include "dce/dce_hwseq.h"
  65#include "clk_mgr.h"
  66#include "virtual/virtual_stream_encoder.h"
  67#include "dce110/dce110_resource.h"
  68#include "dml/display_mode_vba.h"
  69#include "dml/dcn31/dcn31_fpu.h"
  70#include "dcn31/dcn31_dccg.h"
  71#include "dcn10/dcn10_resource.h"
  72#include "dcn31/dcn31_panel_cntl.h"
  73
  74#include "dcn30/dcn30_dwb.h"
  75#include "dcn30/dcn30_mmhubbub.h"
  76
  77#include "dcn/dcn_3_1_6_offset.h"
  78#include "dcn/dcn_3_1_6_sh_mask.h"
  79#include "dpcs/dpcs_4_2_3_offset.h"
  80#include "dpcs/dpcs_4_2_3_sh_mask.h"
  81
  82#define regBIF_BX1_BIOS_SCRATCH_2                                                                       0x003a
  83#define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX                                                              1
  84#define regBIF_BX1_BIOS_SCRATCH_3                                                                       0x003b
  85#define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX                                                              1
  86#define regBIF_BX1_BIOS_SCRATCH_6                                                                       0x003e
  87#define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX                                                              1
  88
  89#define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
  90#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
  91#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
  92#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
  93
  94#define DCN_BASE__INST0_SEG0                       0x00000012
  95#define DCN_BASE__INST0_SEG1                       0x000000C0
  96#define DCN_BASE__INST0_SEG2                       0x000034C0
  97#define DCN_BASE__INST0_SEG3                       0x00009000
  98#define DCN_BASE__INST0_SEG4                       0x02403C00
  99#define DCN_BASE__INST0_SEG5                       0
 100
 101#define DPCS_BASE__INST0_SEG0                      0x00000012
 102#define DPCS_BASE__INST0_SEG1                      0x000000C0
 103#define DPCS_BASE__INST0_SEG2                      0x000034C0
 104#define DPCS_BASE__INST0_SEG3                      0x00009000
 105#define DPCS_BASE__INST0_SEG4                      0x02403C00
 106#define DPCS_BASE__INST0_SEG5                      0
 107
 108#define NBIO_BASE__INST0_SEG0                      0x00000000
 109#define NBIO_BASE__INST0_SEG1                      0x00000014
 110#define NBIO_BASE__INST0_SEG2                      0x00000D20
 111#define NBIO_BASE__INST0_SEG3                      0x00010400
 112#define NBIO_BASE__INST0_SEG4                      0x0241B000
 113#define NBIO_BASE__INST0_SEG5                      0x04040000
 114
 115#include "reg_helper.h"
 116#include "dce/dmub_abm.h"
 117#include "dce/dmub_psr.h"
 118#include "dce/dce_aux.h"
 119#include "dce/dce_i2c.h"
 120
 121#include "dml/dcn30/display_mode_vba_30.h"
 122#include "vm_helper.h"
 123#include "dcn20/dcn20_vmid.h"
 124
 125#include "link_enc_cfg.h"
 126
 127#define DCN3_16_MAX_DET_SIZE 384
 128#define DCN3_16_CRB_SEGMENT_SIZE_KB 64
 129
 130enum dcn31_clk_src_array_id {
 131	DCN31_CLK_SRC_PLL0,
 132	DCN31_CLK_SRC_PLL1,
 133	DCN31_CLK_SRC_PLL2,
 134	DCN31_CLK_SRC_PLL3,
 135	DCN31_CLK_SRC_PLL4,
 136	DCN30_CLK_SRC_TOTAL
 137};
 138
 139/* begin *********************
 140 * macros to expend register list macro defined in HW object header file
 141 */
 142
 143/* DCN */
 144#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 145
 146#define BASE(seg) BASE_INNER(seg)
 147
 148#define SR(reg_name)\
 149		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 150					reg ## reg_name
 151
 152#define SRI(reg_name, block, id)\
 153	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 154					reg ## block ## id ## _ ## reg_name
 155
 156#define SRI2(reg_name, block, id)\
 157	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 158					reg ## reg_name
 159
 160#define SRIR(var_name, reg_name, block, id)\
 161	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 162					reg ## block ## id ## _ ## reg_name
 163
 164#define SRII(reg_name, block, id)\
 165	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 166					reg ## block ## id ## _ ## reg_name
 167
 168#define SRII_MPC_RMU(reg_name, block, id)\
 169	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 170					reg ## block ## id ## _ ## reg_name
 171
 172#define SRII_DWB(reg_name, temp_name, block, id)\
 173	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 174					reg ## block ## id ## _ ## temp_name
 175
 176#define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
 177	.field_name = reg_name ## __ ## field_name ## post_fix
 178
 179#define DCCG_SRII(reg_name, block, id)\
 180	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 181					reg ## block ## id ## _ ## reg_name
 182
 183#define VUPDATE_SRII(reg_name, block, id)\
 184	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 185					reg ## reg_name ## _ ## block ## id
 186
 187/* NBIO */
 188#define NBIO_BASE_INNER(seg) \
 189	NBIO_BASE__INST0_SEG ## seg
 190
 191#define NBIO_BASE(seg) \
 192	NBIO_BASE_INNER(seg)
 193
 194#define NBIO_SR(reg_name)\
 195		.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
 196					regBIF_BX1_ ## reg_name
 197
 198static const struct bios_registers bios_regs = {
 199		NBIO_SR(BIOS_SCRATCH_3),
 200		NBIO_SR(BIOS_SCRATCH_6)
 201};
 202
 203#define clk_src_regs(index, pllid)\
 204[index] = {\
 205	CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 206}
 207
 208static const struct dce110_clk_src_regs clk_src_regs[] = {
 209	clk_src_regs(0, A),
 210	clk_src_regs(1, B),
 211	clk_src_regs(2, C),
 212	clk_src_regs(3, D),
 213	clk_src_regs(4, E)
 214};
 215
 216static const struct dce110_clk_src_shift cs_shift = {
 217		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 218};
 219
 220static const struct dce110_clk_src_mask cs_mask = {
 221		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 222};
 223
 224#define abm_regs(id)\
 225[id] = {\
 226		ABM_DCN302_REG_LIST(id)\
 227}
 228
 229static const struct dce_abm_registers abm_regs[] = {
 230		abm_regs(0),
 231		abm_regs(1),
 232		abm_regs(2),
 233		abm_regs(3),
 234};
 235
 236static const struct dce_abm_shift abm_shift = {
 237		ABM_MASK_SH_LIST_DCN30(__SHIFT)
 238};
 239
 240static const struct dce_abm_mask abm_mask = {
 241		ABM_MASK_SH_LIST_DCN30(_MASK)
 242};
 243
 244#define audio_regs(id)\
 245[id] = {\
 246		AUD_COMMON_REG_LIST(id)\
 247}
 248
 249static const struct dce_audio_registers audio_regs[] = {
 250	audio_regs(0),
 251	audio_regs(1),
 252	audio_regs(2),
 253	audio_regs(3),
 254	audio_regs(4),
 255	audio_regs(5),
 256	audio_regs(6)
 257};
 258
 259#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 260		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 261		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 262		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 263
 264static const struct dce_audio_shift audio_shift = {
 265		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 266};
 267
 268static const struct dce_audio_mask audio_mask = {
 269		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 270};
 271
 272#define vpg_regs(id)\
 273[id] = {\
 274	VPG_DCN31_REG_LIST(id)\
 275}
 276
 277static const struct dcn31_vpg_registers vpg_regs[] = {
 278	vpg_regs(0),
 279	vpg_regs(1),
 280	vpg_regs(2),
 281	vpg_regs(3),
 282	vpg_regs(4),
 283	vpg_regs(5),
 284	vpg_regs(6),
 285	vpg_regs(7),
 286	vpg_regs(8),
 287	vpg_regs(9),
 288};
 289
 290static const struct dcn31_vpg_shift vpg_shift = {
 291	DCN31_VPG_MASK_SH_LIST(__SHIFT)
 292};
 293
 294static const struct dcn31_vpg_mask vpg_mask = {
 295	DCN31_VPG_MASK_SH_LIST(_MASK)
 296};
 297
 298#define afmt_regs(id)\
 299[id] = {\
 300	AFMT_DCN31_REG_LIST(id)\
 301}
 302
 303static const struct dcn31_afmt_registers afmt_regs[] = {
 304	afmt_regs(0),
 305	afmt_regs(1),
 306	afmt_regs(2),
 307	afmt_regs(3),
 308	afmt_regs(4),
 309	afmt_regs(5)
 310};
 311
 312static const struct dcn31_afmt_shift afmt_shift = {
 313	DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 314};
 315
 316static const struct dcn31_afmt_mask afmt_mask = {
 317	DCN31_AFMT_MASK_SH_LIST(_MASK)
 318};
 319
 320
 321#define apg_regs(id)\
 322[id] = {\
 323	APG_DCN31_REG_LIST(id)\
 324}
 325
 326static const struct dcn31_apg_registers apg_regs[] = {
 327	apg_regs(0),
 328	apg_regs(1),
 329	apg_regs(2),
 330	apg_regs(3)
 331};
 332
 333static const struct dcn31_apg_shift apg_shift = {
 334	DCN31_APG_MASK_SH_LIST(__SHIFT)
 335};
 336
 337static const struct dcn31_apg_mask apg_mask = {
 338		DCN31_APG_MASK_SH_LIST(_MASK)
 339};
 340
 341
 342#define stream_enc_regs(id)\
 343[id] = {\
 344	SE_DCN3_REG_LIST(id)\
 345}
 346
 347static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 348	stream_enc_regs(0),
 349	stream_enc_regs(1),
 350	stream_enc_regs(2),
 351	stream_enc_regs(3),
 352	stream_enc_regs(4)
 353};
 354
 355static const struct dcn10_stream_encoder_shift se_shift = {
 356		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 357};
 358
 359static const struct dcn10_stream_encoder_mask se_mask = {
 360		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 361};
 362
 363
 364#define aux_regs(id)\
 365[id] = {\
 366	DCN2_AUX_REG_LIST(id)\
 367}
 368
 369static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 370		aux_regs(0),
 371		aux_regs(1),
 372		aux_regs(2),
 373		aux_regs(3),
 374		aux_regs(4)
 375};
 376
 377#define hpd_regs(id)\
 378[id] = {\
 379	HPD_REG_LIST(id)\
 380}
 381
 382static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 383		hpd_regs(0),
 384		hpd_regs(1),
 385		hpd_regs(2),
 386		hpd_regs(3),
 387		hpd_regs(4)
 388};
 389
 390#define link_regs(id, phyid)\
 391[id] = {\
 392	LE_DCN31_REG_LIST(id), \
 393	UNIPHY_DCN2_REG_LIST(phyid), \
 394	DPCS_DCN31_REG_LIST(id), \
 395}
 396
 397static const struct dce110_aux_registers_shift aux_shift = {
 398	DCN_AUX_MASK_SH_LIST(__SHIFT)
 399};
 400
 401static const struct dce110_aux_registers_mask aux_mask = {
 402	DCN_AUX_MASK_SH_LIST(_MASK)
 403};
 404
 405static const struct dcn10_link_enc_registers link_enc_regs[] = {
 406	link_regs(0, A),
 407	link_regs(1, B),
 408	link_regs(2, C),
 409	link_regs(3, D),
 410	link_regs(4, E)
 411};
 412
 413static const struct dcn10_link_enc_shift le_shift = {
 414	LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 415	DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 416};
 417
 418static const struct dcn10_link_enc_mask le_mask = {
 419	LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 420	DPCS_DCN31_MASK_SH_LIST(_MASK)
 421};
 422
 423
 424
 425#define hpo_dp_stream_encoder_reg_list(id)\
 426[id] = {\
 427	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 428}
 429
 430static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 431	hpo_dp_stream_encoder_reg_list(0),
 432	hpo_dp_stream_encoder_reg_list(1),
 433	hpo_dp_stream_encoder_reg_list(2),
 434	hpo_dp_stream_encoder_reg_list(3),
 435};
 436
 437static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 438	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 439};
 440
 441static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 442	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 443};
 444
 445
 446#define hpo_dp_link_encoder_reg_list(id)\
 447[id] = {\
 448	DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 449	DCN3_1_RDPCSTX_REG_LIST(0),\
 450	DCN3_1_RDPCSTX_REG_LIST(1),\
 451	DCN3_1_RDPCSTX_REG_LIST(2),\
 452	DCN3_1_RDPCSTX_REG_LIST(3),\
 453	DCN3_1_RDPCSTX_REG_LIST(4)\
 454}
 455
 456static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 457	hpo_dp_link_encoder_reg_list(0),
 458	hpo_dp_link_encoder_reg_list(1),
 459};
 460
 461static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 462	DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 463};
 464
 465static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 466	DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 467};
 468
 469
 470#define dpp_regs(id)\
 471[id] = {\
 472	DPP_REG_LIST_DCN30(id),\
 473}
 474
 475static const struct dcn3_dpp_registers dpp_regs[] = {
 476	dpp_regs(0),
 477	dpp_regs(1),
 478	dpp_regs(2),
 479	dpp_regs(3)
 480};
 481
 482static const struct dcn3_dpp_shift tf_shift = {
 483		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 484};
 485
 486static const struct dcn3_dpp_mask tf_mask = {
 487		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 488};
 489
 490#define opp_regs(id)\
 491[id] = {\
 492	OPP_REG_LIST_DCN30(id),\
 493}
 494
 495static const struct dcn20_opp_registers opp_regs[] = {
 496	opp_regs(0),
 497	opp_regs(1),
 498	opp_regs(2),
 499	opp_regs(3)
 500};
 501
 502static const struct dcn20_opp_shift opp_shift = {
 503	OPP_MASK_SH_LIST_DCN20(__SHIFT)
 504};
 505
 506static const struct dcn20_opp_mask opp_mask = {
 507	OPP_MASK_SH_LIST_DCN20(_MASK)
 508};
 509
 510#define aux_engine_regs(id)\
 511[id] = {\
 512	AUX_COMMON_REG_LIST0(id), \
 513	.AUXN_IMPCAL = 0, \
 514	.AUXP_IMPCAL = 0, \
 515	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 516}
 517
 518static const struct dce110_aux_registers aux_engine_regs[] = {
 519		aux_engine_regs(0),
 520		aux_engine_regs(1),
 521		aux_engine_regs(2),
 522		aux_engine_regs(3),
 523		aux_engine_regs(4)
 524};
 525
 526#define dwbc_regs_dcn3(id)\
 527[id] = {\
 528	DWBC_COMMON_REG_LIST_DCN30(id),\
 529}
 530
 531static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 532	dwbc_regs_dcn3(0),
 533};
 534
 535static const struct dcn30_dwbc_shift dwbc30_shift = {
 536	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 537};
 538
 539static const struct dcn30_dwbc_mask dwbc30_mask = {
 540	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 541};
 542
 543#define mcif_wb_regs_dcn3(id)\
 544[id] = {\
 545	MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 546}
 547
 548static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 549	mcif_wb_regs_dcn3(0)
 550};
 551
 552static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 553	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 554};
 555
 556static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 557	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 558};
 559
 560#define dsc_regsDCN20(id)\
 561[id] = {\
 562	DSC_REG_LIST_DCN20(id)\
 563}
 564
 565static const struct dcn20_dsc_registers dsc_regs[] = {
 566	dsc_regsDCN20(0),
 567	dsc_regsDCN20(1),
 568	dsc_regsDCN20(2)
 569};
 570
 571static const struct dcn20_dsc_shift dsc_shift = {
 572	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 573};
 574
 575static const struct dcn20_dsc_mask dsc_mask = {
 576	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 577};
 578
 579static const struct dcn30_mpc_registers mpc_regs = {
 580		MPC_REG_LIST_DCN3_0(0),
 581		MPC_REG_LIST_DCN3_0(1),
 582		MPC_REG_LIST_DCN3_0(2),
 583		MPC_REG_LIST_DCN3_0(3),
 584		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 585		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 586		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 587		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 588		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 589		MPC_RMU_REG_LIST_DCN3AG(0),
 590		MPC_RMU_REG_LIST_DCN3AG(1),
 591		//MPC_RMU_REG_LIST_DCN3AG(2),
 592		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 593};
 594
 595static const struct dcn30_mpc_shift mpc_shift = {
 596	MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 597};
 598
 599static const struct dcn30_mpc_mask mpc_mask = {
 600	MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 601};
 602
 603#define optc_regs(id)\
 604[id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
 605
 606static const struct dcn_optc_registers optc_regs[] = {
 607	optc_regs(0),
 608	optc_regs(1),
 609	optc_regs(2),
 610	optc_regs(3)
 611};
 612
 613static const struct dcn_optc_shift optc_shift = {
 614	OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
 615};
 616
 617static const struct dcn_optc_mask optc_mask = {
 618	OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
 619};
 620
 621#define hubp_regs(id)\
 622[id] = {\
 623	HUBP_REG_LIST_DCN30(id)\
 624}
 625
 626static const struct dcn_hubp2_registers hubp_regs[] = {
 627		hubp_regs(0),
 628		hubp_regs(1),
 629		hubp_regs(2),
 630		hubp_regs(3)
 631};
 632
 633
 634static const struct dcn_hubp2_shift hubp_shift = {
 635		HUBP_MASK_SH_LIST_DCN31(__SHIFT)
 636};
 637
 638static const struct dcn_hubp2_mask hubp_mask = {
 639		HUBP_MASK_SH_LIST_DCN31(_MASK)
 640};
 641static const struct dcn_hubbub_registers hubbub_reg = {
 642		HUBBUB_REG_LIST_DCN31(0)
 643};
 644
 645static const struct dcn_hubbub_shift hubbub_shift = {
 646		HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
 647};
 648
 649static const struct dcn_hubbub_mask hubbub_mask = {
 650		HUBBUB_MASK_SH_LIST_DCN31(_MASK)
 651};
 652
 653static const struct dccg_registers dccg_regs = {
 654		DCCG_REG_LIST_DCN31()
 655};
 656
 657static const struct dccg_shift dccg_shift = {
 658		DCCG_MASK_SH_LIST_DCN31(__SHIFT)
 659};
 660
 661static const struct dccg_mask dccg_mask = {
 662		DCCG_MASK_SH_LIST_DCN31(_MASK)
 663};
 664
 665
 666#define SRII2(reg_name_pre, reg_name_post, id)\
 667	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 668			## id ## _ ## reg_name_post ## _BASE_IDX) + \
 669			reg ## reg_name_pre ## id ## _ ## reg_name_post
 670
 671
 672#define HWSEQ_DCN31_REG_LIST()\
 673	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 674	SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
 675	SR(DIO_MEM_PWR_CTRL), \
 676	SR(ODM_MEM_PWR_CTRL3), \
 677	SR(DMU_MEM_PWR_CNTL), \
 678	SR(MMHUBBUB_MEM_PWR_CNTL), \
 679	SR(DCCG_GATE_DISABLE_CNTL), \
 680	SR(DCCG_GATE_DISABLE_CNTL2), \
 681	SR(DCFCLK_CNTL),\
 682	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 683	SRII(PIXEL_RATE_CNTL, OTG, 0), \
 684	SRII(PIXEL_RATE_CNTL, OTG, 1),\
 685	SRII(PIXEL_RATE_CNTL, OTG, 2),\
 686	SRII(PIXEL_RATE_CNTL, OTG, 3),\
 687	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 688	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 689	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 690	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 691	SR(MICROSECOND_TIME_BASE_DIV), \
 692	SR(MILLISECOND_TIME_BASE_DIV), \
 693	SR(DISPCLK_FREQ_CHANGE_CNTL), \
 694	SR(RBBMIF_TIMEOUT_DIS), \
 695	SR(RBBMIF_TIMEOUT_DIS_2), \
 696	SR(DCHUBBUB_CRC_CTRL), \
 697	SR(DPP_TOP0_DPP_CRC_CTRL), \
 698	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 699	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 700	SR(MPC_CRC_CTRL), \
 701	SR(MPC_CRC_RESULT_GB), \
 702	SR(MPC_CRC_RESULT_C), \
 703	SR(MPC_CRC_RESULT_AR), \
 704	SR(DOMAIN0_PG_CONFIG), \
 705	SR(DOMAIN1_PG_CONFIG), \
 706	SR(DOMAIN2_PG_CONFIG), \
 707	SR(DOMAIN3_PG_CONFIG), \
 708	SR(DOMAIN16_PG_CONFIG), \
 709	SR(DOMAIN17_PG_CONFIG), \
 710	SR(DOMAIN18_PG_CONFIG), \
 711	SR(DOMAIN0_PG_STATUS), \
 712	SR(DOMAIN1_PG_STATUS), \
 713	SR(DOMAIN2_PG_STATUS), \
 714	SR(DOMAIN3_PG_STATUS), \
 715	SR(DOMAIN16_PG_STATUS), \
 716	SR(DOMAIN17_PG_STATUS), \
 717	SR(DOMAIN18_PG_STATUS), \
 718	SR(D1VGA_CONTROL), \
 719	SR(D2VGA_CONTROL), \
 720	SR(D3VGA_CONTROL), \
 721	SR(D4VGA_CONTROL), \
 722	SR(D5VGA_CONTROL), \
 723	SR(D6VGA_CONTROL), \
 724	SR(DC_IP_REQUEST_CNTL), \
 725	SR(AZALIA_AUDIO_DTO), \
 726	SR(AZALIA_CONTROLLER_CLOCK_GATING), \
 727	SR(HPO_TOP_HW_CONTROL)
 728
 729static const struct dce_hwseq_registers hwseq_reg = {
 730		HWSEQ_DCN31_REG_LIST()
 731};
 732
 733#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 734	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 735	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 736	HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 737	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 738	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 739	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 740	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 741	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 742	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 743	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 744	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 745	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 746	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 747	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 748	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 749	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 750	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 751	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 752	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 753	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 754	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 755	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 756	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 757	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 758	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 759	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 760	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 761	HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
 762	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 763	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 764	HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
 765	HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 766	HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
 767
 768static const struct dce_hwseq_shift hwseq_shift = {
 769		HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
 770};
 771
 772static const struct dce_hwseq_mask hwseq_mask = {
 773		HWSEQ_DCN31_MASK_SH_LIST(_MASK)
 774};
 775#define vmid_regs(id)\
 776[id] = {\
 777		DCN20_VMID_REG_LIST(id)\
 778}
 779
 780static const struct dcn_vmid_registers vmid_regs[] = {
 781	vmid_regs(0),
 782	vmid_regs(1),
 783	vmid_regs(2),
 784	vmid_regs(3),
 785	vmid_regs(4),
 786	vmid_regs(5),
 787	vmid_regs(6),
 788	vmid_regs(7),
 789	vmid_regs(8),
 790	vmid_regs(9),
 791	vmid_regs(10),
 792	vmid_regs(11),
 793	vmid_regs(12),
 794	vmid_regs(13),
 795	vmid_regs(14),
 796	vmid_regs(15)
 797};
 798
 799static const struct dcn20_vmid_shift vmid_shifts = {
 800		DCN20_VMID_MASK_SH_LIST(__SHIFT)
 801};
 802
 803static const struct dcn20_vmid_mask vmid_masks = {
 804		DCN20_VMID_MASK_SH_LIST(_MASK)
 805};
 806
 807static const struct resource_caps res_cap_dcn31 = {
 808	.num_timing_generator = 4,
 809	.num_opp = 4,
 810	.num_video_plane = 4,
 811	.num_audio = 5,
 812	.num_stream_encoder = 5,
 813	.num_dig_link_enc = 5,
 814	.num_hpo_dp_stream_encoder = 4,
 815	.num_hpo_dp_link_encoder = 2,
 816	.num_pll = 5,
 817	.num_dwb = 1,
 818	.num_ddc = 5,
 819	.num_vmid = 16,
 820	.num_mpc_3dlut = 2,
 821	.num_dsc = 3,
 822};
 823
 824static const struct dc_plane_cap plane_cap = {
 825	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 826	.per_pixel_alpha = true,
 827
 828	.pixel_format_support = {
 829			.argb8888 = true,
 830			.nv12 = true,
 831			.fp16 = true,
 832			.p010 = true,
 833			.ayuv = false,
 834	},
 835
 836	.max_upscale_factor = {
 837			.argb8888 = 16000,
 838			.nv12 = 16000,
 839			.fp16 = 16000
 840	},
 841
 842	// 6:1 downscaling ratio: 1000/6 = 166.666
 843	.max_downscale_factor = {
 844			.argb8888 = 167,
 845			.nv12 = 167,
 846			.fp16 = 167
 847	},
 848	64,
 849	64
 850};
 851
 852static const struct dc_debug_options debug_defaults_drv = {
 853	.disable_z10 = true, /*hw not support it*/
 854	.disable_dmcu = true,
 855	.force_abm_enable = false,
 856	.clock_trace = true,
 857	.disable_pplib_clock_request = false,
 858	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
 859	.force_single_disp_pipe_split = false,
 860	.disable_dcc = DCC_ENABLE,
 861	.vsr_support = true,
 862	.performance_trace = false,
 863	.max_downscale_src_width = 4096,/*upto true 4k*/
 864	.disable_pplib_wm_range = false,
 865	.scl_reset_length10 = true,
 866	.sanity_checks = false,
 867	.underflow_assert_delay_us = 0xFFFFFFFF,
 868	.dwb_fi_phase = -1, // -1 = disable,
 869	.dmub_command_table = true,
 870	.pstate_enabled = true,
 871	.use_max_lb = true,
 872	.enable_mem_low_power = {
 873		.bits = {
 874			.vga = true,
 875			.i2c = true,
 876			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 877			.dscl = true,
 878			.cm = true,
 879			.mpc = true,
 880			.optc = true,
 881			.vpg = true,
 882			.afmt = true,
 883		}
 884	},
 885	.using_dml2 = false,
 886};
 887
 888static const struct dc_check_config config_defaults = {
 889	.enable_legacy_fast_update = true,
 890};
 891
 892static const struct dc_panel_config panel_config_defaults = {
 893	.psr = {
 894		.disable_psr = false,
 895		.disallow_psrsu = false,
 896		.disallow_replay = false,
 897	},
 898	.ilr = {
 899		.optimize_edp_link_rate = true,
 900	},
 901};
 902
 903static void dcn31_dpp_destroy(struct dpp **dpp)
 904{
 905	kfree(TO_DCN20_DPP(*dpp));
 906	*dpp = NULL;
 907}
 908
 909static struct dpp *dcn31_dpp_create(
 910	struct dc_context *ctx,
 911	uint32_t inst)
 912{
 913	struct dcn3_dpp *dpp =
 914		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 915
 916	if (!dpp)
 917		return NULL;
 918
 919	if (dpp3_construct(dpp, ctx, inst,
 920			&dpp_regs[inst], &tf_shift, &tf_mask))
 921		return &dpp->base;
 922
 923	BREAK_TO_DEBUGGER();
 924	kfree(dpp);
 925	return NULL;
 926}
 927
 928static struct output_pixel_processor *dcn31_opp_create(
 929	struct dc_context *ctx, uint32_t inst)
 930{
 931	struct dcn20_opp *opp =
 932		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 933
 934	if (!opp) {
 935		BREAK_TO_DEBUGGER();
 936		return NULL;
 937	}
 938
 939	dcn20_opp_construct(opp, ctx, inst,
 940			&opp_regs[inst], &opp_shift, &opp_mask);
 941	return &opp->base;
 942}
 943
 944static struct dce_aux *dcn31_aux_engine_create(
 945	struct dc_context *ctx,
 946	uint32_t inst)
 947{
 948	struct aux_engine_dce110 *aux_engine =
 949		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 950
 951	if (!aux_engine)
 952		return NULL;
 953
 954	dce110_aux_engine_construct(aux_engine, ctx, inst,
 955				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 956				    &aux_engine_regs[inst],
 957					&aux_mask,
 958					&aux_shift,
 959					ctx->dc->caps.extended_aux_timeout_support);
 960
 961	return &aux_engine->base;
 962}
 963#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
 964
 965static const struct dce_i2c_registers i2c_hw_regs[] = {
 966		i2c_inst_regs(1),
 967		i2c_inst_regs(2),
 968		i2c_inst_regs(3),
 969		i2c_inst_regs(4),
 970		i2c_inst_regs(5),
 971};
 972
 973static const struct dce_i2c_shift i2c_shifts = {
 974		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 975};
 976
 977static const struct dce_i2c_mask i2c_masks = {
 978		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
 979};
 980
 981static struct dce_i2c_hw *dcn31_i2c_hw_create(
 982	struct dc_context *ctx,
 983	uint32_t inst)
 984{
 985	struct dce_i2c_hw *dce_i2c_hw =
 986		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 987
 988	if (!dce_i2c_hw)
 989		return NULL;
 990
 991	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 992				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 993
 994	return dce_i2c_hw;
 995}
 996static struct mpc *dcn31_mpc_create(
 997		struct dc_context *ctx,
 998		int num_mpcc,
 999		int num_rmu)
1000{
1001	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1002					  GFP_KERNEL);
1003
1004	if (!mpc30)
1005		return NULL;
1006
1007	dcn30_mpc_construct(mpc30, ctx,
1008			&mpc_regs,
1009			&mpc_shift,
1010			&mpc_mask,
1011			num_mpcc,
1012			num_rmu);
1013
1014	return &mpc30->base;
1015}
1016
1017static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1018{
1019	int i;
1020
1021	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1022					  GFP_KERNEL);
1023
1024	if (!hubbub3)
1025		return NULL;
1026
1027	hubbub31_construct(hubbub3, ctx,
1028			&hubbub_reg,
1029			&hubbub_shift,
1030			&hubbub_mask,
1031			dcn3_16_ip.det_buffer_size_kbytes,
1032			dcn3_16_ip.pixel_chunk_size_kbytes,
1033			dcn3_16_ip.config_return_buffer_size_in_kbytes);
1034
1035
1036	for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1037		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1038
1039		vmid->ctx = ctx;
1040
1041		vmid->regs = &vmid_regs[i];
1042		vmid->shifts = &vmid_shifts;
1043		vmid->masks = &vmid_masks;
1044	}
1045
1046	return &hubbub3->base;
1047}
1048
1049static struct timing_generator *dcn31_timing_generator_create(
1050		struct dc_context *ctx,
1051		uint32_t instance)
1052{
1053	struct optc *tgn10 =
1054		kzalloc(sizeof(struct optc), GFP_KERNEL);
1055
1056	if (!tgn10)
1057		return NULL;
1058
1059	tgn10->base.inst = instance;
1060	tgn10->base.ctx = ctx;
1061
1062	tgn10->tg_regs = &optc_regs[instance];
1063	tgn10->tg_shift = &optc_shift;
1064	tgn10->tg_mask = &optc_mask;
1065
1066	dcn31_timing_generator_init(tgn10);
1067
1068	return &tgn10->base;
1069}
1070
1071static const struct encoder_feature_support link_enc_feature = {
1072		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1073		.max_hdmi_pixel_clock = 600000,
1074		.hdmi_ycbcr420_supported = true,
1075		.dp_ycbcr420_supported = true,
1076		.fec_supported = true,
1077		.flags.bits.IS_HBR2_CAPABLE = true,
1078		.flags.bits.IS_HBR3_CAPABLE = true,
1079		.flags.bits.IS_TPS3_CAPABLE = true,
1080		.flags.bits.IS_TPS4_CAPABLE = true
1081};
1082
1083static struct link_encoder *dcn31_link_encoder_create(
1084	struct dc_context *ctx,
1085	const struct encoder_init_data *enc_init_data)
1086{
1087	struct dcn20_link_encoder *enc20 =
1088		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1089
1090	if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1091		return NULL;
1092
1093	dcn31_link_encoder_construct(enc20,
1094			enc_init_data,
1095			&link_enc_feature,
1096			&link_enc_regs[enc_init_data->transmitter],
1097			&link_enc_aux_regs[enc_init_data->channel - 1],
1098			&link_enc_hpd_regs[enc_init_data->hpd_source],
1099			&le_shift,
1100			&le_mask);
1101
1102	return &enc20->enc10.base;
1103}
1104
1105/* Create a minimal link encoder object not associated with a particular
1106 * physical connector.
1107 * resource_funcs.link_enc_create_minimal
1108 */
1109static struct link_encoder *dcn31_link_enc_create_minimal(
1110		struct dc_context *ctx, enum engine_id eng_id)
1111{
1112	struct dcn20_link_encoder *enc20;
1113
1114	if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1115		return NULL;
1116
1117	enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1118	if (!enc20)
1119		return NULL;
1120
1121	dcn31_link_encoder_construct_minimal(
1122			enc20,
1123			ctx,
1124			&link_enc_feature,
1125			&link_enc_regs[eng_id - ENGINE_ID_DIGA],
1126			eng_id);
1127
1128	return &enc20->enc10.base;
1129}
1130
1131static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1132{
1133	struct dcn31_panel_cntl *panel_cntl =
1134		kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1135
1136	if (!panel_cntl)
1137		return NULL;
1138
1139	dcn31_panel_cntl_construct(panel_cntl, init_data);
1140
1141	return &panel_cntl->base;
1142}
1143
1144static void read_dce_straps(
1145	struct dc_context *ctx,
1146	struct resource_straps *straps)
1147{
1148	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1149		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1150
1151}
1152
1153static struct audio *dcn31_create_audio(
1154		struct dc_context *ctx, unsigned int inst)
1155{
1156	return dce_audio_create(ctx, inst,
1157			&audio_regs[inst], &audio_shift, &audio_mask);
1158}
1159
1160static struct vpg *dcn31_vpg_create(
1161	struct dc_context *ctx,
1162	uint32_t inst)
1163{
1164	struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1165
1166	if (!vpg31)
1167		return NULL;
1168
1169	vpg31_construct(vpg31, ctx, inst,
1170			&vpg_regs[inst],
1171			&vpg_shift,
1172			&vpg_mask);
1173
1174	return &vpg31->base;
1175}
1176
1177static struct afmt *dcn31_afmt_create(
1178	struct dc_context *ctx,
1179	uint32_t inst)
1180{
1181	struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1182
1183	if (!afmt31)
1184		return NULL;
1185
1186	afmt31_construct(afmt31, ctx, inst,
1187			&afmt_regs[inst],
1188			&afmt_shift,
1189			&afmt_mask);
1190
1191	// Light sleep by default, no need to power down here
1192
1193	return &afmt31->base;
1194}
1195
1196
1197static struct apg *dcn31_apg_create(
1198	struct dc_context *ctx,
1199	uint32_t inst)
1200{
1201	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1202
1203	if (!apg31)
1204		return NULL;
1205
1206	apg31_construct(apg31, ctx, inst,
1207			&apg_regs[inst],
1208			&apg_shift,
1209			&apg_mask);
1210
1211	return &apg31->base;
1212}
1213
1214
1215static struct stream_encoder *dcn316_stream_encoder_create(
1216	enum engine_id eng_id,
1217	struct dc_context *ctx)
1218{
1219	struct dcn10_stream_encoder *enc1;
1220	struct vpg *vpg;
1221	struct afmt *afmt;
1222	int vpg_inst;
1223	int afmt_inst;
1224
1225	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1226	if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1227		return NULL;
1228
1229	vpg_inst = eng_id;
1230	afmt_inst = eng_id;
1231
1232	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1233	vpg = dcn31_vpg_create(ctx, vpg_inst);
1234	afmt = dcn31_afmt_create(ctx, afmt_inst);
1235
1236	if (!enc1 || !vpg || !afmt) {
1237		kfree(enc1);
1238		kfree(vpg);
1239		kfree(afmt);
1240		return NULL;
1241	}
1242
1243	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1244					eng_id, vpg, afmt,
1245					&stream_enc_regs[eng_id],
1246					&se_shift, &se_mask);
1247
1248	return &enc1->base;
1249}
1250
1251
1252static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1253	enum engine_id eng_id,
1254	struct dc_context *ctx)
1255{
1256	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1257	struct vpg *vpg;
1258	struct apg *apg;
1259	uint32_t hpo_dp_inst;
1260	uint32_t vpg_inst;
1261	uint32_t apg_inst;
1262
1263	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1264	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1265
1266	/* Mapping of VPG register blocks to HPO DP block instance:
1267	 * VPG[6] -> HPO_DP[0]
1268	 * VPG[7] -> HPO_DP[1]
1269	 * VPG[8] -> HPO_DP[2]
1270	 * VPG[9] -> HPO_DP[3]
1271	 */
1272	vpg_inst = hpo_dp_inst + 6;
1273
1274	/* Mapping of APG register blocks to HPO DP block instance:
1275	 * APG[0] -> HPO_DP[0]
1276	 * APG[1] -> HPO_DP[1]
1277	 * APG[2] -> HPO_DP[2]
1278	 * APG[3] -> HPO_DP[3]
1279	 */
1280	apg_inst = hpo_dp_inst;
1281
1282	/* allocate HPO stream encoder and create VPG sub-block */
1283	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1284	vpg = dcn31_vpg_create(ctx, vpg_inst);
1285	apg = dcn31_apg_create(ctx, apg_inst);
1286
1287	if (!hpo_dp_enc31 || !vpg || !apg) {
1288		kfree(hpo_dp_enc31);
1289		kfree(vpg);
1290		kfree(apg);
1291		return NULL;
1292	}
1293
1294	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1295					hpo_dp_inst, eng_id, vpg, apg,
1296					&hpo_dp_stream_enc_regs[hpo_dp_inst],
1297					&hpo_dp_se_shift, &hpo_dp_se_mask);
1298
1299	return &hpo_dp_enc31->base;
1300}
1301
1302static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1303	uint8_t inst,
1304	struct dc_context *ctx)
1305{
1306	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1307
1308	/* allocate HPO link encoder */
1309	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1310	if (!hpo_dp_enc31)
1311		return NULL; /* out of memory */
1312
1313	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1314					&hpo_dp_link_enc_regs[inst],
1315					&hpo_dp_le_shift, &hpo_dp_le_mask);
1316
1317	return &hpo_dp_enc31->base;
1318}
1319
1320
1321static struct dce_hwseq *dcn31_hwseq_create(
1322	struct dc_context *ctx)
1323{
1324	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1325
1326	if (hws) {
1327		hws->ctx = ctx;
1328		hws->regs = &hwseq_reg;
1329		hws->shifts = &hwseq_shift;
1330		hws->masks = &hwseq_mask;
1331	}
1332	return hws;
1333}
1334static const struct resource_create_funcs res_create_funcs = {
1335	.read_dce_straps = read_dce_straps,
1336	.create_audio = dcn31_create_audio,
1337	.create_stream_encoder = dcn316_stream_encoder_create,
1338	.create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1339	.create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1340	.create_hwseq = dcn31_hwseq_create,
1341};
1342
1343static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
1344{
1345	unsigned int i;
1346
1347	for (i = 0; i < pool->base.stream_enc_count; i++) {
1348		if (pool->base.stream_enc[i] != NULL) {
1349			if (pool->base.stream_enc[i]->vpg != NULL) {
1350				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1351				pool->base.stream_enc[i]->vpg = NULL;
1352			}
1353			if (pool->base.stream_enc[i]->afmt != NULL) {
1354				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1355				pool->base.stream_enc[i]->afmt = NULL;
1356			}
1357			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1358			pool->base.stream_enc[i] = NULL;
1359		}
1360	}
1361
1362	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1363		if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1364			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1365				kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1366				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1367			}
1368			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1369				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1370				pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1371			}
1372			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1373			pool->base.hpo_dp_stream_enc[i] = NULL;
1374		}
1375	}
1376
1377	for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1378		if (pool->base.hpo_dp_link_enc[i] != NULL) {
1379			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1380			pool->base.hpo_dp_link_enc[i] = NULL;
1381		}
1382	}
1383
1384	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1385		if (pool->base.dscs[i] != NULL)
1386			dcn20_dsc_destroy(&pool->base.dscs[i]);
1387	}
1388
1389	if (pool->base.mpc != NULL) {
1390		kfree(TO_DCN20_MPC(pool->base.mpc));
1391		pool->base.mpc = NULL;
1392	}
1393	if (pool->base.hubbub != NULL) {
1394		kfree(pool->base.hubbub);
1395		pool->base.hubbub = NULL;
1396	}
1397	for (i = 0; i < pool->base.pipe_count; i++) {
1398		if (pool->base.dpps[i] != NULL)
1399			dcn31_dpp_destroy(&pool->base.dpps[i]);
1400
1401		if (pool->base.ipps[i] != NULL)
1402			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1403
1404		if (pool->base.hubps[i] != NULL) {
1405			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1406			pool->base.hubps[i] = NULL;
1407		}
1408
1409		if (pool->base.irqs != NULL) {
1410			dal_irq_service_destroy(&pool->base.irqs);
1411		}
1412	}
1413
1414	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1415		if (pool->base.engines[i] != NULL)
1416			dce110_engine_destroy(&pool->base.engines[i]);
1417		if (pool->base.hw_i2cs[i] != NULL) {
1418			kfree(pool->base.hw_i2cs[i]);
1419			pool->base.hw_i2cs[i] = NULL;
1420		}
1421		if (pool->base.sw_i2cs[i] != NULL) {
1422			kfree(pool->base.sw_i2cs[i]);
1423			pool->base.sw_i2cs[i] = NULL;
1424		}
1425	}
1426
1427	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1428		if (pool->base.opps[i] != NULL)
1429			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1430	}
1431
1432	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1433		if (pool->base.timing_generators[i] != NULL)	{
1434			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1435			pool->base.timing_generators[i] = NULL;
1436		}
1437	}
1438
1439	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1440		if (pool->base.dwbc[i] != NULL) {
1441			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1442			pool->base.dwbc[i] = NULL;
1443		}
1444		if (pool->base.mcif_wb[i] != NULL) {
1445			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1446			pool->base.mcif_wb[i] = NULL;
1447		}
1448	}
1449
1450	for (i = 0; i < pool->base.audio_count; i++) {
1451		if (pool->base.audios[i])
1452			dce_aud_destroy(&pool->base.audios[i]);
1453	}
1454
1455	for (i = 0; i < pool->base.clk_src_count; i++) {
1456		if (pool->base.clock_sources[i] != NULL) {
1457			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1458			pool->base.clock_sources[i] = NULL;
1459		}
1460	}
1461
1462	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1463		if (pool->base.mpc_lut[i] != NULL) {
1464			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1465			pool->base.mpc_lut[i] = NULL;
1466		}
1467		if (pool->base.mpc_shaper[i] != NULL) {
1468			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1469			pool->base.mpc_shaper[i] = NULL;
1470		}
1471	}
1472
1473	if (pool->base.dp_clock_source != NULL) {
1474		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1475		pool->base.dp_clock_source = NULL;
1476	}
1477
1478	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1479		if (pool->base.multiple_abms[i] != NULL)
1480			dce_abm_destroy(&pool->base.multiple_abms[i]);
1481	}
1482
1483	if (pool->base.psr != NULL)
1484		dmub_psr_destroy(&pool->base.psr);
1485
1486	if (pool->base.dccg != NULL)
1487		dcn_dccg_destroy(&pool->base.dccg);
1488}
1489
1490static struct hubp *dcn31_hubp_create(
1491	struct dc_context *ctx,
1492	uint32_t inst)
1493{
1494	struct dcn20_hubp *hubp2 =
1495		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1496
1497	if (!hubp2)
1498		return NULL;
1499
1500	if (hubp31_construct(hubp2, ctx, inst,
1501			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1502		return &hubp2->base;
1503
1504	BREAK_TO_DEBUGGER();
1505	kfree(hubp2);
1506	return NULL;
1507}
1508
1509static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1510{
1511	int i;
1512	uint32_t pipe_count = pool->res_cap->num_dwb;
1513
1514	for (i = 0; i < pipe_count; i++) {
1515		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1516						    GFP_KERNEL);
1517
1518		if (!dwbc30) {
1519			dm_error("DC: failed to create dwbc30!\n");
1520			return false;
1521		}
1522
1523		dcn30_dwbc_construct(dwbc30, ctx,
1524				&dwbc30_regs[i],
1525				&dwbc30_shift,
1526				&dwbc30_mask,
1527				i);
1528
1529		pool->dwbc[i] = &dwbc30->base;
1530	}
1531	return true;
1532}
1533
1534static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1535{
1536	int i;
1537	uint32_t pipe_count = pool->res_cap->num_dwb;
1538
1539	for (i = 0; i < pipe_count; i++) {
1540		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1541						    GFP_KERNEL);
1542
1543		if (!mcif_wb30) {
1544			dm_error("DC: failed to create mcif_wb30!\n");
1545			return false;
1546		}
1547
1548		dcn30_mmhubbub_construct(mcif_wb30, ctx,
1549				&mcif_wb30_regs[i],
1550				&mcif_wb30_shift,
1551				&mcif_wb30_mask,
1552				i);
1553
1554		pool->mcif_wb[i] = &mcif_wb30->base;
1555	}
1556	return true;
1557}
1558
1559static struct display_stream_compressor *dcn31_dsc_create(
1560	struct dc_context *ctx, uint32_t inst)
1561{
1562	struct dcn20_dsc *dsc =
1563		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1564
1565	if (!dsc) {
1566		BREAK_TO_DEBUGGER();
1567		return NULL;
1568	}
1569
1570	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1571	return &dsc->base;
1572}
1573
1574static void dcn316_destroy_resource_pool(struct resource_pool **pool)
1575{
1576	struct dcn316_resource_pool *dcn31_pool = TO_DCN316_RES_POOL(*pool);
1577
1578	dcn316_resource_destruct(dcn31_pool);
1579	kfree(dcn31_pool);
1580	*pool = NULL;
1581}
1582
1583static struct clock_source *dcn31_clock_source_create(
1584		struct dc_context *ctx,
1585		struct dc_bios *bios,
1586		enum clock_source_id id,
1587		const struct dce110_clk_src_regs *regs,
1588		bool dp_clk_src)
1589{
1590	struct dce110_clk_src *clk_src =
1591		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1592
1593	if (!clk_src)
1594		return NULL;
1595
1596	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1597			regs, &cs_shift, &cs_mask)) {
1598		clk_src->base.dp_clk_src = dp_clk_src;
1599		return &clk_src->base;
1600	}
1601
1602	kfree(clk_src);
1603
1604	BREAK_TO_DEBUGGER();
1605	return NULL;
1606}
1607
1608static bool is_dual_plane(enum surface_pixel_format format)
1609{
1610	return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1611}
1612
1613static int dcn316_populate_dml_pipes_from_context(
1614	struct dc *dc, struct dc_state *context,
1615	display_e2e_pipe_params_st *pipes,
1616	enum dc_validate_mode validate_mode)
1617{
1618	int i, pipe_cnt;
1619	struct resource_context *res_ctx = &context->res_ctx;
1620	struct pipe_ctx *pipe = 0;
1621	const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;
1622
1623	DC_FP_START();
1624	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1625	DC_FP_END();
1626
1627	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1628		struct dc_crtc_timing *timing;
1629
1630		if (!res_ctx->pipe_ctx[i].stream)
1631			continue;
1632		pipe = &res_ctx->pipe_ctx[i];
1633		timing = &pipe->stream->timing;
1634
1635		/*
1636		 * Immediate flip can be set dynamically after enabling the plane.
1637		 * We need to require support for immediate flip or underflow can be
1638		 * intermittently experienced depending on peak b/w requirements.
1639		 */
1640		pipes[pipe_cnt].pipe.src.immediate_flip = true;
1641
1642		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1643		pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1644		pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1645		pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1646		DC_FP_START();
1647		dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1648		DC_FP_END();
1649
1650		if (pipes[pipe_cnt].dout.dsc_enable) {
1651			switch (timing->display_color_depth) {
1652			case COLOR_DEPTH_888:
1653				pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1654				break;
1655			case COLOR_DEPTH_101010:
1656				pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1657				break;
1658			case COLOR_DEPTH_121212:
1659				pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1660				break;
1661			default:
1662				ASSERT(0);
1663				break;
1664			}
1665		}
1666
1667		pipe_cnt++;
1668	}
1669
1670	if (pipe_cnt)
1671		context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1672				(max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1673	if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE)
1674		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE;
1675	ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE);
1676	dc->config.enable_4to1MPC = false;
1677	if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1678		if (is_dual_plane(pipe->plane_state->format)
1679				&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1680			dc->config.enable_4to1MPC = true;
1681			context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1682					(max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / 4) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1683		} else if (!is_dual_plane(pipe->plane_state->format)) {
1684			context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1685			pipes[0].pipe.src.unbounded_req_mode = true;
1686		}
1687	}
1688
1689	return pipe_cnt;
1690}
1691
1692static void dcn316_get_panel_config_defaults(struct dc_panel_config *panel_config)
1693{
1694	*panel_config = panel_config_defaults;
1695}
1696
1697static struct dc_cap_funcs cap_funcs = {
1698	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1699};
1700
1701static struct resource_funcs dcn316_res_pool_funcs = {
1702	.destroy = dcn316_destroy_resource_pool,
1703	.link_enc_create = dcn31_link_encoder_create,
1704	.link_enc_create_minimal = dcn31_link_enc_create_minimal,
1705	.link_encs_assign = link_enc_cfg_link_encs_assign,
1706	.link_enc_unassign = link_enc_cfg_link_enc_unassign,
1707	.panel_cntl_create = dcn31_panel_cntl_create,
1708	.validate_bandwidth = dcn31_validate_bandwidth,
1709	.calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1710	.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1711	.populate_dml_pipes = dcn316_populate_dml_pipes_from_context,
1712	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1713	.release_pipe = dcn20_release_pipe,
1714	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1715	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1716	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1717	.populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1718	.set_mcif_arb_params = dcn31_set_mcif_arb_params,
1719	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1720	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1721	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1722	.update_bw_bounding_box = dcn316_update_bw_bounding_box,
1723	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1724	.get_panel_config_defaults = dcn316_get_panel_config_defaults,
1725	.get_det_buffer_size = dcn31_get_det_buffer_size,
1726	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1727	.update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1728	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
1729};
1730
1731static bool dcn316_resource_construct(
1732	uint8_t num_virtual_links,
1733	struct dc *dc,
1734	struct dcn316_resource_pool *pool)
1735{
1736	int i;
1737	struct dc_context *ctx = dc->ctx;
1738	struct irq_service_init_data init_data;
1739
1740	ctx->dc_bios->regs = &bios_regs;
1741
1742	pool->base.res_cap = &res_cap_dcn31;
1743
1744	pool->base.funcs = &dcn316_res_pool_funcs;
1745
1746	/*************************************************
1747	 *  Resource + asic cap harcoding                *
1748	 *************************************************/
1749	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1750	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1751	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1752	dc->caps.max_downscale_ratio = 600;
1753	dc->caps.i2c_speed_in_khz = 100;
1754	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
1755	dc->caps.max_cursor_size = 256;
1756	dc->caps.min_horizontal_blanking_period = 80;
1757	dc->caps.dmdata_alloc_size = 2048;
1758	dc->caps.max_slave_planes = 2;
1759	dc->caps.max_slave_yuv_planes = 2;
1760	dc->caps.max_slave_rgb_planes = 2;
1761	dc->caps.post_blend_color_processing = true;
1762	dc->caps.force_dp_tps4_for_cp2520 = true;
1763	if (dc->config.forceHBR2CP2520)
1764		dc->caps.force_dp_tps4_for_cp2520 = false;
1765	dc->caps.dp_hpo = true;
1766	dc->caps.dp_hdmi21_pcon_support = true;
1767	dc->caps.edp_dsc_support = true;
1768	dc->caps.extended_aux_timeout_support = true;
1769	dc->caps.dmcub_support = true;
1770	dc->caps.is_apu = true;
1771
1772	/* Color pipeline capabilities */
1773	dc->caps.color.dpp.dcn_arch = 1;
1774	dc->caps.color.dpp.input_lut_shared = 0;
1775	dc->caps.color.dpp.icsc = 1;
1776	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1777	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1778	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1779	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1780	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1781	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1782	dc->caps.color.dpp.post_csc = 1;
1783	dc->caps.color.dpp.gamma_corr = 1;
1784	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1785
1786	dc->caps.color.dpp.hw_3d_lut = 1;
1787	dc->caps.color.dpp.ogam_ram = 1;
1788	// no OGAM ROM on DCN301
1789	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1790	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1791	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1792	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1793	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1794	dc->caps.color.dpp.ocsc = 0;
1795
1796	dc->caps.color.mpc.gamut_remap = 1;
1797	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1798	dc->caps.color.mpc.ogam_ram = 1;
1799	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1800	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1801	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1802	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1803	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1804	dc->caps.color.mpc.ocsc = 1;
1805
1806	/* read VBIOS LTTPR caps */
1807	{
1808		if (ctx->dc_bios->funcs->get_lttpr_caps) {
1809			enum bp_result bp_query_result;
1810			uint8_t is_vbios_lttpr_enable = 0;
1811
1812			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1813			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1814		}
1815
1816		/* interop bit is implicit */
1817		{
1818			dc->caps.vbios_lttpr_aware = true;
1819		}
1820	}
1821	dc->check_config = config_defaults;
1822
1823	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1824		dc->debug = debug_defaults_drv;
1825
1826	// Init the vm_helper
1827	if (dc->vm_helper)
1828		vm_helper_init(dc->vm_helper, 16);
1829
1830	/*************************************************
1831	 *  Create resources                             *
1832	 *************************************************/
1833
1834	/* Clock Sources for Pixel Clock*/
1835	pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1836			dcn31_clock_source_create(ctx, ctx->dc_bios,
1837				CLOCK_SOURCE_COMBO_PHY_PLL0,
1838				&clk_src_regs[0], false);
1839	pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1840			dcn31_clock_source_create(ctx, ctx->dc_bios,
1841				CLOCK_SOURCE_COMBO_PHY_PLL1,
1842				&clk_src_regs[1], false);
1843	pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1844			dcn31_clock_source_create(ctx, ctx->dc_bios,
1845				CLOCK_SOURCE_COMBO_PHY_PLL2,
1846				&clk_src_regs[2], false);
1847	pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1848			dcn31_clock_source_create(ctx, ctx->dc_bios,
1849				CLOCK_SOURCE_COMBO_PHY_PLL3,
1850				&clk_src_regs[3], false);
1851	pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1852			dcn31_clock_source_create(ctx, ctx->dc_bios,
1853				CLOCK_SOURCE_COMBO_PHY_PLL4,
1854				&clk_src_regs[4], false);
1855
1856	pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1857
1858	/* todo: not reuse phy_pll registers */
1859	pool->base.dp_clock_source =
1860			dcn31_clock_source_create(ctx, ctx->dc_bios,
1861				CLOCK_SOURCE_ID_DP_DTO,
1862				&clk_src_regs[0], true);
1863
1864	for (i = 0; i < pool->base.clk_src_count; i++) {
1865		if (pool->base.clock_sources[i] == NULL) {
1866			dm_error("DC: failed to create clock sources!\n");
1867			BREAK_TO_DEBUGGER();
1868			goto create_fail;
1869		}
1870	}
1871
1872	/* TODO: DCCG */
1873	pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1874	if (pool->base.dccg == NULL) {
1875		dm_error("DC: failed to create dccg!\n");
1876		BREAK_TO_DEBUGGER();
1877		goto create_fail;
1878	}
1879
1880	/* TODO: IRQ */
1881	init_data.ctx = dc->ctx;
1882	pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
1883	if (!pool->base.irqs)
1884		goto create_fail;
1885
1886	/* HUBBUB */
1887	pool->base.hubbub = dcn31_hubbub_create(ctx);
1888	if (pool->base.hubbub == NULL) {
1889		BREAK_TO_DEBUGGER();
1890		dm_error("DC: failed to create hubbub!\n");
1891		goto create_fail;
1892	}
1893
1894	/* HUBPs, DPPs, OPPs and TGs */
1895	for (i = 0; i < pool->base.pipe_count; i++) {
1896		pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
1897		if (pool->base.hubps[i] == NULL) {
1898			BREAK_TO_DEBUGGER();
1899			dm_error(
1900				"DC: failed to create hubps!\n");
1901			goto create_fail;
1902		}
1903
1904		pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
1905		if (pool->base.dpps[i] == NULL) {
1906			BREAK_TO_DEBUGGER();
1907			dm_error(
1908				"DC: failed to create dpps!\n");
1909			goto create_fail;
1910		}
1911	}
1912
1913	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1914		pool->base.opps[i] = dcn31_opp_create(ctx, i);
1915		if (pool->base.opps[i] == NULL) {
1916			BREAK_TO_DEBUGGER();
1917			dm_error(
1918				"DC: failed to create output pixel processor!\n");
1919			goto create_fail;
1920		}
1921	}
1922
1923	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1924		pool->base.timing_generators[i] = dcn31_timing_generator_create(
1925				ctx, i);
1926		if (pool->base.timing_generators[i] == NULL) {
1927			BREAK_TO_DEBUGGER();
1928			dm_error("DC: failed to create tg!\n");
1929			goto create_fail;
1930		}
1931	}
1932	pool->base.timing_generator_count = i;
1933
1934	/* PSR */
1935	pool->base.psr = dmub_psr_create(ctx);
1936	if (pool->base.psr == NULL) {
1937		dm_error("DC: failed to create psr obj!\n");
1938		BREAK_TO_DEBUGGER();
1939		goto create_fail;
1940	}
1941
1942	/* ABM */
1943	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1944		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1945				&abm_regs[i],
1946				&abm_shift,
1947				&abm_mask);
1948		if (pool->base.multiple_abms[i] == NULL) {
1949			dm_error("DC: failed to create abm for pipe %d!\n", i);
1950			BREAK_TO_DEBUGGER();
1951			goto create_fail;
1952		}
1953	}
1954
1955	/* MPC and DSC */
1956	pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1957	if (pool->base.mpc == NULL) {
1958		BREAK_TO_DEBUGGER();
1959		dm_error("DC: failed to create mpc!\n");
1960		goto create_fail;
1961	}
1962
1963	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1964		pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
1965		if (pool->base.dscs[i] == NULL) {
1966			BREAK_TO_DEBUGGER();
1967			dm_error("DC: failed to create display stream compressor %d!\n", i);
1968			goto create_fail;
1969		}
1970	}
1971
1972	/* DWB and MMHUBBUB */
1973	if (!dcn31_dwbc_create(ctx, &pool->base)) {
1974		BREAK_TO_DEBUGGER();
1975		dm_error("DC: failed to create dwbc!\n");
1976		goto create_fail;
1977	}
1978
1979	if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
1980		BREAK_TO_DEBUGGER();
1981		dm_error("DC: failed to create mcif_wb!\n");
1982		goto create_fail;
1983	}
1984
1985	/* AUX and I2C */
1986	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1987		pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
1988		if (pool->base.engines[i] == NULL) {
1989			BREAK_TO_DEBUGGER();
1990			dm_error(
1991				"DC:failed to create aux engine!!\n");
1992			goto create_fail;
1993		}
1994		pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
1995		if (pool->base.hw_i2cs[i] == NULL) {
1996			BREAK_TO_DEBUGGER();
1997			dm_error(
1998				"DC:failed to create hw i2c!!\n");
1999			goto create_fail;
2000		}
2001		pool->base.sw_i2cs[i] = NULL;
2002	}
2003
2004	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2005	if (!resource_construct(num_virtual_links, dc, &pool->base,
2006			&res_create_funcs))
2007		goto create_fail;
2008
2009	/* HW Sequencer and Plane caps */
2010	dcn31_hw_sequencer_construct(dc);
2011
2012	dc->caps.max_planes =  pool->base.pipe_count;
2013
2014	for (i = 0; i < dc->caps.max_planes; ++i)
2015		dc->caps.planes[i] = plane_cap;
2016
2017	dc->caps.max_odm_combine_factor = 4;
2018
2019	dc->cap_funcs = cap_funcs;
2020
2021	dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp;
2022
2023	return true;
2024
2025create_fail:
2026
2027	dcn316_resource_destruct(pool);
2028
2029	return false;
2030}
2031
2032struct resource_pool *dcn316_create_resource_pool(
2033		const struct dc_init_data *init_data,
2034		struct dc *dc)
2035{
2036	struct dcn316_resource_pool *pool =
2037		kzalloc(sizeof(struct dcn316_resource_pool), GFP_KERNEL);
2038
2039	if (!pool)
2040		return NULL;
2041
2042	if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool))
2043		return &pool->base;
2044
2045	BREAK_TO_DEBUGGER();
2046	kfree(pool);
2047	return NULL;
2048}