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dcn315_resource.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1/* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27#include "dm_services.h" 28#include "dc.h" 29 30#include "dcn31/dcn31_init.h" 31 32#include "resource.h" 33#include "include/irq_service_interface.h" 34#include "dcn315_resource.h" 35 36#include "dcn20/dcn20_resource.h" 37#include "dcn30/dcn30_resource.h" 38#include "dcn31/dcn31_resource.h" 39 40#include "dcn10/dcn10_ipp.h" 41#include "dcn30/dcn30_hubbub.h" 42#include "dcn31/dcn31_hubbub.h" 43#include "dcn30/dcn30_mpc.h" 44#include "dcn31/dcn31_hubp.h" 45#include "irq/dcn315/irq_service_dcn315.h" 46#include "dcn30/dcn30_dpp.h" 47#include "dcn31/dcn31_optc.h" 48#include "dcn20/dcn20_hwseq.h" 49#include "dcn30/dcn30_hwseq.h" 50#include "dce110/dce110_hwseq.h" 51#include "dcn30/dcn30_opp.h" 52#include "dcn20/dcn20_dsc.h" 53#include "dcn30/dcn30_vpg.h" 54#include "dcn30/dcn30_afmt.h" 55#include "dcn30/dcn30_dio_stream_encoder.h" 56#include "dcn31/dcn31_hpo_dp_stream_encoder.h" 57#include "dcn31/dcn31_hpo_dp_link_encoder.h" 58#include "dcn31/dcn31_apg.h" 59#include "dcn31/dcn31_dio_link_encoder.h" 60#include "dcn31/dcn31_vpg.h" 61#include "dcn31/dcn31_afmt.h" 62#include "dce/dce_clock_source.h" 63#include "dce/dce_audio.h" 64#include "dce/dce_hwseq.h" 65#include "clk_mgr.h" 66#include "virtual/virtual_stream_encoder.h" 67#include "dce110/dce110_resource.h" 68#include "dml/display_mode_vba.h" 69#include "dml/dcn31/dcn31_fpu.h" 70#include "dcn31/dcn31_dccg.h" 71#include "dcn10/dcn10_resource.h" 72#include "dcn31/dcn31_panel_cntl.h" 73 74#include "dcn30/dcn30_dwb.h" 75#include "dcn30/dcn30_mmhubbub.h" 76 77#include "dcn/dcn_3_1_5_offset.h" 78#include "dcn/dcn_3_1_5_sh_mask.h" 79#include "dpcs/dpcs_4_2_2_offset.h" 80#include "dpcs/dpcs_4_2_2_sh_mask.h" 81 82#define NBIO_BASE__INST0_SEG0 0x00000000 83#define NBIO_BASE__INST0_SEG1 0x00000014 84#define NBIO_BASE__INST0_SEG2 0x00000D20 85#define NBIO_BASE__INST0_SEG3 0x00010400 86#define NBIO_BASE__INST0_SEG4 0x0241B000 87#define NBIO_BASE__INST0_SEG5 0x04040000 88 89#define DPCS_BASE__INST0_SEG0 0x00000012 90#define DPCS_BASE__INST0_SEG1 0x000000C0 91#define DPCS_BASE__INST0_SEG2 0x000034C0 92#define DPCS_BASE__INST0_SEG3 0x00009000 93#define DPCS_BASE__INST0_SEG4 0x02403C00 94#define DPCS_BASE__INST0_SEG5 0 95 96#define DCN_BASE__INST0_SEG0 0x00000012 97#define DCN_BASE__INST0_SEG1 0x000000C0 98#define DCN_BASE__INST0_SEG2 0x000034C0 99#define DCN_BASE__INST0_SEG3 0x00009000 100#define DCN_BASE__INST0_SEG4 0x02403C00 101#define DCN_BASE__INST0_SEG5 0 102 103#define regBIF_BX_PF2_RSMU_INDEX 0x0000 104#define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1 105#define regBIF_BX_PF2_RSMU_DATA 0x0001 106#define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1 107#define regBIF_BX2_BIOS_SCRATCH_6 0x003e 108#define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 109#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 110#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL 111#define regBIF_BX2_BIOS_SCRATCH_2 0x003a 112#define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 113#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 114#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL 115#define regBIF_BX2_BIOS_SCRATCH_3 0x003b 116#define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 117#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 118#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL 119 120#define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 121#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 122#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 123#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 124 125#include "reg_helper.h" 126#include "dce/dmub_abm.h" 127#include "dce/dmub_psr.h" 128#include "dce/dmub_replay.h" 129#include "dce/dce_aux.h" 130#include "dce/dce_i2c.h" 131 132#include "dml/dcn30/display_mode_vba_30.h" 133#include "vm_helper.h" 134#include "dcn20/dcn20_vmid.h" 135 136#include "link_enc_cfg.h" 137 138#define DCN3_15_MAX_DET_SIZE 384 139#define DCN3_15_CRB_SEGMENT_SIZE_KB 64 140#define DCN3_15_MAX_DET_SEGS (DCN3_15_MAX_DET_SIZE / DCN3_15_CRB_SEGMENT_SIZE_KB) 141/* Minimum 3 extra segments need to be in compbuf and claimable to guarantee seamless mpo transitions */ 142#define MIN_RESERVED_DET_SEGS 3 143 144enum dcn31_clk_src_array_id { 145 DCN31_CLK_SRC_PLL0, 146 DCN31_CLK_SRC_PLL1, 147 DCN31_CLK_SRC_PLL2, 148 DCN31_CLK_SRC_PLL3, 149 DCN31_CLK_SRC_PLL4, 150 DCN30_CLK_SRC_TOTAL 151}; 152 153/* begin ********************* 154 * macros to expend register list macro defined in HW object header file 155 */ 156 157/* DCN */ 158#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 159 160#define BASE(seg) BASE_INNER(seg) 161 162#define SR(reg_name)\ 163 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 164 reg ## reg_name 165 166#define SRI(reg_name, block, id)\ 167 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 168 reg ## block ## id ## _ ## reg_name 169 170#define SRI2(reg_name, block, id)\ 171 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 172 reg ## reg_name 173 174#define SRIR(var_name, reg_name, block, id)\ 175 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 176 reg ## block ## id ## _ ## reg_name 177 178#define SRII(reg_name, block, id)\ 179 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 180 reg ## block ## id ## _ ## reg_name 181 182#define SRII_MPC_RMU(reg_name, block, id)\ 183 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 184 reg ## block ## id ## _ ## reg_name 185 186#define SRII_DWB(reg_name, temp_name, block, id)\ 187 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 188 reg ## block ## id ## _ ## temp_name 189 190#define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 191 .field_name = reg_name ## __ ## field_name ## post_fix 192 193#define DCCG_SRII(reg_name, block, id)\ 194 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 195 reg ## block ## id ## _ ## reg_name 196 197#define VUPDATE_SRII(reg_name, block, id)\ 198 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 199 reg ## reg_name ## _ ## block ## id 200 201/* NBIO */ 202#define NBIO_BASE_INNER(seg) \ 203 NBIO_BASE__INST0_SEG ## seg 204 205#define NBIO_BASE(seg) \ 206 NBIO_BASE_INNER(seg) 207 208#define NBIO_SR(reg_name)\ 209 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 210 regBIF_BX2_ ## reg_name 211 212static const struct bios_registers bios_regs = { 213 NBIO_SR(BIOS_SCRATCH_3), 214 NBIO_SR(BIOS_SCRATCH_6) 215}; 216 217#define clk_src_regs(index, pllid)\ 218[index] = {\ 219 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 220} 221 222static const struct dce110_clk_src_regs clk_src_regs[] = { 223 clk_src_regs(0, A), 224 clk_src_regs(1, B), 225 clk_src_regs(2, C), 226 clk_src_regs(3, D), 227 clk_src_regs(4, E) 228}; 229 230static const struct dce110_clk_src_shift cs_shift = { 231 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 232}; 233 234static const struct dce110_clk_src_mask cs_mask = { 235 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 236}; 237 238#define abm_regs(id)\ 239[id] = {\ 240 ABM_DCN302_REG_LIST(id)\ 241} 242 243static const struct dce_abm_registers abm_regs[] = { 244 abm_regs(0), 245 abm_regs(1), 246 abm_regs(2), 247 abm_regs(3), 248}; 249 250static const struct dce_abm_shift abm_shift = { 251 ABM_MASK_SH_LIST_DCN30(__SHIFT) 252}; 253 254static const struct dce_abm_mask abm_mask = { 255 ABM_MASK_SH_LIST_DCN30(_MASK) 256}; 257 258#define audio_regs(id)\ 259[id] = {\ 260 AUD_COMMON_REG_LIST(id)\ 261} 262 263static const struct dce_audio_registers audio_regs[] = { 264 audio_regs(0), 265 audio_regs(1), 266 audio_regs(2), 267 audio_regs(3), 268 audio_regs(4), 269 audio_regs(5), 270 audio_regs(6) 271}; 272 273#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 274 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 275 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 276 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 277 278static const struct dce_audio_shift audio_shift = { 279 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 280}; 281 282static const struct dce_audio_mask audio_mask = { 283 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 284}; 285 286#define vpg_regs(id)\ 287[id] = {\ 288 VPG_DCN31_REG_LIST(id)\ 289} 290 291static const struct dcn31_vpg_registers vpg_regs[] = { 292 vpg_regs(0), 293 vpg_regs(1), 294 vpg_regs(2), 295 vpg_regs(3), 296 vpg_regs(4), 297 vpg_regs(5), 298 vpg_regs(6), 299 vpg_regs(7), 300 vpg_regs(8), 301 vpg_regs(9), 302}; 303 304static const struct dcn31_vpg_shift vpg_shift = { 305 DCN31_VPG_MASK_SH_LIST(__SHIFT) 306}; 307 308static const struct dcn31_vpg_mask vpg_mask = { 309 DCN31_VPG_MASK_SH_LIST(_MASK) 310}; 311 312#define afmt_regs(id)\ 313[id] = {\ 314 AFMT_DCN31_REG_LIST(id)\ 315} 316 317static const struct dcn31_afmt_registers afmt_regs[] = { 318 afmt_regs(0), 319 afmt_regs(1), 320 afmt_regs(2), 321 afmt_regs(3), 322 afmt_regs(4), 323 afmt_regs(5) 324}; 325 326static const struct dcn31_afmt_shift afmt_shift = { 327 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 328}; 329 330static const struct dcn31_afmt_mask afmt_mask = { 331 DCN31_AFMT_MASK_SH_LIST(_MASK) 332}; 333 334#define apg_regs(id)\ 335[id] = {\ 336 APG_DCN31_REG_LIST(id)\ 337} 338 339static const struct dcn31_apg_registers apg_regs[] = { 340 apg_regs(0), 341 apg_regs(1), 342 apg_regs(2), 343 apg_regs(3) 344}; 345 346static const struct dcn31_apg_shift apg_shift = { 347 DCN31_APG_MASK_SH_LIST(__SHIFT) 348}; 349 350static const struct dcn31_apg_mask apg_mask = { 351 DCN31_APG_MASK_SH_LIST(_MASK) 352}; 353 354#define stream_enc_regs(id)\ 355[id] = {\ 356 SE_DCN3_REG_LIST(id)\ 357} 358 359static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 360 stream_enc_regs(0), 361 stream_enc_regs(1), 362 stream_enc_regs(2), 363 stream_enc_regs(3), 364 stream_enc_regs(4) 365}; 366 367static const struct dcn10_stream_encoder_shift se_shift = { 368 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 369}; 370 371static const struct dcn10_stream_encoder_mask se_mask = { 372 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 373}; 374 375 376#define aux_regs(id)\ 377[id] = {\ 378 DCN2_AUX_REG_LIST(id)\ 379} 380 381static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 382 aux_regs(0), 383 aux_regs(1), 384 aux_regs(2), 385 aux_regs(3), 386 aux_regs(4) 387}; 388 389#define hpd_regs(id)\ 390[id] = {\ 391 HPD_REG_LIST(id)\ 392} 393 394static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 395 hpd_regs(0), 396 hpd_regs(1), 397 hpd_regs(2), 398 hpd_regs(3), 399 hpd_regs(4) 400}; 401 402#define link_regs(id, phyid)\ 403[id] = {\ 404 LE_DCN31_REG_LIST(id), \ 405 UNIPHY_DCN2_REG_LIST(phyid), \ 406 DPCS_DCN31_REG_LIST(id), \ 407} 408 409static const struct dce110_aux_registers_shift aux_shift = { 410 DCN_AUX_MASK_SH_LIST(__SHIFT) 411}; 412 413static const struct dce110_aux_registers_mask aux_mask = { 414 DCN_AUX_MASK_SH_LIST(_MASK) 415}; 416 417static const struct dcn10_link_enc_registers link_enc_regs[] = { 418 link_regs(0, A), 419 link_regs(1, B), 420 link_regs(2, C), 421 link_regs(3, D), 422 link_regs(4, E) 423}; 424 425static const struct dcn10_link_enc_shift le_shift = { 426 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 427 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 428}; 429 430static const struct dcn10_link_enc_mask le_mask = { 431 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 432 DPCS_DCN31_MASK_SH_LIST(_MASK) 433}; 434 435#define hpo_dp_stream_encoder_reg_list(id)\ 436[id] = {\ 437 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 438} 439 440static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 441 hpo_dp_stream_encoder_reg_list(0), 442 hpo_dp_stream_encoder_reg_list(1), 443 hpo_dp_stream_encoder_reg_list(2), 444 hpo_dp_stream_encoder_reg_list(3), 445}; 446 447static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 448 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 449}; 450 451static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 452 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 453}; 454 455 456#define hpo_dp_link_encoder_reg_list(id)\ 457[id] = {\ 458 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 459 DCN3_1_RDPCSTX_REG_LIST(0),\ 460 DCN3_1_RDPCSTX_REG_LIST(1),\ 461 DCN3_1_RDPCSTX_REG_LIST(2),\ 462 DCN3_1_RDPCSTX_REG_LIST(3),\ 463 DCN3_1_RDPCSTX_REG_LIST(4)\ 464} 465 466static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 467 hpo_dp_link_encoder_reg_list(0), 468 hpo_dp_link_encoder_reg_list(1), 469}; 470 471static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 472 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 473}; 474 475static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 476 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 477}; 478 479#define dpp_regs(id)\ 480[id] = {\ 481 DPP_REG_LIST_DCN30(id),\ 482} 483 484static const struct dcn3_dpp_registers dpp_regs[] = { 485 dpp_regs(0), 486 dpp_regs(1), 487 dpp_regs(2), 488 dpp_regs(3) 489}; 490 491static const struct dcn3_dpp_shift tf_shift = { 492 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 493}; 494 495static const struct dcn3_dpp_mask tf_mask = { 496 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 497}; 498 499#define opp_regs(id)\ 500[id] = {\ 501 OPP_REG_LIST_DCN30(id),\ 502} 503 504static const struct dcn20_opp_registers opp_regs[] = { 505 opp_regs(0), 506 opp_regs(1), 507 opp_regs(2), 508 opp_regs(3) 509}; 510 511static const struct dcn20_opp_shift opp_shift = { 512 OPP_MASK_SH_LIST_DCN20(__SHIFT) 513}; 514 515static const struct dcn20_opp_mask opp_mask = { 516 OPP_MASK_SH_LIST_DCN20(_MASK) 517}; 518 519#define aux_engine_regs(id)\ 520[id] = {\ 521 AUX_COMMON_REG_LIST0(id), \ 522 .AUXN_IMPCAL = 0, \ 523 .AUXP_IMPCAL = 0, \ 524 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 525} 526 527static const struct dce110_aux_registers aux_engine_regs[] = { 528 aux_engine_regs(0), 529 aux_engine_regs(1), 530 aux_engine_regs(2), 531 aux_engine_regs(3), 532 aux_engine_regs(4) 533}; 534 535#define dwbc_regs_dcn3(id)\ 536[id] = {\ 537 DWBC_COMMON_REG_LIST_DCN30(id),\ 538} 539 540static const struct dcn30_dwbc_registers dwbc30_regs[] = { 541 dwbc_regs_dcn3(0), 542}; 543 544static const struct dcn30_dwbc_shift dwbc30_shift = { 545 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 546}; 547 548static const struct dcn30_dwbc_mask dwbc30_mask = { 549 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 550}; 551 552#define mcif_wb_regs_dcn3(id)\ 553[id] = {\ 554 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 555} 556 557static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 558 mcif_wb_regs_dcn3(0) 559}; 560 561static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 562 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 563}; 564 565static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 566 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 567}; 568 569#define dsc_regsDCN20(id)\ 570[id] = {\ 571 DSC_REG_LIST_DCN20(id)\ 572} 573 574static const struct dcn20_dsc_registers dsc_regs[] = { 575 dsc_regsDCN20(0), 576 dsc_regsDCN20(1), 577 dsc_regsDCN20(2) 578}; 579 580static const struct dcn20_dsc_shift dsc_shift = { 581 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 582}; 583 584static const struct dcn20_dsc_mask dsc_mask = { 585 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 586}; 587 588static const struct dcn30_mpc_registers mpc_regs = { 589 MPC_REG_LIST_DCN3_0(0), 590 MPC_REG_LIST_DCN3_0(1), 591 MPC_REG_LIST_DCN3_0(2), 592 MPC_REG_LIST_DCN3_0(3), 593 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 594 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 595 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 596 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 597 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 598}; 599 600static const struct dcn30_mpc_shift mpc_shift = { 601 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 602}; 603 604static const struct dcn30_mpc_mask mpc_mask = { 605 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 606}; 607 608#define optc_regs(id)\ 609[id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 610 611static const struct dcn_optc_registers optc_regs[] = { 612 optc_regs(0), 613 optc_regs(1), 614 optc_regs(2), 615 optc_regs(3) 616}; 617 618static const struct dcn_optc_shift optc_shift = { 619 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 620}; 621 622static const struct dcn_optc_mask optc_mask = { 623 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 624}; 625 626#define hubp_regs(id)\ 627[id] = {\ 628 HUBP_REG_LIST_DCN30(id)\ 629} 630 631static const struct dcn_hubp2_registers hubp_regs[] = { 632 hubp_regs(0), 633 hubp_regs(1), 634 hubp_regs(2), 635 hubp_regs(3) 636}; 637 638 639static const struct dcn_hubp2_shift hubp_shift = { 640 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 641}; 642 643static const struct dcn_hubp2_mask hubp_mask = { 644 HUBP_MASK_SH_LIST_DCN31(_MASK) 645}; 646static const struct dcn_hubbub_registers hubbub_reg = { 647 HUBBUB_REG_LIST_DCN31(0) 648}; 649 650static const struct dcn_hubbub_shift hubbub_shift = { 651 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 652}; 653 654static const struct dcn_hubbub_mask hubbub_mask = { 655 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 656}; 657 658static const struct dccg_registers dccg_regs = { 659 DCCG_REG_LIST_DCN31() 660}; 661 662static const struct dccg_shift dccg_shift = { 663 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 664}; 665 666static const struct dccg_mask dccg_mask = { 667 DCCG_MASK_SH_LIST_DCN31(_MASK) 668}; 669 670 671#define SRII2(reg_name_pre, reg_name_post, id)\ 672 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 673 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 674 reg ## reg_name_pre ## id ## _ ## reg_name_post 675 676 677#define HWSEQ_DCN31_REG_LIST()\ 678 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 679 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 680 SR(DIO_MEM_PWR_CTRL), \ 681 SR(ODM_MEM_PWR_CTRL3), \ 682 SR(DMU_MEM_PWR_CNTL), \ 683 SR(MMHUBBUB_MEM_PWR_CNTL), \ 684 SR(DCCG_GATE_DISABLE_CNTL), \ 685 SR(DCCG_GATE_DISABLE_CNTL2), \ 686 SR(DCFCLK_CNTL),\ 687 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 688 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 689 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 690 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 691 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 692 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 696 SR(MICROSECOND_TIME_BASE_DIV), \ 697 SR(MILLISECOND_TIME_BASE_DIV), \ 698 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 699 SR(RBBMIF_TIMEOUT_DIS), \ 700 SR(RBBMIF_TIMEOUT_DIS_2), \ 701 SR(DCHUBBUB_CRC_CTRL), \ 702 SR(DPP_TOP0_DPP_CRC_CTRL), \ 703 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 704 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 705 SR(MPC_CRC_CTRL), \ 706 SR(MPC_CRC_RESULT_GB), \ 707 SR(MPC_CRC_RESULT_C), \ 708 SR(MPC_CRC_RESULT_AR), \ 709 SR(DOMAIN0_PG_CONFIG), \ 710 SR(DOMAIN1_PG_CONFIG), \ 711 SR(DOMAIN2_PG_CONFIG), \ 712 SR(DOMAIN3_PG_CONFIG), \ 713 SR(DOMAIN16_PG_CONFIG), \ 714 SR(DOMAIN17_PG_CONFIG), \ 715 SR(DOMAIN18_PG_CONFIG), \ 716 SR(DOMAIN0_PG_STATUS), \ 717 SR(DOMAIN1_PG_STATUS), \ 718 SR(DOMAIN2_PG_STATUS), \ 719 SR(DOMAIN3_PG_STATUS), \ 720 SR(DOMAIN16_PG_STATUS), \ 721 SR(DOMAIN17_PG_STATUS), \ 722 SR(DOMAIN18_PG_STATUS), \ 723 SR(D1VGA_CONTROL), \ 724 SR(D2VGA_CONTROL), \ 725 SR(D3VGA_CONTROL), \ 726 SR(D4VGA_CONTROL), \ 727 SR(D5VGA_CONTROL), \ 728 SR(D6VGA_CONTROL), \ 729 SR(DC_IP_REQUEST_CNTL), \ 730 SR(AZALIA_AUDIO_DTO), \ 731 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 732 SR(HPO_TOP_HW_CONTROL) 733 734static const struct dce_hwseq_registers hwseq_reg = { 735 HWSEQ_DCN31_REG_LIST() 736}; 737 738#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 739 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 740 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 741 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 742 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 743 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 744 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 745 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 746 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 747 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 748 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 749 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 750 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 751 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 752 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 753 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 754 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 755 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 756 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 757 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 759 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 760 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 761 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 762 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 763 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 764 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 765 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 766 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 767 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 768 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 769 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 770 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 771 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 772 773static const struct dce_hwseq_shift hwseq_shift = { 774 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 775}; 776 777static const struct dce_hwseq_mask hwseq_mask = { 778 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 779}; 780#define vmid_regs(id)\ 781[id] = {\ 782 DCN20_VMID_REG_LIST(id)\ 783} 784 785static const struct dcn_vmid_registers vmid_regs[] = { 786 vmid_regs(0), 787 vmid_regs(1), 788 vmid_regs(2), 789 vmid_regs(3), 790 vmid_regs(4), 791 vmid_regs(5), 792 vmid_regs(6), 793 vmid_regs(7), 794 vmid_regs(8), 795 vmid_regs(9), 796 vmid_regs(10), 797 vmid_regs(11), 798 vmid_regs(12), 799 vmid_regs(13), 800 vmid_regs(14), 801 vmid_regs(15) 802}; 803 804static const struct dcn20_vmid_shift vmid_shifts = { 805 DCN20_VMID_MASK_SH_LIST(__SHIFT) 806}; 807 808static const struct dcn20_vmid_mask vmid_masks = { 809 DCN20_VMID_MASK_SH_LIST(_MASK) 810}; 811 812static const struct resource_caps res_cap_dcn31 = { 813 .num_timing_generator = 4, 814 .num_opp = 4, 815 .num_video_plane = 4, 816 .num_audio = 5, 817 .num_stream_encoder = 5, 818 .num_dig_link_enc = 5, 819 .num_hpo_dp_stream_encoder = 4, 820 .num_hpo_dp_link_encoder = 2, 821 .num_pll = 5, 822 .num_dwb = 1, 823 .num_ddc = 5, 824 .num_vmid = 16, 825 .num_mpc_3dlut = 2, 826 .num_dsc = 3, 827}; 828 829static const struct dc_plane_cap plane_cap = { 830 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 831 .per_pixel_alpha = true, 832 833 .pixel_format_support = { 834 .argb8888 = true, 835 .nv12 = true, 836 .fp16 = true, 837 .p010 = true, 838 .ayuv = false, 839 }, 840 841 .max_upscale_factor = { 842 .argb8888 = 16000, 843 .nv12 = 16000, 844 .fp16 = 16000 845 }, 846 847 // 6:1 downscaling ratio: 1000/6 = 166.666 848 .max_downscale_factor = { 849 .argb8888 = 167, 850 .nv12 = 167, 851 .fp16 = 167 852 }, 853 64, 854 64 855}; 856 857static const struct dc_debug_options debug_defaults_drv = { 858 .disable_z10 = true, /*hw not support it*/ 859 .disable_dmcu = true, 860 .force_abm_enable = false, 861 .clock_trace = true, 862 .disable_pplib_clock_request = false, 863 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 864 .force_single_disp_pipe_split = false, 865 .disable_dcc = DCC_ENABLE, 866 .vsr_support = true, 867 .performance_trace = false, 868 .max_downscale_src_width = 4096,/*upto true 4k*/ 869 .disable_pplib_wm_range = false, 870 .scl_reset_length10 = true, 871 .sanity_checks = false, 872 .underflow_assert_delay_us = 0xFFFFFFFF, 873 .dwb_fi_phase = -1, // -1 = disable, 874 .dmub_command_table = true, 875 .pstate_enabled = true, 876 .use_max_lb = true, 877 .enable_mem_low_power = { 878 .bits = { 879 .vga = true, 880 .i2c = true, 881 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 882 .dscl = true, 883 .cm = true, 884 .mpc = true, 885 .optc = true, 886 .vpg = true, 887 .afmt = true, 888 } 889 }, 890 .psr_power_use_phy_fsm = 0, 891 .using_dml2 = false, 892 .min_disp_clk_khz = 100000, 893}; 894 895static const struct dc_check_config config_defaults = { 896 .enable_legacy_fast_update = true, 897}; 898 899static const struct dc_panel_config panel_config_defaults = { 900 .psr = { 901 .disable_psr = false, 902 .disallow_psrsu = false, 903 .disallow_replay = false, 904 }, 905 .ilr = { 906 .optimize_edp_link_rate = true, 907 }, 908}; 909 910static void dcn31_dpp_destroy(struct dpp **dpp) 911{ 912 kfree(TO_DCN20_DPP(*dpp)); 913 *dpp = NULL; 914} 915 916static struct dpp *dcn31_dpp_create( 917 struct dc_context *ctx, 918 uint32_t inst) 919{ 920 struct dcn3_dpp *dpp = 921 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 922 923 if (!dpp) 924 return NULL; 925 926 if (dpp3_construct(dpp, ctx, inst, 927 &dpp_regs[inst], &tf_shift, &tf_mask)) 928 return &dpp->base; 929 930 BREAK_TO_DEBUGGER(); 931 kfree(dpp); 932 return NULL; 933} 934 935static struct output_pixel_processor *dcn31_opp_create( 936 struct dc_context *ctx, uint32_t inst) 937{ 938 struct dcn20_opp *opp = 939 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 940 941 if (!opp) { 942 BREAK_TO_DEBUGGER(); 943 return NULL; 944 } 945 946 dcn20_opp_construct(opp, ctx, inst, 947 &opp_regs[inst], &opp_shift, &opp_mask); 948 return &opp->base; 949} 950 951static struct dce_aux *dcn31_aux_engine_create( 952 struct dc_context *ctx, 953 uint32_t inst) 954{ 955 struct aux_engine_dce110 *aux_engine = 956 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 957 958 if (!aux_engine) 959 return NULL; 960 961 dce110_aux_engine_construct(aux_engine, ctx, inst, 962 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 963 &aux_engine_regs[inst], 964 &aux_mask, 965 &aux_shift, 966 ctx->dc->caps.extended_aux_timeout_support); 967 968 return &aux_engine->base; 969} 970#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 971 972static const struct dce_i2c_registers i2c_hw_regs[] = { 973 i2c_inst_regs(1), 974 i2c_inst_regs(2), 975 i2c_inst_regs(3), 976 i2c_inst_regs(4), 977 i2c_inst_regs(5), 978}; 979 980static const struct dce_i2c_shift i2c_shifts = { 981 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 982}; 983 984static const struct dce_i2c_mask i2c_masks = { 985 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 986}; 987 988static struct dce_i2c_hw *dcn31_i2c_hw_create( 989 struct dc_context *ctx, 990 uint32_t inst) 991{ 992 struct dce_i2c_hw *dce_i2c_hw = 993 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 994 995 if (!dce_i2c_hw) 996 return NULL; 997 998 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 999 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1000 1001 return dce_i2c_hw; 1002} 1003static struct mpc *dcn31_mpc_create( 1004 struct dc_context *ctx, 1005 int num_mpcc, 1006 int num_rmu) 1007{ 1008 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1009 GFP_KERNEL); 1010 1011 if (!mpc30) 1012 return NULL; 1013 1014 dcn30_mpc_construct(mpc30, ctx, 1015 &mpc_regs, 1016 &mpc_shift, 1017 &mpc_mask, 1018 num_mpcc, 1019 num_rmu); 1020 1021 return &mpc30->base; 1022} 1023 1024static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1025{ 1026 int i; 1027 1028 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1029 GFP_KERNEL); 1030 1031 if (!hubbub3) 1032 return NULL; 1033 1034 hubbub31_construct(hubbub3, ctx, 1035 &hubbub_reg, 1036 &hubbub_shift, 1037 &hubbub_mask, 1038 dcn3_15_ip.det_buffer_size_kbytes, 1039 dcn3_15_ip.pixel_chunk_size_kbytes, 1040 dcn3_15_ip.config_return_buffer_size_in_kbytes); 1041 1042 1043 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1044 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1045 1046 vmid->ctx = ctx; 1047 1048 vmid->regs = &vmid_regs[i]; 1049 vmid->shifts = &vmid_shifts; 1050 vmid->masks = &vmid_masks; 1051 } 1052 1053 return &hubbub3->base; 1054} 1055 1056static struct timing_generator *dcn31_timing_generator_create( 1057 struct dc_context *ctx, 1058 uint32_t instance) 1059{ 1060 struct optc *tgn10 = 1061 kzalloc(sizeof(struct optc), GFP_KERNEL); 1062 1063 if (!tgn10) 1064 return NULL; 1065 1066 tgn10->base.inst = instance; 1067 tgn10->base.ctx = ctx; 1068 1069 tgn10->tg_regs = &optc_regs[instance]; 1070 tgn10->tg_shift = &optc_shift; 1071 tgn10->tg_mask = &optc_mask; 1072 1073 dcn31_timing_generator_init(tgn10); 1074 1075 return &tgn10->base; 1076} 1077 1078static const struct encoder_feature_support link_enc_feature = { 1079 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1080 .max_hdmi_pixel_clock = 600000, 1081 .hdmi_ycbcr420_supported = true, 1082 .dp_ycbcr420_supported = true, 1083 .fec_supported = true, 1084 .flags.bits.IS_HBR2_CAPABLE = true, 1085 .flags.bits.IS_HBR3_CAPABLE = true, 1086 .flags.bits.IS_TPS3_CAPABLE = true, 1087 .flags.bits.IS_TPS4_CAPABLE = true 1088}; 1089 1090static struct link_encoder *dcn31_link_encoder_create( 1091 struct dc_context *ctx, 1092 const struct encoder_init_data *enc_init_data) 1093{ 1094 struct dcn20_link_encoder *enc20 = 1095 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1096 1097 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 1098 return NULL; 1099 1100 dcn31_link_encoder_construct(enc20, 1101 enc_init_data, 1102 &link_enc_feature, 1103 &link_enc_regs[enc_init_data->transmitter], 1104 &link_enc_aux_regs[enc_init_data->channel - 1], 1105 &link_enc_hpd_regs[enc_init_data->hpd_source], 1106 &le_shift, 1107 &le_mask); 1108 1109 return &enc20->enc10.base; 1110} 1111 1112/* Create a minimal link encoder object not associated with a particular 1113 * physical connector. 1114 * resource_funcs.link_enc_create_minimal 1115 */ 1116static struct link_encoder *dcn31_link_enc_create_minimal( 1117 struct dc_context *ctx, enum engine_id eng_id) 1118{ 1119 struct dcn20_link_encoder *enc20; 1120 1121 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1122 return NULL; 1123 1124 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1125 if (!enc20) 1126 return NULL; 1127 1128 dcn31_link_encoder_construct_minimal( 1129 enc20, 1130 ctx, 1131 &link_enc_feature, 1132 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1133 eng_id); 1134 1135 return &enc20->enc10.base; 1136} 1137 1138static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1139{ 1140 struct dcn31_panel_cntl *panel_cntl = 1141 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1142 1143 if (!panel_cntl) 1144 return NULL; 1145 1146 dcn31_panel_cntl_construct(panel_cntl, init_data); 1147 1148 return &panel_cntl->base; 1149} 1150 1151static void read_dce_straps( 1152 struct dc_context *ctx, 1153 struct resource_straps *straps) 1154{ 1155 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1156 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1157 1158} 1159 1160static struct audio *dcn31_create_audio( 1161 struct dc_context *ctx, unsigned int inst) 1162{ 1163 return dce_audio_create(ctx, inst, 1164 &audio_regs[inst], &audio_shift, &audio_mask); 1165} 1166 1167static struct vpg *dcn31_vpg_create( 1168 struct dc_context *ctx, 1169 uint32_t inst) 1170{ 1171 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1172 1173 if (!vpg31) 1174 return NULL; 1175 1176 vpg31_construct(vpg31, ctx, inst, 1177 &vpg_regs[inst], 1178 &vpg_shift, 1179 &vpg_mask); 1180 1181 return &vpg31->base; 1182} 1183 1184static struct afmt *dcn31_afmt_create( 1185 struct dc_context *ctx, 1186 uint32_t inst) 1187{ 1188 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1189 1190 if (!afmt31) 1191 return NULL; 1192 1193 afmt31_construct(afmt31, ctx, inst, 1194 &afmt_regs[inst], 1195 &afmt_shift, 1196 &afmt_mask); 1197 1198 // Light sleep by default, no need to power down here 1199 1200 return &afmt31->base; 1201} 1202 1203static struct apg *dcn31_apg_create( 1204 struct dc_context *ctx, 1205 uint32_t inst) 1206{ 1207 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1208 1209 if (!apg31) 1210 return NULL; 1211 1212 apg31_construct(apg31, ctx, inst, 1213 &apg_regs[inst], 1214 &apg_shift, 1215 &apg_mask); 1216 1217 return &apg31->base; 1218} 1219 1220static struct stream_encoder *dcn315_stream_encoder_create( 1221 enum engine_id eng_id, 1222 struct dc_context *ctx) 1223{ 1224 struct dcn10_stream_encoder *enc1; 1225 struct vpg *vpg; 1226 struct afmt *afmt; 1227 int vpg_inst; 1228 int afmt_inst; 1229 1230 /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/ 1231 1232 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1233 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) 1234 return NULL; 1235 1236 vpg_inst = eng_id; 1237 afmt_inst = eng_id; 1238 1239 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1240 vpg = dcn31_vpg_create(ctx, vpg_inst); 1241 afmt = dcn31_afmt_create(ctx, afmt_inst); 1242 1243 if (!enc1 || !vpg || !afmt) { 1244 kfree(enc1); 1245 kfree(vpg); 1246 kfree(afmt); 1247 return NULL; 1248 } 1249 1250 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1251 eng_id, vpg, afmt, 1252 &stream_enc_regs[eng_id], 1253 &se_shift, &se_mask); 1254 1255 return &enc1->base; 1256} 1257 1258static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1259 enum engine_id eng_id, 1260 struct dc_context *ctx) 1261{ 1262 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1263 struct vpg *vpg; 1264 struct apg *apg; 1265 uint32_t hpo_dp_inst; 1266 uint32_t vpg_inst; 1267 uint32_t apg_inst; 1268 1269 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1270 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1271 1272 /* Mapping of VPG register blocks to HPO DP block instance: 1273 * VPG[6] -> HPO_DP[0] 1274 * VPG[7] -> HPO_DP[1] 1275 * VPG[8] -> HPO_DP[2] 1276 * VPG[9] -> HPO_DP[3] 1277 */ 1278 vpg_inst = hpo_dp_inst + 6; 1279 1280 /* Mapping of APG register blocks to HPO DP block instance: 1281 * APG[0] -> HPO_DP[0] 1282 * APG[1] -> HPO_DP[1] 1283 * APG[2] -> HPO_DP[2] 1284 * APG[3] -> HPO_DP[3] 1285 */ 1286 apg_inst = hpo_dp_inst; 1287 1288 /* allocate HPO stream encoder and create VPG sub-block */ 1289 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1290 vpg = dcn31_vpg_create(ctx, vpg_inst); 1291 apg = dcn31_apg_create(ctx, apg_inst); 1292 1293 if (!hpo_dp_enc31 || !vpg || !apg) { 1294 kfree(hpo_dp_enc31); 1295 kfree(vpg); 1296 kfree(apg); 1297 return NULL; 1298 } 1299 1300 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1301 hpo_dp_inst, eng_id, vpg, apg, 1302 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1303 &hpo_dp_se_shift, &hpo_dp_se_mask); 1304 1305 return &hpo_dp_enc31->base; 1306} 1307 1308static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1309 uint8_t inst, 1310 struct dc_context *ctx) 1311{ 1312 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1313 1314 /* allocate HPO link encoder */ 1315 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1316 if (!hpo_dp_enc31) 1317 return NULL; /* out of memory */ 1318 1319 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1320 &hpo_dp_link_enc_regs[inst], 1321 &hpo_dp_le_shift, &hpo_dp_le_mask); 1322 1323 return &hpo_dp_enc31->base; 1324} 1325 1326static struct dce_hwseq *dcn31_hwseq_create( 1327 struct dc_context *ctx) 1328{ 1329 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1330 1331 if (hws) { 1332 hws->ctx = ctx; 1333 hws->regs = &hwseq_reg; 1334 hws->shifts = &hwseq_shift; 1335 hws->masks = &hwseq_mask; 1336 } 1337 return hws; 1338} 1339static const struct resource_create_funcs res_create_funcs = { 1340 .read_dce_straps = read_dce_straps, 1341 .create_audio = dcn31_create_audio, 1342 .create_stream_encoder = dcn315_stream_encoder_create, 1343 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1344 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1345 .create_hwseq = dcn31_hwseq_create, 1346}; 1347 1348static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) 1349{ 1350 unsigned int i; 1351 1352 for (i = 0; i < pool->base.stream_enc_count; i++) { 1353 if (pool->base.stream_enc[i] != NULL) { 1354 if (pool->base.stream_enc[i]->vpg != NULL) { 1355 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1356 pool->base.stream_enc[i]->vpg = NULL; 1357 } 1358 if (pool->base.stream_enc[i]->afmt != NULL) { 1359 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1360 pool->base.stream_enc[i]->afmt = NULL; 1361 } 1362 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1363 pool->base.stream_enc[i] = NULL; 1364 } 1365 } 1366 1367 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1368 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1369 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1370 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1371 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1372 } 1373 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1374 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1375 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1376 } 1377 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1378 pool->base.hpo_dp_stream_enc[i] = NULL; 1379 } 1380 } 1381 1382 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1383 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1384 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1385 pool->base.hpo_dp_link_enc[i] = NULL; 1386 } 1387 } 1388 1389 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1390 if (pool->base.dscs[i] != NULL) 1391 dcn20_dsc_destroy(&pool->base.dscs[i]); 1392 } 1393 1394 if (pool->base.mpc != NULL) { 1395 kfree(TO_DCN20_MPC(pool->base.mpc)); 1396 pool->base.mpc = NULL; 1397 } 1398 if (pool->base.hubbub != NULL) { 1399 kfree(pool->base.hubbub); 1400 pool->base.hubbub = NULL; 1401 } 1402 for (i = 0; i < pool->base.pipe_count; i++) { 1403 if (pool->base.dpps[i] != NULL) 1404 dcn31_dpp_destroy(&pool->base.dpps[i]); 1405 1406 if (pool->base.ipps[i] != NULL) 1407 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1408 1409 if (pool->base.hubps[i] != NULL) { 1410 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1411 pool->base.hubps[i] = NULL; 1412 } 1413 1414 if (pool->base.irqs != NULL) { 1415 dal_irq_service_destroy(&pool->base.irqs); 1416 } 1417 } 1418 1419 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1420 if (pool->base.engines[i] != NULL) 1421 dce110_engine_destroy(&pool->base.engines[i]); 1422 if (pool->base.hw_i2cs[i] != NULL) { 1423 kfree(pool->base.hw_i2cs[i]); 1424 pool->base.hw_i2cs[i] = NULL; 1425 } 1426 if (pool->base.sw_i2cs[i] != NULL) { 1427 kfree(pool->base.sw_i2cs[i]); 1428 pool->base.sw_i2cs[i] = NULL; 1429 } 1430 } 1431 1432 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1433 if (pool->base.opps[i] != NULL) 1434 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1435 } 1436 1437 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1438 if (pool->base.timing_generators[i] != NULL) { 1439 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1440 pool->base.timing_generators[i] = NULL; 1441 } 1442 } 1443 1444 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1445 if (pool->base.dwbc[i] != NULL) { 1446 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1447 pool->base.dwbc[i] = NULL; 1448 } 1449 if (pool->base.mcif_wb[i] != NULL) { 1450 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1451 pool->base.mcif_wb[i] = NULL; 1452 } 1453 } 1454 1455 for (i = 0; i < pool->base.audio_count; i++) { 1456 if (pool->base.audios[i]) 1457 dce_aud_destroy(&pool->base.audios[i]); 1458 } 1459 1460 for (i = 0; i < pool->base.clk_src_count; i++) { 1461 if (pool->base.clock_sources[i] != NULL) { 1462 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1463 pool->base.clock_sources[i] = NULL; 1464 } 1465 } 1466 1467 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1468 if (pool->base.mpc_lut[i] != NULL) { 1469 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1470 pool->base.mpc_lut[i] = NULL; 1471 } 1472 if (pool->base.mpc_shaper[i] != NULL) { 1473 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1474 pool->base.mpc_shaper[i] = NULL; 1475 } 1476 } 1477 1478 if (pool->base.dp_clock_source != NULL) { 1479 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1480 pool->base.dp_clock_source = NULL; 1481 } 1482 1483 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1484 if (pool->base.multiple_abms[i] != NULL) 1485 dce_abm_destroy(&pool->base.multiple_abms[i]); 1486 } 1487 1488 if (pool->base.psr != NULL) 1489 dmub_psr_destroy(&pool->base.psr); 1490 1491 if (pool->base.replay != NULL) 1492 dmub_replay_destroy(&pool->base.replay); 1493 1494 if (pool->base.dccg != NULL) 1495 dcn_dccg_destroy(&pool->base.dccg); 1496} 1497 1498static struct hubp *dcn31_hubp_create( 1499 struct dc_context *ctx, 1500 uint32_t inst) 1501{ 1502 struct dcn20_hubp *hubp2 = 1503 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1504 1505 if (!hubp2) 1506 return NULL; 1507 1508 if (hubp31_construct(hubp2, ctx, inst, 1509 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1510 return &hubp2->base; 1511 1512 BREAK_TO_DEBUGGER(); 1513 kfree(hubp2); 1514 return NULL; 1515} 1516 1517static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1518{ 1519 int i; 1520 uint32_t pipe_count = pool->res_cap->num_dwb; 1521 1522 for (i = 0; i < pipe_count; i++) { 1523 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1524 GFP_KERNEL); 1525 1526 if (!dwbc30) { 1527 dm_error("DC: failed to create dwbc30!\n"); 1528 return false; 1529 } 1530 1531 dcn30_dwbc_construct(dwbc30, ctx, 1532 &dwbc30_regs[i], 1533 &dwbc30_shift, 1534 &dwbc30_mask, 1535 i); 1536 1537 pool->dwbc[i] = &dwbc30->base; 1538 } 1539 return true; 1540} 1541 1542static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1543{ 1544 int i; 1545 uint32_t pipe_count = pool->res_cap->num_dwb; 1546 1547 for (i = 0; i < pipe_count; i++) { 1548 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1549 GFP_KERNEL); 1550 1551 if (!mcif_wb30) { 1552 dm_error("DC: failed to create mcif_wb30!\n"); 1553 return false; 1554 } 1555 1556 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1557 &mcif_wb30_regs[i], 1558 &mcif_wb30_shift, 1559 &mcif_wb30_mask, 1560 i); 1561 1562 pool->mcif_wb[i] = &mcif_wb30->base; 1563 } 1564 return true; 1565} 1566 1567static struct display_stream_compressor *dcn31_dsc_create( 1568 struct dc_context *ctx, uint32_t inst) 1569{ 1570 struct dcn20_dsc *dsc = 1571 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1572 1573 if (!dsc) { 1574 BREAK_TO_DEBUGGER(); 1575 return NULL; 1576 } 1577 1578 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1579 return &dsc->base; 1580} 1581 1582static void dcn315_destroy_resource_pool(struct resource_pool **pool) 1583{ 1584 struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool); 1585 1586 dcn315_resource_destruct(dcn31_pool); 1587 kfree(dcn31_pool); 1588 *pool = NULL; 1589} 1590 1591static struct clock_source *dcn31_clock_source_create( 1592 struct dc_context *ctx, 1593 struct dc_bios *bios, 1594 enum clock_source_id id, 1595 const struct dce110_clk_src_regs *regs, 1596 bool dp_clk_src) 1597{ 1598 struct dce110_clk_src *clk_src = 1599 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1600 1601 if (!clk_src) 1602 return NULL; 1603 1604 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1605 regs, &cs_shift, &cs_mask)) { 1606 clk_src->base.dp_clk_src = dp_clk_src; 1607 return &clk_src->base; 1608 } 1609 1610 kfree(clk_src); 1611 BREAK_TO_DEBUGGER(); 1612 return NULL; 1613} 1614 1615static bool is_dual_plane(enum surface_pixel_format format) 1616{ 1617 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1618} 1619 1620static int source_format_to_bpp (enum source_format_class SourcePixelFormat) 1621{ 1622 if (SourcePixelFormat == dm_444_64) 1623 return 8; 1624 else if (SourcePixelFormat == dm_444_16) 1625 return 2; 1626 else if (SourcePixelFormat == dm_444_8) 1627 return 1; 1628 else if (SourcePixelFormat == dm_rgbe_alpha) 1629 return 5; 1630 else if (SourcePixelFormat == dm_420_8) 1631 return 3; 1632 else if (SourcePixelFormat == dm_420_12) 1633 return 6; 1634 else 1635 return 4; 1636} 1637 1638static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context) 1639{ 1640 int i; 1641 struct resource_context *res_ctx = &context->res_ctx; 1642 1643 /* Only apply for dual stream scenarios with edp*/ 1644 if (context->stream_count != 2) 1645 return false; 1646 if (context->streams[0]->signal != SIGNAL_TYPE_EDP && context->streams[1]->signal != SIGNAL_TYPE_EDP) 1647 return false; 1648 1649 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1650 if (!res_ctx->pipe_ctx[i].stream) 1651 continue; 1652 1653 /*Don't apply if scaling*/ 1654 if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width || 1655 res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height || 1656 (res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width 1657 != res_ctx->pipe_ctx[i].plane_state->dst_rect.width || 1658 res_ctx->pipe_ctx[i].plane_state->src_rect.height 1659 != res_ctx->pipe_ctx[i].plane_state->dst_rect.height))) 1660 return false; 1661 /*Don't apply if MPO to avoid transition issues*/ 1662 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state) 1663 return false; 1664 } 1665 return true; 1666} 1667 1668static int dcn315_populate_dml_pipes_from_context( 1669 struct dc *dc, struct dc_state *context, 1670 display_e2e_pipe_params_st *pipes, 1671 enum dc_validate_mode validate_mode) 1672{ 1673 int i, pipe_cnt, crb_idx, crb_pipes; 1674 struct resource_context *res_ctx = &context->res_ctx; 1675 struct pipe_ctx *pipe = NULL; 1676 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB; 1677 int remaining_det_segs = max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB; 1678 bool pixel_rate_crb = allow_pixel_rate_crb(dc, context); 1679 1680 DC_FP_START(); 1681 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); 1682 DC_FP_END(); 1683 1684 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) { 1685 struct dc_crtc_timing *timing; 1686 1687 if (!res_ctx->pipe_ctx[i].stream) 1688 continue; 1689 pipe = &res_ctx->pipe_ctx[i]; 1690 timing = &pipe->stream->timing; 1691 1692 /* 1693 * Immediate flip can be set dynamically after enabling the plane. 1694 * We need to require support for immediate flip or underflow can be 1695 * intermittently experienced depending on peak b/w requirements. 1696 */ 1697 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1698 1699 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1700 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1701 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1702 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1703 DC_FP_START(); 1704 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1705 if (pixel_rate_crb) { 1706 int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format); 1707 /* Ceil to crb segment size */ 1708 int approx_det_segs_required_for_pstate = dcn_get_approx_det_segs_required_for_pstate( 1709 &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB); 1710 1711 if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) { 1712 bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS; 1713 split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); 1714 split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); 1715 1716 /* Minimum 2 segments to allow mpc/odm combine if its used later */ 1717 if (approx_det_segs_required_for_pstate < 2) 1718 approx_det_segs_required_for_pstate = 2; 1719 if (split_required) 1720 approx_det_segs_required_for_pstate += approx_det_segs_required_for_pstate % 2; 1721 pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate; 1722 remaining_det_segs -= approx_det_segs_required_for_pstate; 1723 } else 1724 remaining_det_segs = -1; 1725 crb_pipes++; 1726 } 1727 DC_FP_END(); 1728 1729 if (pipes[pipe_cnt].dout.dsc_enable) { 1730 switch (timing->display_color_depth) { 1731 case COLOR_DEPTH_888: 1732 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1733 break; 1734 case COLOR_DEPTH_101010: 1735 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1736 break; 1737 case COLOR_DEPTH_121212: 1738 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1739 break; 1740 default: 1741 ASSERT(0); 1742 break; 1743 } 1744 } 1745 pipe_cnt++; 1746 } 1747 1748 /* Spread remaining unreserved crb evenly among all pipes*/ 1749 if (pixel_rate_crb) { 1750 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) { 1751 pipe = &res_ctx->pipe_ctx[i]; 1752 if (!pipe->stream) 1753 continue; 1754 1755 /* Do not use asymetric crb if not enough for pstate support */ 1756 if (remaining_det_segs < 0) { 1757 pipes[pipe_cnt].pipe.src.det_size_override = 0; 1758 pipe_cnt++; 1759 continue; 1760 } 1761 1762 bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) 1763 || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); 1764 1765 if (remaining_det_segs > MIN_RESERVED_DET_SEGS && crb_pipes != 0) 1766 pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes + 1767 (crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0); 1768 if (pipes[pipe_cnt].pipe.src.det_size_override > 2 * DCN3_15_MAX_DET_SEGS) { 1769 /* Clamp to 2 pipe split max det segments */ 1770 remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS); 1771 pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS; 1772 } 1773 if (pipes[pipe_cnt].pipe.src.det_size_override > DCN3_15_MAX_DET_SEGS || split_required) { 1774 /* If we are splitting we must have an even number of segments */ 1775 remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2; 1776 pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2; 1777 } 1778 /* Convert segments into size for DML use */ 1779 pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB; 1780 1781 crb_idx++; 1782 pipe_cnt++; 1783 } 1784 } 1785 1786 if (pipe_cnt) 1787 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1788 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1789 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) 1790 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; 1791 1792 dc->config.enable_4to1MPC = false; 1793 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1794 if (is_dual_plane(pipe->plane_state->format) 1795 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1796 dc->config.enable_4to1MPC = true; 1797 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1798 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1799 } else if (!is_dual_plane(pipe->plane_state->format) 1800 && pipe->plane_state->src_rect.width <= 5120 1801 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { 1802 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1803 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1804 pipes[0].pipe.src.unbounded_req_mode = true; 1805 } 1806 } 1807 1808 return pipe_cnt; 1809} 1810 1811static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config) 1812{ 1813 *panel_config = panel_config_defaults; 1814} 1815 1816static int dcn315_get_power_profile(const struct dc_state *context) 1817{ 1818 return !context->bw_ctx.bw.dcn.clk.p_state_change_support; 1819} 1820 1821static struct dc_cap_funcs cap_funcs = { 1822 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1823}; 1824 1825static struct resource_funcs dcn315_res_pool_funcs = { 1826 .destroy = dcn315_destroy_resource_pool, 1827 .link_enc_create = dcn31_link_encoder_create, 1828 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1829 .link_encs_assign = link_enc_cfg_link_encs_assign, 1830 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1831 .panel_cntl_create = dcn31_panel_cntl_create, 1832 .validate_bandwidth = dcn31_validate_bandwidth, 1833 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1834 .update_soc_for_wm_a = dcn315_update_soc_for_wm_a, 1835 .populate_dml_pipes = dcn315_populate_dml_pipes_from_context, 1836 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 1837 .release_pipe = dcn20_release_pipe, 1838 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1839 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1840 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1841 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, 1842 .set_mcif_arb_params = dcn31_set_mcif_arb_params, 1843 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1844 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1845 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1846 .update_bw_bounding_box = dcn315_update_bw_bounding_box, 1847 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1848 .get_panel_config_defaults = dcn315_get_panel_config_defaults, 1849 .get_power_profile = dcn315_get_power_profile, 1850 .get_det_buffer_size = dcn31_get_det_buffer_size, 1851 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, 1852 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, 1853 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params 1854}; 1855 1856static bool dcn315_resource_construct( 1857 uint8_t num_virtual_links, 1858 struct dc *dc, 1859 struct dcn315_resource_pool *pool) 1860{ 1861 int i; 1862 struct dc_context *ctx = dc->ctx; 1863 struct irq_service_init_data init_data; 1864 1865 ctx->dc_bios->regs = &bios_regs; 1866 1867 pool->base.res_cap = &res_cap_dcn31; 1868 1869 pool->base.funcs = &dcn315_res_pool_funcs; 1870 1871 /************************************************* 1872 * Resource + asic cap harcoding * 1873 *************************************************/ 1874 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1875 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1876 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1877 dc->caps.max_downscale_ratio = 600; 1878 dc->caps.i2c_speed_in_khz = 100; 1879 dc->caps.i2c_speed_in_khz_hdcp = 100; 1880 dc->caps.max_cursor_size = 256; 1881 dc->caps.min_horizontal_blanking_period = 80; 1882 dc->caps.dmdata_alloc_size = 2048; 1883 dc->caps.max_slave_planes = 2; 1884 dc->caps.max_slave_yuv_planes = 2; 1885 dc->caps.max_slave_rgb_planes = 2; 1886 dc->caps.post_blend_color_processing = true; 1887 dc->caps.force_dp_tps4_for_cp2520 = true; 1888 if (dc->config.forceHBR2CP2520) 1889 dc->caps.force_dp_tps4_for_cp2520 = false; 1890 dc->caps.dp_hpo = true; 1891 dc->caps.dp_hdmi21_pcon_support = true; 1892 dc->caps.edp_dsc_support = true; 1893 dc->caps.extended_aux_timeout_support = true; 1894 dc->caps.dmcub_support = true; 1895 dc->caps.is_apu = true; 1896 1897 /* Color pipeline capabilities */ 1898 dc->caps.color.dpp.dcn_arch = 1; 1899 dc->caps.color.dpp.input_lut_shared = 0; 1900 dc->caps.color.dpp.icsc = 1; 1901 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1902 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1903 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1904 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1905 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1906 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1907 dc->caps.color.dpp.post_csc = 1; 1908 dc->caps.color.dpp.gamma_corr = 1; 1909 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1910 1911 dc->caps.color.dpp.hw_3d_lut = 1; 1912 dc->caps.color.dpp.ogam_ram = 1; 1913 // no OGAM ROM on DCN301 1914 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1915 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1916 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1917 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1918 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1919 dc->caps.color.dpp.ocsc = 0; 1920 1921 dc->caps.color.mpc.gamut_remap = 1; 1922 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1923 dc->caps.color.mpc.ogam_ram = 1; 1924 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1925 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1926 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1927 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1928 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1929 dc->caps.color.mpc.ocsc = 1; 1930 1931 /* read VBIOS LTTPR caps */ 1932 { 1933 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1934 enum bp_result bp_query_result; 1935 uint8_t is_vbios_lttpr_enable = 0; 1936 1937 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1938 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1939 } 1940 1941 /* interop bit is implicit */ 1942 { 1943 dc->caps.vbios_lttpr_aware = true; 1944 } 1945 } 1946 dc->check_config = config_defaults; 1947 1948 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1949 dc->debug = debug_defaults_drv; 1950 1951 // Init the vm_helper 1952 if (dc->vm_helper) 1953 vm_helper_init(dc->vm_helper, 16); 1954 1955 /************************************************* 1956 * Create resources * 1957 *************************************************/ 1958 1959 /* Clock Sources for Pixel Clock*/ 1960 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1961 dcn31_clock_source_create(ctx, ctx->dc_bios, 1962 CLOCK_SOURCE_COMBO_PHY_PLL0, 1963 &clk_src_regs[0], false); 1964 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1965 dcn31_clock_source_create(ctx, ctx->dc_bios, 1966 CLOCK_SOURCE_COMBO_PHY_PLL1, 1967 &clk_src_regs[1], false); 1968 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1969 dcn31_clock_source_create(ctx, ctx->dc_bios, 1970 CLOCK_SOURCE_COMBO_PHY_PLL2, 1971 &clk_src_regs[2], false); 1972 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1973 dcn31_clock_source_create(ctx, ctx->dc_bios, 1974 CLOCK_SOURCE_COMBO_PHY_PLL3, 1975 &clk_src_regs[3], false); 1976 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1977 dcn31_clock_source_create(ctx, ctx->dc_bios, 1978 CLOCK_SOURCE_COMBO_PHY_PLL4, 1979 &clk_src_regs[4], false); 1980 1981 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1982 1983 /* todo: not reuse phy_pll registers */ 1984 pool->base.dp_clock_source = 1985 dcn31_clock_source_create(ctx, ctx->dc_bios, 1986 CLOCK_SOURCE_ID_DP_DTO, 1987 &clk_src_regs[0], true); 1988 1989 for (i = 0; i < pool->base.clk_src_count; i++) { 1990 if (pool->base.clock_sources[i] == NULL) { 1991 dm_error("DC: failed to create clock sources!\n"); 1992 BREAK_TO_DEBUGGER(); 1993 goto create_fail; 1994 } 1995 } 1996 1997 /* TODO: DCCG */ 1998 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1999 if (pool->base.dccg == NULL) { 2000 dm_error("DC: failed to create dccg!\n"); 2001 BREAK_TO_DEBUGGER(); 2002 goto create_fail; 2003 } 2004 2005 /* TODO: IRQ */ 2006 init_data.ctx = dc->ctx; 2007 pool->base.irqs = dal_irq_service_dcn315_create(&init_data); 2008 if (!pool->base.irqs) 2009 goto create_fail; 2010 2011 /* HUBBUB */ 2012 pool->base.hubbub = dcn31_hubbub_create(ctx); 2013 if (pool->base.hubbub == NULL) { 2014 BREAK_TO_DEBUGGER(); 2015 dm_error("DC: failed to create hubbub!\n"); 2016 goto create_fail; 2017 } 2018 2019 /* HUBPs, DPPs, OPPs and TGs */ 2020 for (i = 0; i < pool->base.pipe_count; i++) { 2021 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2022 if (pool->base.hubps[i] == NULL) { 2023 BREAK_TO_DEBUGGER(); 2024 dm_error( 2025 "DC: failed to create hubps!\n"); 2026 goto create_fail; 2027 } 2028 2029 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2030 if (pool->base.dpps[i] == NULL) { 2031 BREAK_TO_DEBUGGER(); 2032 dm_error( 2033 "DC: failed to create dpps!\n"); 2034 goto create_fail; 2035 } 2036 } 2037 2038 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2039 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2040 if (pool->base.opps[i] == NULL) { 2041 BREAK_TO_DEBUGGER(); 2042 dm_error( 2043 "DC: failed to create output pixel processor!\n"); 2044 goto create_fail; 2045 } 2046 } 2047 2048 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2049 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2050 ctx, i); 2051 if (pool->base.timing_generators[i] == NULL) { 2052 BREAK_TO_DEBUGGER(); 2053 dm_error("DC: failed to create tg!\n"); 2054 goto create_fail; 2055 } 2056 } 2057 pool->base.timing_generator_count = i; 2058 2059 /* PSR */ 2060 pool->base.psr = dmub_psr_create(ctx); 2061 if (pool->base.psr == NULL) { 2062 dm_error("DC: failed to create psr obj!\n"); 2063 BREAK_TO_DEBUGGER(); 2064 goto create_fail; 2065 } 2066 2067 /* Replay */ 2068 pool->base.replay = dmub_replay_create(ctx); 2069 if (pool->base.replay == NULL) { 2070 dm_error("DC: failed to create replay obj!\n"); 2071 BREAK_TO_DEBUGGER(); 2072 goto create_fail; 2073 } 2074 2075 /* ABM */ 2076 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2077 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2078 &abm_regs[i], 2079 &abm_shift, 2080 &abm_mask); 2081 if (pool->base.multiple_abms[i] == NULL) { 2082 dm_error("DC: failed to create abm for pipe %d!\n", i); 2083 BREAK_TO_DEBUGGER(); 2084 goto create_fail; 2085 } 2086 } 2087 2088 /* MPC and DSC */ 2089 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2090 if (pool->base.mpc == NULL) { 2091 BREAK_TO_DEBUGGER(); 2092 dm_error("DC: failed to create mpc!\n"); 2093 goto create_fail; 2094 } 2095 2096 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2097 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2098 if (pool->base.dscs[i] == NULL) { 2099 BREAK_TO_DEBUGGER(); 2100 dm_error("DC: failed to create display stream compressor %d!\n", i); 2101 goto create_fail; 2102 } 2103 } 2104 2105 /* DWB and MMHUBBUB */ 2106 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2107 BREAK_TO_DEBUGGER(); 2108 dm_error("DC: failed to create dwbc!\n"); 2109 goto create_fail; 2110 } 2111 2112 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2113 BREAK_TO_DEBUGGER(); 2114 dm_error("DC: failed to create mcif_wb!\n"); 2115 goto create_fail; 2116 } 2117 2118 /* AUX and I2C */ 2119 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2120 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2121 if (pool->base.engines[i] == NULL) { 2122 BREAK_TO_DEBUGGER(); 2123 dm_error( 2124 "DC:failed to create aux engine!!\n"); 2125 goto create_fail; 2126 } 2127 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2128 if (pool->base.hw_i2cs[i] == NULL) { 2129 BREAK_TO_DEBUGGER(); 2130 dm_error( 2131 "DC:failed to create hw i2c!!\n"); 2132 goto create_fail; 2133 } 2134 pool->base.sw_i2cs[i] = NULL; 2135 } 2136 2137 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2138 if (!resource_construct(num_virtual_links, dc, &pool->base, 2139 &res_create_funcs)) 2140 goto create_fail; 2141 2142 /* HW Sequencer and Plane caps */ 2143 dcn31_hw_sequencer_construct(dc); 2144 2145 dc->caps.max_planes = pool->base.pipe_count; 2146 2147 for (i = 0; i < dc->caps.max_planes; ++i) 2148 dc->caps.planes[i] = plane_cap; 2149 2150 dc->caps.max_odm_combine_factor = 4; 2151 2152 dc->cap_funcs = cap_funcs; 2153 2154 dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp; 2155 2156 return true; 2157 2158create_fail: 2159 2160 dcn315_resource_destruct(pool); 2161 2162 return false; 2163} 2164 2165struct resource_pool *dcn315_create_resource_pool( 2166 const struct dc_init_data *init_data, 2167 struct dc *dc) 2168{ 2169 struct dcn315_resource_pool *pool = 2170 kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL); 2171 2172 if (!pool) 2173 return NULL; 2174 2175 if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool)) 2176 return &pool->base; 2177 2178 BREAK_TO_DEBUGGER(); 2179 kfree(pool); 2180 return NULL; 2181}
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