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dcn314_resource.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1// SPDX-License-Identifier: MIT 2/* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28#include "dm_services.h" 29#include "dc.h" 30 31#include "dcn31/dcn31_init.h" 32#include "dcn314/dcn314_init.h" 33 34#include "resource.h" 35#include "include/irq_service_interface.h" 36#include "dcn314_resource.h" 37 38#include "dcn20/dcn20_resource.h" 39#include "dcn30/dcn30_resource.h" 40#include "dcn31/dcn31_resource.h" 41 42#include "dcn10/dcn10_ipp.h" 43#include "dcn30/dcn30_hubbub.h" 44#include "dcn31/dcn31_hubbub.h" 45#include "dcn30/dcn30_mpc.h" 46#include "dcn31/dcn31_hubp.h" 47#include "irq/dcn31/irq_service_dcn31.h" 48#include "irq/dcn314/irq_service_dcn314.h" 49#include "dcn30/dcn30_dpp.h" 50#include "dcn314/dcn314_optc.h" 51#include "dcn20/dcn20_hwseq.h" 52#include "dcn30/dcn30_hwseq.h" 53#include "dce110/dce110_hwseq.h" 54#include "dcn30/dcn30_opp.h" 55#include "dcn20/dcn20_dsc.h" 56#include "dcn30/dcn30_vpg.h" 57#include "dcn30/dcn30_afmt.h" 58#include "dcn31/dcn31_dio_link_encoder.h" 59#include "dcn314/dcn314_dio_stream_encoder.h" 60#include "dcn31/dcn31_hpo_dp_stream_encoder.h" 61#include "dcn31/dcn31_hpo_dp_link_encoder.h" 62#include "dcn31/dcn31_apg.h" 63#include "dcn31/dcn31_vpg.h" 64#include "dcn31/dcn31_afmt.h" 65#include "dce/dce_clock_source.h" 66#include "dce/dce_audio.h" 67#include "dce/dce_hwseq.h" 68#include "clk_mgr.h" 69#include "virtual/virtual_stream_encoder.h" 70#include "dce110/dce110_resource.h" 71#include "dml/display_mode_vba.h" 72#include "dml/dcn31/dcn31_fpu.h" 73#include "dml/dcn314/dcn314_fpu.h" 74#include "dcn314/dcn314_dccg.h" 75#include "dcn10/dcn10_resource.h" 76#include "dcn31/dcn31_panel_cntl.h" 77#include "dcn314/dcn314_hwseq.h" 78 79#include "dcn30/dcn30_dwb.h" 80#include "dcn30/dcn30_mmhubbub.h" 81 82#include "dcn/dcn_3_1_4_offset.h" 83#include "dcn/dcn_3_1_4_sh_mask.h" 84#include "dpcs/dpcs_3_1_4_offset.h" 85#include "dpcs/dpcs_3_1_4_sh_mask.h" 86 87#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 88#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 89 90#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 91#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL 92 93#include "reg_helper.h" 94#include "dce/dmub_abm.h" 95#include "dce/dmub_psr.h" 96#include "dce/dmub_replay.h" 97#include "dce/dce_aux.h" 98#include "dce/dce_i2c.h" 99#include "dml/dcn314/display_mode_vba_314.h" 100#include "vm_helper.h" 101#include "dcn20/dcn20_vmid.h" 102 103#include "link_enc_cfg.h" 104 105#define DCN_BASE__INST0_SEG1 0x000000C0 106#define DCN_BASE__INST0_SEG2 0x000034C0 107#define DCN_BASE__INST0_SEG3 0x00009000 108 109#define NBIO_BASE__INST0_SEG1 0x00000014 110 111#define MAX_INSTANCE 7 112#define MAX_SEGMENT 8 113 114#define regBIF_BX2_BIOS_SCRATCH_2 0x003a 115#define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 116#define regBIF_BX2_BIOS_SCRATCH_3 0x003b 117#define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 118#define regBIF_BX2_BIOS_SCRATCH_6 0x003e 119#define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 120 121#define DC_LOGGER \ 122 dc->ctx->logger 123#define DC_LOGGER_INIT(logger) 124 125enum dcn31_clk_src_array_id { 126 DCN31_CLK_SRC_PLL0, 127 DCN31_CLK_SRC_PLL1, 128 DCN31_CLK_SRC_PLL2, 129 DCN31_CLK_SRC_PLL3, 130 DCN31_CLK_SRC_PLL4, 131 DCN30_CLK_SRC_TOTAL 132}; 133 134/* begin ********************* 135 * macros to expend register list macro defined in HW object header file 136 */ 137 138/* DCN */ 139/* TODO awful hack. fixup dcn20_dwb.h */ 140#undef BASE_INNER 141#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 142 143#define BASE(seg) BASE_INNER(seg) 144 145#define SR(reg_name)\ 146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 147 reg ## reg_name 148 149#define SRI(reg_name, block, id)\ 150 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 151 reg ## block ## id ## _ ## reg_name 152 153#define SRI2(reg_name, block, id)\ 154 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 155 reg ## reg_name 156 157#define SRIR(var_name, reg_name, block, id)\ 158 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 159 reg ## block ## id ## _ ## reg_name 160 161#define SRII(reg_name, block, id)\ 162 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 163 reg ## block ## id ## _ ## reg_name 164 165#define SRII_MPC_RMU(reg_name, block, id)\ 166 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 167 reg ## block ## id ## _ ## reg_name 168 169#define SRII_DWB(reg_name, temp_name, block, id)\ 170 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 171 reg ## block ## id ## _ ## temp_name 172 173#define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 174 .field_name = reg_name ## __ ## field_name ## post_fix 175 176#define DCCG_SRII(reg_name, block, id)\ 177 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 178 reg ## block ## id ## _ ## reg_name 179 180#define VUPDATE_SRII(reg_name, block, id)\ 181 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 182 reg ## reg_name ## _ ## block ## id 183 184/* NBIO */ 185#define NBIO_BASE_INNER(seg) \ 186 NBIO_BASE__INST0_SEG ## seg 187 188#define NBIO_BASE(seg) \ 189 NBIO_BASE_INNER(seg) 190 191#define NBIO_SR(reg_name)\ 192 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 193 regBIF_BX2_ ## reg_name 194 195/* MMHUB */ 196#define MMHUB_BASE_INNER(seg) \ 197 MMHUB_BASE__INST0_SEG ## seg 198 199#define MMHUB_BASE(seg) \ 200 MMHUB_BASE_INNER(seg) 201 202#define MMHUB_SR(reg_name)\ 203 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \ 204 reg ## reg_name 205 206/* CLOCK */ 207#define CLK_BASE_INNER(seg) \ 208 CLK_BASE__INST0_SEG ## seg 209 210#define CLK_BASE(seg) \ 211 CLK_BASE_INNER(seg) 212 213#define CLK_SRI(reg_name, block, inst)\ 214 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 215 reg ## block ## _ ## inst ## _ ## reg_name 216 217 218static const struct bios_registers bios_regs = { 219 NBIO_SR(BIOS_SCRATCH_3), 220 NBIO_SR(BIOS_SCRATCH_6) 221}; 222 223#define clk_src_regs(index, pllid)\ 224[index] = {\ 225 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 226} 227 228static const struct dce110_clk_src_regs clk_src_regs[] = { 229 clk_src_regs(0, A), 230 clk_src_regs(1, B), 231 clk_src_regs(2, C), 232 clk_src_regs(3, D), 233 clk_src_regs(4, E) 234}; 235 236static const struct dce110_clk_src_shift cs_shift = { 237 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 238}; 239 240static const struct dce110_clk_src_mask cs_mask = { 241 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 242}; 243 244#define abm_regs(id)\ 245[id] = {\ 246 ABM_DCN302_REG_LIST(id)\ 247} 248 249static const struct dce_abm_registers abm_regs[] = { 250 abm_regs(0), 251 abm_regs(1), 252 abm_regs(2), 253 abm_regs(3), 254}; 255 256static const struct dce_abm_shift abm_shift = { 257 ABM_MASK_SH_LIST_DCN30(__SHIFT) 258}; 259 260static const struct dce_abm_mask abm_mask = { 261 ABM_MASK_SH_LIST_DCN30(_MASK) 262}; 263 264#define audio_regs(id)\ 265[id] = {\ 266 AUD_COMMON_REG_LIST(id)\ 267} 268 269static const struct dce_audio_registers audio_regs[] = { 270 audio_regs(0), 271 audio_regs(1), 272 audio_regs(2), 273 audio_regs(3), 274 audio_regs(4), 275 audio_regs(5), 276 audio_regs(6) 277}; 278 279#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 280 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 281 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 282 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 283 284static const struct dce_audio_shift audio_shift = { 285 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 286}; 287 288static const struct dce_audio_mask audio_mask = { 289 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 290}; 291 292#define vpg_regs(id)\ 293[id] = {\ 294 VPG_DCN31_REG_LIST(id)\ 295} 296 297static const struct dcn31_vpg_registers vpg_regs[] = { 298 vpg_regs(0), 299 vpg_regs(1), 300 vpg_regs(2), 301 vpg_regs(3), 302 vpg_regs(4), 303 vpg_regs(5), 304 vpg_regs(6), 305 vpg_regs(7), 306 vpg_regs(8), 307 vpg_regs(9), 308}; 309 310static const struct dcn31_vpg_shift vpg_shift = { 311 DCN31_VPG_MASK_SH_LIST(__SHIFT) 312}; 313 314static const struct dcn31_vpg_mask vpg_mask = { 315 DCN31_VPG_MASK_SH_LIST(_MASK) 316}; 317 318#define afmt_regs(id)\ 319[id] = {\ 320 AFMT_DCN31_REG_LIST(id)\ 321} 322 323static const struct dcn31_afmt_registers afmt_regs[] = { 324 afmt_regs(0), 325 afmt_regs(1), 326 afmt_regs(2), 327 afmt_regs(3), 328 afmt_regs(4), 329 afmt_regs(5) 330}; 331 332static const struct dcn31_afmt_shift afmt_shift = { 333 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 334}; 335 336static const struct dcn31_afmt_mask afmt_mask = { 337 DCN31_AFMT_MASK_SH_LIST(_MASK) 338}; 339 340#define apg_regs(id)\ 341[id] = {\ 342 APG_DCN31_REG_LIST(id)\ 343} 344 345static const struct dcn31_apg_registers apg_regs[] = { 346 apg_regs(0), 347 apg_regs(1), 348 apg_regs(2), 349 apg_regs(3) 350}; 351 352static const struct dcn31_apg_shift apg_shift = { 353 DCN31_APG_MASK_SH_LIST(__SHIFT) 354}; 355 356static const struct dcn31_apg_mask apg_mask = { 357 DCN31_APG_MASK_SH_LIST(_MASK) 358}; 359 360#define stream_enc_regs(id)\ 361[id] = {\ 362 SE_DCN314_REG_LIST(id)\ 363} 364 365static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 366 stream_enc_regs(0), 367 stream_enc_regs(1), 368 stream_enc_regs(2), 369 stream_enc_regs(3), 370 stream_enc_regs(4) 371}; 372 373static const struct dcn10_stream_encoder_shift se_shift = { 374 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT) 375}; 376 377static const struct dcn10_stream_encoder_mask se_mask = { 378 SE_COMMON_MASK_SH_LIST_DCN314(_MASK) 379}; 380 381 382#define aux_regs(id)\ 383[id] = {\ 384 DCN2_AUX_REG_LIST(id)\ 385} 386 387static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 388 aux_regs(0), 389 aux_regs(1), 390 aux_regs(2), 391 aux_regs(3), 392 aux_regs(4) 393}; 394 395#define hpd_regs(id)\ 396[id] = {\ 397 HPD_REG_LIST(id)\ 398} 399 400static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 401 hpd_regs(0), 402 hpd_regs(1), 403 hpd_regs(2), 404 hpd_regs(3), 405 hpd_regs(4) 406}; 407 408#define link_regs(id, phyid)\ 409[id] = {\ 410 LE_DCN31_REG_LIST(id), \ 411 UNIPHY_DCN2_REG_LIST(phyid), \ 412} 413 414static const struct dce110_aux_registers_shift aux_shift = { 415 DCN_AUX_MASK_SH_LIST(__SHIFT) 416}; 417 418static const struct dce110_aux_registers_mask aux_mask = { 419 DCN_AUX_MASK_SH_LIST(_MASK) 420}; 421 422static const struct dcn10_link_enc_registers link_enc_regs[] = { 423 link_regs(0, A), 424 link_regs(1, B), 425 link_regs(2, C), 426 link_regs(3, D), 427 link_regs(4, E) 428}; 429 430static const struct dcn10_link_enc_shift le_shift = { 431 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), 432 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 433}; 434 435static const struct dcn10_link_enc_mask le_mask = { 436 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), 437 DPCS_DCN31_MASK_SH_LIST(_MASK) 438}; 439 440#define hpo_dp_stream_encoder_reg_list(id)\ 441[id] = {\ 442 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 443} 444 445static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 446 hpo_dp_stream_encoder_reg_list(0), 447 hpo_dp_stream_encoder_reg_list(1), 448 hpo_dp_stream_encoder_reg_list(2), 449 hpo_dp_stream_encoder_reg_list(3) 450}; 451 452static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 453 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 454}; 455 456static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 457 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 458}; 459 460 461#define hpo_dp_link_encoder_reg_list(id)\ 462[id] = {\ 463 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 464 DCN3_1_RDPCSTX_REG_LIST(0),\ 465 DCN3_1_RDPCSTX_REG_LIST(1),\ 466 DCN3_1_RDPCSTX_REG_LIST(2),\ 467} 468 469static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 470 hpo_dp_link_encoder_reg_list(0), 471 hpo_dp_link_encoder_reg_list(1), 472}; 473 474static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 475 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 476}; 477 478static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 479 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 480}; 481 482#define dpp_regs(id)\ 483[id] = {\ 484 DPP_REG_LIST_DCN30(id),\ 485} 486 487static const struct dcn3_dpp_registers dpp_regs[] = { 488 dpp_regs(0), 489 dpp_regs(1), 490 dpp_regs(2), 491 dpp_regs(3) 492}; 493 494static const struct dcn3_dpp_shift tf_shift = { 495 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 496}; 497 498static const struct dcn3_dpp_mask tf_mask = { 499 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 500}; 501 502#define opp_regs(id)\ 503[id] = {\ 504 OPP_REG_LIST_DCN30(id),\ 505} 506 507static const struct dcn20_opp_registers opp_regs[] = { 508 opp_regs(0), 509 opp_regs(1), 510 opp_regs(2), 511 opp_regs(3) 512}; 513 514static const struct dcn20_opp_shift opp_shift = { 515 OPP_MASK_SH_LIST_DCN20(__SHIFT) 516}; 517 518static const struct dcn20_opp_mask opp_mask = { 519 OPP_MASK_SH_LIST_DCN20(_MASK) 520}; 521 522#define aux_engine_regs(id)\ 523[id] = {\ 524 AUX_COMMON_REG_LIST0(id), \ 525 .AUXN_IMPCAL = 0, \ 526 .AUXP_IMPCAL = 0, \ 527 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 528} 529 530static const struct dce110_aux_registers aux_engine_regs[] = { 531 aux_engine_regs(0), 532 aux_engine_regs(1), 533 aux_engine_regs(2), 534 aux_engine_regs(3), 535 aux_engine_regs(4) 536}; 537 538#define dwbc_regs_dcn3(id)\ 539[id] = {\ 540 DWBC_COMMON_REG_LIST_DCN30(id),\ 541} 542 543static const struct dcn30_dwbc_registers dwbc30_regs[] = { 544 dwbc_regs_dcn3(0), 545}; 546 547static const struct dcn30_dwbc_shift dwbc30_shift = { 548 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 549}; 550 551static const struct dcn30_dwbc_mask dwbc30_mask = { 552 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 553}; 554 555#define mcif_wb_regs_dcn3(id)\ 556[id] = {\ 557 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 558} 559 560static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 561 mcif_wb_regs_dcn3(0) 562}; 563 564static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 565 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 566}; 567 568static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 569 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 570}; 571 572#define dsc_regsDCN314(id)\ 573[id] = {\ 574 DSC_REG_LIST_DCN20(id)\ 575} 576 577static const struct dcn20_dsc_registers dsc_regs[] = { 578 dsc_regsDCN314(0), 579 dsc_regsDCN314(1), 580 dsc_regsDCN314(2), 581 dsc_regsDCN314(3) 582}; 583 584static const struct dcn20_dsc_shift dsc_shift = { 585 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 586}; 587 588static const struct dcn20_dsc_mask dsc_mask = { 589 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 590}; 591 592static const struct dcn30_mpc_registers mpc_regs = { 593 MPC_REG_LIST_DCN3_0(0), 594 MPC_REG_LIST_DCN3_0(1), 595 MPC_REG_LIST_DCN3_0(2), 596 MPC_REG_LIST_DCN3_0(3), 597 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 598 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 599 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 600 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 601 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 602 MPC_RMU_REG_LIST_DCN3AG(0), 603 MPC_RMU_REG_LIST_DCN3AG(1), 604 //MPC_RMU_REG_LIST_DCN3AG(2), 605 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 606}; 607 608static const struct dcn30_mpc_shift mpc_shift = { 609 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 610}; 611 612static const struct dcn30_mpc_mask mpc_mask = { 613 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 614}; 615 616#define optc_regs(id)\ 617[id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)} 618 619static const struct dcn_optc_registers optc_regs[] = { 620 optc_regs(0), 621 optc_regs(1), 622 optc_regs(2), 623 optc_regs(3) 624}; 625 626static const struct dcn_optc_shift optc_shift = { 627 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT) 628}; 629 630static const struct dcn_optc_mask optc_mask = { 631 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK) 632}; 633 634#define hubp_regs(id)\ 635[id] = {\ 636 HUBP_REG_LIST_DCN30(id)\ 637} 638 639static const struct dcn_hubp2_registers hubp_regs[] = { 640 hubp_regs(0), 641 hubp_regs(1), 642 hubp_regs(2), 643 hubp_regs(3) 644}; 645 646 647static const struct dcn_hubp2_shift hubp_shift = { 648 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 649}; 650 651static const struct dcn_hubp2_mask hubp_mask = { 652 HUBP_MASK_SH_LIST_DCN31(_MASK) 653}; 654static const struct dcn_hubbub_registers hubbub_reg = { 655 HUBBUB_REG_LIST_DCN31(0) 656}; 657 658static const struct dcn_hubbub_shift hubbub_shift = { 659 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 660}; 661 662static const struct dcn_hubbub_mask hubbub_mask = { 663 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 664}; 665 666static const struct dccg_registers dccg_regs = { 667 DCCG_REG_LIST_DCN314() 668}; 669 670static const struct dccg_shift dccg_shift = { 671 DCCG_MASK_SH_LIST_DCN314(__SHIFT) 672}; 673 674static const struct dccg_mask dccg_mask = { 675 DCCG_MASK_SH_LIST_DCN314(_MASK) 676}; 677 678 679#define SRII2(reg_name_pre, reg_name_post, id)\ 680 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 681 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 682 reg ## reg_name_pre ## id ## _ ## reg_name_post 683 684 685#define HWSEQ_DCN31_REG_LIST()\ 686 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 687 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 688 SR(DIO_MEM_PWR_CTRL), \ 689 SR(ODM_MEM_PWR_CTRL3), \ 690 SR(DMU_MEM_PWR_CNTL), \ 691 SR(MMHUBBUB_MEM_PWR_CNTL), \ 692 SR(DCCG_GATE_DISABLE_CNTL), \ 693 SR(DCCG_GATE_DISABLE_CNTL2), \ 694 SR(DCFCLK_CNTL),\ 695 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 696 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 697 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 698 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 699 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 700 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 701 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 702 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 703 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 704 SR(MICROSECOND_TIME_BASE_DIV), \ 705 SR(MILLISECOND_TIME_BASE_DIV), \ 706 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 707 SR(RBBMIF_TIMEOUT_DIS), \ 708 SR(RBBMIF_TIMEOUT_DIS_2), \ 709 SR(DCHUBBUB_CRC_CTRL), \ 710 SR(DPP_TOP0_DPP_CRC_CTRL), \ 711 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 712 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 713 SR(MPC_CRC_CTRL), \ 714 SR(MPC_CRC_RESULT_GB), \ 715 SR(MPC_CRC_RESULT_C), \ 716 SR(MPC_CRC_RESULT_AR), \ 717 SR(DOMAIN0_PG_CONFIG), \ 718 SR(DOMAIN1_PG_CONFIG), \ 719 SR(DOMAIN2_PG_CONFIG), \ 720 SR(DOMAIN3_PG_CONFIG), \ 721 SR(DOMAIN16_PG_CONFIG), \ 722 SR(DOMAIN17_PG_CONFIG), \ 723 SR(DOMAIN18_PG_CONFIG), \ 724 SR(DOMAIN19_PG_CONFIG), \ 725 SR(DOMAIN0_PG_STATUS), \ 726 SR(DOMAIN1_PG_STATUS), \ 727 SR(DOMAIN2_PG_STATUS), \ 728 SR(DOMAIN3_PG_STATUS), \ 729 SR(DOMAIN16_PG_STATUS), \ 730 SR(DOMAIN17_PG_STATUS), \ 731 SR(DOMAIN18_PG_STATUS), \ 732 SR(DOMAIN19_PG_STATUS), \ 733 SR(D1VGA_CONTROL), \ 734 SR(D2VGA_CONTROL), \ 735 SR(D3VGA_CONTROL), \ 736 SR(D4VGA_CONTROL), \ 737 SR(D5VGA_CONTROL), \ 738 SR(D6VGA_CONTROL), \ 739 SR(DC_IP_REQUEST_CNTL), \ 740 SR(AZALIA_AUDIO_DTO), \ 741 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 742 SR(HPO_TOP_HW_CONTROL) 743 744static const struct dce_hwseq_registers hwseq_reg = { 745 HWSEQ_DCN31_REG_LIST() 746}; 747 748#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 749 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 750 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 751 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 752 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 753 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 754 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 755 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 756 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 757 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 758 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 759 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 760 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 761 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 762 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 763 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 764 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 765 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 766 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 767 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 768 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 769 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 770 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 771 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 772 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 773 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 774 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 775 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 776 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 777 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 778 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 779 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 780 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 781 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 782 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 783 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 784 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 785 786static const struct dce_hwseq_shift hwseq_shift = { 787 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 788}; 789 790static const struct dce_hwseq_mask hwseq_mask = { 791 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 792}; 793#define vmid_regs(id)\ 794[id] = {\ 795 DCN20_VMID_REG_LIST(id)\ 796} 797 798static const struct dcn_vmid_registers vmid_regs[] = { 799 vmid_regs(0), 800 vmid_regs(1), 801 vmid_regs(2), 802 vmid_regs(3), 803 vmid_regs(4), 804 vmid_regs(5), 805 vmid_regs(6), 806 vmid_regs(7), 807 vmid_regs(8), 808 vmid_regs(9), 809 vmid_regs(10), 810 vmid_regs(11), 811 vmid_regs(12), 812 vmid_regs(13), 813 vmid_regs(14), 814 vmid_regs(15) 815}; 816 817static const struct dcn20_vmid_shift vmid_shifts = { 818 DCN20_VMID_MASK_SH_LIST(__SHIFT) 819}; 820 821static const struct dcn20_vmid_mask vmid_masks = { 822 DCN20_VMID_MASK_SH_LIST(_MASK) 823}; 824 825static const struct resource_caps res_cap_dcn314 = { 826 .num_timing_generator = 4, 827 .num_opp = 4, 828 .num_video_plane = 4, 829 .num_audio = 5, 830 .num_stream_encoder = 5, 831 .num_dig_link_enc = 5, 832 .num_hpo_dp_stream_encoder = 4, 833 .num_hpo_dp_link_encoder = 2, 834 .num_pll = 5, 835 .num_dwb = 1, 836 .num_ddc = 5, 837 .num_vmid = 16, 838 .num_mpc_3dlut = 2, 839 .num_dsc = 4, 840}; 841 842static const struct dc_plane_cap plane_cap = { 843 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 844 .per_pixel_alpha = true, 845 846 .pixel_format_support = { 847 .argb8888 = true, 848 .nv12 = true, 849 .fp16 = true, 850 .p010 = true, 851 .ayuv = false, 852 }, 853 854 .max_upscale_factor = { 855 .argb8888 = 16000, 856 .nv12 = 16000, 857 .fp16 = 16000 858 }, 859 860 // 6:1 downscaling ratio: 1000/6 = 166.666 861 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250 862 .max_downscale_factor = { 863 .argb8888 = 250, 864 .nv12 = 167, 865 .fp16 = 167 866 }, 867 64, 868 64 869}; 870 871static const struct dc_debug_options debug_defaults_drv = { 872 .disable_z10 = false, 873 .enable_z9_disable_interface = true, 874 .minimum_z8_residency_time = 2100, 875 .psr_skip_crtc_disable = true, 876 .replay_skip_crtc_disabled = true, 877 .disable_dmcu = true, 878 .force_abm_enable = false, 879 .clock_trace = true, 880 .disable_dpp_power_gate = false, 881 .disable_hubp_power_gate = false, 882 .disable_pplib_clock_request = false, 883 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 884 .force_single_disp_pipe_split = false, 885 .disable_dcc = DCC_ENABLE, 886 .vsr_support = true, 887 .performance_trace = false, 888 .max_downscale_src_width = 4096,/*upto true 4k*/ 889 .disable_pplib_wm_range = false, 890 .scl_reset_length10 = true, 891 .sanity_checks = false, 892 .underflow_assert_delay_us = 0xFFFFFFFF, 893 .dwb_fi_phase = -1, // -1 = disable, 894 .dmub_command_table = true, 895 .pstate_enabled = true, 896 .use_max_lb = true, 897 .enable_mem_low_power = { 898 .bits = { 899 .vga = true, 900 .i2c = true, 901 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 902 .dscl = true, 903 .cm = true, 904 .mpc = true, 905 .optc = true, 906 .vpg = true, 907 .afmt = true, 908 } 909 }, 910 911 .root_clock_optimization = { 912 .bits = { 913 .dpp = true, 914 .dsc = true, 915 .hdmistream = true, 916 .hdmichar = true, 917 .dpstream = true, 918 .symclk32_se = false, 919 .symclk32_le = true, 920 .symclk_fe = true, 921 .physymclk = true, 922 .dpiasymclk = true, 923 } 924 }, 925 926 .seamless_boot_odm_combine = true, 927 .using_dml2 = false, 928 .disable_dsc_power_gate = true, 929 .min_disp_clk_khz = 100000, 930}; 931 932static const struct dc_check_config config_defaults = { 933 .enable_legacy_fast_update = true, 934}; 935 936static const struct dc_panel_config panel_config_defaults = { 937 .psr = { 938 .disable_psr = false, 939 .disallow_psrsu = false, 940 .disallow_replay = false, 941 }, 942 .ilr = { 943 .optimize_edp_link_rate = true, 944 }, 945}; 946 947static void dcn31_dpp_destroy(struct dpp **dpp) 948{ 949 kfree(TO_DCN20_DPP(*dpp)); 950 *dpp = NULL; 951} 952 953static struct dpp *dcn31_dpp_create( 954 struct dc_context *ctx, 955 uint32_t inst) 956{ 957 struct dcn3_dpp *dpp = 958 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 959 960 if (!dpp) 961 return NULL; 962 963 if (dpp3_construct(dpp, ctx, inst, 964 &dpp_regs[inst], &tf_shift, &tf_mask)) 965 return &dpp->base; 966 967 BREAK_TO_DEBUGGER(); 968 kfree(dpp); 969 return NULL; 970} 971 972static struct output_pixel_processor *dcn31_opp_create( 973 struct dc_context *ctx, uint32_t inst) 974{ 975 struct dcn20_opp *opp = 976 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 977 978 if (!opp) { 979 BREAK_TO_DEBUGGER(); 980 return NULL; 981 } 982 983 dcn20_opp_construct(opp, ctx, inst, 984 &opp_regs[inst], &opp_shift, &opp_mask); 985 return &opp->base; 986} 987 988static struct dce_aux *dcn31_aux_engine_create( 989 struct dc_context *ctx, 990 uint32_t inst) 991{ 992 struct aux_engine_dce110 *aux_engine = 993 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 994 995 if (!aux_engine) 996 return NULL; 997 998 dce110_aux_engine_construct(aux_engine, ctx, inst, 999 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1000 &aux_engine_regs[inst], 1001 &aux_mask, 1002 &aux_shift, 1003 ctx->dc->caps.extended_aux_timeout_support); 1004 1005 return &aux_engine->base; 1006} 1007#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 1008 1009static const struct dce_i2c_registers i2c_hw_regs[] = { 1010 i2c_inst_regs(1), 1011 i2c_inst_regs(2), 1012 i2c_inst_regs(3), 1013 i2c_inst_regs(4), 1014 i2c_inst_regs(5), 1015}; 1016 1017static const struct dce_i2c_shift i2c_shifts = { 1018 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 1019}; 1020 1021static const struct dce_i2c_mask i2c_masks = { 1022 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 1023}; 1024 1025/* ========================================================== */ 1026 1027/* 1028 * DPIA index | Preferred Encoder | Host Router 1029 * 0 | C | 0 1030 * 1 | First Available | 0 1031 * 2 | D | 1 1032 * 3 | First Available | 1 1033 */ 1034/* ========================================================== */ 1035static const enum engine_id dpia_to_preferred_enc_id_table[] = { 1036 ENGINE_ID_DIGC, 1037 ENGINE_ID_DIGC, 1038 ENGINE_ID_DIGD, 1039 ENGINE_ID_DIGD 1040}; 1041 1042static enum engine_id dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index) 1043{ 1044 return dpia_to_preferred_enc_id_table[dpia_index]; 1045} 1046 1047static struct dce_i2c_hw *dcn31_i2c_hw_create( 1048 struct dc_context *ctx, 1049 uint32_t inst) 1050{ 1051 struct dce_i2c_hw *dce_i2c_hw = 1052 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 1053 1054 if (!dce_i2c_hw) 1055 return NULL; 1056 1057 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1058 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1059 1060 return dce_i2c_hw; 1061} 1062static struct mpc *dcn31_mpc_create( 1063 struct dc_context *ctx, 1064 int num_mpcc, 1065 int num_rmu) 1066{ 1067 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1068 GFP_KERNEL); 1069 1070 if (!mpc30) 1071 return NULL; 1072 1073 dcn30_mpc_construct(mpc30, ctx, 1074 &mpc_regs, 1075 &mpc_shift, 1076 &mpc_mask, 1077 num_mpcc, 1078 num_rmu); 1079 1080 return &mpc30->base; 1081} 1082 1083static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1084{ 1085 int i; 1086 1087 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1088 GFP_KERNEL); 1089 1090 if (!hubbub3) 1091 return NULL; 1092 1093 hubbub31_construct(hubbub3, ctx, 1094 &hubbub_reg, 1095 &hubbub_shift, 1096 &hubbub_mask, 1097 dcn3_14_ip.det_buffer_size_kbytes, 1098 dcn3_14_ip.pixel_chunk_size_kbytes, 1099 dcn3_14_ip.config_return_buffer_size_in_kbytes); 1100 1101 1102 for (i = 0; i < res_cap_dcn314.num_vmid; i++) { 1103 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1104 1105 vmid->ctx = ctx; 1106 1107 vmid->regs = &vmid_regs[i]; 1108 vmid->shifts = &vmid_shifts; 1109 vmid->masks = &vmid_masks; 1110 } 1111 1112 return &hubbub3->base; 1113} 1114 1115static struct timing_generator *dcn31_timing_generator_create( 1116 struct dc_context *ctx, 1117 uint32_t instance) 1118{ 1119 struct optc *tgn10 = 1120 kzalloc(sizeof(struct optc), GFP_KERNEL); 1121 1122 if (!tgn10) 1123 return NULL; 1124 1125 tgn10->base.inst = instance; 1126 tgn10->base.ctx = ctx; 1127 1128 tgn10->tg_regs = &optc_regs[instance]; 1129 tgn10->tg_shift = &optc_shift; 1130 tgn10->tg_mask = &optc_mask; 1131 1132 dcn314_timing_generator_init(tgn10); 1133 1134 return &tgn10->base; 1135} 1136 1137static const struct encoder_feature_support link_enc_feature = { 1138 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1139 .max_hdmi_pixel_clock = 600000, 1140 .hdmi_ycbcr420_supported = true, 1141 .dp_ycbcr420_supported = true, 1142 .fec_supported = true, 1143 .flags.bits.IS_HBR2_CAPABLE = true, 1144 .flags.bits.IS_HBR3_CAPABLE = true, 1145 .flags.bits.IS_TPS3_CAPABLE = true, 1146 .flags.bits.IS_TPS4_CAPABLE = true 1147}; 1148 1149static struct link_encoder *dcn31_link_encoder_create( 1150 struct dc_context *ctx, 1151 const struct encoder_init_data *enc_init_data) 1152{ 1153 struct dcn20_link_encoder *enc20 = 1154 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1155 1156 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 1157 return NULL; 1158 1159 dcn31_link_encoder_construct(enc20, 1160 enc_init_data, 1161 &link_enc_feature, 1162 &link_enc_regs[enc_init_data->transmitter], 1163 &link_enc_aux_regs[enc_init_data->channel - 1], 1164 &link_enc_hpd_regs[enc_init_data->hpd_source], 1165 &le_shift, 1166 &le_mask); 1167 1168 return &enc20->enc10.base; 1169} 1170 1171/* Create a minimal link encoder object not associated with a particular 1172 * physical connector. 1173 * resource_funcs.link_enc_create_minimal 1174 */ 1175static struct link_encoder *dcn31_link_enc_create_minimal( 1176 struct dc_context *ctx, enum engine_id eng_id) 1177{ 1178 struct dcn20_link_encoder *enc20; 1179 1180 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1181 return NULL; 1182 1183 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1184 if (!enc20) 1185 return NULL; 1186 1187 dcn31_link_encoder_construct_minimal( 1188 enc20, 1189 ctx, 1190 &link_enc_feature, 1191 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1192 eng_id); 1193 1194 return &enc20->enc10.base; 1195} 1196 1197static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1198{ 1199 struct dcn31_panel_cntl *panel_cntl = 1200 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1201 1202 if (!panel_cntl) 1203 return NULL; 1204 1205 dcn31_panel_cntl_construct(panel_cntl, init_data); 1206 1207 return &panel_cntl->base; 1208} 1209 1210static void read_dce_straps( 1211 struct dc_context *ctx, 1212 struct resource_straps *straps) 1213{ 1214 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1215 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1216 1217} 1218 1219static struct audio *dcn31_create_audio( 1220 struct dc_context *ctx, unsigned int inst) 1221{ 1222 return dce_audio_create(ctx, inst, 1223 &audio_regs[inst], &audio_shift, &audio_mask); 1224} 1225 1226static struct vpg *dcn31_vpg_create( 1227 struct dc_context *ctx, 1228 uint32_t inst) 1229{ 1230 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1231 1232 if (!vpg31) 1233 return NULL; 1234 1235 vpg31_construct(vpg31, ctx, inst, 1236 &vpg_regs[inst], 1237 &vpg_shift, 1238 &vpg_mask); 1239 1240 return &vpg31->base; 1241} 1242 1243static struct afmt *dcn31_afmt_create( 1244 struct dc_context *ctx, 1245 uint32_t inst) 1246{ 1247 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1248 1249 if (!afmt31) 1250 return NULL; 1251 1252 afmt31_construct(afmt31, ctx, inst, 1253 &afmt_regs[inst], 1254 &afmt_shift, 1255 &afmt_mask); 1256 1257 // Light sleep by default, no need to power down here 1258 1259 return &afmt31->base; 1260} 1261 1262static struct apg *dcn31_apg_create( 1263 struct dc_context *ctx, 1264 uint32_t inst) 1265{ 1266 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1267 1268 if (!apg31) 1269 return NULL; 1270 1271 apg31_construct(apg31, ctx, inst, 1272 &apg_regs[inst], 1273 &apg_shift, 1274 &apg_mask); 1275 1276 return &apg31->base; 1277} 1278 1279static struct stream_encoder *dcn314_stream_encoder_create( 1280 enum engine_id eng_id, 1281 struct dc_context *ctx) 1282{ 1283 struct dcn10_stream_encoder *enc1; 1284 struct vpg *vpg; 1285 struct afmt *afmt; 1286 int vpg_inst; 1287 int afmt_inst; 1288 1289 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1290 if (eng_id < ENGINE_ID_DIGF) { 1291 vpg_inst = eng_id; 1292 afmt_inst = eng_id; 1293 } else 1294 return NULL; 1295 1296 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1297 vpg = dcn31_vpg_create(ctx, vpg_inst); 1298 afmt = dcn31_afmt_create(ctx, afmt_inst); 1299 1300 if (!enc1 || !vpg || !afmt) { 1301 kfree(enc1); 1302 kfree(vpg); 1303 kfree(afmt); 1304 return NULL; 1305 } 1306 1307 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1308 eng_id, vpg, afmt, 1309 &stream_enc_regs[eng_id], 1310 &se_shift, &se_mask); 1311 1312 return &enc1->base; 1313} 1314 1315static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1316 enum engine_id eng_id, 1317 struct dc_context *ctx) 1318{ 1319 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1320 struct vpg *vpg; 1321 struct apg *apg; 1322 uint32_t hpo_dp_inst; 1323 uint32_t vpg_inst; 1324 uint32_t apg_inst; 1325 1326 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1327 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1328 1329 /* Mapping of VPG register blocks to HPO DP block instance: 1330 * VPG[6] -> HPO_DP[0] 1331 * VPG[7] -> HPO_DP[1] 1332 * VPG[8] -> HPO_DP[2] 1333 * VPG[9] -> HPO_DP[3] 1334 */ 1335 //Uses offset index 5-8, but actually maps to vpg_inst 6-9 1336 vpg_inst = hpo_dp_inst + 5; 1337 1338 /* Mapping of APG register blocks to HPO DP block instance: 1339 * APG[0] -> HPO_DP[0] 1340 * APG[1] -> HPO_DP[1] 1341 * APG[2] -> HPO_DP[2] 1342 * APG[3] -> HPO_DP[3] 1343 */ 1344 apg_inst = hpo_dp_inst; 1345 1346 /* allocate HPO stream encoder and create VPG sub-block */ 1347 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1348 vpg = dcn31_vpg_create(ctx, vpg_inst); 1349 apg = dcn31_apg_create(ctx, apg_inst); 1350 1351 if (!hpo_dp_enc31 || !vpg || !apg) { 1352 kfree(hpo_dp_enc31); 1353 kfree(vpg); 1354 kfree(apg); 1355 return NULL; 1356 } 1357 1358 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1359 hpo_dp_inst, eng_id, vpg, apg, 1360 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1361 &hpo_dp_se_shift, &hpo_dp_se_mask); 1362 1363 return &hpo_dp_enc31->base; 1364} 1365 1366static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1367 uint8_t inst, 1368 struct dc_context *ctx) 1369{ 1370 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1371 1372 /* allocate HPO link encoder */ 1373 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1374 if (!hpo_dp_enc31) 1375 return NULL; /* out of memory */ 1376 1377 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1378 &hpo_dp_link_enc_regs[inst], 1379 &hpo_dp_le_shift, &hpo_dp_le_mask); 1380 1381 return &hpo_dp_enc31->base; 1382} 1383 1384static struct dce_hwseq *dcn314_hwseq_create( 1385 struct dc_context *ctx) 1386{ 1387 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1388 1389 if (hws) { 1390 hws->ctx = ctx; 1391 hws->regs = &hwseq_reg; 1392 hws->shifts = &hwseq_shift; 1393 hws->masks = &hwseq_mask; 1394 } 1395 return hws; 1396} 1397static const struct resource_create_funcs res_create_funcs = { 1398 .read_dce_straps = read_dce_straps, 1399 .create_audio = dcn31_create_audio, 1400 .create_stream_encoder = dcn314_stream_encoder_create, 1401 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1402 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1403 .create_hwseq = dcn314_hwseq_create, 1404}; 1405 1406static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) 1407{ 1408 unsigned int i; 1409 1410 for (i = 0; i < pool->base.stream_enc_count; i++) { 1411 if (pool->base.stream_enc[i] != NULL) { 1412 if (pool->base.stream_enc[i]->vpg != NULL) { 1413 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1414 pool->base.stream_enc[i]->vpg = NULL; 1415 } 1416 if (pool->base.stream_enc[i]->afmt != NULL) { 1417 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1418 pool->base.stream_enc[i]->afmt = NULL; 1419 } 1420 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1421 pool->base.stream_enc[i] = NULL; 1422 } 1423 } 1424 1425 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1426 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1427 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1428 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1429 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1430 } 1431 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1432 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1433 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1434 } 1435 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1436 pool->base.hpo_dp_stream_enc[i] = NULL; 1437 } 1438 } 1439 1440 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1441 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1442 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1443 pool->base.hpo_dp_link_enc[i] = NULL; 1444 } 1445 } 1446 1447 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1448 if (pool->base.dscs[i] != NULL) 1449 dcn20_dsc_destroy(&pool->base.dscs[i]); 1450 } 1451 1452 if (pool->base.mpc != NULL) { 1453 kfree(TO_DCN20_MPC(pool->base.mpc)); 1454 pool->base.mpc = NULL; 1455 } 1456 if (pool->base.hubbub != NULL) { 1457 kfree(pool->base.hubbub); 1458 pool->base.hubbub = NULL; 1459 } 1460 for (i = 0; i < pool->base.pipe_count; i++) { 1461 if (pool->base.dpps[i] != NULL) 1462 dcn31_dpp_destroy(&pool->base.dpps[i]); 1463 1464 if (pool->base.ipps[i] != NULL) 1465 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1466 1467 if (pool->base.hubps[i] != NULL) { 1468 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1469 pool->base.hubps[i] = NULL; 1470 } 1471 1472 if (pool->base.irqs != NULL) 1473 dal_irq_service_destroy(&pool->base.irqs); 1474 } 1475 1476 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1477 if (pool->base.engines[i] != NULL) 1478 dce110_engine_destroy(&pool->base.engines[i]); 1479 if (pool->base.hw_i2cs[i] != NULL) { 1480 kfree(pool->base.hw_i2cs[i]); 1481 pool->base.hw_i2cs[i] = NULL; 1482 } 1483 if (pool->base.sw_i2cs[i] != NULL) { 1484 kfree(pool->base.sw_i2cs[i]); 1485 pool->base.sw_i2cs[i] = NULL; 1486 } 1487 } 1488 1489 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1490 if (pool->base.opps[i] != NULL) 1491 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1492 } 1493 1494 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1495 if (pool->base.timing_generators[i] != NULL) { 1496 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1497 pool->base.timing_generators[i] = NULL; 1498 } 1499 } 1500 1501 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1502 if (pool->base.dwbc[i] != NULL) { 1503 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1504 pool->base.dwbc[i] = NULL; 1505 } 1506 if (pool->base.mcif_wb[i] != NULL) { 1507 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1508 pool->base.mcif_wb[i] = NULL; 1509 } 1510 } 1511 1512 for (i = 0; i < pool->base.audio_count; i++) { 1513 if (pool->base.audios[i]) 1514 dce_aud_destroy(&pool->base.audios[i]); 1515 } 1516 1517 for (i = 0; i < pool->base.clk_src_count; i++) { 1518 if (pool->base.clock_sources[i] != NULL) { 1519 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1520 pool->base.clock_sources[i] = NULL; 1521 } 1522 } 1523 1524 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1525 if (pool->base.mpc_lut[i] != NULL) { 1526 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1527 pool->base.mpc_lut[i] = NULL; 1528 } 1529 if (pool->base.mpc_shaper[i] != NULL) { 1530 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1531 pool->base.mpc_shaper[i] = NULL; 1532 } 1533 } 1534 1535 if (pool->base.dp_clock_source != NULL) { 1536 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1537 pool->base.dp_clock_source = NULL; 1538 } 1539 1540 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1541 if (pool->base.multiple_abms[i] != NULL) 1542 dce_abm_destroy(&pool->base.multiple_abms[i]); 1543 } 1544 1545 if (pool->base.psr != NULL) 1546 dmub_psr_destroy(&pool->base.psr); 1547 1548 if (pool->base.replay != NULL) 1549 dmub_replay_destroy(&pool->base.replay); 1550 1551 if (pool->base.dccg != NULL) 1552 dcn_dccg_destroy(&pool->base.dccg); 1553} 1554 1555static struct hubp *dcn31_hubp_create( 1556 struct dc_context *ctx, 1557 uint32_t inst) 1558{ 1559 struct dcn20_hubp *hubp2 = 1560 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1561 1562 if (!hubp2) 1563 return NULL; 1564 1565 if (hubp31_construct(hubp2, ctx, inst, 1566 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1567 return &hubp2->base; 1568 1569 BREAK_TO_DEBUGGER(); 1570 kfree(hubp2); 1571 return NULL; 1572} 1573 1574static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1575{ 1576 int i; 1577 uint32_t pipe_count = pool->res_cap->num_dwb; 1578 1579 for (i = 0; i < pipe_count; i++) { 1580 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1581 GFP_KERNEL); 1582 1583 if (!dwbc30) { 1584 dm_error("DC: failed to create dwbc30!\n"); 1585 return false; 1586 } 1587 1588 dcn30_dwbc_construct(dwbc30, ctx, 1589 &dwbc30_regs[i], 1590 &dwbc30_shift, 1591 &dwbc30_mask, 1592 i); 1593 1594 pool->dwbc[i] = &dwbc30->base; 1595 } 1596 return true; 1597} 1598 1599static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1600{ 1601 int i; 1602 uint32_t pipe_count = pool->res_cap->num_dwb; 1603 1604 for (i = 0; i < pipe_count; i++) { 1605 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1606 GFP_KERNEL); 1607 1608 if (!mcif_wb30) { 1609 dm_error("DC: failed to create mcif_wb30!\n"); 1610 return false; 1611 } 1612 1613 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1614 &mcif_wb30_regs[i], 1615 &mcif_wb30_shift, 1616 &mcif_wb30_mask, 1617 i); 1618 1619 pool->mcif_wb[i] = &mcif_wb30->base; 1620 } 1621 return true; 1622} 1623 1624static struct display_stream_compressor *dcn314_dsc_create( 1625 struct dc_context *ctx, uint32_t inst) 1626{ 1627 struct dcn20_dsc *dsc = 1628 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1629 1630 if (!dsc) { 1631 BREAK_TO_DEBUGGER(); 1632 return NULL; 1633 } 1634 1635 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1636 return &dsc->base; 1637} 1638 1639static void dcn314_destroy_resource_pool(struct resource_pool **pool) 1640{ 1641 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool); 1642 1643 dcn314_resource_destruct(dcn314_pool); 1644 kfree(dcn314_pool); 1645 *pool = NULL; 1646} 1647 1648static struct clock_source *dcn31_clock_source_create( 1649 struct dc_context *ctx, 1650 struct dc_bios *bios, 1651 enum clock_source_id id, 1652 const struct dce110_clk_src_regs *regs, 1653 bool dp_clk_src) 1654{ 1655 struct dce110_clk_src *clk_src = 1656 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1657 1658 if (!clk_src) 1659 return NULL; 1660 1661 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1662 regs, &cs_shift, &cs_mask)) { 1663 clk_src->base.dp_clk_src = dp_clk_src; 1664 return &clk_src->base; 1665 } 1666 1667 kfree(clk_src); 1668 BREAK_TO_DEBUGGER(); 1669 return NULL; 1670} 1671 1672static int dcn314_populate_dml_pipes_from_context( 1673 struct dc *dc, struct dc_state *context, 1674 display_e2e_pipe_params_st *pipes, 1675 enum dc_validate_mode validate_mode) 1676{ 1677 int pipe_cnt; 1678 1679 DC_FP_START(); 1680 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode); 1681 DC_FP_END(); 1682 1683 return pipe_cnt; 1684} 1685 1686static struct dc_cap_funcs cap_funcs = { 1687 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1688}; 1689 1690static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1691{ 1692 DC_FP_START(); 1693 dcn314_update_bw_bounding_box_fpu(dc, bw_params); 1694 DC_FP_END(); 1695} 1696 1697static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config) 1698{ 1699 *panel_config = panel_config_defaults; 1700} 1701 1702enum dc_status dcn314_validate_bandwidth(struct dc *dc, 1703 struct dc_state *context, 1704 enum dc_validate_mode validate_mode) 1705{ 1706 bool out = false; 1707 1708 BW_VAL_TRACE_SETUP(); 1709 1710 int vlevel = 0; 1711 int pipe_cnt = 0; 1712 display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count, 1713 sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1714 DC_LOGGER_INIT(dc->ctx->logger); 1715 1716 BW_VAL_TRACE_COUNT(); 1717 1718 if (!pipes) 1719 goto validate_fail; 1720 1721 DC_FP_START(); 1722 // do not support self refresh only 1723 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false); 1724 DC_FP_END(); 1725 1726 // Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calculate_wm_and_dlg 1727 if (pipe_cnt == 0) 1728 validate_mode = DC_VALIDATE_MODE_AND_PROGRAMMING; 1729 1730 if (!out) 1731 goto validate_fail; 1732 1733 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1734 1735 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) { 1736 BW_VAL_TRACE_SKIP(fast); 1737 goto validate_out; 1738 } 1739 if (dc->res_pool->funcs->calculate_wm_and_dlg) 1740 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1741 1742 BW_VAL_TRACE_END_WATERMARKS(); 1743 1744 goto validate_out; 1745 1746validate_fail: 1747 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1748 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1749 1750 BW_VAL_TRACE_SKIP(fail); 1751 out = false; 1752 1753validate_out: 1754 kfree(pipes); 1755 1756 BW_VAL_TRACE_FINISH(); 1757 1758 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1759} 1760 1761static struct resource_funcs dcn314_res_pool_funcs = { 1762 .destroy = dcn314_destroy_resource_pool, 1763 .link_enc_create = dcn31_link_encoder_create, 1764 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1765 .link_encs_assign = link_enc_cfg_link_encs_assign, 1766 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1767 .panel_cntl_create = dcn31_panel_cntl_create, 1768 .validate_bandwidth = dcn314_validate_bandwidth, 1769 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1770 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1771 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context, 1772 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 1773 .release_pipe = dcn20_release_pipe, 1774 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1775 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1776 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1777 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1778 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1779 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1780 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1781 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1782 .update_bw_bounding_box = dcn314_update_bw_bounding_box, 1783 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1784 .get_panel_config_defaults = dcn314_get_panel_config_defaults, 1785 .get_preferred_eng_id_dpia = dcn314_get_preferred_eng_id_dpia, 1786 .get_det_buffer_size = dcn31_get_det_buffer_size, 1787 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, 1788 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, 1789 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params 1790}; 1791 1792static struct clock_source *dcn30_clock_source_create( 1793 struct dc_context *ctx, 1794 struct dc_bios *bios, 1795 enum clock_source_id id, 1796 const struct dce110_clk_src_regs *regs, 1797 bool dp_clk_src) 1798{ 1799 struct dce110_clk_src *clk_src = 1800 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1801 1802 if (!clk_src) 1803 return NULL; 1804 1805 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1806 regs, &cs_shift, &cs_mask)) { 1807 clk_src->base.dp_clk_src = dp_clk_src; 1808 return &clk_src->base; 1809 } 1810 1811 kfree(clk_src); 1812 BREAK_TO_DEBUGGER(); 1813 return NULL; 1814} 1815 1816static bool dcn314_resource_construct( 1817 uint8_t num_virtual_links, 1818 struct dc *dc, 1819 struct dcn314_resource_pool *pool) 1820{ 1821 int i; 1822 struct dc_context *ctx = dc->ctx; 1823 struct irq_service_init_data init_data; 1824 1825 ctx->dc_bios->regs = &bios_regs; 1826 1827 pool->base.res_cap = &res_cap_dcn314; 1828 pool->base.funcs = &dcn314_res_pool_funcs; 1829 1830 /************************************************* 1831 * Resource + asic cap harcoding * 1832 *************************************************/ 1833 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1834 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1835 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1836 dc->caps.max_downscale_ratio = 400; 1837 dc->caps.i2c_speed_in_khz = 100; 1838 dc->caps.i2c_speed_in_khz_hdcp = 100; 1839 dc->caps.max_cursor_size = 256; 1840 dc->caps.min_horizontal_blanking_period = 80; 1841 dc->caps.dmdata_alloc_size = 2048; 1842 dc->caps.max_slave_planes = 2; 1843 dc->caps.max_slave_yuv_planes = 2; 1844 dc->caps.max_slave_rgb_planes = 2; 1845 dc->caps.post_blend_color_processing = true; 1846 dc->caps.force_dp_tps4_for_cp2520 = true; 1847 if (dc->config.forceHBR2CP2520) 1848 dc->caps.force_dp_tps4_for_cp2520 = false; 1849 dc->caps.dp_hpo = true; 1850 dc->caps.dp_hdmi21_pcon_support = true; 1851 dc->caps.edp_dsc_support = true; 1852 dc->caps.extended_aux_timeout_support = true; 1853 dc->caps.dmcub_support = true; 1854 dc->caps.is_apu = true; 1855 dc->caps.seamless_odm = true; 1856 1857 dc->caps.zstate_support = true; 1858 1859 /* Color pipeline capabilities */ 1860 dc->caps.color.dpp.dcn_arch = 1; 1861 dc->caps.color.dpp.input_lut_shared = 0; 1862 dc->caps.color.dpp.icsc = 1; 1863 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1864 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1865 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1866 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1867 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1868 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1869 dc->caps.color.dpp.post_csc = 1; 1870 dc->caps.color.dpp.gamma_corr = 1; 1871 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1872 1873 dc->caps.color.dpp.hw_3d_lut = 1; 1874 dc->caps.color.dpp.ogam_ram = 1; 1875 // no OGAM ROM on DCN301 1876 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1877 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1878 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1879 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1880 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1881 dc->caps.color.dpp.ocsc = 0; 1882 1883 dc->caps.color.mpc.gamut_remap = 1; 1884 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1885 dc->caps.color.mpc.ogam_ram = 1; 1886 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1887 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1888 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1889 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1890 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1891 dc->caps.color.mpc.ocsc = 1; 1892 1893 dc->caps.max_disp_clock_khz_at_vmin = 650000; 1894 1895 dc->caps.num_of_host_routers = 2; 1896 dc->caps.num_of_dpias_per_host_router = 2; 1897 1898 /* Use pipe context based otg sync logic */ 1899 dc->config.use_pipe_ctx_sync_logic = true; 1900 1901 /* read VBIOS LTTPR caps */ 1902 { 1903 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1904 enum bp_result bp_query_result; 1905 uint8_t is_vbios_lttpr_enable = 0; 1906 1907 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1908 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1909 } 1910 1911 /* interop bit is implicit */ 1912 { 1913 dc->caps.vbios_lttpr_aware = true; 1914 } 1915 } 1916 dc->check_config = config_defaults; 1917 1918 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1919 dc->debug = debug_defaults_drv; 1920 1921 /* Disable pipe power gating */ 1922 dc->debug.disable_dpp_power_gate = true; 1923 dc->debug.disable_hubp_power_gate = true; 1924 1925 /* Disable root clock optimization */ 1926 dc->debug.root_clock_optimization.u32All = 0; 1927 1928 // Init the vm_helper 1929 if (dc->vm_helper) 1930 vm_helper_init(dc->vm_helper, 16); 1931 1932 /************************************************* 1933 * Create resources * 1934 *************************************************/ 1935 1936 /* Clock Sources for Pixel Clock*/ 1937 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1938 dcn30_clock_source_create(ctx, ctx->dc_bios, 1939 CLOCK_SOURCE_COMBO_PHY_PLL0, 1940 &clk_src_regs[0], false); 1941 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1942 dcn30_clock_source_create(ctx, ctx->dc_bios, 1943 CLOCK_SOURCE_COMBO_PHY_PLL1, 1944 &clk_src_regs[1], false); 1945 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1946 dcn30_clock_source_create(ctx, ctx->dc_bios, 1947 CLOCK_SOURCE_COMBO_PHY_PLL2, 1948 &clk_src_regs[2], false); 1949 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1950 dcn30_clock_source_create(ctx, ctx->dc_bios, 1951 CLOCK_SOURCE_COMBO_PHY_PLL3, 1952 &clk_src_regs[3], false); 1953 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1954 dcn30_clock_source_create(ctx, ctx->dc_bios, 1955 CLOCK_SOURCE_COMBO_PHY_PLL4, 1956 &clk_src_regs[4], false); 1957 1958 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1959 1960 /* todo: not reuse phy_pll registers */ 1961 pool->base.dp_clock_source = 1962 dcn31_clock_source_create(ctx, ctx->dc_bios, 1963 CLOCK_SOURCE_ID_DP_DTO, 1964 &clk_src_regs[0], true); 1965 1966 for (i = 0; i < pool->base.clk_src_count; i++) { 1967 if (pool->base.clock_sources[i] == NULL) { 1968 dm_error("DC: failed to create clock sources!\n"); 1969 BREAK_TO_DEBUGGER(); 1970 goto create_fail; 1971 } 1972 } 1973 1974 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1975 if (pool->base.dccg == NULL) { 1976 dm_error("DC: failed to create dccg!\n"); 1977 BREAK_TO_DEBUGGER(); 1978 goto create_fail; 1979 } 1980 1981 init_data.ctx = dc->ctx; 1982 pool->base.irqs = dal_irq_service_dcn314_create(&init_data); 1983 if (!pool->base.irqs) 1984 goto create_fail; 1985 1986 /* HUBBUB */ 1987 pool->base.hubbub = dcn31_hubbub_create(ctx); 1988 if (pool->base.hubbub == NULL) { 1989 BREAK_TO_DEBUGGER(); 1990 dm_error("DC: failed to create hubbub!\n"); 1991 goto create_fail; 1992 } 1993 1994 /* HUBPs, DPPs, OPPs and TGs */ 1995 for (i = 0; i < pool->base.pipe_count; i++) { 1996 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 1997 if (pool->base.hubps[i] == NULL) { 1998 BREAK_TO_DEBUGGER(); 1999 dm_error( 2000 "DC: failed to create hubps!\n"); 2001 goto create_fail; 2002 } 2003 2004 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2005 if (pool->base.dpps[i] == NULL) { 2006 BREAK_TO_DEBUGGER(); 2007 dm_error( 2008 "DC: failed to create dpps!\n"); 2009 goto create_fail; 2010 } 2011 } 2012 2013 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2014 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2015 if (pool->base.opps[i] == NULL) { 2016 BREAK_TO_DEBUGGER(); 2017 dm_error( 2018 "DC: failed to create output pixel processor!\n"); 2019 goto create_fail; 2020 } 2021 } 2022 2023 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2024 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2025 ctx, i); 2026 if (pool->base.timing_generators[i] == NULL) { 2027 BREAK_TO_DEBUGGER(); 2028 dm_error("DC: failed to create tg!\n"); 2029 goto create_fail; 2030 } 2031 } 2032 pool->base.timing_generator_count = i; 2033 2034 /* PSR */ 2035 pool->base.psr = dmub_psr_create(ctx); 2036 if (pool->base.psr == NULL) { 2037 dm_error("DC: failed to create psr obj!\n"); 2038 BREAK_TO_DEBUGGER(); 2039 goto create_fail; 2040 } 2041 2042 /* Replay */ 2043 pool->base.replay = dmub_replay_create(ctx); 2044 if (pool->base.replay == NULL) { 2045 dm_error("DC: failed to create replay obj!\n"); 2046 BREAK_TO_DEBUGGER(); 2047 goto create_fail; 2048 } 2049 2050 /* ABM */ 2051 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2052 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2053 &abm_regs[i], 2054 &abm_shift, 2055 &abm_mask); 2056 if (pool->base.multiple_abms[i] == NULL) { 2057 dm_error("DC: failed to create abm for pipe %d!\n", i); 2058 BREAK_TO_DEBUGGER(); 2059 goto create_fail; 2060 } 2061 } 2062 2063 /* MPC and DSC */ 2064 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2065 if (pool->base.mpc == NULL) { 2066 BREAK_TO_DEBUGGER(); 2067 dm_error("DC: failed to create mpc!\n"); 2068 goto create_fail; 2069 } 2070 2071 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2072 pool->base.dscs[i] = dcn314_dsc_create(ctx, i); 2073 if (pool->base.dscs[i] == NULL) { 2074 BREAK_TO_DEBUGGER(); 2075 dm_error("DC: failed to create display stream compressor %d!\n", i); 2076 goto create_fail; 2077 } 2078 } 2079 2080 /* DWB and MMHUBBUB */ 2081 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2082 BREAK_TO_DEBUGGER(); 2083 dm_error("DC: failed to create dwbc!\n"); 2084 goto create_fail; 2085 } 2086 2087 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2088 BREAK_TO_DEBUGGER(); 2089 dm_error("DC: failed to create mcif_wb!\n"); 2090 goto create_fail; 2091 } 2092 2093 /* AUX and I2C */ 2094 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2095 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2096 if (pool->base.engines[i] == NULL) { 2097 BREAK_TO_DEBUGGER(); 2098 dm_error( 2099 "DC:failed to create aux engine!!\n"); 2100 goto create_fail; 2101 } 2102 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2103 if (pool->base.hw_i2cs[i] == NULL) { 2104 BREAK_TO_DEBUGGER(); 2105 dm_error( 2106 "DC:failed to create hw i2c!!\n"); 2107 goto create_fail; 2108 } 2109 pool->base.sw_i2cs[i] = NULL; 2110 } 2111 2112 /* DCN314 has 4 DPIA */ 2113 pool->base.usb4_dpia_count = 4; 2114 2115 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2116 if (!resource_construct(num_virtual_links, dc, &pool->base, 2117 &res_create_funcs)) 2118 goto create_fail; 2119 2120 /* HW Sequencer and Plane caps */ 2121 dcn314_hw_sequencer_construct(dc); 2122 2123 dc->caps.max_planes = pool->base.pipe_count; 2124 2125 for (i = 0; i < dc->caps.max_planes; ++i) 2126 dc->caps.planes[i] = plane_cap; 2127 2128 dc->caps.max_odm_combine_factor = 4; 2129 2130 dc->cap_funcs = cap_funcs; 2131 2132 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp; 2133 2134 return true; 2135 2136create_fail: 2137 2138 dcn314_resource_destruct(pool); 2139 2140 return false; 2141} 2142 2143struct resource_pool *dcn314_create_resource_pool( 2144 const struct dc_init_data *init_data, 2145 struct dc *dc) 2146{ 2147 struct dcn314_resource_pool *pool = 2148 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL); 2149 2150 if (!pool) 2151 return NULL; 2152 2153 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) 2154 return &pool->base; 2155 2156 BREAK_TO_DEBUGGER(); 2157 kfree(pool); 2158 return NULL; 2159}
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