dcn303_resource.c

   1// SPDX-License-Identifier: MIT
   2/*
   3 * Copyright (C) 2021 Advanced Micro Devices, Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: AMD
  24 */
  25
  26#include "dcn303/dcn303_init.h"
  27#include "dcn303_resource.h"
  28#include "dcn303/dcn303_dccg.h"
  29#include "irq/dcn303/irq_service_dcn303.h"
  30
  31#include "dcn30/dcn30_dio_link_encoder.h"
  32#include "dcn30/dcn30_dio_stream_encoder.h"
  33#include "dcn30/dcn30_dpp.h"
  34#include "dcn30/dcn30_dwb.h"
  35#include "dcn30/dcn30_hubbub.h"
  36#include "dcn30/dcn30_hubp.h"
  37#include "dcn30/dcn30_mmhubbub.h"
  38#include "dcn30/dcn30_mpc.h"
  39#include "dcn30/dcn30_opp.h"
  40#include "dcn30/dcn30_optc.h"
  41#include "dcn30/dcn30_resource.h"
  42
  43#include "dcn20/dcn20_dsc.h"
  44#include "dcn20/dcn20_resource.h"
  45
  46#include "dml/dcn30/dcn30_fpu.h"
  47
  48#include "dcn10/dcn10_resource.h"
  49
  50#include "link_service.h"
  51
  52#include "dce/dce_abm.h"
  53#include "dce/dce_audio.h"
  54#include "dce/dce_aux.h"
  55#include "dce/dce_clock_source.h"
  56#include "dce/dce_hwseq.h"
  57#include "dce/dce_i2c_hw.h"
  58#include "dce/dce_panel_cntl.h"
  59#include "dce/dmub_abm.h"
  60#include "dce/dmub_psr.h"
  61#include "clk_mgr.h"
  62
  63#include "hw_sequencer_private.h"
  64#include "reg_helper.h"
  65#include "resource.h"
  66#include "vm_helper.h"
  67
  68#include "sienna_cichlid_ip_offset.h"
  69#include "dcn/dcn_3_0_3_offset.h"
  70#include "dcn/dcn_3_0_3_sh_mask.h"
  71#include "dpcs/dpcs_3_0_3_offset.h"
  72#include "dpcs/dpcs_3_0_3_sh_mask.h"
  73#include "nbio/nbio_2_3_offset.h"
  74
  75#include "dml/dcn303/dcn303_fpu.h"
  76
  77#define DC_LOGGER \
  78	dc->ctx->logger
  79#define DC_LOGGER_INIT(logger)
  80
  81
  82static const struct dc_debug_options debug_defaults_drv = {
  83		.disable_dmcu = true,
  84		.force_abm_enable = false,
  85		.clock_trace = true,
  86		.disable_pplib_clock_request = true,
  87		.pipe_split_policy = MPC_SPLIT_AVOID,
  88		.force_single_disp_pipe_split = false,
  89		.disable_dcc = DCC_ENABLE,
  90		.vsr_support = true,
  91		.performance_trace = false,
  92		.max_downscale_src_width = 7680,/*upto 8K*/
  93		.disable_pplib_wm_range = false,
  94		.scl_reset_length10 = true,
  95		.sanity_checks = false,
  96		.underflow_assert_delay_us = 0xFFFFFFFF,
  97		.dwb_fi_phase = -1, // -1 = disable,
  98		.dmub_command_table = true,
  99		.use_max_lb = true,
 100		.exit_idle_opt_for_cursor_updates = true,
 101		.using_dml2 = false,
 102};
 103
 104static const struct dc_check_config config_defaults = {
 105		.enable_legacy_fast_update = false,
 106};
 107
 108static const struct dc_panel_config panel_config_defaults = {
 109		.psr = {
 110			.disable_psr = false,
 111			.disallow_psrsu = false,
 112			.disallow_replay = false,
 113		},
 114};
 115
 116enum dcn303_clk_src_array_id {
 117	DCN303_CLK_SRC_PLL0,
 118	DCN303_CLK_SRC_PLL1,
 119	DCN303_CLK_SRC_TOTAL
 120};
 121
 122static const struct resource_caps res_cap_dcn303 = {
 123		.num_timing_generator = 2,
 124		.num_opp = 2,
 125		.num_video_plane = 2,
 126		.num_audio = 2,
 127		.num_stream_encoder = 2,
 128		.num_dwb = 1,
 129		.num_ddc = 2,
 130		.num_vmid = 16,
 131		.num_mpc_3dlut = 1,
 132		.num_dsc = 2,
 133};
 134
 135static const struct dc_plane_cap plane_cap = {
 136		.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 137		.per_pixel_alpha = true,
 138		.pixel_format_support = {
 139				.argb8888 = true,
 140				.nv12 = true,
 141				.fp16 = true,
 142				.p010 = true,
 143				.ayuv = false,
 144		},
 145		.max_upscale_factor = {
 146				.argb8888 = 16000,
 147				.nv12 = 16000,
 148				.fp16 = 16000
 149		},
 150		.max_downscale_factor = {
 151				.argb8888 = 167,
 152				.nv12 = 167,
 153				.fp16 = 167
 154		},
 155		16,
 156		16
 157};
 158
 159/* NBIO */
 160#define NBIO_BASE_INNER(seg) \
 161		NBIO_BASE__INST0_SEG ## seg
 162
 163#define NBIO_BASE(seg) \
 164		NBIO_BASE_INNER(seg)
 165
 166#define NBIO_SR(reg_name)\
 167		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 168		mm ## reg_name
 169
 170/* DCN */
 171#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 172
 173#define BASE(seg) BASE_INNER(seg)
 174
 175#define SR(reg_name)\
 176		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
 177
 178#define SF(reg_name, field_name, post_fix)\
 179		.field_name = reg_name ## __ ## field_name ## post_fix
 180
 181#define SRI(reg_name, block, id)\
 182		.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
 183
 184#define SRI2(reg_name, block, id)\
 185		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
 186
 187#define SRII(reg_name, block, id)\
 188		.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 189		mm ## block ## id ## _ ## reg_name
 190
 191#define DCCG_SRII(reg_name, block, id)\
 192		.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 193		mm ## block ## id ## _ ## reg_name
 194
 195#define VUPDATE_SRII(reg_name, block, id)\
 196		.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 197		mm ## reg_name ## _ ## block ## id
 198
 199#define SRII_DWB(reg_name, temp_name, block, id)\
 200		.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 201		mm ## block ## id ## _ ## temp_name
 202
 203#define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
 204	.field_name = reg_name ## __ ## field_name ## post_fix
 205
 206#define SRII_MPC_RMU(reg_name, block, id)\
 207		.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 208		mm ## block ## id ## _ ## reg_name
 209
 210static const struct dcn_hubbub_registers hubbub_reg = {
 211		HUBBUB_REG_LIST_DCN30(0)
 212};
 213
 214static const struct dcn_hubbub_shift hubbub_shift = {
 215		HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
 216};
 217
 218static const struct dcn_hubbub_mask hubbub_mask = {
 219		HUBBUB_MASK_SH_LIST_DCN30(_MASK)
 220};
 221
 222#define vmid_regs(id)\
 223		[id] = { DCN20_VMID_REG_LIST(id) }
 224
 225static const struct dcn_vmid_registers vmid_regs[] = {
 226		vmid_regs(0),
 227		vmid_regs(1),
 228		vmid_regs(2),
 229		vmid_regs(3),
 230		vmid_regs(4),
 231		vmid_regs(5),
 232		vmid_regs(6),
 233		vmid_regs(7),
 234		vmid_regs(8),
 235		vmid_regs(9),
 236		vmid_regs(10),
 237		vmid_regs(11),
 238		vmid_regs(12),
 239		vmid_regs(13),
 240		vmid_regs(14),
 241		vmid_regs(15)
 242};
 243
 244static const struct dcn20_vmid_shift vmid_shifts = {
 245		DCN20_VMID_MASK_SH_LIST(__SHIFT)
 246};
 247
 248static const struct dcn20_vmid_mask vmid_masks = {
 249		DCN20_VMID_MASK_SH_LIST(_MASK)
 250};
 251
 252static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx)
 253{
 254	int i;
 255
 256	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
 257
 258	if (!hubbub3)
 259		return NULL;
 260
 261	hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
 262
 263	for (i = 0; i < res_cap_dcn303.num_vmid; i++) {
 264		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
 265
 266		vmid->ctx = ctx;
 267
 268		vmid->regs = &vmid_regs[i];
 269		vmid->shifts = &vmid_shifts;
 270		vmid->masks = &vmid_masks;
 271	}
 272
 273	return &hubbub3->base;
 274}
 275
 276#define vpg_regs(id)\
 277		[id] = { VPG_DCN3_REG_LIST(id) }
 278
 279static const struct dcn30_vpg_registers vpg_regs[] = {
 280		vpg_regs(0),
 281		vpg_regs(1),
 282		vpg_regs(2)
 283};
 284
 285static const struct dcn30_vpg_shift vpg_shift = {
 286		DCN3_VPG_MASK_SH_LIST(__SHIFT)
 287};
 288
 289static const struct dcn30_vpg_mask vpg_mask = {
 290		DCN3_VPG_MASK_SH_LIST(_MASK)
 291};
 292
 293static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)
 294{
 295	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
 296
 297	if (!vpg3)
 298		return NULL;
 299
 300	vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
 301
 302	return &vpg3->base;
 303}
 304
 305#define afmt_regs(id)\
 306		[id] = { AFMT_DCN3_REG_LIST(id) }
 307
 308static const struct dcn30_afmt_registers afmt_regs[] = {
 309		afmt_regs(0),
 310		afmt_regs(1),
 311		afmt_regs(2)
 312};
 313
 314static const struct dcn30_afmt_shift afmt_shift = {
 315		DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 316};
 317
 318static const struct dcn30_afmt_mask afmt_mask = {
 319		DCN3_AFMT_MASK_SH_LIST(_MASK)
 320};
 321
 322static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)
 323{
 324	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
 325
 326	if (!afmt3)
 327		return NULL;
 328
 329	afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
 330
 331	return &afmt3->base;
 332}
 333
 334#define audio_regs(id)\
 335		[id] = { AUD_COMMON_REG_LIST(id) }
 336
 337static const struct dce_audio_registers audio_regs[] = {
 338		audio_regs(0),
 339		audio_regs(1),
 340		audio_regs(2),
 341		audio_regs(3),
 342		audio_regs(4),
 343		audio_regs(5),
 344		audio_regs(6)
 345};
 346
 347#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 348		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 349		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 350		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 351
 352static const struct dce_audio_shift audio_shift = {
 353		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 354};
 355
 356static const struct dce_audio_mask audio_mask = {
 357		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 358};
 359
 360static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst)
 361{
 362	return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
 363}
 364
 365#define stream_enc_regs(id)\
 366		[id] = { SE_DCN3_REG_LIST(id) }
 367
 368static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 369		stream_enc_regs(0),
 370		stream_enc_regs(1)
 371};
 372
 373static const struct dcn10_stream_encoder_shift se_shift = {
 374		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 375};
 376
 377static const struct dcn10_stream_encoder_mask se_mask = {
 378		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 379};
 380
 381static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
 382{
 383	struct dcn10_stream_encoder *enc1;
 384	struct vpg *vpg;
 385	struct afmt *afmt;
 386	int vpg_inst;
 387	int afmt_inst;
 388
 389	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
 390	if (eng_id <= ENGINE_ID_DIGB) {
 391		vpg_inst = eng_id;
 392		afmt_inst = eng_id;
 393	} else
 394		return NULL;
 395
 396	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
 397	vpg = dcn303_vpg_create(ctx, vpg_inst);
 398	afmt = dcn303_afmt_create(ctx, afmt_inst);
 399
 400	if (!enc1 || !vpg || !afmt) {
 401		kfree(enc1);
 402		kfree(vpg);
 403		kfree(afmt);
 404		return NULL;
 405	}
 406
 407	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
 408			&se_shift, &se_mask);
 409
 410	return &enc1->base;
 411}
 412
 413#define clk_src_regs(index, pllid)\
 414		[index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) }
 415
 416static const struct dce110_clk_src_regs clk_src_regs[] = {
 417		clk_src_regs(0, A),
 418		clk_src_regs(1, B)
 419};
 420
 421static const struct dce110_clk_src_shift cs_shift = {
 422		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 423};
 424
 425static const struct dce110_clk_src_mask cs_mask = {
 426		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 427};
 428
 429static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
 430		enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
 431{
 432	struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 433
 434	if (!clk_src)
 435		return NULL;
 436
 437	if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
 438		clk_src->base.dp_clk_src = dp_clk_src;
 439		return &clk_src->base;
 440	}
 441
 442	kfree(clk_src);
 443	BREAK_TO_DEBUGGER();
 444	return NULL;
 445}
 446
 447static const struct dce_hwseq_registers hwseq_reg = {
 448		HWSEQ_DCN303_REG_LIST()
 449};
 450
 451static const struct dce_hwseq_shift hwseq_shift = {
 452		HWSEQ_DCN303_MASK_SH_LIST(__SHIFT)
 453};
 454
 455static const struct dce_hwseq_mask hwseq_mask = {
 456		HWSEQ_DCN303_MASK_SH_LIST(_MASK)
 457};
 458
 459static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx)
 460{
 461	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 462
 463	if (hws) {
 464		hws->ctx = ctx;
 465		hws->regs = &hwseq_reg;
 466		hws->shifts = &hwseq_shift;
 467		hws->masks = &hwseq_mask;
 468	}
 469	return hws;
 470}
 471
 472#define hubp_regs(id)\
 473		[id] = { HUBP_REG_LIST_DCN30(id) }
 474
 475static const struct dcn_hubp2_registers hubp_regs[] = {
 476		hubp_regs(0),
 477		hubp_regs(1)
 478};
 479
 480static const struct dcn_hubp2_shift hubp_shift = {
 481		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
 482};
 483
 484static const struct dcn_hubp2_mask hubp_mask = {
 485		HUBP_MASK_SH_LIST_DCN30(_MASK)
 486};
 487
 488static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)
 489{
 490	struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
 491
 492	if (!hubp2)
 493		return NULL;
 494
 495	if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
 496		return &hubp2->base;
 497
 498	BREAK_TO_DEBUGGER();
 499	kfree(hubp2);
 500	return NULL;
 501}
 502
 503#define dpp_regs(id)\
 504		[id] = { DPP_REG_LIST_DCN30(id) }
 505
 506static const struct dcn3_dpp_registers dpp_regs[] = {
 507		dpp_regs(0),
 508		dpp_regs(1)
 509};
 510
 511static const struct dcn3_dpp_shift tf_shift = {
 512		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 513};
 514
 515static const struct dcn3_dpp_mask tf_mask = {
 516		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 517};
 518
 519static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)
 520{
 521	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 522
 523	if (!dpp)
 524		return NULL;
 525
 526	if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
 527		return &dpp->base;
 528
 529	BREAK_TO_DEBUGGER();
 530	kfree(dpp);
 531	return NULL;
 532}
 533
 534#define opp_regs(id)\
 535		[id] = { OPP_REG_LIST_DCN30(id) }
 536
 537static const struct dcn20_opp_registers opp_regs[] = {
 538		opp_regs(0),
 539		opp_regs(1)
 540};
 541
 542static const struct dcn20_opp_shift opp_shift = {
 543		OPP_MASK_SH_LIST_DCN20(__SHIFT)
 544};
 545
 546static const struct dcn20_opp_mask opp_mask = {
 547		OPP_MASK_SH_LIST_DCN20(_MASK)
 548};
 549
 550static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)
 551{
 552	struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 553
 554	if (!opp) {
 555		BREAK_TO_DEBUGGER();
 556		return NULL;
 557	}
 558
 559	dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 560	return &opp->base;
 561}
 562
 563#define optc_regs(id)\
 564		[id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
 565
 566static const struct dcn_optc_registers optc_regs[] = {
 567		optc_regs(0),
 568		optc_regs(1)
 569};
 570
 571static const struct dcn_optc_shift optc_shift = {
 572		OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 573};
 574
 575static const struct dcn_optc_mask optc_mask = {
 576		OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 577};
 578
 579static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance)
 580{
 581	struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
 582
 583	if (!tgn10)
 584		return NULL;
 585
 586	tgn10->base.inst = instance;
 587	tgn10->base.ctx = ctx;
 588
 589	tgn10->tg_regs = &optc_regs[instance];
 590	tgn10->tg_shift = &optc_shift;
 591	tgn10->tg_mask = &optc_mask;
 592
 593	dcn30_timing_generator_init(tgn10);
 594
 595	return &tgn10->base;
 596}
 597
 598static const struct dcn30_mpc_registers mpc_regs = {
 599		MPC_REG_LIST_DCN3_0(0),
 600		MPC_REG_LIST_DCN3_0(1),
 601		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 602		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 603		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 604		MPC_RMU_REG_LIST_DCN3AG(0),
 605		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 606};
 607
 608static const struct dcn30_mpc_shift mpc_shift = {
 609		MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT)
 610};
 611
 612static const struct dcn30_mpc_mask mpc_mask = {
 613		MPC_COMMON_MASK_SH_LIST_DCN303(_MASK)
 614};
 615
 616static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
 617{
 618	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
 619
 620	if (!mpc30)
 621		return NULL;
 622
 623	dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
 624
 625	return &mpc30->base;
 626}
 627
 628#define dsc_regsDCN20(id)\
 629[id] = { DSC_REG_LIST_DCN20(id) }
 630
 631static const struct dcn20_dsc_registers dsc_regs[] = {
 632		dsc_regsDCN20(0),
 633		dsc_regsDCN20(1)
 634};
 635
 636static const struct dcn20_dsc_shift dsc_shift = {
 637		DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 638};
 639
 640static const struct dcn20_dsc_mask dsc_mask = {
 641		DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 642};
 643
 644static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)
 645{
 646	struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
 647
 648	if (!dsc) {
 649		BREAK_TO_DEBUGGER();
 650		return NULL;
 651	}
 652
 653	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
 654	return &dsc->base;
 655}
 656
 657#define dwbc_regs_dcn3(id)\
 658[id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
 659
 660static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 661		dwbc_regs_dcn3(0)
 662};
 663
 664static const struct dcn30_dwbc_shift dwbc30_shift = {
 665		DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 666};
 667
 668static const struct dcn30_dwbc_mask dwbc30_mask = {
 669		DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 670};
 671
 672static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
 673{
 674	int i;
 675	uint32_t pipe_count = pool->res_cap->num_dwb;
 676
 677	for (i = 0; i < pipe_count; i++) {
 678		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
 679
 680		if (!dwbc30) {
 681			dm_error("DC: failed to create dwbc30!\n");
 682			return false;
 683		}
 684
 685		dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
 686
 687		pool->dwbc[i] = &dwbc30->base;
 688	}
 689	return true;
 690}
 691
 692#define mcif_wb_regs_dcn3(id)\
 693[id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
 694
 695static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 696		mcif_wb_regs_dcn3(0)
 697};
 698
 699static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 700		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 701};
 702
 703static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 704		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 705};
 706
 707static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
 708{
 709	int i;
 710	uint32_t pipe_count = pool->res_cap->num_dwb;
 711
 712	for (i = 0; i < pipe_count; i++) {
 713		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
 714
 715		if (!mcif_wb30) {
 716			dm_error("DC: failed to create mcif_wb30!\n");
 717			return false;
 718		}
 719
 720		dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
 721
 722		pool->mcif_wb[i] = &mcif_wb30->base;
 723	}
 724	return true;
 725}
 726
 727#define aux_engine_regs(id)\
 728[id] = {\
 729		AUX_COMMON_REG_LIST0(id), \
 730		.AUXN_IMPCAL = 0, \
 731		.AUXP_IMPCAL = 0, \
 732		.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 733}
 734
 735static const struct dce110_aux_registers aux_engine_regs[] = {
 736		aux_engine_regs(0),
 737		aux_engine_regs(1)
 738};
 739
 740static const struct dce110_aux_registers_shift aux_shift = {
 741		DCN_AUX_MASK_SH_LIST(__SHIFT)
 742};
 743
 744static const struct dce110_aux_registers_mask aux_mask = {
 745		DCN_AUX_MASK_SH_LIST(_MASK)
 746};
 747
 748static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)
 749{
 750	struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 751
 752	if (!aux_engine)
 753		return NULL;
 754
 755	dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 756			&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
 757
 758	return &aux_engine->base;
 759}
 760
 761#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 762
 763static const struct dce_i2c_registers i2c_hw_regs[] = {
 764		i2c_inst_regs(1),
 765		i2c_inst_regs(2)
 766};
 767
 768static const struct dce_i2c_shift i2c_shifts = {
 769		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 770};
 771
 772static const struct dce_i2c_mask i2c_masks = {
 773		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 774};
 775
 776static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
 777{
 778	struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 779
 780	if (!dce_i2c_hw)
 781		return NULL;
 782
 783	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 784
 785	return dce_i2c_hw;
 786}
 787
 788static const struct encoder_feature_support link_enc_feature = {
 789		.max_hdmi_deep_color = COLOR_DEPTH_121212,
 790		.max_hdmi_pixel_clock = 600000,
 791		.hdmi_ycbcr420_supported = true,
 792		.dp_ycbcr420_supported = true,
 793		.fec_supported = true,
 794		.flags.bits.IS_HBR2_CAPABLE = true,
 795		.flags.bits.IS_HBR3_CAPABLE = true,
 796		.flags.bits.IS_TPS3_CAPABLE = true,
 797		.flags.bits.IS_TPS4_CAPABLE = true
 798};
 799
 800#define link_regs(id, phyid)\
 801		[id] = {\
 802				LE_DCN3_REG_LIST(id), \
 803				UNIPHY_DCN2_REG_LIST(phyid), \
 804				SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 805		}
 806
 807static const struct dcn10_link_enc_registers link_enc_regs[] = {
 808		link_regs(0, A),
 809		link_regs(1, B)
 810};
 811
 812static const struct dcn10_link_enc_shift le_shift = {
 813		LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
 814		DPCS_DCN2_MASK_SH_LIST(__SHIFT)
 815};
 816
 817static const struct dcn10_link_enc_mask le_mask = {
 818		LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
 819		DPCS_DCN2_MASK_SH_LIST(_MASK)
 820};
 821
 822#define aux_regs(id)\
 823		[id] = { DCN2_AUX_REG_LIST(id) }
 824
 825static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 826		aux_regs(0),
 827		aux_regs(1)
 828};
 829
 830#define hpd_regs(id)\
 831		[id] = { HPD_REG_LIST(id) }
 832
 833static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 834		hpd_regs(0),
 835		hpd_regs(1)
 836};
 837
 838static struct link_encoder *dcn303_link_encoder_create(
 839	struct dc_context *ctx,
 840	const struct encoder_init_data *enc_init_data)
 841{
 842	struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
 843
 844	if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
 845		return NULL;
 846
 847	dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
 848			&link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
 849			&link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
 850
 851	return &enc20->enc10.base;
 852}
 853
 854static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 855		{ DCN_PANEL_CNTL_REG_LIST() }
 856};
 857
 858static const struct dce_panel_cntl_shift panel_cntl_shift = {
 859		DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 860};
 861
 862static const struct dce_panel_cntl_mask panel_cntl_mask = {
 863		DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 864};
 865
 866static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data)
 867{
 868	struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
 869
 870	if (!panel_cntl)
 871		return NULL;
 872
 873	dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
 874			&panel_cntl_shift, &panel_cntl_mask);
 875
 876	return &panel_cntl->base;
 877}
 878
 879static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
 880{
 881	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 882			FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 883}
 884
 885static const struct resource_create_funcs res_create_funcs = {
 886		.read_dce_straps = read_dce_straps,
 887		.create_audio = dcn303_create_audio,
 888		.create_stream_encoder = dcn303_stream_encoder_create,
 889		.create_hwseq = dcn303_hwseq_create,
 890};
 891
 892static bool is_soc_bounding_box_valid(struct dc *dc)
 893{
 894	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
 895
 896	if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev))
 897		return true;
 898
 899	return false;
 900}
 901
 902static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
 903{
 904	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc;
 905	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip;
 906
 907	DC_LOGGER_INIT(dc->ctx->logger);
 908
 909	if (!is_soc_bounding_box_valid(dc)) {
 910		DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
 911		return false;
 912	}
 913
 914	loaded_ip->max_num_otg = pool->pipe_count;
 915	loaded_ip->max_num_dpp = pool->pipe_count;
 916	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
 917	DC_FP_START();
 918	dcn20_patch_bounding_box(dc, loaded_bb);
 919	DC_FP_END();
 920
 921	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
 922		struct bp_soc_bb_info bb_info = { 0 };
 923
 924		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
 925			    dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
 926					DC_FP_START();
 927					dcn303_fpu_init_soc_bounding_box(bb_info);
 928					DC_FP_END();
 929		}
 930	}
 931
 932	return true;
 933}
 934
 935static void dcn303_resource_destruct(struct resource_pool *pool)
 936{
 937	unsigned int i;
 938
 939	for (i = 0; i < pool->stream_enc_count; i++) {
 940		if (pool->stream_enc[i] != NULL) {
 941			if (pool->stream_enc[i]->vpg != NULL) {
 942				kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
 943				pool->stream_enc[i]->vpg = NULL;
 944			}
 945			if (pool->stream_enc[i]->afmt != NULL) {
 946				kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
 947				pool->stream_enc[i]->afmt = NULL;
 948			}
 949			kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
 950			pool->stream_enc[i] = NULL;
 951		}
 952	}
 953
 954	for (i = 0; i < pool->res_cap->num_dsc; i++) {
 955		if (pool->dscs[i] != NULL)
 956			dcn20_dsc_destroy(&pool->dscs[i]);
 957	}
 958
 959	if (pool->mpc != NULL) {
 960		kfree(TO_DCN20_MPC(pool->mpc));
 961		pool->mpc = NULL;
 962	}
 963
 964	if (pool->hubbub != NULL) {
 965		kfree(pool->hubbub);
 966		pool->hubbub = NULL;
 967	}
 968
 969	for (i = 0; i < pool->pipe_count; i++) {
 970		if (pool->dpps[i] != NULL) {
 971			kfree(TO_DCN20_DPP(pool->dpps[i]));
 972			pool->dpps[i] = NULL;
 973		}
 974
 975		if (pool->hubps[i] != NULL) {
 976			kfree(TO_DCN20_HUBP(pool->hubps[i]));
 977			pool->hubps[i] = NULL;
 978		}
 979
 980		if (pool->irqs != NULL)
 981			dal_irq_service_destroy(&pool->irqs);
 982	}
 983
 984	for (i = 0; i < pool->res_cap->num_ddc; i++) {
 985		if (pool->engines[i] != NULL)
 986			dce110_engine_destroy(&pool->engines[i]);
 987		if (pool->hw_i2cs[i] != NULL) {
 988			kfree(pool->hw_i2cs[i]);
 989			pool->hw_i2cs[i] = NULL;
 990		}
 991		if (pool->sw_i2cs[i] != NULL) {
 992			kfree(pool->sw_i2cs[i]);
 993			pool->sw_i2cs[i] = NULL;
 994		}
 995	}
 996
 997	for (i = 0; i < pool->res_cap->num_opp; i++) {
 998		if (pool->opps[i] != NULL)
 999			pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1000	}
1001
1002	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1003		if (pool->timing_generators[i] != NULL)	{
1004			kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1005			pool->timing_generators[i] = NULL;
1006		}
1007	}
1008
1009	for (i = 0; i < pool->res_cap->num_dwb; i++) {
1010		if (pool->dwbc[i] != NULL) {
1011			kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1012			pool->dwbc[i] = NULL;
1013		}
1014		if (pool->mcif_wb[i] != NULL) {
1015			kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1016			pool->mcif_wb[i] = NULL;
1017		}
1018	}
1019
1020	for (i = 0; i < pool->audio_count; i++) {
1021		if (pool->audios[i])
1022			dce_aud_destroy(&pool->audios[i]);
1023	}
1024
1025	for (i = 0; i < pool->clk_src_count; i++) {
1026		if (pool->clock_sources[i] != NULL)
1027			dcn20_clock_source_destroy(&pool->clock_sources[i]);
1028	}
1029
1030	if (pool->dp_clock_source != NULL)
1031		dcn20_clock_source_destroy(&pool->dp_clock_source);
1032
1033	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1034		if (pool->mpc_lut[i] != NULL) {
1035			dc_3dlut_func_release(pool->mpc_lut[i]);
1036			pool->mpc_lut[i] = NULL;
1037		}
1038		if (pool->mpc_shaper[i] != NULL) {
1039			dc_transfer_func_release(pool->mpc_shaper[i]);
1040			pool->mpc_shaper[i] = NULL;
1041		}
1042	}
1043
1044	for (i = 0; i < pool->pipe_count; i++) {
1045		if (pool->multiple_abms[i] != NULL)
1046			dce_abm_destroy(&pool->multiple_abms[i]);
1047	}
1048
1049	if (pool->psr != NULL)
1050		dmub_psr_destroy(&pool->psr);
1051
1052	if (pool->dccg != NULL)
1053		dcn_dccg_destroy(&pool->dccg);
1054
1055	if (pool->oem_device != NULL) {
1056		struct dc *dc = pool->oem_device->ctx->dc;
1057
1058		dc->link_srv->destroy_ddc_service(&pool->oem_device);
1059	}
1060}
1061
1062static void dcn303_destroy_resource_pool(struct resource_pool **pool)
1063{
1064	dcn303_resource_destruct(*pool);
1065	kfree(*pool);
1066	*pool = NULL;
1067}
1068
1069static void dcn303_get_panel_config_defaults(struct dc_panel_config *panel_config)
1070{
1071	*panel_config = panel_config_defaults;
1072}
1073
1074void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1075{
1076	DC_FP_START();
1077	dcn303_fpu_update_bw_bounding_box(dc, bw_params);
1078	DC_FP_END();
1079}
1080
1081static struct resource_funcs dcn303_res_pool_funcs = {
1082		.destroy = dcn303_destroy_resource_pool,
1083		.link_enc_create = dcn303_link_encoder_create,
1084		.panel_cntl_create = dcn303_panel_cntl_create,
1085		.validate_bandwidth = dcn30_validate_bandwidth,
1086		.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1087		.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1088		.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1089		.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1090		.release_pipe = dcn20_release_pipe,
1091		.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1092		.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1093		.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1094		.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1095		.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1096		.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1097		.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1098		.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1099		.update_bw_bounding_box = dcn303_update_bw_bounding_box,
1100		.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1101		.get_panel_config_defaults = dcn303_get_panel_config_defaults,
1102		.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
1103};
1104
1105static struct dc_cap_funcs cap_funcs = {
1106		.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1107};
1108
1109static const struct bios_registers bios_regs = {
1110		NBIO_SR(BIOS_SCRATCH_3),
1111		NBIO_SR(BIOS_SCRATCH_6)
1112};
1113
1114static const struct dccg_registers dccg_regs = {
1115		DCCG_REG_LIST_DCN3_03()
1116};
1117
1118static const struct dccg_shift dccg_shift = {
1119		DCCG_MASK_SH_LIST_DCN3_03(__SHIFT)
1120};
1121
1122static const struct dccg_mask dccg_mask = {
1123		DCCG_MASK_SH_LIST_DCN3_03(_MASK)
1124};
1125
1126#define abm_regs(id)\
1127		[id] = { ABM_DCN302_REG_LIST(id) }
1128
1129static const struct dce_abm_registers abm_regs[] = {
1130		abm_regs(0),
1131		abm_regs(1)
1132};
1133
1134static const struct dce_abm_shift abm_shift = {
1135		ABM_MASK_SH_LIST_DCN30(__SHIFT)
1136};
1137
1138static const struct dce_abm_mask abm_mask = {
1139		ABM_MASK_SH_LIST_DCN30(_MASK)
1140};
1141
1142static bool dcn303_resource_construct(
1143		uint8_t num_virtual_links,
1144		struct dc *dc,
1145		struct resource_pool *pool)
1146{
1147	int i;
1148	struct dc_context *ctx = dc->ctx;
1149	struct irq_service_init_data init_data;
1150	struct ddc_service_init_data ddc_init_data = {0};
1151
1152	ctx->dc_bios->regs = &bios_regs;
1153
1154	pool->res_cap = &res_cap_dcn303;
1155
1156	pool->funcs = &dcn303_res_pool_funcs;
1157
1158	/*************************************************
1159	 *  Resource + asic cap harcoding                *
1160	 *************************************************/
1161	pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1162	pool->pipe_count = pool->res_cap->num_timing_generator;
1163	pool->mpcc_count = pool->res_cap->num_timing_generator;
1164	dc->caps.max_downscale_ratio = 600;
1165	dc->caps.i2c_speed_in_khz = 100;
1166	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1167	dc->caps.max_cursor_size = 256;
1168	dc->caps.min_horizontal_blanking_period = 80;
1169	dc->caps.dmdata_alloc_size = 2048;
1170	dc->caps.mall_size_per_mem_channel = 4;
1171	/* total size = mall per channel * num channels * 1024 * 1024 */
1172	dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *
1173				   dc->ctx->dc_bios->vram_info.num_chans *
1174				   1024 * 1024;
1175	dc->caps.cursor_cache_size =
1176		dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1177	dc->caps.max_slave_planes = 1;
1178	dc->caps.max_slave_yuv_planes = 1;
1179	dc->caps.max_slave_rgb_planes = 1;
1180	dc->caps.post_blend_color_processing = true;
1181	dc->caps.force_dp_tps4_for_cp2520 = true;
1182	dc->caps.extended_aux_timeout_support = true;
1183	dc->caps.dmcub_support = true;
1184	dc->caps.max_v_total = (1 << 15) - 1;
1185	dc->caps.vtotal_limited_by_fp2 = true;
1186
1187	/* Color pipeline capabilities */
1188	dc->caps.color.dpp.dcn_arch = 1;
1189	dc->caps.color.dpp.input_lut_shared = 0;
1190	dc->caps.color.dpp.icsc = 1;
1191	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1192	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1193	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1194	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1195	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1196	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1197	dc->caps.color.dpp.post_csc = 1;
1198	dc->caps.color.dpp.gamma_corr = 1;
1199	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1200
1201	dc->caps.color.dpp.hw_3d_lut = 1;
1202	dc->caps.color.dpp.ogam_ram = 1;
1203	// no OGAM ROM on DCN3
1204	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1205	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1206	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1207	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1208	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1209	dc->caps.color.dpp.ocsc = 0;
1210
1211	dc->caps.color.mpc.gamut_remap = 1;
1212	dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1213	dc->caps.color.mpc.ogam_ram = 1;
1214	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1215	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1216	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1217	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1218	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1219	dc->caps.color.mpc.ocsc = 1;
1220
1221	dc->caps.dp_hdmi21_pcon_support = true;
1222
1223	dc->config.dc_mode_clk_limit_support = true;
1224	/* read VBIOS LTTPR caps */
1225	if (ctx->dc_bios->funcs->get_lttpr_caps) {
1226		enum bp_result bp_query_result;
1227		uint8_t is_vbios_lttpr_enable = 0;
1228
1229		bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1230		dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1231	}
1232
1233	if (ctx->dc_bios->funcs->get_lttpr_interop) {
1234		enum bp_result bp_query_result;
1235		uint8_t is_vbios_interop_enabled = 0;
1236
1237		bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1238		dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1239	}
1240	dc->check_config = config_defaults;
1241
1242	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1243		dc->debug = debug_defaults_drv;
1244
1245	// Init the vm_helper
1246	if (dc->vm_helper)
1247		vm_helper_init(dc->vm_helper, 16);
1248
1249	/*************************************************
1250	 *  Create resources                             *
1251	 *************************************************/
1252
1253	/* Clock Sources for Pixel Clock*/
1254	pool->clock_sources[DCN303_CLK_SRC_PLL0] =
1255			dcn303_clock_source_create(ctx, ctx->dc_bios,
1256					CLOCK_SOURCE_COMBO_PHY_PLL0,
1257					&clk_src_regs[0], false);
1258	pool->clock_sources[DCN303_CLK_SRC_PLL1] =
1259			dcn303_clock_source_create(ctx, ctx->dc_bios,
1260					CLOCK_SOURCE_COMBO_PHY_PLL1,
1261					&clk_src_regs[1], false);
1262
1263	pool->clk_src_count = DCN303_CLK_SRC_TOTAL;
1264
1265	/* todo: not reuse phy_pll registers */
1266	pool->dp_clock_source =
1267			dcn303_clock_source_create(ctx, ctx->dc_bios,
1268					CLOCK_SOURCE_ID_DP_DTO,
1269					&clk_src_regs[0], true);
1270
1271	for (i = 0; i < pool->clk_src_count; i++) {
1272		if (pool->clock_sources[i] == NULL) {
1273			dm_error("DC: failed to create clock sources!\n");
1274			BREAK_TO_DEBUGGER();
1275			goto create_fail;
1276		}
1277	}
1278
1279	/* DCCG */
1280	pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1281	if (pool->dccg == NULL) {
1282		dm_error("DC: failed to create dccg!\n");
1283		BREAK_TO_DEBUGGER();
1284		goto create_fail;
1285	}
1286
1287	/* PP Lib and SMU interfaces */
1288	init_soc_bounding_box(dc, pool);
1289
1290	/* DML */
1291	dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
1292
1293	/* IRQ */
1294	init_data.ctx = dc->ctx;
1295	pool->irqs = dal_irq_service_dcn303_create(&init_data);
1296	if (!pool->irqs)
1297		goto create_fail;
1298
1299	/* HUBBUB */
1300	pool->hubbub = dcn303_hubbub_create(ctx);
1301	if (pool->hubbub == NULL) {
1302		BREAK_TO_DEBUGGER();
1303		dm_error("DC: failed to create hubbub!\n");
1304		goto create_fail;
1305	}
1306
1307	/* HUBPs, DPPs, OPPs and TGs */
1308	for (i = 0; i < pool->pipe_count; i++) {
1309		pool->hubps[i] = dcn303_hubp_create(ctx, i);
1310		if (pool->hubps[i] == NULL) {
1311			BREAK_TO_DEBUGGER();
1312			dm_error("DC: failed to create hubps!\n");
1313			goto create_fail;
1314		}
1315
1316		pool->dpps[i] = dcn303_dpp_create(ctx, i);
1317		if (pool->dpps[i] == NULL) {
1318			BREAK_TO_DEBUGGER();
1319			dm_error("DC: failed to create dpps!\n");
1320			goto create_fail;
1321		}
1322	}
1323
1324	for (i = 0; i < pool->res_cap->num_opp; i++) {
1325		pool->opps[i] = dcn303_opp_create(ctx, i);
1326		if (pool->opps[i] == NULL) {
1327			BREAK_TO_DEBUGGER();
1328			dm_error("DC: failed to create output pixel processor!\n");
1329			goto create_fail;
1330		}
1331	}
1332
1333	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1334		pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i);
1335		if (pool->timing_generators[i] == NULL) {
1336			BREAK_TO_DEBUGGER();
1337			dm_error("DC: failed to create tg!\n");
1338			goto create_fail;
1339		}
1340	}
1341	pool->timing_generator_count = i;
1342
1343	/* PSR */
1344	pool->psr = dmub_psr_create(ctx);
1345	if (pool->psr == NULL) {
1346		dm_error("DC: failed to create psr!\n");
1347		BREAK_TO_DEBUGGER();
1348		goto create_fail;
1349	}
1350
1351	/* ABM */
1352	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1353		pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1354		if (pool->multiple_abms[i] == NULL) {
1355			dm_error("DC: failed to create abm for pipe %d!\n", i);
1356			BREAK_TO_DEBUGGER();
1357			goto create_fail;
1358		}
1359	}
1360
1361	/* MPC and DSC */
1362	pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1363	if (pool->mpc == NULL) {
1364		BREAK_TO_DEBUGGER();
1365		dm_error("DC: failed to create mpc!\n");
1366		goto create_fail;
1367	}
1368
1369	for (i = 0; i < pool->res_cap->num_dsc; i++) {
1370		pool->dscs[i] = dcn303_dsc_create(ctx, i);
1371		if (pool->dscs[i] == NULL) {
1372			BREAK_TO_DEBUGGER();
1373			dm_error("DC: failed to create display stream compressor %d!\n", i);
1374			goto create_fail;
1375		}
1376	}
1377
1378	/* DWB and MMHUBBUB */
1379	if (!dcn303_dwbc_create(ctx, pool)) {
1380		BREAK_TO_DEBUGGER();
1381		dm_error("DC: failed to create dwbc!\n");
1382		goto create_fail;
1383	}
1384
1385	if (!dcn303_mmhubbub_create(ctx, pool)) {
1386		BREAK_TO_DEBUGGER();
1387		dm_error("DC: failed to create mcif_wb!\n");
1388		goto create_fail;
1389	}
1390
1391	/* AUX and I2C */
1392	for (i = 0; i < pool->res_cap->num_ddc; i++) {
1393		pool->engines[i] = dcn303_aux_engine_create(ctx, i);
1394		if (pool->engines[i] == NULL) {
1395			BREAK_TO_DEBUGGER();
1396			dm_error("DC:failed to create aux engine!!\n");
1397			goto create_fail;
1398		}
1399		pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i);
1400		if (pool->hw_i2cs[i] == NULL) {
1401			BREAK_TO_DEBUGGER();
1402			dm_error("DC:failed to create hw i2c!!\n");
1403			goto create_fail;
1404		}
1405		pool->sw_i2cs[i] = NULL;
1406	}
1407
1408	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1409	if (!resource_construct(num_virtual_links, dc, pool,
1410			&res_create_funcs))
1411		goto create_fail;
1412
1413	/* HW Sequencer and Plane caps */
1414	dcn303_hw_sequencer_construct(dc);
1415
1416	dc->caps.max_planes =  pool->pipe_count;
1417
1418	for (i = 0; i < dc->caps.max_planes; ++i)
1419		dc->caps.planes[i] = plane_cap;
1420
1421	dc->caps.max_odm_combine_factor = 4;
1422
1423	dc->cap_funcs = cap_funcs;
1424
1425	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1426		ddc_init_data.ctx = dc->ctx;
1427		ddc_init_data.link = NULL;
1428		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1429		ddc_init_data.id.enum_id = 0;
1430		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1431		pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
1432	} else {
1433		pool->oem_device = NULL;
1434	}
1435
1436	return true;
1437
1438create_fail:
1439
1440	dcn303_resource_destruct(pool);
1441
1442	return false;
1443}
1444
1445struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1446{
1447	struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1448
1449	if (!pool)
1450		return NULL;
1451
1452	if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))
1453		return pool;
1454
1455	BREAK_TO_DEBUGGER();
1456	kfree(pool);
1457	return NULL;
1458}