dcn302_resource.c

   1/*
   2 * Copyright 2020 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "dcn302/dcn302_init.h"
  27#include "dcn302_resource.h"
  28#include "dcn302/dcn302_dccg.h"
  29#include "irq/dcn302/irq_service_dcn302.h"
  30
  31#include "dcn30/dcn30_dio_link_encoder.h"
  32#include "dcn30/dcn30_dio_stream_encoder.h"
  33#include "dcn30/dcn30_dwb.h"
  34#include "dcn30/dcn30_dpp.h"
  35#include "dcn30/dcn30_hubbub.h"
  36#include "dcn30/dcn30_hubp.h"
  37#include "dcn30/dcn30_mmhubbub.h"
  38#include "dcn30/dcn30_mpc.h"
  39#include "dcn30/dcn30_opp.h"
  40#include "dcn30/dcn30_optc.h"
  41#include "dcn30/dcn30_resource.h"
  42
  43#include "dcn20/dcn20_dsc.h"
  44#include "dcn20/dcn20_resource.h"
  45
  46#include "dml/dcn30/dcn30_fpu.h"
  47
  48#include "dcn10/dcn10_resource.h"
  49
  50#include "link_service.h"
  51
  52#include "dce/dce_abm.h"
  53#include "dce/dce_audio.h"
  54#include "dce/dce_aux.h"
  55#include "dce/dce_clock_source.h"
  56#include "dce/dce_hwseq.h"
  57#include "dce/dce_i2c_hw.h"
  58#include "dce/dce_panel_cntl.h"
  59#include "dce/dmub_abm.h"
  60#include "dce/dmub_psr.h"
  61#include "clk_mgr.h"
  62
  63#include "hw_sequencer_private.h"
  64#include "reg_helper.h"
  65#include "resource.h"
  66#include "vm_helper.h"
  67
  68#include "dml/dcn302/dcn302_fpu.h"
  69
  70#include "dimgrey_cavefish_ip_offset.h"
  71#include "dcn/dcn_3_0_2_offset.h"
  72#include "dcn/dcn_3_0_2_sh_mask.h"
  73#include "dpcs/dpcs_3_0_0_offset.h"
  74#include "dpcs/dpcs_3_0_0_sh_mask.h"
  75#include "nbio/nbio_7_4_offset.h"
  76#include "amdgpu_socbb.h"
  77
  78#define DC_LOGGER \
  79	dc->ctx->logger
  80#define DC_LOGGER_INIT(logger)
  81
  82static const struct dc_debug_options debug_defaults_drv = {
  83		.disable_dmcu = true,
  84		.force_abm_enable = false,
  85		.clock_trace = true,
  86		.disable_pplib_clock_request = true,
  87		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
  88		.force_single_disp_pipe_split = false,
  89		.disable_dcc = DCC_ENABLE,
  90		.vsr_support = true,
  91		.performance_trace = false,
  92		.max_downscale_src_width = 7680,/*upto 8K*/
  93		.disable_pplib_wm_range = false,
  94		.scl_reset_length10 = true,
  95		.sanity_checks = false,
  96		.underflow_assert_delay_us = 0xFFFFFFFF,
  97		.dwb_fi_phase = -1, // -1 = disable,
  98		.dmub_command_table = true,
  99		.use_max_lb = true,
 100		.exit_idle_opt_for_cursor_updates = true,
 101		.using_dml2 = false,
 102};
 103
 104static const struct dc_check_config config_defaults = {
 105		.enable_legacy_fast_update = false,
 106};
 107
 108static const struct dc_panel_config panel_config_defaults = {
 109		.psr = {
 110			.disable_psr = false,
 111			.disallow_psrsu = false,
 112			.disallow_replay = false,
 113		},
 114};
 115
 116enum dcn302_clk_src_array_id {
 117	DCN302_CLK_SRC_PLL0,
 118	DCN302_CLK_SRC_PLL1,
 119	DCN302_CLK_SRC_PLL2,
 120	DCN302_CLK_SRC_PLL3,
 121	DCN302_CLK_SRC_PLL4,
 122	DCN302_CLK_SRC_TOTAL
 123};
 124
 125static const struct resource_caps res_cap_dcn302 = {
 126		.num_timing_generator = 5,
 127		.num_opp = 5,
 128		.num_video_plane = 5,
 129		.num_audio = 5,
 130		.num_stream_encoder = 5,
 131		.num_dwb = 1,
 132		.num_ddc = 5,
 133		.num_vmid = 16,
 134		.num_mpc_3dlut = 2,
 135		.num_dsc = 5,
 136};
 137
 138static const struct dc_plane_cap plane_cap = {
 139		.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 140		.per_pixel_alpha = true,
 141		.pixel_format_support = {
 142				.argb8888 = true,
 143				.nv12 = true,
 144				.fp16 = true,
 145				.p010 = true,
 146				.ayuv = false,
 147		},
 148		.max_upscale_factor = {
 149				.argb8888 = 16000,
 150				.nv12 = 16000,
 151				.fp16 = 16000
 152		},
 153		/* 6:1 downscaling ratio: 1000/6 = 166.666 */
 154		.max_downscale_factor = {
 155				.argb8888 = 167,
 156				.nv12 = 167,
 157				.fp16 = 167
 158		},
 159		16,
 160		16
 161};
 162
 163/* NBIO */
 164#define NBIO_BASE_INNER(seg) \
 165		NBIO_BASE__INST0_SEG ## seg
 166
 167#define NBIO_BASE(seg) \
 168		NBIO_BASE_INNER(seg)
 169
 170#define NBIO_SR(reg_name)\
 171		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 172		mm ## reg_name
 173
 174/* DCN */
 175#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 176
 177#define BASE(seg) BASE_INNER(seg)
 178
 179#define SR(reg_name)\
 180		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
 181
 182#define SF(reg_name, field_name, post_fix)\
 183		.field_name = reg_name ## __ ## field_name ## post_fix
 184
 185#define SRI(reg_name, block, id)\
 186		.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
 187
 188#define SRI2(reg_name, block, id)\
 189		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
 190
 191#define SRII(reg_name, block, id)\
 192		.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 193		mm ## block ## id ## _ ## reg_name
 194
 195#define DCCG_SRII(reg_name, block, id)\
 196		.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 197		mm ## block ## id ## _ ## reg_name
 198
 199#define VUPDATE_SRII(reg_name, block, id)\
 200		.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 201		mm ## reg_name ## _ ## block ## id
 202
 203#define SRII_DWB(reg_name, temp_name, block, id)\
 204		.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 205		mm ## block ## id ## _ ## temp_name
 206
 207#define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
 208	.field_name = reg_name ## __ ## field_name ## post_fix
 209
 210#define SRII_MPC_RMU(reg_name, block, id)\
 211		.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 212		mm ## block ## id ## _ ## reg_name
 213
 214static const struct dcn_hubbub_registers hubbub_reg = {
 215		HUBBUB_REG_LIST_DCN30(0)
 216};
 217
 218static const struct dcn_hubbub_shift hubbub_shift = {
 219		HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
 220};
 221
 222static const struct dcn_hubbub_mask hubbub_mask = {
 223		HUBBUB_MASK_SH_LIST_DCN30(_MASK)
 224};
 225
 226#define vmid_regs(id)\
 227		[id] = { DCN20_VMID_REG_LIST(id) }
 228
 229static const struct dcn_vmid_registers vmid_regs[] = {
 230		vmid_regs(0),
 231		vmid_regs(1),
 232		vmid_regs(2),
 233		vmid_regs(3),
 234		vmid_regs(4),
 235		vmid_regs(5),
 236		vmid_regs(6),
 237		vmid_regs(7),
 238		vmid_regs(8),
 239		vmid_regs(9),
 240		vmid_regs(10),
 241		vmid_regs(11),
 242		vmid_regs(12),
 243		vmid_regs(13),
 244		vmid_regs(14),
 245		vmid_regs(15)
 246};
 247
 248static const struct dcn20_vmid_shift vmid_shifts = {
 249		DCN20_VMID_MASK_SH_LIST(__SHIFT)
 250};
 251
 252static const struct dcn20_vmid_mask vmid_masks = {
 253		DCN20_VMID_MASK_SH_LIST(_MASK)
 254};
 255
 256static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
 257{
 258	int i;
 259
 260	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
 261
 262	if (!hubbub3)
 263		return NULL;
 264
 265	hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
 266
 267	for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
 268		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
 269
 270		vmid->ctx = ctx;
 271
 272		vmid->regs = &vmid_regs[i];
 273		vmid->shifts = &vmid_shifts;
 274		vmid->masks = &vmid_masks;
 275	}
 276
 277	return &hubbub3->base;
 278}
 279
 280#define vpg_regs(id)\
 281		[id] = { VPG_DCN3_REG_LIST(id) }
 282
 283static const struct dcn30_vpg_registers vpg_regs[] = {
 284		vpg_regs(0),
 285		vpg_regs(1),
 286		vpg_regs(2),
 287		vpg_regs(3),
 288		vpg_regs(4),
 289		vpg_regs(5)
 290};
 291
 292static const struct dcn30_vpg_shift vpg_shift = {
 293		DCN3_VPG_MASK_SH_LIST(__SHIFT)
 294};
 295
 296static const struct dcn30_vpg_mask vpg_mask = {
 297		DCN3_VPG_MASK_SH_LIST(_MASK)
 298};
 299
 300static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
 301{
 302	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
 303
 304	if (!vpg3)
 305		return NULL;
 306
 307	vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
 308
 309	return &vpg3->base;
 310}
 311
 312#define afmt_regs(id)\
 313		[id] = { AFMT_DCN3_REG_LIST(id) }
 314
 315static const struct dcn30_afmt_registers afmt_regs[] = {
 316		afmt_regs(0),
 317		afmt_regs(1),
 318		afmt_regs(2),
 319		afmt_regs(3),
 320		afmt_regs(4),
 321		afmt_regs(5)
 322};
 323
 324static const struct dcn30_afmt_shift afmt_shift = {
 325		DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 326};
 327
 328static const struct dcn30_afmt_mask afmt_mask = {
 329		DCN3_AFMT_MASK_SH_LIST(_MASK)
 330};
 331
 332static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
 333{
 334	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
 335
 336	if (!afmt3)
 337		return NULL;
 338
 339	afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
 340
 341	return &afmt3->base;
 342}
 343
 344#define audio_regs(id)\
 345		[id] = { AUD_COMMON_REG_LIST(id) }
 346
 347static const struct dce_audio_registers audio_regs[] = {
 348		audio_regs(0),
 349		audio_regs(1),
 350		audio_regs(2),
 351		audio_regs(3),
 352		audio_regs(4),
 353		audio_regs(5),
 354		audio_regs(6)
 355};
 356
 357#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 358		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 359		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 360		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 361
 362static const struct dce_audio_shift audio_shift = {
 363		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 364};
 365
 366static const struct dce_audio_mask audio_mask = {
 367		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 368};
 369
 370static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
 371{
 372	return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
 373}
 374
 375#define stream_enc_regs(id)\
 376		[id] = { SE_DCN3_REG_LIST(id) }
 377
 378static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 379		stream_enc_regs(0),
 380		stream_enc_regs(1),
 381		stream_enc_regs(2),
 382		stream_enc_regs(3),
 383		stream_enc_regs(4)
 384};
 385
 386static const struct dcn10_stream_encoder_shift se_shift = {
 387		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 388};
 389
 390static const struct dcn10_stream_encoder_mask se_mask = {
 391		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 392};
 393
 394static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
 395{
 396	struct dcn10_stream_encoder *enc1;
 397	struct vpg *vpg;
 398	struct afmt *afmt;
 399	int vpg_inst;
 400	int afmt_inst;
 401
 402	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
 403	if (eng_id <= ENGINE_ID_DIGE) {
 404		vpg_inst = eng_id;
 405		afmt_inst = eng_id;
 406	} else
 407		return NULL;
 408
 409	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
 410	vpg = dcn302_vpg_create(ctx, vpg_inst);
 411	afmt = dcn302_afmt_create(ctx, afmt_inst);
 412
 413	if (!enc1 || !vpg || !afmt) {
 414		kfree(enc1);
 415		kfree(vpg);
 416		kfree(afmt);
 417		return NULL;
 418	}
 419
 420	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
 421			&se_shift, &se_mask);
 422
 423	return &enc1->base;
 424}
 425
 426#define clk_src_regs(index, pllid)\
 427		[index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
 428
 429static const struct dce110_clk_src_regs clk_src_regs[] = {
 430		clk_src_regs(0, A),
 431		clk_src_regs(1, B),
 432		clk_src_regs(2, C),
 433		clk_src_regs(3, D),
 434		clk_src_regs(4, E)
 435};
 436
 437static const struct dce110_clk_src_shift cs_shift = {
 438		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 439};
 440
 441static const struct dce110_clk_src_mask cs_mask = {
 442		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 443};
 444
 445static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
 446		enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
 447{
 448	struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 449
 450	if (!clk_src)
 451		return NULL;
 452
 453	if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
 454		clk_src->base.dp_clk_src = dp_clk_src;
 455		return &clk_src->base;
 456	}
 457
 458	kfree(clk_src);
 459	BREAK_TO_DEBUGGER();
 460	return NULL;
 461}
 462
 463static const struct dce_hwseq_registers hwseq_reg = {
 464		HWSEQ_DCN302_REG_LIST()
 465};
 466
 467static const struct dce_hwseq_shift hwseq_shift = {
 468		HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
 469};
 470
 471static const struct dce_hwseq_mask hwseq_mask = {
 472		HWSEQ_DCN302_MASK_SH_LIST(_MASK)
 473};
 474
 475static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
 476{
 477	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 478
 479	if (hws) {
 480		hws->ctx = ctx;
 481		hws->regs = &hwseq_reg;
 482		hws->shifts = &hwseq_shift;
 483		hws->masks = &hwseq_mask;
 484	}
 485	return hws;
 486}
 487
 488#define hubp_regs(id)\
 489		[id] = { HUBP_REG_LIST_DCN30(id) }
 490
 491static const struct dcn_hubp2_registers hubp_regs[] = {
 492		hubp_regs(0),
 493		hubp_regs(1),
 494		hubp_regs(2),
 495		hubp_regs(3),
 496		hubp_regs(4)
 497};
 498
 499static const struct dcn_hubp2_shift hubp_shift = {
 500		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
 501};
 502
 503static const struct dcn_hubp2_mask hubp_mask = {
 504		HUBP_MASK_SH_LIST_DCN30(_MASK)
 505};
 506
 507static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
 508{
 509	struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
 510
 511	if (!hubp2)
 512		return NULL;
 513
 514	if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
 515		return &hubp2->base;
 516
 517	BREAK_TO_DEBUGGER();
 518	kfree(hubp2);
 519	return NULL;
 520}
 521
 522#define dpp_regs(id)\
 523		[id] = { DPP_REG_LIST_DCN30(id) }
 524
 525static const struct dcn3_dpp_registers dpp_regs[] = {
 526		dpp_regs(0),
 527		dpp_regs(1),
 528		dpp_regs(2),
 529		dpp_regs(3),
 530		dpp_regs(4)
 531};
 532
 533static const struct dcn3_dpp_shift tf_shift = {
 534		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 535};
 536
 537static const struct dcn3_dpp_mask tf_mask = {
 538		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 539};
 540
 541static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
 542{
 543	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 544
 545	if (!dpp)
 546		return NULL;
 547
 548	if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
 549		return &dpp->base;
 550
 551	BREAK_TO_DEBUGGER();
 552	kfree(dpp);
 553	return NULL;
 554}
 555
 556#define opp_regs(id)\
 557		[id] = { OPP_REG_LIST_DCN30(id) }
 558
 559static const struct dcn20_opp_registers opp_regs[] = {
 560		opp_regs(0),
 561		opp_regs(1),
 562		opp_regs(2),
 563		opp_regs(3),
 564		opp_regs(4)
 565};
 566
 567static const struct dcn20_opp_shift opp_shift = {
 568		OPP_MASK_SH_LIST_DCN20(__SHIFT)
 569};
 570
 571static const struct dcn20_opp_mask opp_mask = {
 572		OPP_MASK_SH_LIST_DCN20(_MASK)
 573};
 574
 575static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
 576{
 577	struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 578
 579	if (!opp) {
 580		BREAK_TO_DEBUGGER();
 581		return NULL;
 582	}
 583
 584	dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 585	return &opp->base;
 586}
 587
 588#define optc_regs(id)\
 589		[id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
 590
 591static const struct dcn_optc_registers optc_regs[] = {
 592		optc_regs(0),
 593		optc_regs(1),
 594		optc_regs(2),
 595		optc_regs(3),
 596		optc_regs(4)
 597};
 598
 599static const struct dcn_optc_shift optc_shift = {
 600		OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 601};
 602
 603static const struct dcn_optc_mask optc_mask = {
 604		OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 605};
 606
 607static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
 608{
 609	struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
 610
 611	if (!tgn10)
 612		return NULL;
 613
 614	tgn10->base.inst = instance;
 615	tgn10->base.ctx = ctx;
 616
 617	tgn10->tg_regs = &optc_regs[instance];
 618	tgn10->tg_shift = &optc_shift;
 619	tgn10->tg_mask = &optc_mask;
 620
 621	dcn30_timing_generator_init(tgn10);
 622
 623	return &tgn10->base;
 624}
 625
 626static const struct dcn30_mpc_registers mpc_regs = {
 627		MPC_REG_LIST_DCN3_0(0),
 628		MPC_REG_LIST_DCN3_0(1),
 629		MPC_REG_LIST_DCN3_0(2),
 630		MPC_REG_LIST_DCN3_0(3),
 631		MPC_REG_LIST_DCN3_0(4),
 632		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 633		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 634		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 635		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 636		MPC_OUT_MUX_REG_LIST_DCN3_0(4),
 637		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 638		MPC_RMU_REG_LIST_DCN3AG(0),
 639		MPC_RMU_REG_LIST_DCN3AG(1),
 640		MPC_RMU_REG_LIST_DCN3AG(2),
 641		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 642};
 643
 644static const struct dcn30_mpc_shift mpc_shift = {
 645		MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 646};
 647
 648static const struct dcn30_mpc_mask mpc_mask = {
 649		MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 650};
 651
 652static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
 653{
 654	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
 655
 656	if (!mpc30)
 657		return NULL;
 658
 659	dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
 660
 661	return &mpc30->base;
 662}
 663
 664#define dsc_regsDCN20(id)\
 665[id] = { DSC_REG_LIST_DCN20(id) }
 666
 667static const struct dcn20_dsc_registers dsc_regs[] = {
 668		dsc_regsDCN20(0),
 669		dsc_regsDCN20(1),
 670		dsc_regsDCN20(2),
 671		dsc_regsDCN20(3),
 672		dsc_regsDCN20(4)
 673};
 674
 675static const struct dcn20_dsc_shift dsc_shift = {
 676		DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 677};
 678
 679static const struct dcn20_dsc_mask dsc_mask = {
 680		DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 681};
 682
 683static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
 684{
 685	struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
 686
 687	if (!dsc) {
 688		BREAK_TO_DEBUGGER();
 689		return NULL;
 690	}
 691
 692	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
 693	return &dsc->base;
 694}
 695
 696#define dwbc_regs_dcn3(id)\
 697[id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
 698
 699static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 700		dwbc_regs_dcn3(0)
 701};
 702
 703static const struct dcn30_dwbc_shift dwbc30_shift = {
 704		DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 705};
 706
 707static const struct dcn30_dwbc_mask dwbc30_mask = {
 708		DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 709};
 710
 711static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
 712{
 713	int i;
 714	uint32_t pipe_count = pool->res_cap->num_dwb;
 715
 716	for (i = 0; i < pipe_count; i++) {
 717		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
 718
 719		if (!dwbc30) {
 720			dm_error("DC: failed to create dwbc30!\n");
 721			return false;
 722		}
 723
 724		dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
 725
 726		pool->dwbc[i] = &dwbc30->base;
 727	}
 728	return true;
 729}
 730
 731#define mcif_wb_regs_dcn3(id)\
 732[id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
 733
 734static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 735		mcif_wb_regs_dcn3(0)
 736};
 737
 738static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 739		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 740};
 741
 742static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 743		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 744};
 745
 746static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
 747{
 748	int i;
 749	uint32_t pipe_count = pool->res_cap->num_dwb;
 750
 751	for (i = 0; i < pipe_count; i++) {
 752		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
 753
 754		if (!mcif_wb30) {
 755			dm_error("DC: failed to create mcif_wb30!\n");
 756			return false;
 757		}
 758
 759		dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
 760
 761		pool->mcif_wb[i] = &mcif_wb30->base;
 762	}
 763	return true;
 764}
 765
 766#define aux_engine_regs(id)\
 767[id] = {\
 768		AUX_COMMON_REG_LIST0(id), \
 769		.AUXN_IMPCAL = 0, \
 770		.AUXP_IMPCAL = 0, \
 771		.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 772}
 773
 774static const struct dce110_aux_registers aux_engine_regs[] = {
 775		aux_engine_regs(0),
 776		aux_engine_regs(1),
 777		aux_engine_regs(2),
 778		aux_engine_regs(3),
 779		aux_engine_regs(4)
 780};
 781
 782static const struct dce110_aux_registers_shift aux_shift = {
 783		DCN_AUX_MASK_SH_LIST(__SHIFT)
 784};
 785
 786static const struct dce110_aux_registers_mask aux_mask = {
 787		DCN_AUX_MASK_SH_LIST(_MASK)
 788};
 789
 790static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
 791{
 792	struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 793
 794	if (!aux_engine)
 795		return NULL;
 796
 797	dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 798			&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
 799
 800	return &aux_engine->base;
 801}
 802
 803#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 804
 805static const struct dce_i2c_registers i2c_hw_regs[] = {
 806		i2c_inst_regs(1),
 807		i2c_inst_regs(2),
 808		i2c_inst_regs(3),
 809		i2c_inst_regs(4),
 810		i2c_inst_regs(5)
 811};
 812
 813static const struct dce_i2c_shift i2c_shifts = {
 814		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 815};
 816
 817static const struct dce_i2c_mask i2c_masks = {
 818		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 819};
 820
 821static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
 822{
 823	struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 824
 825	if (!dce_i2c_hw)
 826		return NULL;
 827
 828	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 829
 830	return dce_i2c_hw;
 831}
 832
 833static const struct encoder_feature_support link_enc_feature = {
 834		.max_hdmi_deep_color = COLOR_DEPTH_121212,
 835		.max_hdmi_pixel_clock = 600000,
 836		.hdmi_ycbcr420_supported = true,
 837		.dp_ycbcr420_supported = true,
 838		.fec_supported = true,
 839		.flags.bits.IS_HBR2_CAPABLE = true,
 840		.flags.bits.IS_HBR3_CAPABLE = true,
 841		.flags.bits.IS_TPS3_CAPABLE = true,
 842		.flags.bits.IS_TPS4_CAPABLE = true
 843};
 844
 845#define link_regs(id, phyid)\
 846		[id] = {\
 847				LE_DCN3_REG_LIST(id), \
 848				UNIPHY_DCN2_REG_LIST(phyid), \
 849				DPCS_DCN2_REG_LIST(id), \
 850				SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 851		}
 852
 853static const struct dcn10_link_enc_registers link_enc_regs[] = {
 854		link_regs(0, A),
 855		link_regs(1, B),
 856		link_regs(2, C),
 857		link_regs(3, D),
 858		link_regs(4, E)
 859};
 860
 861static const struct dcn10_link_enc_shift le_shift = {
 862		LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
 863		DPCS_DCN2_MASK_SH_LIST(__SHIFT)
 864};
 865
 866static const struct dcn10_link_enc_mask le_mask = {
 867		LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
 868		DPCS_DCN2_MASK_SH_LIST(_MASK)
 869};
 870
 871#define aux_regs(id)\
 872		[id] = { DCN2_AUX_REG_LIST(id) }
 873
 874static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 875		aux_regs(0),
 876		aux_regs(1),
 877		aux_regs(2),
 878		aux_regs(3),
 879		aux_regs(4)
 880};
 881
 882#define hpd_regs(id)\
 883		[id] = { HPD_REG_LIST(id) }
 884
 885static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 886		hpd_regs(0),
 887		hpd_regs(1),
 888		hpd_regs(2),
 889		hpd_regs(3),
 890		hpd_regs(4)
 891};
 892
 893static struct link_encoder *dcn302_link_encoder_create(
 894	struct dc_context *ctx,
 895	const struct encoder_init_data *enc_init_data)
 896{
 897	struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
 898
 899	if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
 900		return NULL;
 901
 902	dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
 903			&link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
 904			&link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
 905
 906	return &enc20->enc10.base;
 907}
 908
 909static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 910		{ DCN_PANEL_CNTL_REG_LIST() }
 911};
 912
 913static const struct dce_panel_cntl_shift panel_cntl_shift = {
 914		DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 915};
 916
 917static const struct dce_panel_cntl_mask panel_cntl_mask = {
 918		DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 919};
 920
 921static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
 922{
 923	struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
 924
 925	if (!panel_cntl)
 926		return NULL;
 927
 928	dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
 929			&panel_cntl_shift, &panel_cntl_mask);
 930
 931	return &panel_cntl->base;
 932}
 933
 934static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
 935{
 936	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 937			FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 938}
 939
 940static const struct resource_create_funcs res_create_funcs = {
 941		.read_dce_straps = read_dce_straps,
 942		.create_audio = dcn302_create_audio,
 943		.create_stream_encoder = dcn302_stream_encoder_create,
 944		.create_hwseq = dcn302_hwseq_create,
 945};
 946
 947static bool is_soc_bounding_box_valid(struct dc *dc)
 948{
 949	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
 950
 951	if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
 952		return true;
 953
 954	return false;
 955}
 956
 957static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
 958{
 959	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
 960	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
 961
 962	DC_LOGGER_INIT(dc->ctx->logger);
 963
 964	if (!is_soc_bounding_box_valid(dc)) {
 965		DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
 966		return false;
 967	}
 968
 969	loaded_ip->max_num_otg = pool->pipe_count;
 970	loaded_ip->max_num_dpp = pool->pipe_count;
 971	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
 972	DC_FP_START();
 973	dcn20_patch_bounding_box(dc, loaded_bb);
 974	DC_FP_END();
 975
 976	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
 977		struct bp_soc_bb_info bb_info = { 0 };
 978
 979		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
 980			    dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
 981
 982				DC_FP_START();
 983				dcn302_fpu_init_soc_bounding_box(bb_info);
 984				DC_FP_END();
 985		}
 986	}
 987
 988	return true;
 989}
 990
 991static void dcn302_resource_destruct(struct resource_pool *pool)
 992{
 993	unsigned int i;
 994
 995	for (i = 0; i < pool->stream_enc_count; i++) {
 996		if (pool->stream_enc[i] != NULL) {
 997			if (pool->stream_enc[i]->vpg != NULL) {
 998				kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
 999				pool->stream_enc[i]->vpg = NULL;
1000			}
1001			if (pool->stream_enc[i]->afmt != NULL) {
1002				kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
1003				pool->stream_enc[i]->afmt = NULL;
1004			}
1005			kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
1006			pool->stream_enc[i] = NULL;
1007		}
1008	}
1009
1010	for (i = 0; i < pool->res_cap->num_dsc; i++) {
1011		if (pool->dscs[i] != NULL)
1012			dcn20_dsc_destroy(&pool->dscs[i]);
1013	}
1014
1015	if (pool->mpc != NULL) {
1016		kfree(TO_DCN20_MPC(pool->mpc));
1017		pool->mpc = NULL;
1018	}
1019
1020	if (pool->hubbub != NULL) {
1021		kfree(pool->hubbub);
1022		pool->hubbub = NULL;
1023	}
1024
1025	for (i = 0; i < pool->pipe_count; i++) {
1026		if (pool->dpps[i] != NULL) {
1027			kfree(TO_DCN20_DPP(pool->dpps[i]));
1028			pool->dpps[i] = NULL;
1029		}
1030
1031		if (pool->hubps[i] != NULL) {
1032			kfree(TO_DCN20_HUBP(pool->hubps[i]));
1033			pool->hubps[i] = NULL;
1034		}
1035
1036		if (pool->irqs != NULL)
1037			dal_irq_service_destroy(&pool->irqs);
1038	}
1039
1040	for (i = 0; i < pool->res_cap->num_ddc; i++) {
1041		if (pool->engines[i] != NULL)
1042			dce110_engine_destroy(&pool->engines[i]);
1043		if (pool->hw_i2cs[i] != NULL) {
1044			kfree(pool->hw_i2cs[i]);
1045			pool->hw_i2cs[i] = NULL;
1046		}
1047		if (pool->sw_i2cs[i] != NULL) {
1048			kfree(pool->sw_i2cs[i]);
1049			pool->sw_i2cs[i] = NULL;
1050		}
1051	}
1052
1053	for (i = 0; i < pool->res_cap->num_opp; i++) {
1054		if (pool->opps[i] != NULL)
1055			pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1056	}
1057
1058	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1059		if (pool->timing_generators[i] != NULL)	{
1060			kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1061			pool->timing_generators[i] = NULL;
1062		}
1063	}
1064
1065	for (i = 0; i < pool->res_cap->num_dwb; i++) {
1066		if (pool->dwbc[i] != NULL) {
1067			kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1068			pool->dwbc[i] = NULL;
1069		}
1070		if (pool->mcif_wb[i] != NULL) {
1071			kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1072			pool->mcif_wb[i] = NULL;
1073		}
1074	}
1075
1076	for (i = 0; i < pool->audio_count; i++) {
1077		if (pool->audios[i])
1078			dce_aud_destroy(&pool->audios[i]);
1079	}
1080
1081	for (i = 0; i < pool->clk_src_count; i++) {
1082		if (pool->clock_sources[i] != NULL)
1083			dcn20_clock_source_destroy(&pool->clock_sources[i]);
1084	}
1085
1086	if (pool->dp_clock_source != NULL)
1087		dcn20_clock_source_destroy(&pool->dp_clock_source);
1088
1089	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1090		if (pool->mpc_lut[i] != NULL) {
1091			dc_3dlut_func_release(pool->mpc_lut[i]);
1092			pool->mpc_lut[i] = NULL;
1093		}
1094		if (pool->mpc_shaper[i] != NULL) {
1095			dc_transfer_func_release(pool->mpc_shaper[i]);
1096			pool->mpc_shaper[i] = NULL;
1097		}
1098	}
1099
1100	for (i = 0; i < pool->pipe_count; i++) {
1101		if (pool->multiple_abms[i] != NULL)
1102			dce_abm_destroy(&pool->multiple_abms[i]);
1103	}
1104
1105	if (pool->psr != NULL)
1106		dmub_psr_destroy(&pool->psr);
1107
1108	if (pool->dccg != NULL)
1109		dcn_dccg_destroy(&pool->dccg);
1110
1111	if (pool->oem_device != NULL) {
1112		struct dc *dc = pool->oem_device->ctx->dc;
1113
1114		dc->link_srv->destroy_ddc_service(&pool->oem_device);
1115	}
1116}
1117
1118static void dcn302_destroy_resource_pool(struct resource_pool **pool)
1119{
1120	dcn302_resource_destruct(*pool);
1121	kfree(*pool);
1122	*pool = NULL;
1123}
1124
1125void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1126{
1127	DC_FP_START();
1128	dcn302_fpu_update_bw_bounding_box(dc, bw_params);
1129	DC_FP_END();
1130}
1131
1132static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config)
1133{
1134	*panel_config = panel_config_defaults;
1135}
1136
1137static struct resource_funcs dcn302_res_pool_funcs = {
1138		.destroy = dcn302_destroy_resource_pool,
1139		.link_enc_create = dcn302_link_encoder_create,
1140		.panel_cntl_create = dcn302_panel_cntl_create,
1141		.validate_bandwidth = dcn30_validate_bandwidth,
1142		.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1143		.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1144		.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1145		.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1146		.release_pipe = dcn20_release_pipe,
1147		.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1148		.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1149		.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1150		.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1151		.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1152		.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1153		.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1154		.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1155		.update_bw_bounding_box = dcn302_update_bw_bounding_box,
1156		.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1157		.get_panel_config_defaults = dcn302_get_panel_config_defaults,
1158		.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
1159};
1160
1161static struct dc_cap_funcs cap_funcs = {
1162		.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1163};
1164
1165static const struct bios_registers bios_regs = {
1166		NBIO_SR(BIOS_SCRATCH_3),
1167		NBIO_SR(BIOS_SCRATCH_6)
1168};
1169
1170static const struct dccg_registers dccg_regs = {
1171		DCCG_REG_LIST_DCN3_02()
1172};
1173
1174static const struct dccg_shift dccg_shift = {
1175		DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
1176};
1177
1178static const struct dccg_mask dccg_mask = {
1179		DCCG_MASK_SH_LIST_DCN3_02(_MASK)
1180};
1181
1182#define abm_regs(id)\
1183		[id] = { ABM_DCN302_REG_LIST(id) }
1184
1185static const struct dce_abm_registers abm_regs[] = {
1186		abm_regs(0),
1187		abm_regs(1),
1188		abm_regs(2),
1189		abm_regs(3),
1190		abm_regs(4)
1191};
1192
1193static const struct dce_abm_shift abm_shift = {
1194		ABM_MASK_SH_LIST_DCN30(__SHIFT)
1195};
1196
1197static const struct dce_abm_mask abm_mask = {
1198		ABM_MASK_SH_LIST_DCN30(_MASK)
1199};
1200
1201static bool dcn302_resource_construct(
1202		uint8_t num_virtual_links,
1203		struct dc *dc,
1204		struct resource_pool *pool)
1205{
1206	int i;
1207	struct dc_context *ctx = dc->ctx;
1208	struct irq_service_init_data init_data;
1209	struct ddc_service_init_data ddc_init_data = {0};
1210
1211	ctx->dc_bios->regs = &bios_regs;
1212
1213	pool->res_cap = &res_cap_dcn302;
1214
1215	pool->funcs = &dcn302_res_pool_funcs;
1216
1217	/*************************************************
1218	 *  Resource + asic cap harcoding                *
1219	 *************************************************/
1220	pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1221	pool->pipe_count = pool->res_cap->num_timing_generator;
1222	pool->mpcc_count = pool->res_cap->num_timing_generator;
1223	dc->caps.max_downscale_ratio = 600;
1224	dc->caps.i2c_speed_in_khz = 100;
1225	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1226	dc->caps.max_cursor_size = 256;
1227	dc->caps.min_horizontal_blanking_period = 80;
1228	dc->caps.dmdata_alloc_size = 2048;
1229	dc->caps.mall_size_per_mem_channel = 4;
1230	/* total size = mall per channel * num channels * 1024 * 1024 */
1231	dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1232	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1233	dc->caps.max_slave_planes = 2;
1234	dc->caps.max_slave_yuv_planes = 2;
1235	dc->caps.max_slave_rgb_planes = 2;
1236	dc->caps.post_blend_color_processing = true;
1237	dc->caps.force_dp_tps4_for_cp2520 = true;
1238	dc->caps.extended_aux_timeout_support = true;
1239	dc->caps.dmcub_support = true;
1240	dc->caps.max_v_total = (1 << 15) - 1;
1241	dc->caps.vtotal_limited_by_fp2 = true;
1242
1243	/* Color pipeline capabilities */
1244	dc->caps.color.dpp.dcn_arch = 1;
1245	dc->caps.color.dpp.input_lut_shared = 0;
1246	dc->caps.color.dpp.icsc = 1;
1247	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1248	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1249	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1250	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1251	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1252	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1253	dc->caps.color.dpp.post_csc = 1;
1254	dc->caps.color.dpp.gamma_corr = 1;
1255	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1256
1257	dc->caps.color.dpp.hw_3d_lut = 1;
1258	dc->caps.color.dpp.ogam_ram = 1;
1259	// no OGAM ROM on DCN3
1260	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1261	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1262	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1263	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1264	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1265	dc->caps.color.dpp.ocsc = 0;
1266
1267	dc->caps.color.mpc.gamut_remap = 1;
1268	dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1269	dc->caps.color.mpc.ogam_ram = 1;
1270	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1271	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1272	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1273	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1274	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1275	dc->caps.color.mpc.ocsc = 1;
1276
1277	dc->caps.dp_hdmi21_pcon_support = true;
1278
1279	/* read VBIOS LTTPR caps */
1280	if (ctx->dc_bios->funcs->get_lttpr_caps) {
1281		enum bp_result bp_query_result;
1282		uint8_t is_vbios_lttpr_enable = 0;
1283
1284		bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1285		dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1286	}
1287
1288	if (ctx->dc_bios->funcs->get_lttpr_interop) {
1289		enum bp_result bp_query_result;
1290		uint8_t is_vbios_interop_enabled = 0;
1291
1292		bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
1293				&is_vbios_interop_enabled);
1294		dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1295	}
1296	dc->check_config = config_defaults;
1297
1298	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1299		dc->debug = debug_defaults_drv;
1300
1301	// Init the vm_helper
1302	if (dc->vm_helper)
1303		vm_helper_init(dc->vm_helper, 16);
1304
1305	/*************************************************
1306	 *  Create resources                             *
1307	 *************************************************/
1308
1309	/* Clock Sources for Pixel Clock*/
1310	pool->clock_sources[DCN302_CLK_SRC_PLL0] =
1311			dcn302_clock_source_create(ctx, ctx->dc_bios,
1312					CLOCK_SOURCE_COMBO_PHY_PLL0,
1313					&clk_src_regs[0], false);
1314	pool->clock_sources[DCN302_CLK_SRC_PLL1] =
1315			dcn302_clock_source_create(ctx, ctx->dc_bios,
1316					CLOCK_SOURCE_COMBO_PHY_PLL1,
1317					&clk_src_regs[1], false);
1318	pool->clock_sources[DCN302_CLK_SRC_PLL2] =
1319			dcn302_clock_source_create(ctx, ctx->dc_bios,
1320					CLOCK_SOURCE_COMBO_PHY_PLL2,
1321					&clk_src_regs[2], false);
1322	pool->clock_sources[DCN302_CLK_SRC_PLL3] =
1323			dcn302_clock_source_create(ctx, ctx->dc_bios,
1324					CLOCK_SOURCE_COMBO_PHY_PLL3,
1325					&clk_src_regs[3], false);
1326	pool->clock_sources[DCN302_CLK_SRC_PLL4] =
1327			dcn302_clock_source_create(ctx, ctx->dc_bios,
1328					CLOCK_SOURCE_COMBO_PHY_PLL4,
1329					&clk_src_regs[4], false);
1330
1331	pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
1332
1333	/* todo: not reuse phy_pll registers */
1334	pool->dp_clock_source =
1335			dcn302_clock_source_create(ctx, ctx->dc_bios,
1336					CLOCK_SOURCE_ID_DP_DTO,
1337					&clk_src_regs[0], true);
1338
1339	for (i = 0; i < pool->clk_src_count; i++) {
1340		if (pool->clock_sources[i] == NULL) {
1341			dm_error("DC: failed to create clock sources!\n");
1342			BREAK_TO_DEBUGGER();
1343			goto create_fail;
1344		}
1345	}
1346
1347	/* DCCG */
1348	pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1349	if (pool->dccg == NULL) {
1350		dm_error("DC: failed to create dccg!\n");
1351		BREAK_TO_DEBUGGER();
1352		goto create_fail;
1353	}
1354
1355	/* PP Lib and SMU interfaces */
1356	init_soc_bounding_box(dc, pool);
1357
1358	/* DML */
1359	dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1360
1361	/* IRQ */
1362	init_data.ctx = dc->ctx;
1363	pool->irqs = dal_irq_service_dcn302_create(&init_data);
1364	if (!pool->irqs)
1365		goto create_fail;
1366
1367	/* HUBBUB */
1368	pool->hubbub = dcn302_hubbub_create(ctx);
1369	if (pool->hubbub == NULL) {
1370		BREAK_TO_DEBUGGER();
1371		dm_error("DC: failed to create hubbub!\n");
1372		goto create_fail;
1373	}
1374
1375	/* HUBPs, DPPs, OPPs and TGs */
1376	for (i = 0; i < pool->pipe_count; i++) {
1377		pool->hubps[i] = dcn302_hubp_create(ctx, i);
1378		if (pool->hubps[i] == NULL) {
1379			BREAK_TO_DEBUGGER();
1380			dm_error("DC: failed to create hubps!\n");
1381			goto create_fail;
1382		}
1383
1384		pool->dpps[i] = dcn302_dpp_create(ctx, i);
1385		if (pool->dpps[i] == NULL) {
1386			BREAK_TO_DEBUGGER();
1387			dm_error("DC: failed to create dpps!\n");
1388			goto create_fail;
1389		}
1390	}
1391
1392	for (i = 0; i < pool->res_cap->num_opp; i++) {
1393		pool->opps[i] = dcn302_opp_create(ctx, i);
1394		if (pool->opps[i] == NULL) {
1395			BREAK_TO_DEBUGGER();
1396			dm_error("DC: failed to create output pixel processor!\n");
1397			goto create_fail;
1398		}
1399	}
1400
1401	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1402		pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
1403		if (pool->timing_generators[i] == NULL) {
1404			BREAK_TO_DEBUGGER();
1405			dm_error("DC: failed to create tg!\n");
1406			goto create_fail;
1407		}
1408	}
1409	pool->timing_generator_count = i;
1410
1411	/* PSR */
1412	pool->psr = dmub_psr_create(ctx);
1413	if (pool->psr == NULL) {
1414		dm_error("DC: failed to create psr!\n");
1415		BREAK_TO_DEBUGGER();
1416		goto create_fail;
1417	}
1418
1419	/* ABMs */
1420	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1421		pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1422		if (pool->multiple_abms[i] == NULL) {
1423			dm_error("DC: failed to create abm for pipe %d!\n", i);
1424			BREAK_TO_DEBUGGER();
1425			goto create_fail;
1426		}
1427	}
1428
1429	/* MPC and DSC */
1430	pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1431	if (pool->mpc == NULL) {
1432		BREAK_TO_DEBUGGER();
1433		dm_error("DC: failed to create mpc!\n");
1434		goto create_fail;
1435	}
1436
1437	for (i = 0; i < pool->res_cap->num_dsc; i++) {
1438		pool->dscs[i] = dcn302_dsc_create(ctx, i);
1439		if (pool->dscs[i] == NULL) {
1440			BREAK_TO_DEBUGGER();
1441			dm_error("DC: failed to create display stream compressor %d!\n", i);
1442			goto create_fail;
1443		}
1444	}
1445
1446	/* DWB and MMHUBBUB */
1447	if (!dcn302_dwbc_create(ctx, pool)) {
1448		BREAK_TO_DEBUGGER();
1449		dm_error("DC: failed to create dwbc!\n");
1450		goto create_fail;
1451	}
1452
1453	if (!dcn302_mmhubbub_create(ctx, pool)) {
1454		BREAK_TO_DEBUGGER();
1455		dm_error("DC: failed to create mcif_wb!\n");
1456		goto create_fail;
1457	}
1458
1459	/* AUX and I2C */
1460	for (i = 0; i < pool->res_cap->num_ddc; i++) {
1461		pool->engines[i] = dcn302_aux_engine_create(ctx, i);
1462		if (pool->engines[i] == NULL) {
1463			BREAK_TO_DEBUGGER();
1464			dm_error("DC:failed to create aux engine!!\n");
1465			goto create_fail;
1466		}
1467		pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
1468		if (pool->hw_i2cs[i] == NULL) {
1469			BREAK_TO_DEBUGGER();
1470			dm_error("DC:failed to create hw i2c!!\n");
1471			goto create_fail;
1472		}
1473		pool->sw_i2cs[i] = NULL;
1474	}
1475
1476	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1477	if (!resource_construct(num_virtual_links, dc, pool,
1478			&res_create_funcs))
1479		goto create_fail;
1480
1481	/* HW Sequencer and Plane caps */
1482	dcn302_hw_sequencer_construct(dc);
1483
1484	dc->caps.max_planes =  pool->pipe_count;
1485
1486	for (i = 0; i < dc->caps.max_planes; ++i)
1487		dc->caps.planes[i] = plane_cap;
1488
1489	dc->caps.max_odm_combine_factor = 4;
1490
1491	dc->cap_funcs = cap_funcs;
1492
1493	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1494		ddc_init_data.ctx = dc->ctx;
1495		ddc_init_data.link = NULL;
1496		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1497		ddc_init_data.id.enum_id = 0;
1498		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1499		pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
1500	} else {
1501		pool->oem_device = NULL;
1502	}
1503
1504	return true;
1505
1506create_fail:
1507
1508	dcn302_resource_destruct(pool);
1509
1510	return false;
1511}
1512
1513struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1514{
1515	struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1516
1517	if (!pool)
1518		return NULL;
1519
1520	if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
1521		return pool;
1522
1523	BREAK_TO_DEBUGGER();
1524	kfree(pool);
1525	return NULL;
1526}