dcn301_resource.c

   1/*
   2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26
  27#include "dm_services.h"
  28#include "dc.h"
  29
  30#include "dcn301/dcn301_init.h"
  31
  32#include "resource.h"
  33#include "include/irq_service_interface.h"
  34#include "dcn30/dcn30_resource.h"
  35#include "dcn301_resource.h"
  36
  37#include "dcn20/dcn20_resource.h"
  38
  39#include "dcn10/dcn10_ipp.h"
  40#include "dcn301/dcn301_hubbub.h"
  41#include "dcn30/dcn30_mpc.h"
  42#include "dcn30/dcn30_hubp.h"
  43#include "irq/dcn30/irq_service_dcn30.h"
  44#include "dcn30/dcn30_dpp.h"
  45#include "dcn301/dcn301_optc.h"
  46#include "dcn20/dcn20_hwseq.h"
  47#include "dcn30/dcn30_hwseq.h"
  48#include "dce110/dce110_hwseq.h"
  49#include "dcn30/dcn30_opp.h"
  50#include "dcn20/dcn20_dsc.h"
  51#include "dcn30/dcn30_vpg.h"
  52#include "dcn30/dcn30_afmt.h"
  53#include "dce/dce_clock_source.h"
  54#include "dce/dce_audio.h"
  55#include "dce/dce_hwseq.h"
  56#include "clk_mgr.h"
  57#include "virtual/virtual_stream_encoder.h"
  58#include "dce110/dce110_resource.h"
  59#include "dml/display_mode_vba.h"
  60#include "dcn301/dcn301_dccg.h"
  61#include "dcn10/dcn10_resource.h"
  62#include "dcn30/dcn30_dio_stream_encoder.h"
  63#include "dcn301/dcn301_dio_link_encoder.h"
  64#include "dcn301/dcn301_panel_cntl.h"
  65
  66#include "vangogh_ip_offset.h"
  67
  68#include "dcn30/dcn30_dwb.h"
  69#include "dcn30/dcn30_mmhubbub.h"
  70
  71#include "dcn/dcn_3_0_1_offset.h"
  72#include "dcn/dcn_3_0_1_sh_mask.h"
  73
  74#include "nbio/nbio_7_2_0_offset.h"
  75
  76#include "dpcs/dpcs_3_0_0_offset.h"
  77#include "dpcs/dpcs_3_0_0_sh_mask.h"
  78
  79#include "reg_helper.h"
  80#include "dce/dmub_abm.h"
  81#include "dce/dce_aux.h"
  82#include "dce/dce_i2c.h"
  83
  84#include "dml/dcn30/dcn30_fpu.h"
  85
  86#include "dml/dcn30/display_mode_vba_30.h"
  87#include "dml/dcn301/dcn301_fpu.h"
  88#include "vm_helper.h"
  89#include "dcn20/dcn20_vmid.h"
  90#include "amdgpu_socbb.h"
  91
  92#define TO_DCN301_RES_POOL(pool)\
  93	container_of(pool, struct dcn301_resource_pool, base)
  94
  95#define DC_LOGGER \
  96	dc->ctx->logger
  97#define DC_LOGGER_INIT(logger)
  98
  99enum dcn301_clk_src_array_id {
 100	DCN301_CLK_SRC_PLL0,
 101	DCN301_CLK_SRC_PLL1,
 102	DCN301_CLK_SRC_PLL2,
 103	DCN301_CLK_SRC_PLL3,
 104	DCN301_CLK_SRC_TOTAL
 105};
 106
 107/* begin *********************
 108 * macros to expend register list macro defined in HW object header file
 109 */
 110
 111/* DCN */
 112#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 113
 114#define BASE(seg) BASE_INNER(seg)
 115
 116#define SR(reg_name)\
 117		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 118					mm ## reg_name
 119
 120#define SRI(reg_name, block, id)\
 121	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 122					mm ## block ## id ## _ ## reg_name
 123
 124#define SRI2(reg_name, block, id)\
 125	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
 126					mm ## reg_name
 127
 128#define SRIR(var_name, reg_name, block, id)\
 129	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 130					mm ## block ## id ## _ ## reg_name
 131
 132#define SRII(reg_name, block, id)\
 133	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 134					mm ## block ## id ## _ ## reg_name
 135
 136#define SRII2(reg_name_pre, reg_name_post, id)\
 137	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(mm ## reg_name_pre \
 138			## id ## _ ## reg_name_post ## _BASE_IDX) + \
 139			mm ## reg_name_pre ## id ## _ ## reg_name_post
 140
 141#define SRII_MPC_RMU(reg_name, block, id)\
 142	.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 143					mm ## block ## id ## _ ## reg_name
 144
 145#define SRII_DWB(reg_name, temp_name, block, id)\
 146	.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 147					mm ## block ## id ## _ ## temp_name
 148
 149#define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
 150	.field_name = reg_name ## __ ## field_name ## post_fix
 151
 152#define DCCG_SRII(reg_name, block, id)\
 153	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 154					mm ## block ## id ## _ ## reg_name
 155
 156#define VUPDATE_SRII(reg_name, block, id)\
 157	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 158					mm ## reg_name ## _ ## block ## id
 159
 160/* NBIO */
 161#define NBIO_BASE_INNER(seg) \
 162	NBIO_BASE__INST0_SEG ## seg
 163
 164#define NBIO_BASE(seg) \
 165	NBIO_BASE_INNER(seg)
 166
 167#define NBIO_SR(reg_name)\
 168		.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
 169					regBIF_BX0_ ## reg_name
 170
 171/* MMHUB */
 172#define MMHUB_BASE_INNER(seg) \
 173	MMHUB_BASE__INST0_SEG ## seg
 174
 175#define MMHUB_BASE(seg) \
 176	MMHUB_BASE_INNER(seg)
 177
 178#define MMHUB_SR(reg_name)\
 179		.reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
 180					regMM ## reg_name
 181
 182/* CLOCK */
 183#define CLK_BASE_INNER(seg) \
 184	CLK_BASE__INST0_SEG ## seg
 185
 186#define CLK_BASE(seg) \
 187	CLK_BASE_INNER(seg)
 188
 189#define CLK_SRI(reg_name, block, inst)\
 190	.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 191					mm ## block ## _ ## inst ## _ ## reg_name
 192
 193static const struct bios_registers bios_regs = {
 194		NBIO_SR(BIOS_SCRATCH_3),
 195		NBIO_SR(BIOS_SCRATCH_6)
 196};
 197
 198#define clk_src_regs(index, pllid)\
 199[index] = {\
 200	CS_COMMON_REG_LIST_DCN3_01(index, pllid),\
 201}
 202
 203static const struct dce110_clk_src_regs clk_src_regs[] = {
 204	clk_src_regs(0, A),
 205	clk_src_regs(1, B),
 206	clk_src_regs(2, C),
 207	clk_src_regs(3, D)
 208};
 209
 210static const struct dce110_clk_src_shift cs_shift = {
 211		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 212};
 213
 214static const struct dce110_clk_src_mask cs_mask = {
 215		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 216};
 217
 218#define abm_regs(id)\
 219[id] = {\
 220		ABM_DCN301_REG_LIST(id)\
 221}
 222
 223static const struct dce_abm_registers abm_regs[] = {
 224		abm_regs(0),
 225		abm_regs(1),
 226		abm_regs(2),
 227		abm_regs(3),
 228};
 229
 230static const struct dce_abm_shift abm_shift = {
 231		ABM_MASK_SH_LIST_DCN30(__SHIFT)
 232};
 233
 234static const struct dce_abm_mask abm_mask = {
 235		ABM_MASK_SH_LIST_DCN30(_MASK)
 236};
 237
 238#define audio_regs(id)\
 239[id] = {\
 240		AUD_COMMON_REG_LIST(id)\
 241}
 242
 243static const struct dce_audio_registers audio_regs[] = {
 244	audio_regs(0),
 245	audio_regs(1),
 246	audio_regs(2),
 247	audio_regs(3),
 248	audio_regs(4),
 249	audio_regs(5),
 250	audio_regs(6)
 251};
 252
 253#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 254		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 255		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 256		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 257
 258static const struct dce_audio_shift audio_shift = {
 259		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 260};
 261
 262static const struct dce_audio_mask audio_mask = {
 263		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 264};
 265
 266#define vpg_regs(id)\
 267[id] = {\
 268	VPG_DCN3_REG_LIST(id)\
 269}
 270
 271static const struct dcn30_vpg_registers vpg_regs[] = {
 272	vpg_regs(0),
 273	vpg_regs(1),
 274	vpg_regs(2),
 275	vpg_regs(3),
 276};
 277
 278static const struct dcn30_vpg_shift vpg_shift = {
 279	DCN3_VPG_MASK_SH_LIST(__SHIFT)
 280};
 281
 282static const struct dcn30_vpg_mask vpg_mask = {
 283	DCN3_VPG_MASK_SH_LIST(_MASK)
 284};
 285
 286#define afmt_regs(id)\
 287[id] = {\
 288	AFMT_DCN3_REG_LIST(id)\
 289}
 290
 291static const struct dcn30_afmt_registers afmt_regs[] = {
 292	afmt_regs(0),
 293	afmt_regs(1),
 294	afmt_regs(2),
 295	afmt_regs(3),
 296};
 297
 298static const struct dcn30_afmt_shift afmt_shift = {
 299	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 300};
 301
 302static const struct dcn30_afmt_mask afmt_mask = {
 303	DCN3_AFMT_MASK_SH_LIST(_MASK)
 304};
 305
 306#define stream_enc_regs(id)\
 307[id] = {\
 308	SE_DCN3_REG_LIST(id)\
 309}
 310
 311static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 312	stream_enc_regs(0),
 313	stream_enc_regs(1),
 314	stream_enc_regs(2),
 315	stream_enc_regs(3),
 316};
 317
 318static const struct dcn10_stream_encoder_shift se_shift = {
 319		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 320};
 321
 322static const struct dcn10_stream_encoder_mask se_mask = {
 323		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 324};
 325
 326
 327#define aux_regs(id)\
 328[id] = {\
 329	DCN2_AUX_REG_LIST(id)\
 330}
 331
 332static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 333		aux_regs(0),
 334		aux_regs(1),
 335		aux_regs(2),
 336		aux_regs(3),
 337};
 338
 339#define hpd_regs(id)\
 340[id] = {\
 341	HPD_REG_LIST(id)\
 342}
 343
 344static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 345		hpd_regs(0),
 346		hpd_regs(1),
 347		hpd_regs(2),
 348		hpd_regs(3),
 349};
 350
 351
 352#define link_regs(id, phyid)\
 353[id] = {\
 354	LE_DCN301_REG_LIST(id), \
 355	UNIPHY_DCN2_REG_LIST(phyid), \
 356	DPCS_DCN2_REG_LIST(id), \
 357	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 358}
 359
 360static const struct dce110_aux_registers_shift aux_shift = {
 361	DCN_AUX_MASK_SH_LIST(__SHIFT)
 362};
 363
 364static const struct dce110_aux_registers_mask aux_mask = {
 365	DCN_AUX_MASK_SH_LIST(_MASK)
 366};
 367
 368static const struct dcn10_link_enc_registers link_enc_regs[] = {
 369	link_regs(0, A),
 370	link_regs(1, B),
 371	link_regs(2, C),
 372	link_regs(3, D),
 373};
 374
 375static const struct dcn10_link_enc_shift le_shift = {
 376	LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\
 377	DPCS_DCN2_MASK_SH_LIST(__SHIFT)
 378};
 379
 380static const struct dcn10_link_enc_mask le_mask = {
 381	LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\
 382	DPCS_DCN2_MASK_SH_LIST(_MASK)
 383};
 384
 385#define panel_cntl_regs(id)\
 386[id] = {\
 387	DCN301_PANEL_CNTL_REG_LIST(id),\
 388}
 389
 390static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 391	panel_cntl_regs(0),
 392	panel_cntl_regs(1),
 393};
 394
 395static const struct dcn301_panel_cntl_shift panel_cntl_shift = {
 396	DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 397};
 398
 399static const struct dcn301_panel_cntl_mask panel_cntl_mask = {
 400	DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK)
 401};
 402
 403#define dpp_regs(id)\
 404[id] = {\
 405	DPP_REG_LIST_DCN30(id),\
 406}
 407
 408static const struct dcn3_dpp_registers dpp_regs[] = {
 409	dpp_regs(0),
 410	dpp_regs(1),
 411	dpp_regs(2),
 412	dpp_regs(3),
 413};
 414
 415static const struct dcn3_dpp_shift tf_shift = {
 416		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 417};
 418
 419static const struct dcn3_dpp_mask tf_mask = {
 420		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 421};
 422
 423#define opp_regs(id)\
 424[id] = {\
 425	OPP_REG_LIST_DCN30(id),\
 426}
 427
 428static const struct dcn20_opp_registers opp_regs[] = {
 429	opp_regs(0),
 430	opp_regs(1),
 431	opp_regs(2),
 432	opp_regs(3),
 433};
 434
 435static const struct dcn20_opp_shift opp_shift = {
 436	OPP_MASK_SH_LIST_DCN20(__SHIFT)
 437};
 438
 439static const struct dcn20_opp_mask opp_mask = {
 440	OPP_MASK_SH_LIST_DCN20(_MASK)
 441};
 442
 443#define aux_engine_regs(id)\
 444[id] = {\
 445	AUX_COMMON_REG_LIST0(id), \
 446	.AUXN_IMPCAL = 0, \
 447	.AUXP_IMPCAL = 0, \
 448	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 449}
 450
 451static const struct dce110_aux_registers aux_engine_regs[] = {
 452		aux_engine_regs(0),
 453		aux_engine_regs(1),
 454		aux_engine_regs(2),
 455		aux_engine_regs(3),
 456};
 457
 458#define dwbc_regs_dcn3(id)\
 459[id] = {\
 460	DWBC_COMMON_REG_LIST_DCN30(id),\
 461}
 462
 463static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 464	dwbc_regs_dcn3(0),
 465};
 466
 467static const struct dcn30_dwbc_shift dwbc30_shift = {
 468	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 469};
 470
 471static const struct dcn30_dwbc_mask dwbc30_mask = {
 472	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 473};
 474
 475#define mcif_wb_regs_dcn3(id)\
 476[id] = {\
 477	MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 478}
 479
 480static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 481	mcif_wb_regs_dcn3(0)
 482};
 483
 484static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 485	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 486};
 487
 488static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 489	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 490};
 491
 492#define dsc_regsDCN20(id)\
 493[id] = {\
 494	DSC_REG_LIST_DCN20(id)\
 495}
 496
 497static const struct dcn20_dsc_registers dsc_regs[] = {
 498	dsc_regsDCN20(0),
 499	dsc_regsDCN20(1),
 500	dsc_regsDCN20(2),
 501};
 502
 503static const struct dcn20_dsc_shift dsc_shift = {
 504	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 505};
 506
 507static const struct dcn20_dsc_mask dsc_mask = {
 508	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 509};
 510
 511static const struct dcn30_mpc_registers mpc_regs = {
 512		MPC_REG_LIST_DCN3_0(0),
 513		MPC_REG_LIST_DCN3_0(1),
 514		MPC_REG_LIST_DCN3_0(2),
 515		MPC_REG_LIST_DCN3_0(3),
 516		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 517		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 518		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 519		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 520		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 521		MPC_RMU_REG_LIST_DCN3AG(0),
 522		MPC_RMU_REG_LIST_DCN3AG(1),
 523		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 524};
 525
 526static const struct dcn30_mpc_shift mpc_shift = {
 527	MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 528};
 529
 530static const struct dcn30_mpc_mask mpc_mask = {
 531	MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 532};
 533
 534#define optc_regs(id)\
 535[id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
 536
 537
 538static const struct dcn_optc_registers optc_regs[] = {
 539	optc_regs(0),
 540	optc_regs(1),
 541	optc_regs(2),
 542	optc_regs(3),
 543};
 544
 545static const struct dcn_optc_shift optc_shift = {
 546	OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 547};
 548
 549static const struct dcn_optc_mask optc_mask = {
 550	OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 551};
 552
 553#define hubp_regs(id)\
 554[id] = {\
 555	HUBP_REG_LIST_DCN30(id)\
 556}
 557
 558static const struct dcn_hubp2_registers hubp_regs[] = {
 559		hubp_regs(0),
 560		hubp_regs(1),
 561		hubp_regs(2),
 562		hubp_regs(3),
 563};
 564
 565static const struct dcn_hubp2_shift hubp_shift = {
 566		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
 567};
 568
 569static const struct dcn_hubp2_mask hubp_mask = {
 570		HUBP_MASK_SH_LIST_DCN30(_MASK)
 571};
 572
 573static const struct dcn_hubbub_registers hubbub_reg = {
 574		HUBBUB_REG_LIST_DCN301(0)
 575};
 576
 577static const struct dcn_hubbub_shift hubbub_shift = {
 578		HUBBUB_MASK_SH_LIST_DCN301(__SHIFT)
 579};
 580
 581static const struct dcn_hubbub_mask hubbub_mask = {
 582		HUBBUB_MASK_SH_LIST_DCN301(_MASK)
 583};
 584
 585static const struct dccg_registers dccg_regs = {
 586		DCCG_REG_LIST_DCN301()
 587};
 588
 589static const struct dccg_shift dccg_shift = {
 590		DCCG_MASK_SH_LIST_DCN301(__SHIFT)
 591};
 592
 593static const struct dccg_mask dccg_mask = {
 594		DCCG_MASK_SH_LIST_DCN301(_MASK)
 595};
 596
 597static const struct dce_hwseq_registers hwseq_reg = {
 598		HWSEQ_DCN301_REG_LIST()
 599};
 600
 601static const struct dce_hwseq_shift hwseq_shift = {
 602		HWSEQ_DCN301_MASK_SH_LIST(__SHIFT)
 603};
 604
 605static const struct dce_hwseq_mask hwseq_mask = {
 606		HWSEQ_DCN301_MASK_SH_LIST(_MASK)
 607};
 608#define vmid_regs(id)\
 609[id] = {\
 610		DCN20_VMID_REG_LIST(id)\
 611}
 612
 613static const struct dcn_vmid_registers vmid_regs[] = {
 614	vmid_regs(0),
 615	vmid_regs(1),
 616	vmid_regs(2),
 617	vmid_regs(3),
 618	vmid_regs(4),
 619	vmid_regs(5),
 620	vmid_regs(6),
 621	vmid_regs(7),
 622	vmid_regs(8),
 623	vmid_regs(9),
 624	vmid_regs(10),
 625	vmid_regs(11),
 626	vmid_regs(12),
 627	vmid_regs(13),
 628	vmid_regs(14),
 629	vmid_regs(15)
 630};
 631
 632static const struct dcn20_vmid_shift vmid_shifts = {
 633		DCN20_VMID_MASK_SH_LIST(__SHIFT)
 634};
 635
 636static const struct dcn20_vmid_mask vmid_masks = {
 637		DCN20_VMID_MASK_SH_LIST(_MASK)
 638};
 639
 640static struct resource_caps res_cap_dcn301 = {
 641	.num_timing_generator = 4,
 642	.num_opp = 4,
 643	.num_video_plane = 4,
 644	.num_audio = 4,
 645	.num_stream_encoder = 4,
 646	.num_pll = 4,
 647	.num_dwb = 1,
 648	.num_ddc = 4,
 649	.num_vmid = 16,
 650	.num_mpc_3dlut = 2,
 651	.num_dsc = 3,
 652};
 653
 654static const struct dc_plane_cap plane_cap = {
 655	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 656	.per_pixel_alpha = true,
 657
 658	.pixel_format_support = {
 659			.argb8888 = true,
 660			.nv12 = true,
 661			.fp16 = true,
 662			.p010 = true,
 663			.ayuv = false,
 664	},
 665
 666	.max_upscale_factor = {
 667			.argb8888 = 16000,
 668			.nv12 = 16000,
 669			.fp16 = 16000
 670	},
 671
 672	/* 6:1 downscaling ratio: 1000/6 = 166.666 */
 673	.max_downscale_factor = {
 674			.argb8888 = 358,
 675			.nv12 = 358,
 676			.fp16 = 358
 677	},
 678	64,
 679	64
 680};
 681
 682static const struct dc_debug_options debug_defaults_drv = {
 683	.disable_dmcu = true,
 684	.force_abm_enable = false,
 685	.clock_trace = true,
 686	.disable_dpp_power_gate = false,
 687	.disable_hubp_power_gate = false,
 688	.disable_clock_gate = true,
 689	.disable_pplib_clock_request = true,
 690	.disable_pplib_wm_range = true,
 691	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
 692	.force_single_disp_pipe_split = false,
 693	.disable_dcc = DCC_ENABLE,
 694	.vsr_support = true,
 695	.performance_trace = false,
 696	.max_downscale_src_width = 4096,/*upto true 4k*/
 697	.scl_reset_length10 = true,
 698	.sanity_checks = false,
 699	.underflow_assert_delay_us = 0xFFFFFFFF,
 700	.dwb_fi_phase = -1, // -1 = disable
 701	.dmub_command_table = true,
 702	.use_max_lb = false,
 703	.exit_idle_opt_for_cursor_updates = true,
 704	.using_dml2 = false,
 705};
 706
 707static const struct dc_check_config config_defaults = {
 708	.enable_legacy_fast_update = true,
 709};
 710
 711static void dcn301_dpp_destroy(struct dpp **dpp)
 712{
 713	kfree(TO_DCN20_DPP(*dpp));
 714	*dpp = NULL;
 715}
 716
 717static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)
 718{
 719	struct dcn3_dpp *dpp =
 720		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 721
 722	if (!dpp)
 723		return NULL;
 724
 725	if (dpp3_construct(dpp, ctx, inst,
 726			&dpp_regs[inst], &tf_shift, &tf_mask))
 727		return &dpp->base;
 728
 729	BREAK_TO_DEBUGGER();
 730	kfree(dpp);
 731	return NULL;
 732}
 733static struct output_pixel_processor *dcn301_opp_create(struct dc_context *ctx,
 734							uint32_t inst)
 735{
 736	struct dcn20_opp *opp =
 737		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 738
 739	if (!opp) {
 740		BREAK_TO_DEBUGGER();
 741		return NULL;
 742	}
 743
 744	dcn20_opp_construct(opp, ctx, inst,
 745			&opp_regs[inst], &opp_shift, &opp_mask);
 746	return &opp->base;
 747}
 748
 749static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst)
 750{
 751	struct aux_engine_dce110 *aux_engine =
 752		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 753
 754	if (!aux_engine)
 755		return NULL;
 756
 757	dce110_aux_engine_construct(aux_engine, ctx, inst,
 758				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 759				    &aux_engine_regs[inst],
 760					&aux_mask,
 761					&aux_shift,
 762					ctx->dc->caps.extended_aux_timeout_support);
 763
 764	return &aux_engine->base;
 765}
 766#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 767
 768static const struct dce_i2c_registers i2c_hw_regs[] = {
 769		i2c_inst_regs(1),
 770		i2c_inst_regs(2),
 771		i2c_inst_regs(3),
 772		i2c_inst_regs(4),
 773};
 774
 775static const struct dce_i2c_shift i2c_shifts = {
 776		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 777};
 778
 779static const struct dce_i2c_mask i2c_masks = {
 780		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 781};
 782
 783static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
 784{
 785	struct dce_i2c_hw *dce_i2c_hw =
 786		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 787
 788	if (!dce_i2c_hw)
 789		return NULL;
 790
 791	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 792				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 793
 794	return dce_i2c_hw;
 795}
 796static struct mpc *dcn301_mpc_create(
 797		struct dc_context *ctx,
 798		int num_mpcc,
 799		int num_rmu)
 800{
 801	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
 802					  GFP_KERNEL);
 803
 804	if (!mpc30)
 805		return NULL;
 806
 807	dcn30_mpc_construct(mpc30, ctx,
 808			&mpc_regs,
 809			&mpc_shift,
 810			&mpc_mask,
 811			num_mpcc,
 812			num_rmu);
 813
 814	return &mpc30->base;
 815}
 816
 817static struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
 818{
 819	int i;
 820
 821	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
 822					  GFP_KERNEL);
 823
 824	if (!hubbub3)
 825		return NULL;
 826
 827	hubbub301_construct(hubbub3, ctx,
 828			&hubbub_reg,
 829			&hubbub_shift,
 830			&hubbub_mask);
 831
 832
 833	for (i = 0; i < res_cap_dcn301.num_vmid; i++) {
 834		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
 835
 836		vmid->ctx = ctx;
 837
 838		vmid->regs = &vmid_regs[i];
 839		vmid->shifts = &vmid_shifts;
 840		vmid->masks = &vmid_masks;
 841	}
 842
 843	hubbub3->num_vmid = res_cap_dcn301.num_vmid;
 844
 845	return &hubbub3->base;
 846}
 847
 848static struct timing_generator *dcn301_timing_generator_create(
 849	struct dc_context *ctx, uint32_t instance)
 850{
 851	struct optc *tgn10 =
 852		kzalloc(sizeof(struct optc), GFP_KERNEL);
 853
 854	if (!tgn10)
 855		return NULL;
 856
 857	tgn10->base.inst = instance;
 858	tgn10->base.ctx = ctx;
 859
 860	tgn10->tg_regs = &optc_regs[instance];
 861	tgn10->tg_shift = &optc_shift;
 862	tgn10->tg_mask = &optc_mask;
 863
 864	dcn301_timing_generator_init(tgn10);
 865
 866	return &tgn10->base;
 867}
 868
 869static const struct encoder_feature_support link_enc_feature = {
 870		.max_hdmi_deep_color = COLOR_DEPTH_121212,
 871		.max_hdmi_pixel_clock = 600000,
 872		.hdmi_ycbcr420_supported = true,
 873		.dp_ycbcr420_supported = true,
 874		.fec_supported = true,
 875		.flags.bits.IS_HBR2_CAPABLE = true,
 876		.flags.bits.IS_HBR3_CAPABLE = true,
 877		.flags.bits.IS_TPS3_CAPABLE = true,
 878		.flags.bits.IS_TPS4_CAPABLE = true
 879};
 880
 881static struct link_encoder *dcn301_link_encoder_create(
 882	struct dc_context *ctx,
 883	const struct encoder_init_data *enc_init_data)
 884{
 885	struct dcn20_link_encoder *enc20 =
 886		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
 887
 888	if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
 889		return NULL;
 890
 891	dcn301_link_encoder_construct(enc20,
 892			enc_init_data,
 893			&link_enc_feature,
 894			&link_enc_regs[enc_init_data->transmitter],
 895			&link_enc_aux_regs[enc_init_data->channel - 1],
 896			&link_enc_hpd_regs[enc_init_data->hpd_source],
 897			&le_shift,
 898			&le_mask);
 899
 900	return &enc20->enc10.base;
 901}
 902
 903static struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
 904{
 905	struct dcn301_panel_cntl *panel_cntl =
 906		kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL);
 907
 908	if (!panel_cntl)
 909		return NULL;
 910
 911	dcn301_panel_cntl_construct(panel_cntl,
 912			init_data,
 913			&panel_cntl_regs[init_data->inst],
 914			&panel_cntl_shift,
 915			&panel_cntl_mask);
 916
 917	return &panel_cntl->base;
 918}
 919
 920
 921#define CTX ctx
 922
 923#define REG(reg_name) \
 924	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
 925
 926static uint32_t read_pipe_fuses(struct dc_context *ctx)
 927{
 928	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
 929	/* RV1 support max 4 pipes */
 930	value = value & 0xf;
 931	return value;
 932}
 933
 934
 935static void read_dce_straps(
 936	struct dc_context *ctx,
 937	struct resource_straps *straps)
 938{
 939	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 940		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 941
 942}
 943
 944static struct audio *dcn301_create_audio(
 945		struct dc_context *ctx, unsigned int inst)
 946{
 947	return dce_audio_create(ctx, inst,
 948			&audio_regs[inst], &audio_shift, &audio_mask);
 949}
 950
 951static struct vpg *dcn301_vpg_create(
 952	struct dc_context *ctx,
 953	uint32_t inst)
 954{
 955	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
 956
 957	if (!vpg3)
 958		return NULL;
 959
 960	vpg3_construct(vpg3, ctx, inst,
 961			&vpg_regs[inst],
 962			&vpg_shift,
 963			&vpg_mask);
 964
 965	return &vpg3->base;
 966}
 967
 968static struct afmt *dcn301_afmt_create(
 969	struct dc_context *ctx,
 970	uint32_t inst)
 971{
 972	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
 973
 974	if (!afmt3)
 975		return NULL;
 976
 977	afmt3_construct(afmt3, ctx, inst,
 978			&afmt_regs[inst],
 979			&afmt_shift,
 980			&afmt_mask);
 981
 982	return &afmt3->base;
 983}
 984
 985static struct stream_encoder *dcn301_stream_encoder_create(enum engine_id eng_id,
 986							   struct dc_context *ctx)
 987{
 988	struct dcn10_stream_encoder *enc1;
 989	struct vpg *vpg;
 990	struct afmt *afmt;
 991	int vpg_inst;
 992	int afmt_inst;
 993
 994	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
 995	if (eng_id <= ENGINE_ID_DIGF) {
 996		vpg_inst = eng_id;
 997		afmt_inst = eng_id;
 998	} else
 999		return NULL;
1000
1001	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1002	vpg = dcn301_vpg_create(ctx, vpg_inst);
1003	afmt = dcn301_afmt_create(ctx, afmt_inst);
1004
1005	if (!enc1 || !vpg || !afmt || eng_id >= ARRAY_SIZE(stream_enc_regs)) {
1006		kfree(enc1);
1007		kfree(vpg);
1008		kfree(afmt);
1009		return NULL;
1010	}
1011
1012	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1013					eng_id, vpg, afmt,
1014					&stream_enc_regs[eng_id],
1015					&se_shift, &se_mask);
1016
1017	return &enc1->base;
1018}
1019
1020static struct dce_hwseq *dcn301_hwseq_create(struct dc_context *ctx)
1021{
1022	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1023
1024	if (hws) {
1025		hws->ctx = ctx;
1026		hws->regs = &hwseq_reg;
1027		hws->shifts = &hwseq_shift;
1028		hws->masks = &hwseq_mask;
1029	}
1030	return hws;
1031}
1032static const struct resource_create_funcs res_create_funcs = {
1033	.read_dce_straps = read_dce_straps,
1034	.create_audio = dcn301_create_audio,
1035	.create_stream_encoder = dcn301_stream_encoder_create,
1036	.create_hwseq = dcn301_hwseq_create,
1037};
1038
1039static void dcn301_destruct(struct dcn301_resource_pool *pool)
1040{
1041	unsigned int i;
1042
1043	for (i = 0; i < pool->base.stream_enc_count; i++) {
1044		if (pool->base.stream_enc[i] != NULL) {
1045			if (pool->base.stream_enc[i]->vpg != NULL) {
1046				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1047				pool->base.stream_enc[i]->vpg = NULL;
1048			}
1049			if (pool->base.stream_enc[i]->afmt != NULL) {
1050				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1051				pool->base.stream_enc[i]->afmt = NULL;
1052			}
1053			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1054			pool->base.stream_enc[i] = NULL;
1055		}
1056	}
1057
1058	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1059		if (pool->base.dscs[i] != NULL)
1060			dcn20_dsc_destroy(&pool->base.dscs[i]);
1061	}
1062
1063	if (pool->base.mpc != NULL) {
1064		kfree(TO_DCN20_MPC(pool->base.mpc));
1065		pool->base.mpc = NULL;
1066	}
1067	if (pool->base.hubbub != NULL) {
1068		kfree(pool->base.hubbub);
1069		pool->base.hubbub = NULL;
1070	}
1071	for (i = 0; i < pool->base.pipe_count; i++) {
1072		if (pool->base.dpps[i] != NULL)
1073			dcn301_dpp_destroy(&pool->base.dpps[i]);
1074
1075		if (pool->base.ipps[i] != NULL)
1076			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1077
1078		if (pool->base.hubps[i] != NULL) {
1079			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1080			pool->base.hubps[i] = NULL;
1081		}
1082
1083		if (pool->base.irqs != NULL) {
1084			dal_irq_service_destroy(&pool->base.irqs);
1085		}
1086	}
1087
1088	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1089		if (pool->base.engines[i] != NULL)
1090			dce110_engine_destroy(&pool->base.engines[i]);
1091		if (pool->base.hw_i2cs[i] != NULL) {
1092			kfree(pool->base.hw_i2cs[i]);
1093			pool->base.hw_i2cs[i] = NULL;
1094		}
1095		if (pool->base.sw_i2cs[i] != NULL) {
1096			kfree(pool->base.sw_i2cs[i]);
1097			pool->base.sw_i2cs[i] = NULL;
1098		}
1099	}
1100
1101	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1102		if (pool->base.opps[i] != NULL)
1103			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1104	}
1105
1106	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1107		if (pool->base.timing_generators[i] != NULL)	{
1108			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1109			pool->base.timing_generators[i] = NULL;
1110		}
1111	}
1112
1113	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1114		if (pool->base.dwbc[i] != NULL) {
1115			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1116			pool->base.dwbc[i] = NULL;
1117		}
1118		if (pool->base.mcif_wb[i] != NULL) {
1119			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1120			pool->base.mcif_wb[i] = NULL;
1121		}
1122	}
1123
1124	for (i = 0; i < pool->base.audio_count; i++) {
1125		if (pool->base.audios[i])
1126			dce_aud_destroy(&pool->base.audios[i]);
1127	}
1128
1129	for (i = 0; i < pool->base.clk_src_count; i++) {
1130		if (pool->base.clock_sources[i] != NULL) {
1131			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1132			pool->base.clock_sources[i] = NULL;
1133		}
1134	}
1135
1136	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1137		if (pool->base.mpc_lut[i] != NULL) {
1138			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1139			pool->base.mpc_lut[i] = NULL;
1140		}
1141		if (pool->base.mpc_shaper[i] != NULL) {
1142			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1143			pool->base.mpc_shaper[i] = NULL;
1144		}
1145	}
1146
1147	if (pool->base.dp_clock_source != NULL) {
1148		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1149		pool->base.dp_clock_source = NULL;
1150	}
1151
1152	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1153		if (pool->base.multiple_abms[i] != NULL)
1154			dce_abm_destroy(&pool->base.multiple_abms[i]);
1155	}
1156
1157	if (pool->base.dccg != NULL)
1158		dcn_dccg_destroy(&pool->base.dccg);
1159}
1160
1161static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)
1162{
1163	struct dcn20_hubp *hubp2 =
1164		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1165
1166	if (!hubp2)
1167		return NULL;
1168
1169	if (hubp3_construct(hubp2, ctx, inst,
1170			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1171		return &hubp2->base;
1172
1173	BREAK_TO_DEBUGGER();
1174	kfree(hubp2);
1175	return NULL;
1176}
1177
1178static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1179{
1180	int i;
1181	uint32_t pipe_count = pool->res_cap->num_dwb;
1182
1183	for (i = 0; i < pipe_count; i++) {
1184		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1185						    GFP_KERNEL);
1186
1187		if (!dwbc30) {
1188			dm_error("DC: failed to create dwbc30!\n");
1189			return false;
1190		}
1191
1192		dcn30_dwbc_construct(dwbc30, ctx,
1193				&dwbc30_regs[i],
1194				&dwbc30_shift,
1195				&dwbc30_mask,
1196				i);
1197
1198		pool->dwbc[i] = &dwbc30->base;
1199	}
1200	return true;
1201}
1202
1203static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1204{
1205	int i;
1206	uint32_t pipe_count = pool->res_cap->num_dwb;
1207
1208	for (i = 0; i < pipe_count; i++) {
1209		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1210						    GFP_KERNEL);
1211
1212		if (!mcif_wb30) {
1213			dm_error("DC: failed to create mcif_wb30!\n");
1214			return false;
1215		}
1216
1217		dcn30_mmhubbub_construct(mcif_wb30, ctx,
1218				&mcif_wb30_regs[i],
1219				&mcif_wb30_shift,
1220				&mcif_wb30_mask,
1221				i);
1222
1223		pool->mcif_wb[i] = &mcif_wb30->base;
1224	}
1225	return true;
1226}
1227
1228static struct display_stream_compressor *dcn301_dsc_create(
1229	struct dc_context *ctx, uint32_t inst)
1230{
1231	struct dcn20_dsc *dsc =
1232		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1233
1234	if (!dsc) {
1235		BREAK_TO_DEBUGGER();
1236		return NULL;
1237	}
1238
1239	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1240	return &dsc->base;
1241}
1242
1243
1244static void dcn301_destroy_resource_pool(struct resource_pool **pool)
1245{
1246	struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool);
1247
1248	dcn301_destruct(dcn301_pool);
1249	kfree(dcn301_pool);
1250	*pool = NULL;
1251}
1252
1253static struct clock_source *dcn301_clock_source_create(
1254		struct dc_context *ctx,
1255		struct dc_bios *bios,
1256		enum clock_source_id id,
1257		const struct dce110_clk_src_regs *regs,
1258		bool dp_clk_src)
1259{
1260	struct dce110_clk_src *clk_src =
1261		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1262
1263	if (!clk_src)
1264		return NULL;
1265
1266	if (dcn301_clk_src_construct(clk_src, ctx, bios, id,
1267			regs, &cs_shift, &cs_mask)) {
1268		clk_src->base.dp_clk_src = dp_clk_src;
1269		return &clk_src->base;
1270	}
1271
1272	kfree(clk_src);
1273	BREAK_TO_DEBUGGER();
1274	return NULL;
1275}
1276
1277static struct dc_cap_funcs cap_funcs = {
1278	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1279};
1280
1281
1282static bool is_soc_bounding_box_valid(struct dc *dc)
1283{
1284	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1285
1286	if (ASICREV_IS_VANGOGH(hw_internal_rev))
1287		return true;
1288
1289	return false;
1290}
1291
1292static bool init_soc_bounding_box(struct dc *dc,
1293				  struct dcn301_resource_pool *pool)
1294{
1295	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc;
1296	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip;
1297
1298	DC_LOGGER_INIT(dc->ctx->logger);
1299
1300	if (!is_soc_bounding_box_valid(dc)) {
1301		DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1302		return false;
1303	}
1304
1305	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1306	loaded_ip->max_num_dpp = pool->base.pipe_count;
1307	DC_FP_START();
1308	dcn20_patch_bounding_box(dc, loaded_bb);
1309	DC_FP_END();
1310
1311	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1312		struct bp_soc_bb_info bb_info = {0};
1313
1314		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1315			DC_FP_START();
1316			dcn301_fpu_init_soc_bounding_box(bb_info);
1317			DC_FP_END();
1318		}
1319	}
1320
1321	return true;
1322}
1323
1324
1325static void set_wm_ranges(
1326		struct pp_smu_funcs *pp_smu,
1327		struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1328{
1329	struct pp_smu_wm_range_sets ranges = {0};
1330	int i;
1331
1332	ranges.num_reader_wm_sets = 0;
1333
1334	if (loaded_bb->num_states == 1) {
1335		ranges.reader_wm_sets[0].wm_inst = 0;
1336		ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1337		ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1338		ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1339		ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1340
1341		ranges.num_reader_wm_sets = 1;
1342	} else if (loaded_bb->num_states > 1) {
1343		for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
1344			ranges.reader_wm_sets[i].wm_inst = i;
1345			ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1346			ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1347			DC_FP_START();
1348			dcn301_fpu_set_wm_ranges(i, &ranges, loaded_bb);
1349			DC_FP_END();
1350			ranges.num_reader_wm_sets = i + 1;
1351		}
1352
1353		ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1354		ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1355	}
1356
1357	ranges.num_writer_wm_sets = 1;
1358
1359	ranges.writer_wm_sets[0].wm_inst = 0;
1360	ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1361	ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1362	ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1363	ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1364
1365	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1366	pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
1367}
1368
1369static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1370{
1371	DC_FP_START();
1372	dcn301_fpu_update_bw_bounding_box(dc, bw_params);
1373	DC_FP_END();
1374}
1375
1376static void dcn301_calculate_wm_and_dlg(struct dc *dc,
1377					struct dc_state *context,
1378					display_e2e_pipe_params_st *pipes,
1379					int pipe_cnt,
1380					int vlevel_req)
1381{
1382	DC_FP_START();
1383	dcn301_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel_req);
1384	DC_FP_END();
1385}
1386
1387static struct resource_funcs dcn301_res_pool_funcs = {
1388	.destroy = dcn301_destroy_resource_pool,
1389	.link_enc_create = dcn301_link_encoder_create,
1390	.panel_cntl_create = dcn301_panel_cntl_create,
1391	.validate_bandwidth = dcn30_validate_bandwidth,
1392	.calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg,
1393	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1394	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1395	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1396	.release_pipe = dcn20_release_pipe,
1397	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1398	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1399	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1400	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1401	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1402	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1403	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1404	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1405	.update_bw_bounding_box = dcn301_update_bw_bounding_box,
1406	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1407	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
1408};
1409
1410static bool dcn301_resource_construct(
1411	uint8_t num_virtual_links,
1412	struct dc *dc,
1413	struct dcn301_resource_pool *pool)
1414{
1415	int i, j;
1416	struct dc_context *ctx = dc->ctx;
1417	struct irq_service_init_data init_data;
1418	uint32_t pipe_fuses = read_pipe_fuses(ctx);
1419	uint32_t num_pipes = 0;
1420
1421	DC_LOGGER_INIT(dc->ctx->logger);
1422
1423	ctx->dc_bios->regs = &bios_regs;
1424
1425	if (dc->ctx->asic_id.chip_id == DEVICE_ID_VGH_1435)
1426		res_cap_dcn301.num_pll = 2;
1427	pool->base.res_cap = &res_cap_dcn301;
1428
1429	pool->base.funcs = &dcn301_res_pool_funcs;
1430
1431	/*************************************************
1432	 *  Resource + asic cap harcoding                *
1433	 *************************************************/
1434	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1435	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1436	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1437	dc->caps.max_downscale_ratio = 600;
1438	dc->caps.i2c_speed_in_khz = 100;
1439	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/
1440	dc->caps.max_cursor_size = 256;
1441	dc->caps.min_horizontal_blanking_period = 80;
1442	dc->caps.dmdata_alloc_size = 2048;
1443	dc->caps.max_slave_planes = 2;
1444	dc->caps.max_slave_yuv_planes = 2;
1445	dc->caps.max_slave_rgb_planes = 2;
1446	dc->caps.is_apu = true;
1447	dc->caps.post_blend_color_processing = true;
1448	dc->caps.force_dp_tps4_for_cp2520 = true;
1449	dc->caps.extended_aux_timeout_support = true;
1450	dc->caps.dmcub_support = true;
1451
1452	/* Color pipeline capabilities */
1453	dc->caps.color.dpp.dcn_arch = 1;
1454	dc->caps.color.dpp.input_lut_shared = 0;
1455	dc->caps.color.dpp.icsc = 1;
1456	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1457	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1458	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1459	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1460	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1461	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1462	dc->caps.color.dpp.post_csc = 1;
1463	dc->caps.color.dpp.gamma_corr = 1;
1464	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1465
1466	dc->caps.color.dpp.hw_3d_lut = 1;
1467	dc->caps.color.dpp.ogam_ram = 1;
1468	// no OGAM ROM on DCN301
1469	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1470	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1471	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1472	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1473	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1474	dc->caps.color.dpp.ocsc = 0;
1475
1476	dc->caps.color.mpc.gamut_remap = 1;
1477	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1478	dc->caps.color.mpc.ogam_ram = 1;
1479	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1480	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1481	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1482	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1483	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1484	dc->caps.color.mpc.ocsc = 1;
1485
1486	dc->caps.dp_hdmi21_pcon_support = true;
1487
1488	/* read VBIOS LTTPR caps */
1489	if (ctx->dc_bios->funcs->get_lttpr_caps) {
1490		enum bp_result bp_query_result;
1491		uint8_t is_vbios_lttpr_enable = 0;
1492
1493		bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1494		dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1495	}
1496
1497	if (ctx->dc_bios->funcs->get_lttpr_interop) {
1498		enum bp_result bp_query_result;
1499		uint8_t is_vbios_interop_enabled = 0;
1500
1501		bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1502		dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1503	}
1504	dc->check_config = config_defaults;
1505
1506	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1507		dc->debug = debug_defaults_drv;
1508
1509	// Init the vm_helper
1510	if (dc->vm_helper)
1511		vm_helper_init(dc->vm_helper, 16);
1512
1513	/*************************************************
1514	 *  Create resources                             *
1515	 *************************************************/
1516
1517	/* Clock Sources for Pixel Clock*/
1518	pool->base.clock_sources[DCN301_CLK_SRC_PLL0] =
1519			dcn301_clock_source_create(ctx, ctx->dc_bios,
1520				CLOCK_SOURCE_COMBO_PHY_PLL0,
1521				&clk_src_regs[0], false);
1522	pool->base.clock_sources[DCN301_CLK_SRC_PLL1] =
1523			dcn301_clock_source_create(ctx, ctx->dc_bios,
1524				CLOCK_SOURCE_COMBO_PHY_PLL1,
1525				&clk_src_regs[1], false);
1526	pool->base.clock_sources[DCN301_CLK_SRC_PLL2] =
1527			dcn301_clock_source_create(ctx, ctx->dc_bios,
1528				CLOCK_SOURCE_COMBO_PHY_PLL2,
1529				&clk_src_regs[2], false);
1530	pool->base.clock_sources[DCN301_CLK_SRC_PLL3] =
1531			dcn301_clock_source_create(ctx, ctx->dc_bios,
1532				CLOCK_SOURCE_COMBO_PHY_PLL3,
1533				&clk_src_regs[3], false);
1534
1535	pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL;
1536
1537	/* todo: not reuse phy_pll registers */
1538	pool->base.dp_clock_source =
1539			dcn301_clock_source_create(ctx, ctx->dc_bios,
1540				CLOCK_SOURCE_ID_DP_DTO,
1541				&clk_src_regs[0], true);
1542
1543	for (i = 0; i < pool->base.clk_src_count; i++) {
1544		if (pool->base.clock_sources[i] == NULL) {
1545			dm_error("DC: failed to create clock sources!\n");
1546			BREAK_TO_DEBUGGER();
1547			goto create_fail;
1548		}
1549	}
1550
1551	/* DCCG */
1552	pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1553	if (pool->base.dccg == NULL) {
1554		dm_error("DC: failed to create dccg!\n");
1555		BREAK_TO_DEBUGGER();
1556		goto create_fail;
1557	}
1558
1559	init_soc_bounding_box(dc, pool);
1560
1561	if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)
1562		set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);
1563
1564	num_pipes = dcn3_01_ip.max_num_dpp;
1565
1566	for (i = 0; i < dcn3_01_ip.max_num_dpp; i++)
1567		if (pipe_fuses & 1 << i)
1568			num_pipes--;
1569	dcn3_01_ip.max_num_dpp = num_pipes;
1570	dcn3_01_ip.max_num_otg = num_pipes;
1571
1572
1573	dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
1574
1575	/* IRQ */
1576	init_data.ctx = dc->ctx;
1577	pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
1578	if (!pool->base.irqs)
1579		goto create_fail;
1580
1581	/* HUBBUB */
1582	pool->base.hubbub = dcn301_hubbub_create(ctx);
1583	if (pool->base.hubbub == NULL) {
1584		BREAK_TO_DEBUGGER();
1585		dm_error("DC: failed to create hubbub!\n");
1586		goto create_fail;
1587	}
1588
1589	j = 0;
1590	/* HUBPs, DPPs, OPPs and TGs */
1591	for (i = 0; i < pool->base.pipe_count; i++) {
1592
1593		/* if pipe is disabled, skip instance of HW pipe,
1594		 * i.e, skip ASIC register instance
1595		 */
1596		if ((pipe_fuses & (1 << i)) != 0) {
1597			DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i);
1598			continue;
1599		}
1600
1601		pool->base.hubps[j] = dcn301_hubp_create(ctx, i);
1602		if (pool->base.hubps[j] == NULL) {
1603			BREAK_TO_DEBUGGER();
1604			dm_error(
1605				"DC: failed to create hubps!\n");
1606			goto create_fail;
1607		}
1608
1609		pool->base.dpps[j] = dcn301_dpp_create(ctx, i);
1610		if (pool->base.dpps[j] == NULL) {
1611			BREAK_TO_DEBUGGER();
1612			dm_error(
1613				"DC: failed to create dpps!\n");
1614			goto create_fail;
1615		}
1616
1617		pool->base.opps[j] = dcn301_opp_create(ctx, i);
1618		if (pool->base.opps[j] == NULL) {
1619			BREAK_TO_DEBUGGER();
1620			dm_error(
1621				"DC: failed to create output pixel processor!\n");
1622			goto create_fail;
1623		}
1624
1625		pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i);
1626		if (pool->base.timing_generators[j] == NULL) {
1627			BREAK_TO_DEBUGGER();
1628			dm_error("DC: failed to create tg!\n");
1629			goto create_fail;
1630		}
1631		j++;
1632	}
1633	pool->base.timing_generator_count = j;
1634	pool->base.pipe_count = j;
1635	pool->base.mpcc_count = j;
1636
1637	/* ABM (or ABMs for NV2x) */
1638	/* TODO: */
1639	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1640		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1641				&abm_regs[i],
1642				&abm_shift,
1643				&abm_mask);
1644		if (pool->base.multiple_abms[i] == NULL) {
1645			dm_error("DC: failed to create abm for pipe %d!\n", i);
1646			BREAK_TO_DEBUGGER();
1647			goto create_fail;
1648		}
1649	}
1650
1651	/* MPC and DSC */
1652	pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1653	if (pool->base.mpc == NULL) {
1654		BREAK_TO_DEBUGGER();
1655		dm_error("DC: failed to create mpc!\n");
1656		goto create_fail;
1657	}
1658
1659	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1660		pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
1661		if (pool->base.dscs[i] == NULL) {
1662			BREAK_TO_DEBUGGER();
1663			dm_error("DC: failed to create display stream compressor %d!\n", i);
1664			goto create_fail;
1665		}
1666	}
1667
1668	/* DWB and MMHUBBUB */
1669	if (!dcn301_dwbc_create(ctx, &pool->base)) {
1670		BREAK_TO_DEBUGGER();
1671		dm_error("DC: failed to create dwbc!\n");
1672		goto create_fail;
1673	}
1674
1675	if (!dcn301_mmhubbub_create(ctx, &pool->base)) {
1676		BREAK_TO_DEBUGGER();
1677		dm_error("DC: failed to create mcif_wb!\n");
1678		goto create_fail;
1679	}
1680
1681	/* AUX and I2C */
1682	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1683		pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
1684		if (pool->base.engines[i] == NULL) {
1685			BREAK_TO_DEBUGGER();
1686			dm_error(
1687				"DC:failed to create aux engine!!\n");
1688			goto create_fail;
1689		}
1690		pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i);
1691		if (pool->base.hw_i2cs[i] == NULL) {
1692			BREAK_TO_DEBUGGER();
1693			dm_error(
1694				"DC:failed to create hw i2c!!\n");
1695			goto create_fail;
1696		}
1697		pool->base.sw_i2cs[i] = NULL;
1698	}
1699
1700	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1701	if (!resource_construct(num_virtual_links, dc, &pool->base,
1702			&res_create_funcs))
1703		goto create_fail;
1704
1705	/* HW Sequencer and Plane caps */
1706	dcn301_hw_sequencer_construct(dc);
1707
1708	dc->caps.max_planes =  pool->base.pipe_count;
1709
1710	for (i = 0; i < dc->caps.max_planes; ++i)
1711		dc->caps.planes[i] = plane_cap;
1712
1713	dc->caps.max_odm_combine_factor = 4;
1714
1715	dc->cap_funcs = cap_funcs;
1716
1717	return true;
1718
1719create_fail:
1720
1721	dcn301_destruct(pool);
1722
1723	return false;
1724}
1725
1726struct resource_pool *dcn301_create_resource_pool(
1727		const struct dc_init_data *init_data,
1728		struct dc *dc)
1729{
1730	struct dcn301_resource_pool *pool =
1731		kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL);
1732
1733	if (!pool)
1734		return NULL;
1735
1736	if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
1737		return &pool->base;
1738
1739	BREAK_TO_DEBUGGER();
1740	kfree(pool);
1741	return NULL;
1742}