dcn21_resource.c

   1/*
   2* Copyright 2018 Advanced Micro Devices, Inc.
   3 * Copyright 2019 Raptor Engineering, LLC
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: AMD
  24 *
  25 */
  26
  27#include <linux/slab.h>
  28
  29#include "dm_services.h"
  30#include "dc.h"
  31
  32#include "dcn21/dcn21_init.h"
  33
  34#include "resource.h"
  35#include "include/irq_service_interface.h"
  36#include "dcn20/dcn20_resource.h"
  37#include "dcn21/dcn21_resource.h"
  38
  39#include "dml/dcn20/dcn20_fpu.h"
  40
  41#include "clk_mgr.h"
  42#include "dcn10/dcn10_hubp.h"
  43#include "dcn10/dcn10_ipp.h"
  44#include "dcn20/dcn20_hubbub.h"
  45#include "dcn20/dcn20_mpc.h"
  46#include "dcn20/dcn20_hubp.h"
  47#include "dcn21/dcn21_hubp.h"
  48#include "irq/dcn21/irq_service_dcn21.h"
  49#include "dcn20/dcn20_dpp.h"
  50#include "dcn20/dcn20_optc.h"
  51#include "dcn21/dcn21_hwseq.h"
  52#include "dce110/dce110_hwseq.h"
  53#include "dcn20/dcn20_opp.h"
  54#include "dcn20/dcn20_dsc.h"
  55#include "dcn21/dcn21_link_encoder.h"
  56#include "dcn20/dcn20_stream_encoder.h"
  57#include "dce/dce_clock_source.h"
  58#include "dce/dce_audio.h"
  59#include "dce/dce_hwseq.h"
  60#include "virtual/virtual_stream_encoder.h"
  61#include "dml/display_mode_vba.h"
  62#include "dcn20/dcn20_dccg.h"
  63#include "dcn21/dcn21_dccg.h"
  64#include "dcn21/dcn21_hubbub.h"
  65#include "dcn10/dcn10_resource.h"
  66#include "dce/dce_panel_cntl.h"
  67
  68#include "dcn20/dcn20_dwb.h"
  69#include "dcn20/dcn20_mmhubbub.h"
  70#include "dpcs/dpcs_2_1_0_offset.h"
  71#include "dpcs/dpcs_2_1_0_sh_mask.h"
  72
  73#include "renoir_ip_offset.h"
  74#include "dcn/dcn_2_1_0_offset.h"
  75#include "dcn/dcn_2_1_0_sh_mask.h"
  76
  77#include "nbio/nbio_7_0_offset.h"
  78
  79#include "mmhub/mmhub_2_0_0_offset.h"
  80#include "mmhub/mmhub_2_0_0_sh_mask.h"
  81
  82#include "reg_helper.h"
  83#include "dce/dce_abm.h"
  84#include "dce/dce_dmcu.h"
  85#include "dce/dce_aux.h"
  86#include "dce/dce_i2c.h"
  87#include "dcn21_resource.h"
  88#include "vm_helper.h"
  89#include "dcn20/dcn20_vmid.h"
  90#include "dce/dmub_psr.h"
  91#include "dce/dmub_abm.h"
  92
  93/* begin *********************
  94 * macros to expend register list macro defined in HW object header file */
  95
  96/* DCN */
  97#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
  98
  99#define BASE(seg) BASE_INNER(seg)
 100
 101#define SR(reg_name)\
 102		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 103					mm ## reg_name
 104
 105#define SRI(reg_name, block, id)\
 106	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 107					mm ## block ## id ## _ ## reg_name
 108
 109#define SRIR(var_name, reg_name, block, id)\
 110	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 111					mm ## block ## id ## _ ## reg_name
 112
 113#define SRII(reg_name, block, id)\
 114	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 115					mm ## block ## id ## _ ## reg_name
 116
 117#define DCCG_SRII(reg_name, block, id)\
 118	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 119					mm ## block ## id ## _ ## reg_name
 120
 121#define VUPDATE_SRII(reg_name, block, id)\
 122	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 123					mm ## reg_name ## _ ## block ## id
 124
 125/* NBIO */
 126#define NBIO_BASE_INNER(seg) \
 127	NBIF0_BASE__INST0_SEG ## seg
 128
 129#define NBIO_BASE(seg) \
 130	NBIO_BASE_INNER(seg)
 131
 132#define NBIO_SR(reg_name)\
 133		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 134					mm ## reg_name
 135
 136/* MMHUB */
 137#define MMHUB_BASE_INNER(seg) \
 138	MMHUB_BASE__INST0_SEG ## seg
 139
 140#define MMHUB_BASE(seg) \
 141	MMHUB_BASE_INNER(seg)
 142
 143#define MMHUB_SR(reg_name)\
 144		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 145					mmMM ## reg_name
 146
 147#define clk_src_regs(index, pllid)\
 148[index] = {\
 149	CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
 150}
 151
 152static const struct dce110_clk_src_regs clk_src_regs[] = {
 153	clk_src_regs(0, A),
 154	clk_src_regs(1, B),
 155	clk_src_regs(2, C),
 156	clk_src_regs(3, D),
 157	clk_src_regs(4, E),
 158};
 159
 160static const struct dce110_clk_src_shift cs_shift = {
 161		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 162};
 163
 164static const struct dce110_clk_src_mask cs_mask = {
 165		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 166};
 167
 168static const struct bios_registers bios_regs = {
 169		NBIO_SR(BIOS_SCRATCH_3),
 170		NBIO_SR(BIOS_SCRATCH_6)
 171};
 172
 173static const struct dce_dmcu_registers dmcu_regs = {
 174		DMCU_DCN20_REG_LIST()
 175};
 176
 177static const struct dce_dmcu_shift dmcu_shift = {
 178		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 179};
 180
 181static const struct dce_dmcu_mask dmcu_mask = {
 182		DMCU_MASK_SH_LIST_DCN10(_MASK)
 183};
 184
 185static const struct dce_abm_registers abm_regs = {
 186		ABM_DCN20_REG_LIST()
 187};
 188
 189static const struct dce_abm_shift abm_shift = {
 190		ABM_MASK_SH_LIST_DCN20(__SHIFT)
 191};
 192
 193static const struct dce_abm_mask abm_mask = {
 194		ABM_MASK_SH_LIST_DCN20(_MASK)
 195};
 196
 197#define audio_regs(id)\
 198[id] = {\
 199		AUD_COMMON_REG_LIST(id)\
 200}
 201
 202static const struct dce_audio_registers audio_regs[] = {
 203	audio_regs(0),
 204	audio_regs(1),
 205	audio_regs(2),
 206	audio_regs(3),
 207	audio_regs(4),
 208	audio_regs(5),
 209};
 210
 211#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 212		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 213		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 214		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 215
 216static const struct dce_audio_shift audio_shift = {
 217		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 218};
 219
 220static const struct dce_audio_mask audio_mask = {
 221		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 222};
 223
 224static const struct dccg_registers dccg_regs = {
 225		DCCG_COMMON_REG_LIST_DCN_BASE()
 226};
 227
 228static const struct dccg_shift dccg_shift = {
 229		DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
 230};
 231
 232static const struct dccg_mask dccg_mask = {
 233		DCCG_MASK_SH_LIST_DCN2_1(_MASK)
 234};
 235
 236#define opp_regs(id)\
 237[id] = {\
 238	OPP_REG_LIST_DCN20(id),\
 239}
 240
 241static const struct dcn20_opp_registers opp_regs[] = {
 242	opp_regs(0),
 243	opp_regs(1),
 244	opp_regs(2),
 245	opp_regs(3),
 246	opp_regs(4),
 247	opp_regs(5),
 248};
 249
 250static const struct dcn20_opp_shift opp_shift = {
 251		OPP_MASK_SH_LIST_DCN20(__SHIFT)
 252};
 253
 254static const struct dcn20_opp_mask opp_mask = {
 255		OPP_MASK_SH_LIST_DCN20(_MASK)
 256};
 257
 258#define tg_regs(id)\
 259[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 260
 261static const struct dcn_optc_registers tg_regs[] = {
 262	tg_regs(0),
 263	tg_regs(1),
 264	tg_regs(2),
 265	tg_regs(3)
 266};
 267
 268static const struct dcn_optc_shift tg_shift = {
 269	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 270};
 271
 272static const struct dcn_optc_mask tg_mask = {
 273	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 274};
 275
 276static const struct dcn20_mpc_registers mpc_regs = {
 277		MPC_REG_LIST_DCN2_0(0),
 278		MPC_REG_LIST_DCN2_0(1),
 279		MPC_REG_LIST_DCN2_0(2),
 280		MPC_REG_LIST_DCN2_0(3),
 281		MPC_REG_LIST_DCN2_0(4),
 282		MPC_REG_LIST_DCN2_0(5),
 283		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 284		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 285		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 286		MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 287		MPC_DBG_REG_LIST_DCN2_0()
 288};
 289
 290static const struct dcn20_mpc_shift mpc_shift = {
 291	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
 292	MPC_DEBUG_REG_LIST_SH_DCN20
 293};
 294
 295static const struct dcn20_mpc_mask mpc_mask = {
 296	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
 297	MPC_DEBUG_REG_LIST_MASK_DCN20
 298};
 299
 300#define hubp_regs(id)\
 301[id] = {\
 302	HUBP_REG_LIST_DCN21(id)\
 303}
 304
 305static const struct dcn_hubp2_registers hubp_regs[] = {
 306		hubp_regs(0),
 307		hubp_regs(1),
 308		hubp_regs(2),
 309		hubp_regs(3)
 310};
 311
 312static const struct dcn_hubp2_shift hubp_shift = {
 313		HUBP_MASK_SH_LIST_DCN21(__SHIFT)
 314};
 315
 316static const struct dcn_hubp2_mask hubp_mask = {
 317		HUBP_MASK_SH_LIST_DCN21(_MASK)
 318};
 319
 320static const struct dcn_hubbub_registers hubbub_reg = {
 321		HUBBUB_REG_LIST_DCN21()
 322};
 323
 324static const struct dcn_hubbub_shift hubbub_shift = {
 325		HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
 326};
 327
 328static const struct dcn_hubbub_mask hubbub_mask = {
 329		HUBBUB_MASK_SH_LIST_DCN21(_MASK)
 330};
 331
 332
 333#define vmid_regs(id)\
 334[id] = {\
 335		DCN20_VMID_REG_LIST(id)\
 336}
 337
 338static const struct dcn_vmid_registers vmid_regs[] = {
 339	vmid_regs(0),
 340	vmid_regs(1),
 341	vmid_regs(2),
 342	vmid_regs(3),
 343	vmid_regs(4),
 344	vmid_regs(5),
 345	vmid_regs(6),
 346	vmid_regs(7),
 347	vmid_regs(8),
 348	vmid_regs(9),
 349	vmid_regs(10),
 350	vmid_regs(11),
 351	vmid_regs(12),
 352	vmid_regs(13),
 353	vmid_regs(14),
 354	vmid_regs(15)
 355};
 356
 357static const struct dcn20_vmid_shift vmid_shifts = {
 358		DCN20_VMID_MASK_SH_LIST(__SHIFT)
 359};
 360
 361static const struct dcn20_vmid_mask vmid_masks = {
 362		DCN20_VMID_MASK_SH_LIST(_MASK)
 363};
 364
 365#define dsc_regsDCN20(id)\
 366[id] = {\
 367	DSC_REG_LIST_DCN20(id)\
 368}
 369
 370static const struct dcn20_dsc_registers dsc_regs[] = {
 371	dsc_regsDCN20(0),
 372	dsc_regsDCN20(1),
 373	dsc_regsDCN20(2),
 374	dsc_regsDCN20(3),
 375	dsc_regsDCN20(4),
 376	dsc_regsDCN20(5)
 377};
 378
 379static const struct dcn20_dsc_shift dsc_shift = {
 380	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 381};
 382
 383static const struct dcn20_dsc_mask dsc_mask = {
 384	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 385};
 386
 387#define ipp_regs(id)\
 388[id] = {\
 389	IPP_REG_LIST_DCN20(id),\
 390}
 391
 392static const struct dcn10_ipp_registers ipp_regs[] = {
 393	ipp_regs(0),
 394	ipp_regs(1),
 395	ipp_regs(2),
 396	ipp_regs(3),
 397};
 398
 399static const struct dcn10_ipp_shift ipp_shift = {
 400		IPP_MASK_SH_LIST_DCN20(__SHIFT)
 401};
 402
 403static const struct dcn10_ipp_mask ipp_mask = {
 404		IPP_MASK_SH_LIST_DCN20(_MASK),
 405};
 406
 407#define opp_regs(id)\
 408[id] = {\
 409	OPP_REG_LIST_DCN20(id),\
 410}
 411
 412
 413#define aux_engine_regs(id)\
 414[id] = {\
 415	AUX_COMMON_REG_LIST0(id), \
 416	.AUXN_IMPCAL = 0, \
 417	.AUXP_IMPCAL = 0, \
 418	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 419}
 420
 421static const struct dce110_aux_registers aux_engine_regs[] = {
 422		aux_engine_regs(0),
 423		aux_engine_regs(1),
 424		aux_engine_regs(2),
 425		aux_engine_regs(3),
 426		aux_engine_regs(4),
 427};
 428
 429#define tf_regs(id)\
 430[id] = {\
 431	TF_REG_LIST_DCN20(id),\
 432	TF_REG_LIST_DCN20_COMMON_APPEND(id),\
 433}
 434
 435static const struct dcn2_dpp_registers tf_regs[] = {
 436	tf_regs(0),
 437	tf_regs(1),
 438	tf_regs(2),
 439	tf_regs(3),
 440};
 441
 442static const struct dcn2_dpp_shift tf_shift = {
 443		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
 444		TF_DEBUG_REG_LIST_SH_DCN20
 445};
 446
 447static const struct dcn2_dpp_mask tf_mask = {
 448		TF_REG_LIST_SH_MASK_DCN20(_MASK),
 449		TF_DEBUG_REG_LIST_MASK_DCN20
 450};
 451
 452#define stream_enc_regs(id)\
 453[id] = {\
 454	SE_DCN2_REG_LIST(id)\
 455}
 456
 457static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 458	stream_enc_regs(0),
 459	stream_enc_regs(1),
 460	stream_enc_regs(2),
 461	stream_enc_regs(3),
 462	stream_enc_regs(4),
 463};
 464
 465static const struct dce110_aux_registers_shift aux_shift = {
 466	DCN_AUX_MASK_SH_LIST(__SHIFT)
 467};
 468
 469static const struct dce110_aux_registers_mask aux_mask = {
 470	DCN_AUX_MASK_SH_LIST(_MASK)
 471};
 472
 473static const struct dcn10_stream_encoder_shift se_shift = {
 474		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 475};
 476
 477static const struct dcn10_stream_encoder_mask se_mask = {
 478		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 479};
 480
 481static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
 482
 483static struct input_pixel_processor *dcn21_ipp_create(
 484	struct dc_context *ctx, uint32_t inst)
 485{
 486	struct dcn10_ipp *ipp =
 487		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 488
 489	if (!ipp) {
 490		BREAK_TO_DEBUGGER();
 491		return NULL;
 492	}
 493
 494	dcn20_ipp_construct(ipp, ctx, inst,
 495			&ipp_regs[inst], &ipp_shift, &ipp_mask);
 496	return &ipp->base;
 497}
 498
 499static struct dpp *dcn21_dpp_create(
 500	struct dc_context *ctx,
 501	uint32_t inst)
 502{
 503	struct dcn20_dpp *dpp =
 504		kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
 505
 506	if (!dpp)
 507		return NULL;
 508
 509	if (dpp2_construct(dpp, ctx, inst,
 510			&tf_regs[inst], &tf_shift, &tf_mask))
 511		return &dpp->base;
 512
 513	BREAK_TO_DEBUGGER();
 514	kfree(dpp);
 515	return NULL;
 516}
 517
 518static struct dce_aux *dcn21_aux_engine_create(
 519	struct dc_context *ctx,
 520	uint32_t inst)
 521{
 522	struct aux_engine_dce110 *aux_engine =
 523		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 524
 525	if (!aux_engine)
 526		return NULL;
 527
 528	dce110_aux_engine_construct(aux_engine, ctx, inst,
 529				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 530				    &aux_engine_regs[inst],
 531					&aux_mask,
 532					&aux_shift,
 533					ctx->dc->caps.extended_aux_timeout_support);
 534
 535	return &aux_engine->base;
 536}
 537
 538#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 539
 540static const struct dce_i2c_registers i2c_hw_regs[] = {
 541		i2c_inst_regs(1),
 542		i2c_inst_regs(2),
 543		i2c_inst_regs(3),
 544		i2c_inst_regs(4),
 545		i2c_inst_regs(5),
 546};
 547
 548static const struct dce_i2c_shift i2c_shifts = {
 549		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 550};
 551
 552static const struct dce_i2c_mask i2c_masks = {
 553		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 554};
 555
 556static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx,
 557					      uint32_t inst)
 558{
 559	struct dce_i2c_hw *dce_i2c_hw =
 560		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 561
 562	if (!dce_i2c_hw)
 563		return NULL;
 564
 565	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 566				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 567
 568	return dce_i2c_hw;
 569}
 570
 571static const struct resource_caps res_cap_rn = {
 572		.num_timing_generator = 4,
 573		.num_opp = 4,
 574		.num_video_plane = 4,
 575		.num_audio = 4, // 4 audio endpoints.  4 audio streams
 576		.num_stream_encoder = 5,
 577		.num_pll = 5,  // maybe 3 because the last two used for USB-c
 578		.num_dwb = 1,
 579		.num_ddc = 5,
 580		.num_vmid = 16,
 581		.num_dsc = 3,
 582};
 583
 584static const struct dc_plane_cap plane_cap = {
 585	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 586	.per_pixel_alpha = true,
 587
 588	.pixel_format_support = {
 589			.argb8888 = true,
 590			.nv12 = true,
 591			.fp16 = true,
 592			.p010 = true
 593	},
 594
 595	.max_upscale_factor = {
 596			.argb8888 = 16000,
 597			.nv12 = 16000,
 598			.fp16 = 16000
 599	},
 600
 601	.max_downscale_factor = {
 602			.argb8888 = 250,
 603			.nv12 = 250,
 604			.fp16 = 250
 605	},
 606	64,
 607	64
 608};
 609
 610static const struct dc_debug_options debug_defaults_drv = {
 611		.disable_dmcu = false,
 612		.force_abm_enable = false,
 613		.clock_trace = true,
 614		.disable_pplib_clock_request = true,
 615		.min_disp_clk_khz = 100000,
 616		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
 617		.force_single_disp_pipe_split = false,
 618		.disable_dcc = DCC_ENABLE,
 619		.vsr_support = true,
 620		.performance_trace = false,
 621		.max_downscale_src_width = 4096,
 622		.disable_pplib_wm_range = false,
 623		.scl_reset_length10 = true,
 624		.sanity_checks = true,
 625		.disable_48mhz_pwrdwn = false,
 626		.usbc_combo_phy_reset_wa = true,
 627		.dmub_command_table = true,
 628		.use_max_lb = true,
 629		.using_dml2 = false,
 630};
 631
 632static const struct dc_check_config config_defaults = {
 633		.enable_legacy_fast_update = true,
 634};
 635
 636static const struct dc_panel_config panel_config_defaults = {
 637		.psr = {
 638			.disable_psr = false,
 639			.disallow_psrsu = false,
 640			.disallow_replay = false,
 641		},
 642		.ilr = {
 643			.optimize_edp_link_rate = true,
 644		},
 645};
 646
 647enum dcn20_clk_src_array_id {
 648	DCN20_CLK_SRC_PLL0,
 649	DCN20_CLK_SRC_PLL1,
 650	DCN20_CLK_SRC_PLL2,
 651	DCN20_CLK_SRC_PLL3,
 652	DCN20_CLK_SRC_PLL4,
 653	DCN20_CLK_SRC_TOTAL_DCN21
 654};
 655
 656static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
 657{
 658	unsigned int i;
 659
 660	for (i = 0; i < pool->base.stream_enc_count; i++) {
 661		if (pool->base.stream_enc[i] != NULL) {
 662			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 663			pool->base.stream_enc[i] = NULL;
 664		}
 665	}
 666
 667	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
 668		if (pool->base.dscs[i] != NULL)
 669			dcn20_dsc_destroy(&pool->base.dscs[i]);
 670	}
 671
 672	if (pool->base.mpc != NULL) {
 673		kfree(TO_DCN20_MPC(pool->base.mpc));
 674		pool->base.mpc = NULL;
 675	}
 676	if (pool->base.hubbub != NULL) {
 677		kfree(pool->base.hubbub);
 678		pool->base.hubbub = NULL;
 679	}
 680	for (i = 0; i < pool->base.pipe_count; i++) {
 681		if (pool->base.dpps[i] != NULL)
 682			dcn20_dpp_destroy(&pool->base.dpps[i]);
 683
 684		if (pool->base.ipps[i] != NULL)
 685			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 686
 687		if (pool->base.hubps[i] != NULL) {
 688			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
 689			pool->base.hubps[i] = NULL;
 690		}
 691
 692		if (pool->base.irqs != NULL)
 693			dal_irq_service_destroy(&pool->base.irqs);
 694	}
 695
 696	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 697		if (pool->base.engines[i] != NULL)
 698			dce110_engine_destroy(&pool->base.engines[i]);
 699		if (pool->base.hw_i2cs[i] != NULL) {
 700			kfree(pool->base.hw_i2cs[i]);
 701			pool->base.hw_i2cs[i] = NULL;
 702		}
 703		if (pool->base.sw_i2cs[i] != NULL) {
 704			kfree(pool->base.sw_i2cs[i]);
 705			pool->base.sw_i2cs[i] = NULL;
 706		}
 707	}
 708
 709	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
 710		if (pool->base.opps[i] != NULL)
 711			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 712	}
 713
 714	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
 715		if (pool->base.timing_generators[i] != NULL)	{
 716			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 717			pool->base.timing_generators[i] = NULL;
 718		}
 719	}
 720
 721	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
 722		if (pool->base.dwbc[i] != NULL) {
 723			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
 724			pool->base.dwbc[i] = NULL;
 725		}
 726		if (pool->base.mcif_wb[i] != NULL) {
 727			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
 728			pool->base.mcif_wb[i] = NULL;
 729		}
 730	}
 731
 732	for (i = 0; i < pool->base.audio_count; i++) {
 733		if (pool->base.audios[i])
 734			dce_aud_destroy(&pool->base.audios[i]);
 735	}
 736
 737	for (i = 0; i < pool->base.clk_src_count; i++) {
 738		if (pool->base.clock_sources[i] != NULL) {
 739			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
 740			pool->base.clock_sources[i] = NULL;
 741		}
 742	}
 743
 744	if (pool->base.dp_clock_source != NULL) {
 745		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
 746		pool->base.dp_clock_source = NULL;
 747	}
 748
 749	if (pool->base.abm != NULL) {
 750		if (pool->base.abm->ctx->dc->config.disable_dmcu)
 751			dmub_abm_destroy(&pool->base.abm);
 752		else
 753			dce_abm_destroy(&pool->base.abm);
 754	}
 755
 756	if (pool->base.dmcu != NULL)
 757		dce_dmcu_destroy(&pool->base.dmcu);
 758
 759	if (pool->base.psr != NULL)
 760		dmub_psr_destroy(&pool->base.psr);
 761
 762	if (pool->base.dccg != NULL)
 763		dcn_dccg_destroy(&pool->base.dccg);
 764
 765	if (pool->base.pp_smu != NULL)
 766		dcn21_pp_smu_destroy(&pool->base.pp_smu);
 767}
 768
 769bool dcn21_fast_validate_bw(struct dc *dc,
 770			    struct dc_state *context,
 771			    display_e2e_pipe_params_st *pipes,
 772			    int *pipe_cnt_out,
 773			    int *pipe_split_from,
 774			    int *vlevel_out,
 775			    enum dc_validate_mode validate_mode)
 776{
 777	bool out = false;
 778	int split[MAX_PIPES] = { 0 };
 779	bool merge[MAX_PIPES] = { false };
 780	int pipe_cnt, i, pipe_idx, vlevel;
 781
 782	ASSERT(pipes);
 783	if (!pipes)
 784		return false;
 785
 786	dcn20_merge_pipes_for_validate(dc, context);
 787
 788	DC_FP_START();
 789	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
 790	DC_FP_END();
 791
 792	*pipe_cnt_out = pipe_cnt;
 793
 794	if (!pipe_cnt) {
 795		out = true;
 796		goto validate_out;
 797	}
 798	/*
 799	 * DML favors voltage over p-state, but we're more interested in
 800	 * supporting p-state over voltage. We can't support p-state in
 801	 * prefetch mode > 0 so try capping the prefetch mode to start.
 802	 */
 803	context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
 804				dm_allow_self_refresh_and_mclk_switch;
 805	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
 806
 807	if (vlevel > context->bw_ctx.dml.soc.num_states) {
 808		/*
 809		 * If mode is unsupported or there's still no p-state support then
 810		 * fall back to favoring voltage.
 811		 *
 812		 * We don't actually support prefetch mode 2, so require that we
 813		 * at least support prefetch mode 1.
 814		 */
 815		context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
 816					dm_allow_self_refresh;
 817		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
 818		if (vlevel > context->bw_ctx.dml.soc.num_states)
 819			goto validate_fail;
 820	}
 821
 822	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
 823
 824	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 825		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 826		struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
 827		struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 828
 829		if (!pipe->stream)
 830			continue;
 831
 832		/* We only support full screen mpo with ODM */
 833		if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
 834				&& pipe->plane_state && mpo_pipe
 835				&& memcmp(&mpo_pipe->plane_state->clip_rect,
 836						&pipe->stream->src,
 837						sizeof(struct rect)) != 0) {
 838			ASSERT(mpo_pipe->plane_state != pipe->plane_state);
 839			goto validate_fail;
 840		}
 841		pipe_idx++;
 842	}
 843
 844	/*initialize pipe_just_split_from to invalid idx*/
 845	for (i = 0; i < MAX_PIPES; i++)
 846		pipe_split_from[i] = -1;
 847
 848	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
 849		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 850		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
 851
 852		if (!pipe->stream || pipe_split_from[i] >= 0)
 853			continue;
 854
 855		pipe_idx++;
 856
 857		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
 858			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
 859			ASSERT(hsplit_pipe);
 860			if (!dcn20_split_stream_for_odm(
 861					dc, &context->res_ctx,
 862					pipe, hsplit_pipe))
 863				goto validate_fail;
 864			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
 865			dcn20_build_mapped_resource(dc, context, pipe->stream);
 866		}
 867
 868		if (!pipe->plane_state)
 869			continue;
 870		/* Skip 2nd half of already split pipe */
 871		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
 872			continue;
 873
 874		if (split[i] == 2) {
 875			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
 876				/* pipe not split previously needs split */
 877				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
 878				ASSERT(hsplit_pipe);
 879				if (!hsplit_pipe) {
 880					DC_FP_START();
 881					dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
 882					DC_FP_END();
 883					continue;
 884				}
 885				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
 886					if (!dcn20_split_stream_for_odm(
 887							dc, &context->res_ctx,
 888							pipe, hsplit_pipe))
 889						goto validate_fail;
 890					dcn20_build_mapped_resource(dc, context, pipe->stream);
 891				} else {
 892					dcn20_split_stream_for_mpc(
 893							&context->res_ctx, dc->res_pool,
 894							pipe, hsplit_pipe);
 895					resource_build_scaling_params(pipe);
 896					resource_build_scaling_params(hsplit_pipe);
 897				}
 898				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
 899			}
 900		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
 901			/* merge should already have been done */
 902			ASSERT(0);
 903		}
 904	}
 905	/* Actual dsc count per stream dsc validation*/
 906	if (!dcn20_validate_dsc(dc, context)) {
 907		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
 908				DML_FAIL_DSC_VALIDATION_FAILURE;
 909		goto validate_fail;
 910	}
 911
 912	*vlevel_out = vlevel;
 913
 914	out = true;
 915	goto validate_out;
 916
 917validate_fail:
 918	out = false;
 919
 920validate_out:
 921	return out;
 922}
 923
 924/*
 925 * Some of the functions further below use the FPU, so we need to wrap this
 926 * with DC_FP_START()/DC_FP_END(). Use the same approach as for
 927 * dcn20_validate_bandwidth in dcn20_resource.c.
 928 */
 929static enum dc_status dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
 930		enum dc_validate_mode validate_mode)
 931{
 932	bool voltage_supported;
 933	display_e2e_pipe_params_st *pipes;
 934
 935	pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
 936	if (!pipes)
 937		return DC_FAIL_BANDWIDTH_VALIDATE;
 938
 939	DC_FP_START();
 940	voltage_supported = dcn21_validate_bandwidth_fp(dc, context, validate_mode, pipes);
 941	DC_FP_END();
 942
 943	kfree(pipes);
 944	return voltage_supported ? DC_OK : DC_NOT_SUPPORTED;
 945}
 946
 947static void dcn21_destroy_resource_pool(struct resource_pool **pool)
 948{
 949	struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
 950
 951	dcn21_resource_destruct(dcn21_pool);
 952	kfree(dcn21_pool);
 953	*pool = NULL;
 954}
 955
 956static struct clock_source *dcn21_clock_source_create(
 957		struct dc_context *ctx,
 958		struct dc_bios *bios,
 959		enum clock_source_id id,
 960		const struct dce110_clk_src_regs *regs,
 961		bool dp_clk_src)
 962{
 963	struct dce110_clk_src *clk_src =
 964		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 965
 966	if (!clk_src)
 967		return NULL;
 968
 969	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
 970			regs, &cs_shift, &cs_mask)) {
 971		clk_src->base.dp_clk_src = dp_clk_src;
 972		return &clk_src->base;
 973	}
 974
 975	kfree(clk_src);
 976	BREAK_TO_DEBUGGER();
 977	return NULL;
 978}
 979
 980static struct hubp *dcn21_hubp_create(
 981	struct dc_context *ctx,
 982	uint32_t inst)
 983{
 984	struct dcn21_hubp *hubp21 =
 985		kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
 986
 987	if (!hubp21)
 988		return NULL;
 989
 990	if (hubp21_construct(hubp21, ctx, inst,
 991			&hubp_regs[inst], &hubp_shift, &hubp_mask))
 992		return &hubp21->base;
 993
 994	BREAK_TO_DEBUGGER();
 995	kfree(hubp21);
 996	return NULL;
 997}
 998
 999static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1000{
1001	int i;
1002
1003	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1004					  GFP_KERNEL);
1005
1006	if (!hubbub)
1007		return NULL;
1008
1009	hubbub21_construct(hubbub, ctx,
1010			&hubbub_reg,
1011			&hubbub_shift,
1012			&hubbub_mask);
1013
1014	for (i = 0; i < res_cap_rn.num_vmid; i++) {
1015		struct dcn20_vmid *vmid = &hubbub->vmid[i];
1016
1017		vmid->ctx = ctx;
1018
1019		vmid->regs = &vmid_regs[i];
1020		vmid->shifts = &vmid_shifts;
1021		vmid->masks = &vmid_masks;
1022	}
1023	hubbub->num_vmid = res_cap_rn.num_vmid;
1024
1025	return &hubbub->base;
1026}
1027
1028static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx,
1029						       uint32_t inst)
1030{
1031	struct dcn20_opp *opp =
1032		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1033
1034	if (!opp) {
1035		BREAK_TO_DEBUGGER();
1036		return NULL;
1037	}
1038
1039	dcn20_opp_construct(opp, ctx, inst,
1040			&opp_regs[inst], &opp_shift, &opp_mask);
1041	return &opp->base;
1042}
1043
1044static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx,
1045							      uint32_t instance)
1046{
1047	struct optc *tgn10 =
1048		kzalloc(sizeof(struct optc), GFP_KERNEL);
1049
1050	if (!tgn10)
1051		return NULL;
1052
1053	tgn10->base.inst = instance;
1054	tgn10->base.ctx = ctx;
1055
1056	tgn10->tg_regs = &tg_regs[instance];
1057	tgn10->tg_shift = &tg_shift;
1058	tgn10->tg_mask = &tg_mask;
1059
1060	dcn20_timing_generator_init(tgn10);
1061
1062	return &tgn10->base;
1063}
1064
1065static struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1066{
1067	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1068					  GFP_KERNEL);
1069
1070	if (!mpc20)
1071		return NULL;
1072
1073	dcn20_mpc_construct(mpc20, ctx,
1074			&mpc_regs,
1075			&mpc_shift,
1076			&mpc_mask,
1077			6);
1078
1079	return &mpc20->base;
1080}
1081
1082static void read_dce_straps(
1083	struct dc_context *ctx,
1084	struct resource_straps *straps)
1085{
1086	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1087		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1088
1089}
1090
1091
1092static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx,
1093							  uint32_t inst)
1094{
1095	struct dcn20_dsc *dsc =
1096		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1097
1098	if (!dsc) {
1099		BREAK_TO_DEBUGGER();
1100		return NULL;
1101	}
1102
1103	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1104	return &dsc->base;
1105}
1106
1107static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1108{
1109	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1110
1111	if (!pp_smu)
1112		return pp_smu;
1113
1114	dm_pp_get_funcs(ctx, pp_smu);
1115
1116	if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1117		pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1118
1119
1120	return pp_smu;
1121}
1122
1123static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1124{
1125	if (pp_smu && *pp_smu) {
1126		kfree(*pp_smu);
1127		*pp_smu = NULL;
1128	}
1129}
1130
1131static struct audio *dcn21_create_audio(
1132		struct dc_context *ctx, unsigned int inst)
1133{
1134	return dce_audio_create(ctx, inst,
1135			&audio_regs[inst], &audio_shift, &audio_mask);
1136}
1137
1138static struct dc_cap_funcs cap_funcs = {
1139	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1140};
1141
1142static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id,
1143							  struct dc_context *ctx)
1144{
1145	struct dcn10_stream_encoder *enc1 =
1146		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1147
1148	if (!enc1)
1149		return NULL;
1150
1151	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1152					&stream_enc_regs[eng_id],
1153					&se_shift, &se_mask);
1154
1155	return &enc1->base;
1156}
1157
1158static const struct dce_hwseq_registers hwseq_reg = {
1159		HWSEQ_DCN21_REG_LIST()
1160};
1161
1162static const struct dce_hwseq_shift hwseq_shift = {
1163		HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1164};
1165
1166static const struct dce_hwseq_mask hwseq_mask = {
1167		HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1168};
1169
1170static struct dce_hwseq *dcn21_hwseq_create(
1171	struct dc_context *ctx)
1172{
1173	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1174
1175	if (hws) {
1176		hws->ctx = ctx;
1177		hws->regs = &hwseq_reg;
1178		hws->shifts = &hwseq_shift;
1179		hws->masks = &hwseq_mask;
1180		hws->wa.DEGVIDCN21 = true;
1181		hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1182	}
1183	return hws;
1184}
1185
1186static const struct resource_create_funcs res_create_funcs = {
1187	.read_dce_straps = read_dce_straps,
1188	.create_audio = dcn21_create_audio,
1189	.create_stream_encoder = dcn21_stream_encoder_create,
1190	.create_hwseq = dcn21_hwseq_create,
1191};
1192
1193static const struct encoder_feature_support link_enc_feature = {
1194		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1195		.max_hdmi_pixel_clock = 600000,
1196		.hdmi_ycbcr420_supported = true,
1197		.dp_ycbcr420_supported = true,
1198		.fec_supported = true,
1199		.flags.bits.IS_HBR2_CAPABLE = true,
1200		.flags.bits.IS_HBR3_CAPABLE = true,
1201		.flags.bits.IS_TPS3_CAPABLE = true,
1202		.flags.bits.IS_TPS4_CAPABLE = true
1203};
1204
1205
1206#define link_regs(id, phyid)\
1207[id] = {\
1208	LE_DCN2_REG_LIST(id), \
1209	UNIPHY_DCN2_REG_LIST(phyid), \
1210	DPCS_DCN21_REG_LIST(id), \
1211	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1212}
1213
1214static const struct dcn10_link_enc_registers link_enc_regs[] = {
1215	link_regs(0, A),
1216	link_regs(1, B),
1217	link_regs(2, C),
1218	link_regs(3, D),
1219	link_regs(4, E),
1220};
1221
1222static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1223	{ DCN_PANEL_CNTL_REG_LIST() }
1224};
1225
1226static const struct dce_panel_cntl_shift panel_cntl_shift = {
1227	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1228};
1229
1230static const struct dce_panel_cntl_mask panel_cntl_mask = {
1231	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1232};
1233
1234#define aux_regs(id)\
1235[id] = {\
1236	DCN2_AUX_REG_LIST(id)\
1237}
1238
1239static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1240		aux_regs(0),
1241		aux_regs(1),
1242		aux_regs(2),
1243		aux_regs(3),
1244		aux_regs(4)
1245};
1246
1247#define hpd_regs(id)\
1248[id] = {\
1249	HPD_REG_LIST(id)\
1250}
1251
1252static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1253		hpd_regs(0),
1254		hpd_regs(1),
1255		hpd_regs(2),
1256		hpd_regs(3),
1257		hpd_regs(4)
1258};
1259
1260static const struct dcn10_link_enc_shift le_shift = {
1261	LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1262	DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1263};
1264
1265static const struct dcn10_link_enc_mask le_mask = {
1266	LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1267	DPCS_DCN21_MASK_SH_LIST(_MASK)
1268};
1269
1270static int map_transmitter_id_to_phy_instance(
1271	enum transmitter transmitter)
1272{
1273	switch (transmitter) {
1274	case TRANSMITTER_UNIPHY_A:
1275		return 0;
1276	break;
1277	case TRANSMITTER_UNIPHY_B:
1278		return 1;
1279	break;
1280	case TRANSMITTER_UNIPHY_C:
1281		return 2;
1282	break;
1283	case TRANSMITTER_UNIPHY_D:
1284		return 3;
1285	break;
1286	case TRANSMITTER_UNIPHY_E:
1287		return 4;
1288	break;
1289	default:
1290		ASSERT(0);
1291		return 0;
1292	}
1293}
1294
1295static struct link_encoder *dcn21_link_encoder_create(
1296	struct dc_context *ctx,
1297	const struct encoder_init_data *enc_init_data)
1298{
1299	struct dcn21_link_encoder *enc21 =
1300		kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1301	int link_regs_id;
1302
1303	if (!enc21 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1304		return NULL;
1305
1306	link_regs_id =
1307		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1308
1309	dcn21_link_encoder_construct(enc21,
1310				      enc_init_data,
1311				      &link_enc_feature,
1312				      &link_enc_regs[link_regs_id],
1313				      &link_enc_aux_regs[enc_init_data->channel - 1],
1314				      &link_enc_hpd_regs[enc_init_data->hpd_source],
1315				      &le_shift,
1316				      &le_mask);
1317
1318	return &enc21->enc10.base;
1319}
1320
1321static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1322{
1323	struct dce_panel_cntl *panel_cntl =
1324		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1325
1326	if (!panel_cntl)
1327		return NULL;
1328
1329	dce_panel_cntl_construct(panel_cntl,
1330			init_data,
1331			&panel_cntl_regs[init_data->inst],
1332			&panel_cntl_shift,
1333			&panel_cntl_mask);
1334
1335	return &panel_cntl->base;
1336}
1337
1338static void dcn21_get_panel_config_defaults(struct dc_panel_config *panel_config)
1339{
1340	*panel_config = panel_config_defaults;
1341}
1342
1343#define CTX ctx
1344
1345#define REG(reg_name) \
1346	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1347
1348static uint32_t read_pipe_fuses(struct dc_context *ctx)
1349{
1350	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1351	/* RV1 support max 4 pipes */
1352	value = value & 0xf;
1353	return value;
1354}
1355
1356static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1357{
1358	if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1359		plane_state->dcc.enable = 1;
1360		/* align to our worst case block width */
1361		plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1362	}
1363
1364	return dcn20_patch_unknown_plane_state(plane_state);
1365}
1366
1367static const struct resource_funcs dcn21_res_pool_funcs = {
1368	.destroy = dcn21_destroy_resource_pool,
1369	.link_enc_create = dcn21_link_encoder_create,
1370	.panel_cntl_create = dcn21_panel_cntl_create,
1371	.validate_bandwidth = dcn21_validate_bandwidth,
1372	.populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1373	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
1374	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1375	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1376	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1377	.release_pipe = dcn20_release_pipe,
1378	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1379	.patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1380	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
1381	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1382	.update_bw_bounding_box = dcn21_update_bw_bounding_box,
1383	.get_panel_config_defaults = dcn21_get_panel_config_defaults,
1384	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
1385};
1386
1387static bool dcn21_resource_construct(
1388	uint8_t num_virtual_links,
1389	struct dc *dc,
1390	struct dcn21_resource_pool *pool)
1391{
1392	int i, j;
1393	struct dc_context *ctx = dc->ctx;
1394	struct irq_service_init_data init_data;
1395	uint32_t pipe_fuses = read_pipe_fuses(ctx);
1396	uint32_t num_pipes = 0;
1397
1398	ctx->dc_bios->regs = &bios_regs;
1399
1400	pool->base.res_cap = &res_cap_rn;
1401
1402	pool->base.funcs = &dcn21_res_pool_funcs;
1403
1404	/*************************************************
1405	 *  Resource + asic cap harcoding                *
1406	 *************************************************/
1407	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1408
1409	/* max pipe num for ASIC before check pipe fuses */
1410	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1411
1412	dc->caps.max_downscale_ratio = 200;
1413	dc->caps.i2c_speed_in_khz = 100;
1414	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1415	dc->caps.max_cursor_size = 256;
1416	dc->caps.min_horizontal_blanking_period = 80;
1417	dc->caps.dmdata_alloc_size = 2048;
1418
1419	dc->caps.max_slave_planes = 3;
1420	dc->caps.max_slave_yuv_planes = 3;
1421	dc->caps.max_slave_rgb_planes = 3;
1422	dc->caps.post_blend_color_processing = true;
1423	dc->caps.force_dp_tps4_for_cp2520 = true;
1424	dc->caps.extended_aux_timeout_support = true;
1425	dc->caps.dmcub_support = true;
1426	dc->caps.is_apu = true;
1427
1428	/* Color pipeline capabilities */
1429	dc->caps.color.dpp.dcn_arch = 1;
1430	dc->caps.color.dpp.input_lut_shared = 0;
1431	dc->caps.color.dpp.icsc = 1;
1432	dc->caps.color.dpp.dgam_ram = 1;
1433	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1434	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1435	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1436	dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1437	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1438	dc->caps.color.dpp.post_csc = 0;
1439	dc->caps.color.dpp.gamma_corr = 0;
1440	dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1441
1442	dc->caps.color.dpp.hw_3d_lut = 1;
1443	dc->caps.color.dpp.ogam_ram = 1;
1444	// no OGAM ROM on DCN2
1445	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1446	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1447	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1448	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1449	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1450	dc->caps.color.dpp.ocsc = 0;
1451
1452	dc->caps.color.mpc.gamut_remap = 0;
1453	dc->caps.color.mpc.num_3dluts = 0;
1454	dc->caps.color.mpc.shared_3d_lut = 0;
1455	dc->caps.color.mpc.ogam_ram = 1;
1456	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1457	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1458	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1459	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1460	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1461	dc->caps.color.mpc.ocsc = 1;
1462
1463	dc->caps.dp_hdmi21_pcon_support = true;
1464	dc->check_config = config_defaults;
1465
1466	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1467		dc->debug = debug_defaults_drv;
1468
1469	// Init the vm_helper
1470	if (dc->vm_helper)
1471		vm_helper_init(dc->vm_helper, 16);
1472
1473	/*************************************************
1474	 *  Create resources                             *
1475	 *************************************************/
1476
1477	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1478			dcn21_clock_source_create(ctx, ctx->dc_bios,
1479				CLOCK_SOURCE_COMBO_PHY_PLL0,
1480				&clk_src_regs[0], false);
1481	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1482			dcn21_clock_source_create(ctx, ctx->dc_bios,
1483				CLOCK_SOURCE_COMBO_PHY_PLL1,
1484				&clk_src_regs[1], false);
1485	pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1486			dcn21_clock_source_create(ctx, ctx->dc_bios,
1487				CLOCK_SOURCE_COMBO_PHY_PLL2,
1488				&clk_src_regs[2], false);
1489	pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
1490			dcn21_clock_source_create(ctx, ctx->dc_bios,
1491				CLOCK_SOURCE_COMBO_PHY_PLL3,
1492				&clk_src_regs[3], false);
1493	pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
1494			dcn21_clock_source_create(ctx, ctx->dc_bios,
1495				CLOCK_SOURCE_COMBO_PHY_PLL4,
1496				&clk_src_regs[4], false);
1497
1498	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1499
1500	/* todo: not reuse phy_pll registers */
1501	pool->base.dp_clock_source =
1502			dcn21_clock_source_create(ctx, ctx->dc_bios,
1503				CLOCK_SOURCE_ID_DP_DTO,
1504				&clk_src_regs[0], true);
1505
1506	for (i = 0; i < pool->base.clk_src_count; i++) {
1507		if (pool->base.clock_sources[i] == NULL) {
1508			dm_error("DC: failed to create clock sources!\n");
1509			BREAK_TO_DEBUGGER();
1510			goto create_fail;
1511		}
1512	}
1513
1514	pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1515	if (pool->base.dccg == NULL) {
1516		dm_error("DC: failed to create dccg!\n");
1517		BREAK_TO_DEBUGGER();
1518		goto create_fail;
1519	}
1520
1521	if (!dc->config.disable_dmcu) {
1522		pool->base.dmcu = dcn21_dmcu_create(ctx,
1523				&dmcu_regs,
1524				&dmcu_shift,
1525				&dmcu_mask);
1526		if (pool->base.dmcu == NULL) {
1527			dm_error("DC: failed to create dmcu!\n");
1528			BREAK_TO_DEBUGGER();
1529			goto create_fail;
1530		}
1531
1532		dc->debug.dmub_command_table = false;
1533	}
1534
1535	if (dc->config.disable_dmcu) {
1536		pool->base.psr = dmub_psr_create(ctx);
1537
1538		if (pool->base.psr == NULL) {
1539			dm_error("DC: failed to create psr obj!\n");
1540			BREAK_TO_DEBUGGER();
1541			goto create_fail;
1542		}
1543	}
1544
1545	if (dc->config.disable_dmcu)
1546		pool->base.abm = dmub_abm_create(ctx,
1547			&abm_regs,
1548			&abm_shift,
1549			&abm_mask);
1550	else
1551		pool->base.abm = dce_abm_create(ctx,
1552			&abm_regs,
1553			&abm_shift,
1554			&abm_mask);
1555
1556	pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1557
1558	num_pipes = dcn2_1_ip.max_num_dpp;
1559
1560	for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1561		if (pipe_fuses & 1 << i)
1562			num_pipes--;
1563	dcn2_1_ip.max_num_dpp = num_pipes;
1564	dcn2_1_ip.max_num_otg = num_pipes;
1565
1566	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1567
1568	init_data.ctx = dc->ctx;
1569	pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1570	if (!pool->base.irqs)
1571		goto create_fail;
1572
1573	j = 0;
1574	/* mem input -> ipp -> dpp -> opp -> TG */
1575	for (i = 0; i < pool->base.pipe_count; i++) {
1576		/* if pipe is disabled, skip instance of HW pipe,
1577		 * i.e, skip ASIC register instance
1578		 */
1579		if ((pipe_fuses & (1 << i)) != 0)
1580			continue;
1581
1582		pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1583		if (pool->base.hubps[j] == NULL) {
1584			BREAK_TO_DEBUGGER();
1585			dm_error(
1586				"DC: failed to create memory input!\n");
1587			goto create_fail;
1588		}
1589
1590		pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1591		if (pool->base.ipps[j] == NULL) {
1592			BREAK_TO_DEBUGGER();
1593			dm_error(
1594				"DC: failed to create input pixel processor!\n");
1595			goto create_fail;
1596		}
1597
1598		pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1599		if (pool->base.dpps[j] == NULL) {
1600			BREAK_TO_DEBUGGER();
1601			dm_error(
1602				"DC: failed to create dpps!\n");
1603			goto create_fail;
1604		}
1605
1606		pool->base.opps[j] = dcn21_opp_create(ctx, i);
1607		if (pool->base.opps[j] == NULL) {
1608			BREAK_TO_DEBUGGER();
1609			dm_error(
1610				"DC: failed to create output pixel processor!\n");
1611			goto create_fail;
1612		}
1613
1614		pool->base.timing_generators[j] = dcn21_timing_generator_create(
1615				ctx, i);
1616		if (pool->base.timing_generators[j] == NULL) {
1617			BREAK_TO_DEBUGGER();
1618			dm_error("DC: failed to create tg!\n");
1619			goto create_fail;
1620		}
1621		j++;
1622	}
1623
1624	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1625		pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1626		if (pool->base.engines[i] == NULL) {
1627			BREAK_TO_DEBUGGER();
1628			dm_error(
1629				"DC:failed to create aux engine!!\n");
1630			goto create_fail;
1631		}
1632		pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1633		if (pool->base.hw_i2cs[i] == NULL) {
1634			BREAK_TO_DEBUGGER();
1635			dm_error(
1636				"DC:failed to create hw i2c!!\n");
1637			goto create_fail;
1638		}
1639		pool->base.sw_i2cs[i] = NULL;
1640	}
1641
1642	pool->base.timing_generator_count = j;
1643	pool->base.pipe_count = j;
1644	pool->base.mpcc_count = j;
1645
1646	pool->base.mpc = dcn21_mpc_create(ctx);
1647	if (pool->base.mpc == NULL) {
1648		BREAK_TO_DEBUGGER();
1649		dm_error("DC: failed to create mpc!\n");
1650		goto create_fail;
1651	}
1652
1653	pool->base.hubbub = dcn21_hubbub_create(ctx);
1654	if (pool->base.hubbub == NULL) {
1655		BREAK_TO_DEBUGGER();
1656		dm_error("DC: failed to create hubbub!\n");
1657		goto create_fail;
1658	}
1659
1660	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1661		pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1662		if (pool->base.dscs[i] == NULL) {
1663			BREAK_TO_DEBUGGER();
1664			dm_error("DC: failed to create display stream compressor %d!\n", i);
1665			goto create_fail;
1666		}
1667	}
1668
1669	if (!dcn20_dwbc_create(ctx, &pool->base)) {
1670		BREAK_TO_DEBUGGER();
1671		dm_error("DC: failed to create dwbc!\n");
1672		goto create_fail;
1673	}
1674	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1675		BREAK_TO_DEBUGGER();
1676		dm_error("DC: failed to create mcif_wb!\n");
1677		goto create_fail;
1678	}
1679
1680	if (!resource_construct(num_virtual_links, dc, &pool->base,
1681			&res_create_funcs))
1682		goto create_fail;
1683
1684	dcn21_hw_sequencer_construct(dc);
1685
1686	dc->caps.max_planes =  pool->base.pipe_count;
1687
1688	for (i = 0; i < dc->caps.max_planes; ++i)
1689		dc->caps.planes[i] = plane_cap;
1690
1691	dc->caps.max_odm_combine_factor = 2;
1692
1693	dc->cap_funcs = cap_funcs;
1694
1695	return true;
1696
1697create_fail:
1698
1699	dcn21_resource_destruct(pool);
1700
1701	return false;
1702}
1703
1704struct resource_pool *dcn21_create_resource_pool(
1705		const struct dc_init_data *init_data,
1706		struct dc *dc)
1707{
1708	struct dcn21_resource_pool *pool =
1709		kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
1710
1711	if (!pool)
1712		return NULL;
1713
1714	if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
1715		return &pool->base;
1716
1717	BREAK_TO_DEBUGGER();
1718	kfree(pool);
1719	return NULL;
1720}