dcn10_resource.c

   1/*
   2* Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "core_status.h"
  27#include "dm_services.h"
  28#include "dc.h"
  29
  30#include "dcn10/dcn10_init.h"
  31
  32#include "resource.h"
  33#include "include/irq_service_interface.h"
  34#include "dcn10/dcn10_resource.h"
  35#include "dcn10/dcn10_ipp.h"
  36#include "dcn10/dcn10_mpc.h"
  37
  38#include "dcn10/dcn10_dwb.h"
  39
  40#include "irq/dcn10/irq_service_dcn10.h"
  41#include "dcn10/dcn10_dpp.h"
  42#include "dcn10/dcn10_optc.h"
  43#include "dcn10/dcn10_hwseq.h"
  44#include "dce110/dce110_hwseq.h"
  45#include "dcn10/dcn10_opp.h"
  46#include "dcn10/dcn10_link_encoder.h"
  47#include "dcn10/dcn10_stream_encoder.h"
  48#include "dce/dce_clock_source.h"
  49#include "dce/dce_audio.h"
  50#include "dce/dce_hwseq.h"
  51#include "virtual/virtual_stream_encoder.h"
  52#include "dce110/dce110_resource.h"
  53#include "dce112/dce112_resource.h"
  54#include "dcn10/dcn10_hubp.h"
  55#include "dcn10/dcn10_hubbub.h"
  56#include "dce/dce_panel_cntl.h"
  57
  58#include "soc15_hw_ip.h"
  59#include "vega10_ip_offset.h"
  60
  61#include "dcn/dcn_1_0_offset.h"
  62#include "dcn/dcn_1_0_sh_mask.h"
  63
  64#include "nbio/nbio_7_0_offset.h"
  65
  66#include "mmhub/mmhub_9_1_offset.h"
  67#include "mmhub/mmhub_9_1_sh_mask.h"
  68
  69#include "reg_helper.h"
  70#include "dce/dce_abm.h"
  71#include "dce/dce_dmcu.h"
  72#include "dce/dce_aux.h"
  73#include "dce/dce_i2c.h"
  74
  75#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
  76	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
  77	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
  78	#define mmDP1_DP_DPHY_INTERNAL_CTRL		0x220f
  79	#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
  80	#define mmDP2_DP_DPHY_INTERNAL_CTRL		0x230f
  81	#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
  82	#define mmDP3_DP_DPHY_INTERNAL_CTRL		0x240f
  83	#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
  84	#define mmDP4_DP_DPHY_INTERNAL_CTRL		0x250f
  85	#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
  86	#define mmDP5_DP_DPHY_INTERNAL_CTRL		0x260f
  87	#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
  88	#define mmDP6_DP_DPHY_INTERNAL_CTRL		0x270f
  89	#define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
  90#endif
  91
  92
  93enum dcn10_clk_src_array_id {
  94	DCN10_CLK_SRC_PLL0,
  95	DCN10_CLK_SRC_PLL1,
  96	DCN10_CLK_SRC_PLL2,
  97	DCN10_CLK_SRC_PLL3,
  98	DCN10_CLK_SRC_TOTAL,
  99	DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
 100};
 101
 102/* begin *********************
 103 * macros to expend register list macro defined in HW object header file */
 104
 105/* DCN */
 106#define BASE_INNER(seg) \
 107	DCE_BASE__INST0_SEG ## seg
 108
 109#define BASE(seg) \
 110	BASE_INNER(seg)
 111
 112#define SR(reg_name)\
 113		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 114					mm ## reg_name
 115
 116#define SRI(reg_name, block, id)\
 117	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 118					mm ## block ## id ## _ ## reg_name
 119
 120
 121#define SRII(reg_name, block, id)\
 122	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 123					mm ## block ## id ## _ ## reg_name
 124
 125#define VUPDATE_SRII(reg_name, block, id)\
 126	.reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
 127					mm ## reg_name ## 0 ## _ ## block ## id
 128
 129/* set field/register/bitfield name */
 130#define SFRB(field_name, reg_name, bitfield, post_fix)\
 131	.field_name = reg_name ## __ ## bitfield ## post_fix
 132
 133/* NBIO */
 134#define NBIO_BASE_INNER(seg) \
 135	NBIF_BASE__INST0_SEG ## seg
 136
 137#define NBIO_BASE(seg) \
 138	NBIO_BASE_INNER(seg)
 139
 140#define NBIO_SR(reg_name)\
 141		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) +  \
 142					mm ## reg_name
 143
 144/* MMHUB */
 145#define MMHUB_BASE_INNER(seg) \
 146	MMHUB_BASE__INST0_SEG ## seg
 147
 148#define MMHUB_BASE(seg) \
 149	MMHUB_BASE_INNER(seg)
 150
 151#define MMHUB_SR(reg_name)\
 152		.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
 153					mm ## reg_name
 154
 155/* macros to expend register list macro defined in HW object header file
 156 * end *********************/
 157
 158
 159static const struct dce_dmcu_registers dmcu_regs = {
 160		DMCU_DCN10_REG_LIST()
 161};
 162
 163static const struct dce_dmcu_shift dmcu_shift = {
 164		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 165};
 166
 167static const struct dce_dmcu_mask dmcu_mask = {
 168		DMCU_MASK_SH_LIST_DCN10(_MASK)
 169};
 170
 171static const struct dce_abm_registers abm_regs = {
 172		ABM_DCN10_REG_LIST(0)
 173};
 174
 175static const struct dce_abm_shift abm_shift = {
 176		ABM_MASK_SH_LIST_DCN10(__SHIFT)
 177};
 178
 179static const struct dce_abm_mask abm_mask = {
 180		ABM_MASK_SH_LIST_DCN10(_MASK)
 181};
 182
 183#define stream_enc_regs(id)\
 184[id] = {\
 185	SE_DCN_REG_LIST(id)\
 186}
 187
 188static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 189	stream_enc_regs(0),
 190	stream_enc_regs(1),
 191	stream_enc_regs(2),
 192	stream_enc_regs(3),
 193};
 194
 195static const struct dcn10_stream_encoder_shift se_shift = {
 196		SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
 197};
 198
 199static const struct dcn10_stream_encoder_mask se_mask = {
 200		SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
 201};
 202
 203#define audio_regs(id)\
 204[id] = {\
 205		AUD_COMMON_REG_LIST(id)\
 206}
 207
 208static const struct dce_audio_registers audio_regs[] = {
 209	audio_regs(0),
 210	audio_regs(1),
 211	audio_regs(2),
 212	audio_regs(3),
 213};
 214
 215#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 216		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 217		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 218		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 219
 220static const struct dce_audio_shift audio_shift = {
 221		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 222};
 223
 224static const struct dce_audio_mask audio_mask = {
 225		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 226};
 227
 228#define aux_regs(id)\
 229[id] = {\
 230	AUX_REG_LIST(id)\
 231}
 232
 233static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 234		aux_regs(0),
 235		aux_regs(1),
 236		aux_regs(2),
 237		aux_regs(3)
 238};
 239
 240#define hpd_regs(id)\
 241[id] = {\
 242	HPD_REG_LIST(id)\
 243}
 244
 245static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 246		hpd_regs(0),
 247		hpd_regs(1),
 248		hpd_regs(2),
 249		hpd_regs(3)
 250};
 251
 252#define link_regs(id)\
 253[id] = {\
 254	LE_DCN10_REG_LIST(id), \
 255	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 256}
 257
 258static const struct dcn10_link_enc_registers link_enc_regs[] = {
 259	link_regs(0),
 260	link_regs(1),
 261	link_regs(2),
 262	link_regs(3)
 263};
 264
 265static const struct dcn10_link_enc_shift le_shift = {
 266		LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
 267};
 268
 269static const struct dcn10_link_enc_mask le_mask = {
 270		LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
 271};
 272
 273static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 274	{ DCN_PANEL_CNTL_REG_LIST() }
 275};
 276
 277static const struct dce_panel_cntl_shift panel_cntl_shift = {
 278	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 279};
 280
 281static const struct dce_panel_cntl_mask panel_cntl_mask = {
 282	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 283};
 284
 285static const struct dce110_aux_registers_shift aux_shift = {
 286	DCN10_AUX_MASK_SH_LIST(__SHIFT)
 287};
 288
 289static const struct dce110_aux_registers_mask aux_mask = {
 290	DCN10_AUX_MASK_SH_LIST(_MASK)
 291};
 292
 293#define ipp_regs(id)\
 294[id] = {\
 295	IPP_REG_LIST_DCN10(id),\
 296}
 297
 298static const struct dcn10_ipp_registers ipp_regs[] = {
 299	ipp_regs(0),
 300	ipp_regs(1),
 301	ipp_regs(2),
 302	ipp_regs(3),
 303};
 304
 305static const struct dcn10_ipp_shift ipp_shift = {
 306		IPP_MASK_SH_LIST_DCN10(__SHIFT)
 307};
 308
 309static const struct dcn10_ipp_mask ipp_mask = {
 310		IPP_MASK_SH_LIST_DCN10(_MASK),
 311};
 312
 313#define opp_regs(id)\
 314[id] = {\
 315	OPP_REG_LIST_DCN10(id),\
 316}
 317
 318static const struct dcn10_opp_registers opp_regs[] = {
 319	opp_regs(0),
 320	opp_regs(1),
 321	opp_regs(2),
 322	opp_regs(3),
 323};
 324
 325static const struct dcn10_opp_shift opp_shift = {
 326		OPP_MASK_SH_LIST_DCN10(__SHIFT)
 327};
 328
 329static const struct dcn10_opp_mask opp_mask = {
 330		OPP_MASK_SH_LIST_DCN10(_MASK),
 331};
 332
 333#define aux_engine_regs(id)\
 334[id] = {\
 335	AUX_COMMON_REG_LIST(id), \
 336	.AUX_RESET_MASK = 0 \
 337}
 338
 339static const struct dce110_aux_registers aux_engine_regs[] = {
 340		aux_engine_regs(0),
 341		aux_engine_regs(1),
 342		aux_engine_regs(2),
 343		aux_engine_regs(3),
 344		aux_engine_regs(4),
 345		aux_engine_regs(5)
 346};
 347
 348#define tf_regs(id)\
 349[id] = {\
 350	TF_REG_LIST_DCN10(id),\
 351}
 352
 353static const struct dcn_dpp_registers tf_regs[] = {
 354	tf_regs(0),
 355	tf_regs(1),
 356	tf_regs(2),
 357	tf_regs(3),
 358};
 359
 360static const struct dcn_dpp_shift tf_shift = {
 361	TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
 362	TF_DEBUG_REG_LIST_SH_DCN10
 363
 364};
 365
 366static const struct dcn_dpp_mask tf_mask = {
 367	TF_REG_LIST_SH_MASK_DCN10(_MASK),
 368	TF_DEBUG_REG_LIST_MASK_DCN10
 369};
 370
 371static const struct dcn_mpc_registers mpc_regs = {
 372		MPC_COMMON_REG_LIST_DCN1_0(0),
 373		MPC_COMMON_REG_LIST_DCN1_0(1),
 374		MPC_COMMON_REG_LIST_DCN1_0(2),
 375		MPC_COMMON_REG_LIST_DCN1_0(3),
 376		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
 377		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
 378		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
 379		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
 380};
 381
 382static const struct dcn_mpc_shift mpc_shift = {
 383	MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\
 384	SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT)
 385};
 386
 387static const struct dcn_mpc_mask mpc_mask = {
 388	MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\
 389	SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK)
 390};
 391
 392#define tg_regs(id)\
 393[id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
 394
 395static const struct dcn_optc_registers tg_regs[] = {
 396	tg_regs(0),
 397	tg_regs(1),
 398	tg_regs(2),
 399	tg_regs(3),
 400};
 401
 402static const struct dcn_optc_shift tg_shift = {
 403	TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 404};
 405
 406static const struct dcn_optc_mask tg_mask = {
 407	TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
 408};
 409
 410static const struct bios_registers bios_regs = {
 411		NBIO_SR(BIOS_SCRATCH_3),
 412		NBIO_SR(BIOS_SCRATCH_6)
 413};
 414
 415#define hubp_regs(id)\
 416[id] = {\
 417	HUBP_REG_LIST_DCN10(id)\
 418}
 419
 420static const struct dcn_mi_registers hubp_regs[] = {
 421	hubp_regs(0),
 422	hubp_regs(1),
 423	hubp_regs(2),
 424	hubp_regs(3),
 425};
 426
 427static const struct dcn_mi_shift hubp_shift = {
 428		HUBP_MASK_SH_LIST_DCN10(__SHIFT)
 429};
 430
 431static const struct dcn_mi_mask hubp_mask = {
 432		HUBP_MASK_SH_LIST_DCN10(_MASK)
 433};
 434
 435static const struct dcn_hubbub_registers hubbub_reg = {
 436		HUBBUB_REG_LIST_DCN10(0)
 437};
 438
 439static const struct dcn_hubbub_shift hubbub_shift = {
 440		HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
 441};
 442
 443static const struct dcn_hubbub_mask hubbub_mask = {
 444		HUBBUB_MASK_SH_LIST_DCN10(_MASK)
 445};
 446
 447static int map_transmitter_id_to_phy_instance(
 448	enum transmitter transmitter)
 449{
 450	switch (transmitter) {
 451	case TRANSMITTER_UNIPHY_A:
 452		return 0;
 453	break;
 454	case TRANSMITTER_UNIPHY_B:
 455		return 1;
 456	break;
 457	case TRANSMITTER_UNIPHY_C:
 458		return 2;
 459	break;
 460	case TRANSMITTER_UNIPHY_D:
 461		return 3;
 462	break;
 463	default:
 464		ASSERT(0);
 465		return 0;
 466	}
 467}
 468
 469#define clk_src_regs(index, pllid)\
 470[index] = {\
 471	CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
 472}
 473
 474static const struct dce110_clk_src_regs clk_src_regs[] = {
 475	clk_src_regs(0, A),
 476	clk_src_regs(1, B),
 477	clk_src_regs(2, C),
 478	clk_src_regs(3, D)
 479};
 480
 481static const struct dce110_clk_src_shift cs_shift = {
 482		CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 483};
 484
 485static const struct dce110_clk_src_mask cs_mask = {
 486		CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
 487};
 488
 489static const struct resource_caps res_cap = {
 490		.num_timing_generator = 4,
 491		.num_opp = 4,
 492		.num_video_plane = 4,
 493		.num_audio = 4,
 494		.num_stream_encoder = 4,
 495		.num_pll = 4,
 496		.num_ddc = 4,
 497};
 498
 499static const struct resource_caps rv2_res_cap = {
 500		.num_timing_generator = 3,
 501		.num_opp = 3,
 502		.num_video_plane = 3,
 503		.num_audio = 3,
 504		.num_stream_encoder = 3,
 505		.num_pll = 3,
 506		.num_ddc = 4,
 507};
 508
 509static const struct dc_plane_cap plane_cap = {
 510	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 511	.per_pixel_alpha = true,
 512
 513	.pixel_format_support = {
 514			.argb8888 = true,
 515			.nv12 = true,
 516			.fp16 = true,
 517			.p010 = false
 518	},
 519
 520	.max_upscale_factor = {
 521			.argb8888 = 16000,
 522			.nv12 = 16000,
 523			.fp16 = 1
 524	},
 525
 526	.max_downscale_factor = {
 527			.argb8888 = 250,
 528			.nv12 = 250,
 529			.fp16 = 1
 530	}
 531};
 532
 533static const struct dc_debug_options debug_defaults_drv = {
 534		.sanity_checks = true,
 535		.disable_dmcu = false,
 536		.force_abm_enable = false,
 537		.clock_trace = true,
 538
 539		/* raven smu dones't allow 0 disp clk,
 540		 * smu min disp clk limit is 50Mhz
 541		 * keep min disp clk 100Mhz avoid smu hang
 542		 */
 543		.min_disp_clk_khz = 100000,
 544
 545		.disable_pplib_clock_request = false,
 546		.disable_pplib_wm_range = false,
 547		.pplib_wm_report_mode = WM_REPORT_DEFAULT,
 548		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
 549		.force_single_disp_pipe_split = true,
 550		.disable_dcc = DCC_ENABLE,
 551		.voltage_align_fclk = true,
 552		.disable_stereo_support = true,
 553		.vsr_support = true,
 554		.performance_trace = false,
 555		.az_endpoint_mute_only = true,
 556		.recovery_enabled = false, /*enable this by default after testing.*/
 557		.max_downscale_src_width = 3840,
 558		.underflow_assert_delay_us = 0xFFFFFFFF,
 559		.using_dml2 = false,
 560};
 561
 562static const struct dc_check_config config_defaults = {
 563		.enable_legacy_fast_update = true,
 564};
 565
 566static void dcn10_dpp_destroy(struct dpp **dpp)
 567{
 568	kfree(TO_DCN10_DPP(*dpp));
 569	*dpp = NULL;
 570}
 571
 572static struct dpp *dcn10_dpp_create(
 573	struct dc_context *ctx,
 574	uint32_t inst)
 575{
 576	struct dcn10_dpp *dpp =
 577		kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
 578
 579	if (!dpp)
 580		return NULL;
 581
 582	dpp1_construct(dpp, ctx, inst,
 583		       &tf_regs[inst], &tf_shift, &tf_mask);
 584	return &dpp->base;
 585}
 586
 587static struct input_pixel_processor *dcn10_ipp_create(
 588	struct dc_context *ctx, uint32_t inst)
 589{
 590	struct dcn10_ipp *ipp =
 591		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 592
 593	if (!ipp) {
 594		BREAK_TO_DEBUGGER();
 595		return NULL;
 596	}
 597
 598	dcn10_ipp_construct(ipp, ctx, inst,
 599			&ipp_regs[inst], &ipp_shift, &ipp_mask);
 600	return &ipp->base;
 601}
 602
 603
 604static struct output_pixel_processor *dcn10_opp_create(
 605	struct dc_context *ctx, uint32_t inst)
 606{
 607	struct dcn10_opp *opp =
 608		kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
 609
 610	if (!opp) {
 611		BREAK_TO_DEBUGGER();
 612		return NULL;
 613	}
 614
 615	dcn10_opp_construct(opp, ctx, inst,
 616			&opp_regs[inst], &opp_shift, &opp_mask);
 617	return &opp->base;
 618}
 619
 620static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx,
 621					       uint32_t inst)
 622{
 623	struct aux_engine_dce110 *aux_engine =
 624		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 625
 626	if (!aux_engine)
 627		return NULL;
 628
 629	dce110_aux_engine_construct(aux_engine, ctx, inst,
 630				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 631				    &aux_engine_regs[inst],
 632					&aux_mask,
 633					&aux_shift,
 634					ctx->dc->caps.extended_aux_timeout_support);
 635
 636	return &aux_engine->base;
 637}
 638#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 639
 640static const struct dce_i2c_registers i2c_hw_regs[] = {
 641		i2c_inst_regs(1),
 642		i2c_inst_regs(2),
 643		i2c_inst_regs(3),
 644		i2c_inst_regs(4),
 645		i2c_inst_regs(5),
 646		i2c_inst_regs(6),
 647};
 648
 649static const struct dce_i2c_shift i2c_shifts = {
 650		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 651};
 652
 653static const struct dce_i2c_mask i2c_masks = {
 654		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
 655};
 656
 657static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx,
 658					      uint32_t inst)
 659{
 660	struct dce_i2c_hw *dce_i2c_hw =
 661		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 662
 663	if (!dce_i2c_hw)
 664		return NULL;
 665
 666	dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 667				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 668
 669	return dce_i2c_hw;
 670}
 671static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
 672{
 673	struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
 674					  GFP_KERNEL);
 675
 676	if (!mpc10)
 677		return NULL;
 678
 679	dcn10_mpc_construct(mpc10, ctx,
 680			&mpc_regs,
 681			&mpc_shift,
 682			&mpc_mask,
 683			4);
 684
 685	return &mpc10->base;
 686}
 687
 688static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
 689{
 690	struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub),
 691					  GFP_KERNEL);
 692
 693	if (!dcn10_hubbub)
 694		return NULL;
 695
 696	hubbub1_construct(&dcn10_hubbub->base, ctx,
 697			&hubbub_reg,
 698			&hubbub_shift,
 699			&hubbub_mask);
 700
 701	return &dcn10_hubbub->base;
 702}
 703
 704static struct timing_generator *dcn10_timing_generator_create(
 705		struct dc_context *ctx,
 706		uint32_t instance)
 707{
 708	struct optc *tgn10 =
 709		kzalloc(sizeof(struct optc), GFP_KERNEL);
 710
 711	if (!tgn10)
 712		return NULL;
 713
 714	tgn10->base.inst = instance;
 715	tgn10->base.ctx = ctx;
 716
 717	tgn10->tg_regs = &tg_regs[instance];
 718	tgn10->tg_shift = &tg_shift;
 719	tgn10->tg_mask = &tg_mask;
 720
 721	dcn10_timing_generator_init(tgn10);
 722
 723	return &tgn10->base;
 724}
 725
 726static const struct encoder_feature_support link_enc_feature = {
 727		.max_hdmi_deep_color = COLOR_DEPTH_121212,
 728		.max_hdmi_pixel_clock = 600000,
 729		.hdmi_ycbcr420_supported = true,
 730		.dp_ycbcr420_supported = true,
 731		.flags.bits.IS_HBR2_CAPABLE = true,
 732		.flags.bits.IS_HBR3_CAPABLE = true,
 733		.flags.bits.IS_TPS3_CAPABLE = true,
 734		.flags.bits.IS_TPS4_CAPABLE = true
 735};
 736
 737static struct link_encoder *dcn10_link_encoder_create(
 738	struct dc_context *ctx,
 739	const struct encoder_init_data *enc_init_data)
 740{
 741	struct dcn10_link_encoder *enc10 =
 742		kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
 743	int link_regs_id;
 744
 745	if (!enc10 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
 746		return NULL;
 747
 748	link_regs_id =
 749		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
 750
 751	dcn10_link_encoder_construct(enc10,
 752				      enc_init_data,
 753				      &link_enc_feature,
 754				      &link_enc_regs[link_regs_id],
 755				      &link_enc_aux_regs[enc_init_data->channel - 1],
 756				      &link_enc_hpd_regs[enc_init_data->hpd_source],
 757				      &le_shift,
 758				      &le_mask);
 759
 760	return &enc10->base;
 761}
 762
 763static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data)
 764{
 765	struct dce_panel_cntl *panel_cntl =
 766		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
 767
 768	if (!panel_cntl)
 769		return NULL;
 770
 771	dce_panel_cntl_construct(panel_cntl,
 772			init_data,
 773			&panel_cntl_regs[init_data->inst],
 774			&panel_cntl_shift,
 775			&panel_cntl_mask);
 776
 777	return &panel_cntl->base;
 778}
 779
 780static struct clock_source *dcn10_clock_source_create(
 781	struct dc_context *ctx,
 782	struct dc_bios *bios,
 783	enum clock_source_id id,
 784	const struct dce110_clk_src_regs *regs,
 785	bool dp_clk_src)
 786{
 787	struct dce110_clk_src *clk_src =
 788		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 789
 790	if (!clk_src)
 791		return NULL;
 792
 793	if (dce112_clk_src_construct(clk_src, ctx, bios, id,
 794			regs, &cs_shift, &cs_mask)) {
 795		clk_src->base.dp_clk_src = dp_clk_src;
 796		return &clk_src->base;
 797	}
 798
 799	kfree(clk_src);
 800	BREAK_TO_DEBUGGER();
 801	return NULL;
 802}
 803
 804static void read_dce_straps(
 805	struct dc_context *ctx,
 806	struct resource_straps *straps)
 807{
 808	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 809		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 810}
 811
 812static struct audio *create_audio(
 813		struct dc_context *ctx, unsigned int inst)
 814{
 815	return dce_audio_create(ctx, inst,
 816			&audio_regs[inst], &audio_shift, &audio_mask);
 817}
 818
 819static struct stream_encoder *dcn10_stream_encoder_create(
 820	enum engine_id eng_id,
 821	struct dc_context *ctx)
 822{
 823	struct dcn10_stream_encoder *enc1 =
 824		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
 825
 826	if (!enc1)
 827		return NULL;
 828
 829	dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
 830					&stream_enc_regs[eng_id],
 831					&se_shift, &se_mask);
 832	return &enc1->base;
 833}
 834
 835static const struct dce_hwseq_registers hwseq_reg = {
 836		HWSEQ_DCN1_REG_LIST()
 837};
 838
 839static const struct dce_hwseq_shift hwseq_shift = {
 840		HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
 841};
 842
 843static const struct dce_hwseq_mask hwseq_mask = {
 844		HWSEQ_DCN1_MASK_SH_LIST(_MASK)
 845};
 846
 847static struct dce_hwseq *dcn10_hwseq_create(
 848	struct dc_context *ctx)
 849{
 850	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 851
 852	if (hws) {
 853		hws->ctx = ctx;
 854		hws->regs = &hwseq_reg;
 855		hws->shifts = &hwseq_shift;
 856		hws->masks = &hwseq_mask;
 857		hws->wa.DEGVIDCN10_253 = true;
 858		hws->wa.false_optc_underflow = true;
 859		hws->wa.DEGVIDCN10_254 = true;
 860
 861		if ((ctx->asic_id.chip_family == FAMILY_RV) &&
 862			ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev))
 863			switch (ctx->asic_id.pci_revision_id) {
 864			case PRID_POLLOCK_94:
 865			case PRID_POLLOCK_95:
 866			case PRID_POLLOCK_E9:
 867			case PRID_POLLOCK_EA:
 868			case PRID_POLLOCK_EB:
 869				hws->wa.wait_hubpret_read_start_during_mpo_transition = true;
 870				break;
 871			default:
 872				hws->wa.wait_hubpret_read_start_during_mpo_transition = false;
 873				break;
 874			}
 875	}
 876	return hws;
 877}
 878
 879static const struct resource_create_funcs res_create_funcs = {
 880	.read_dce_straps = read_dce_straps,
 881	.create_audio = create_audio,
 882	.create_stream_encoder = dcn10_stream_encoder_create,
 883	.create_hwseq = dcn10_hwseq_create,
 884};
 885
 886static void dcn10_clock_source_destroy(struct clock_source **clk_src)
 887{
 888	kfree(TO_DCE110_CLK_SRC(*clk_src));
 889	*clk_src = NULL;
 890}
 891
 892static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)
 893{
 894	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
 895
 896	if (!pp_smu)
 897		return pp_smu;
 898
 899	dm_pp_get_funcs(ctx, pp_smu);
 900	return pp_smu;
 901}
 902
 903static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
 904{
 905	unsigned int i;
 906
 907	for (i = 0; i < pool->base.stream_enc_count; i++) {
 908		if (pool->base.stream_enc[i] != NULL) {
 909			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 910			pool->base.stream_enc[i] = NULL;
 911		}
 912	}
 913
 914	if (pool->base.mpc != NULL) {
 915		kfree(TO_DCN10_MPC(pool->base.mpc));
 916		pool->base.mpc = NULL;
 917	}
 918
 919	kfree(pool->base.hubbub);
 920	pool->base.hubbub = NULL;
 921
 922	for (i = 0; i < pool->base.pipe_count; i++) {
 923		if (pool->base.opps[i] != NULL)
 924			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 925
 926		if (pool->base.dpps[i] != NULL)
 927			dcn10_dpp_destroy(&pool->base.dpps[i]);
 928
 929		if (pool->base.ipps[i] != NULL)
 930			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 931
 932		if (pool->base.hubps[i] != NULL) {
 933			kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
 934			pool->base.hubps[i] = NULL;
 935		}
 936
 937		if (pool->base.irqs != NULL) {
 938			dal_irq_service_destroy(&pool->base.irqs);
 939		}
 940
 941		if (pool->base.timing_generators[i] != NULL)	{
 942			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 943			pool->base.timing_generators[i] = NULL;
 944		}
 945	}
 946
 947	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 948		if (pool->base.engines[i] != NULL)
 949			dce110_engine_destroy(&pool->base.engines[i]);
 950		kfree(pool->base.hw_i2cs[i]);
 951		pool->base.hw_i2cs[i] = NULL;
 952		kfree(pool->base.sw_i2cs[i]);
 953		pool->base.sw_i2cs[i] = NULL;
 954	}
 955
 956	for (i = 0; i < pool->base.audio_count; i++) {
 957		if (pool->base.audios[i])
 958			dce_aud_destroy(&pool->base.audios[i]);
 959	}
 960
 961	for (i = 0; i < pool->base.clk_src_count; i++) {
 962		if (pool->base.clock_sources[i] != NULL) {
 963			dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
 964			pool->base.clock_sources[i] = NULL;
 965		}
 966	}
 967
 968	if (pool->base.dp_clock_source != NULL) {
 969		dcn10_clock_source_destroy(&pool->base.dp_clock_source);
 970		pool->base.dp_clock_source = NULL;
 971	}
 972
 973	if (pool->base.abm != NULL)
 974		dce_abm_destroy(&pool->base.abm);
 975
 976	if (pool->base.dmcu != NULL)
 977		dce_dmcu_destroy(&pool->base.dmcu);
 978
 979	kfree(pool->base.pp_smu);
 980}
 981
 982static struct hubp *dcn10_hubp_create(
 983	struct dc_context *ctx,
 984	uint32_t inst)
 985{
 986	struct dcn10_hubp *hubp1 =
 987		kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
 988
 989	if (!hubp1)
 990		return NULL;
 991
 992	dcn10_hubp_construct(hubp1, ctx, inst,
 993			     &hubp_regs[inst], &hubp_shift, &hubp_mask);
 994	return &hubp1->base;
 995}
 996
 997static void get_pixel_clock_parameters(
 998	const struct pipe_ctx *pipe_ctx,
 999	struct pixel_clk_params *pixel_clk_params)
1000{
1001	const struct dc_stream_state *stream = pipe_ctx->stream;
1002	pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1003	pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1004	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1005	pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1006	/* TODO: un-hardcode*/
1007	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1008		LINK_RATE_REF_FREQ_IN_KHZ;
1009	pixel_clk_params->flags.ENABLE_SS = 0;
1010	pixel_clk_params->color_depth =
1011		stream->timing.display_color_depth;
1012	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1013	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1014
1015	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1016		pixel_clk_params->color_depth = COLOR_DEPTH_888;
1017
1018	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1019		pixel_clk_params->requested_pix_clk_100hz  /= 2;
1020	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1021		pixel_clk_params->requested_pix_clk_100hz *= 2;
1022
1023}
1024
1025static void build_clamping_params(struct dc_stream_state *stream)
1026{
1027	stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1028	stream->clamping.c_depth = stream->timing.display_color_depth;
1029	stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1030}
1031
1032static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1033{
1034
1035	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1036
1037	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1038		pipe_ctx->clock_source,
1039		&pipe_ctx->stream_res.pix_clk_params,
1040		&pipe_ctx->pll_settings);
1041
1042	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1043
1044	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1045					&pipe_ctx->stream->bit_depth_params);
1046	build_clamping_params(pipe_ctx->stream);
1047}
1048
1049static enum dc_status build_mapped_resource(
1050		const struct dc *dc,
1051		struct dc_state *context,
1052		struct dc_stream_state *stream)
1053{
1054	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
1055
1056	if (!pipe_ctx)
1057		return DC_ERROR_UNEXPECTED;
1058
1059	build_pipe_hw_param(pipe_ctx);
1060	return DC_OK;
1061}
1062
1063static enum dc_status dcn10_add_stream_to_ctx(
1064		struct dc *dc,
1065		struct dc_state *new_ctx,
1066		struct dc_stream_state *dc_stream)
1067{
1068	enum dc_status result = DC_ERROR_UNEXPECTED;
1069
1070	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1071
1072	if (result == DC_OK)
1073		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1074
1075
1076	if (result == DC_OK)
1077		result = build_mapped_resource(dc, new_ctx, dc_stream);
1078
1079	return result;
1080}
1081
1082static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer(
1083		const struct dc_state *cur_ctx,
1084		struct dc_state *new_ctx,
1085		const struct resource_pool *pool,
1086		const struct pipe_ctx *opp_head_pipe)
1087{
1088	struct resource_context *res_ctx = &new_ctx->res_ctx;
1089	struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);
1090	struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);
1091
1092	if (!head_pipe) {
1093		ASSERT(0);
1094		return NULL;
1095	}
1096
1097	if (!idle_pipe)
1098		return NULL;
1099
1100	idle_pipe->stream = head_pipe->stream;
1101	idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1102	idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1103	idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1104
1105	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1106	idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1107	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1108	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1109
1110	return idle_pipe;
1111}
1112
1113static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1114		const struct dc_dcc_surface_param *input,
1115		struct dc_surface_dcc_cap *output)
1116{
1117	return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1118			dc->res_pool->hubbub,
1119			input,
1120			output);
1121}
1122
1123static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1124{
1125	struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1126
1127	dcn10_resource_destruct(dcn10_pool);
1128	kfree(dcn10_pool);
1129	*pool = NULL;
1130}
1131
1132static enum dc_status dcn10_validate_bandwidth(
1133		struct dc *dc,
1134		struct dc_state *context,
1135		enum dc_validate_mode validate_mode)
1136{
1137	bool voltage_supported;
1138
1139	DC_FP_START();
1140	voltage_supported = dcn_validate_bandwidth(dc, context, validate_mode);
1141	DC_FP_END();
1142
1143	return voltage_supported ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1144}
1145
1146static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1147{
1148	if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1149			&& caps->max_video_width != 0
1150			&& plane_state->src_rect.width > caps->max_video_width)
1151		return DC_FAIL_SURFACE_VALIDATE;
1152
1153	return DC_OK;
1154}
1155
1156static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)
1157{
1158	int i, j;
1159	bool video_down_scaled = false;
1160	bool video_large = false;
1161	bool desktop_large = false;
1162	bool dcc_disabled = false;
1163	bool mpo_enabled = false;
1164
1165	for (i = 0; i < context->stream_count; i++) {
1166		if (context->stream_status[i].plane_count == 0)
1167			continue;
1168
1169		if (context->stream_status[i].plane_count > 2)
1170			return DC_FAIL_UNSUPPORTED_1;
1171
1172		if (context->stream_status[i].plane_count > 1)
1173			mpo_enabled = true;
1174
1175		for (j = 0; j < context->stream_status[i].plane_count; j++) {
1176			struct dc_plane_state *plane =
1177				context->stream_status[i].plane_states[j];
1178
1179
1180			if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1181
1182				if (plane->src_rect.width > plane->dst_rect.width ||
1183						plane->src_rect.height > plane->dst_rect.height)
1184					video_down_scaled = true;
1185
1186				if (plane->src_rect.width >= 3840)
1187					video_large = true;
1188
1189			} else {
1190				if (plane->src_rect.width >= 3840)
1191					desktop_large = true;
1192				if (!plane->dcc.enable)
1193					dcc_disabled = true;
1194			}
1195		}
1196	}
1197
1198	/* Disable MPO in multi-display configurations. */
1199	if (context->stream_count > 1 && mpo_enabled)
1200		return DC_FAIL_UNSUPPORTED_1;
1201
1202	/*
1203	 * Workaround: On DCN10 there is UMC issue that causes underflow when
1204	 * playing 4k video on 4k desktop with video downscaled and single channel
1205	 * memory
1206	 */
1207	if (video_large && desktop_large && video_down_scaled && dcc_disabled &&
1208			dc->dcn_soc->number_of_channels == 1)
1209		return DC_FAIL_SURFACE_VALIDATE;
1210
1211	return DC_OK;
1212}
1213
1214static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1215{
1216	enum surface_pixel_format surf_pix_format = plane_state->format;
1217	unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
1218
1219	enum swizzle_mode_values swizzle = DC_SW_LINEAR;
1220
1221	if (bpp == 64)
1222		swizzle = DC_SW_64KB_D;
1223	else
1224		swizzle = DC_SW_64KB_S;
1225
1226	plane_state->tiling_info.gfx9.swizzle = swizzle;
1227	return DC_OK;
1228}
1229
1230struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
1231		struct resource_context *res_ctx,
1232		const struct resource_pool *pool,
1233		struct dc_stream_state *stream)
1234{
1235	int i;
1236	int j = -1;
1237	struct dc_link *link = stream->link;
1238
1239	for (i = 0; i < pool->stream_enc_count; i++) {
1240		if (!res_ctx->is_stream_enc_acquired[i] &&
1241				pool->stream_enc[i]) {
1242			/* Store first available for MST second display
1243			 * in daisy chain use case
1244			 */
1245
1246			if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL)
1247				j = i;
1248
1249			if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id ==
1250					link->link_enc->preferred_engine)
1251				return pool->stream_enc[i];
1252
1253			if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && pool->stream_enc[i]->id ==
1254					link->dpia_preferred_eng_id)
1255				return pool->stream_enc[i];
1256		}
1257	}
1258
1259	/*
1260	 * For CZ and later, we can allow DIG FE and BE to differ for all display types
1261	 */
1262
1263	if (j >= 0)
1264		return pool->stream_enc[j];
1265
1266	return NULL;
1267}
1268
1269unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)
1270{
1271	return pipe_ctx->pipe_dlg_param.vstartup_start;
1272}
1273
1274static const struct dc_cap_funcs cap_funcs = {
1275	.get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1276};
1277
1278static const struct resource_funcs dcn10_res_pool_funcs = {
1279	.destroy = dcn10_destroy_resource_pool,
1280	.link_enc_create = dcn10_link_encoder_create,
1281	.panel_cntl_create = dcn10_panel_cntl_create,
1282	.validate_bandwidth = dcn10_validate_bandwidth,
1283	.acquire_free_pipe_as_secondary_dpp_pipe = dcn10_acquire_free_pipe_for_layer,
1284	.validate_plane = dcn10_validate_plane,
1285	.validate_global = dcn10_validate_global,
1286	.add_stream_to_ctx = dcn10_add_stream_to_ctx,
1287	.patch_unknown_plane_state = dcn10_patch_unknown_plane_state,
1288	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1289	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
1290};
1291
1292static uint32_t read_pipe_fuses(struct dc_context *ctx)
1293{
1294	uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1295	/* RV1 support max 4 pipes */
1296	value = value & 0xf;
1297	return value;
1298}
1299
1300static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1301{
1302	int i;
1303
1304	if (clks->num_levels == 0)
1305		return false;
1306
1307	for (i = 0; i < clks->num_levels; i++)
1308		/* Ensure that the result is sane */
1309		if (clks->data[i].clocks_in_khz == 0)
1310			return false;
1311
1312	return true;
1313}
1314
1315static bool dcn10_resource_construct(
1316	uint8_t num_virtual_links,
1317	struct dc *dc,
1318	struct dcn10_resource_pool *pool)
1319{
1320	int i;
1321	int j;
1322	struct dc_context *ctx = dc->ctx;
1323	uint32_t pipe_fuses = read_pipe_fuses(ctx);
1324	struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1325	int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1326	bool res;
1327
1328	ctx->dc_bios->regs = &bios_regs;
1329
1330	if (ctx->dce_version == DCN_VERSION_1_01)
1331		pool->base.res_cap = &rv2_res_cap;
1332	else
1333		pool->base.res_cap = &res_cap;
1334	pool->base.funcs = &dcn10_res_pool_funcs;
1335
1336	/*
1337	 * TODO fill in from actual raven resource when we create
1338	 * more than virtual encoder
1339	 */
1340
1341	/*************************************************
1342	 *  Resource + asic cap harcoding                *
1343	 *************************************************/
1344	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1345
1346	/* max pipe num for ASIC before check pipe fuses */
1347	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1348
1349	if (dc->ctx->dce_version == DCN_VERSION_1_01)
1350		pool->base.pipe_count = 3;
1351	dc->caps.max_video_width = 3840;
1352	dc->caps.max_downscale_ratio = 200;
1353	dc->caps.i2c_speed_in_khz = 100;
1354	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1355	dc->caps.max_cursor_size = 256;
1356	dc->caps.min_horizontal_blanking_period = 80;
1357	dc->caps.max_slave_planes = 1;
1358	dc->caps.max_slave_yuv_planes = 1;
1359	dc->caps.max_slave_rgb_planes = 0;
1360	dc->caps.is_apu = true;
1361	dc->caps.post_blend_color_processing = false;
1362	dc->caps.extended_aux_timeout_support = false;
1363
1364	/* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1365	dc->caps.force_dp_tps4_for_cp2520 = true;
1366
1367	/* Color pipeline capabilities */
1368	dc->caps.color.dpp.dcn_arch = 1;
1369	dc->caps.color.dpp.input_lut_shared = 1;
1370	dc->caps.color.dpp.icsc = 1;
1371	dc->caps.color.dpp.dgam_ram = 1;
1372	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1373	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1374	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1375	dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1376	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1377	dc->caps.color.dpp.post_csc = 0;
1378	dc->caps.color.dpp.gamma_corr = 0;
1379	dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1380
1381	dc->caps.color.dpp.hw_3d_lut = 0;
1382	dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1
1383	dc->caps.color.dpp.ogam_rom_caps.srgb = 1;
1384	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;
1385	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1386	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1387	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1388	dc->caps.color.dpp.ocsc = 1;
1389
1390	/* no post-blend color operations */
1391	dc->caps.color.mpc.gamut_remap = 0;
1392	dc->caps.color.mpc.num_3dluts = 0;
1393	dc->caps.color.mpc.shared_3d_lut = 0;
1394	dc->caps.color.mpc.ogam_ram = 0;
1395	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1396	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1397	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1398	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1399	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1400	dc->caps.color.mpc.ocsc = 0;
1401	dc->debug = debug_defaults_drv;
1402	dc->check_config = config_defaults;
1403
1404	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1405		dc->debug = debug_defaults_drv;
1406
1407	/*************************************************
1408	 *  Create resources                             *
1409	 *************************************************/
1410
1411	pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1412			dcn10_clock_source_create(ctx, ctx->dc_bios,
1413				CLOCK_SOURCE_COMBO_PHY_PLL0,
1414				&clk_src_regs[0], false);
1415	pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1416			dcn10_clock_source_create(ctx, ctx->dc_bios,
1417				CLOCK_SOURCE_COMBO_PHY_PLL1,
1418				&clk_src_regs[1], false);
1419	pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1420			dcn10_clock_source_create(ctx, ctx->dc_bios,
1421				CLOCK_SOURCE_COMBO_PHY_PLL2,
1422				&clk_src_regs[2], false);
1423
1424	if (dc->ctx->dce_version == DCN_VERSION_1_0) {
1425		pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1426				dcn10_clock_source_create(ctx, ctx->dc_bios,
1427					CLOCK_SOURCE_COMBO_PHY_PLL3,
1428					&clk_src_regs[3], false);
1429	}
1430
1431	pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1432
1433	if (dc->ctx->dce_version == DCN_VERSION_1_01)
1434		pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1435
1436	pool->base.dp_clock_source =
1437			dcn10_clock_source_create(ctx, ctx->dc_bios,
1438				CLOCK_SOURCE_ID_DP_DTO,
1439				/* todo: not reuse phy_pll registers */
1440				&clk_src_regs[0], true);
1441
1442	for (i = 0; i < pool->base.clk_src_count; i++) {
1443		if (pool->base.clock_sources[i] == NULL) {
1444			dm_error("DC: failed to create clock sources!\n");
1445			BREAK_TO_DEBUGGER();
1446			goto fail;
1447		}
1448	}
1449
1450	pool->base.dmcu = dcn10_dmcu_create(ctx,
1451			&dmcu_regs,
1452			&dmcu_shift,
1453			&dmcu_mask);
1454	if (pool->base.dmcu == NULL) {
1455		dm_error("DC: failed to create dmcu!\n");
1456		BREAK_TO_DEBUGGER();
1457		goto fail;
1458	}
1459
1460	pool->base.abm = dce_abm_create(ctx,
1461			&abm_regs,
1462			&abm_shift,
1463			&abm_mask);
1464	if (pool->base.abm == NULL) {
1465		dm_error("DC: failed to create abm!\n");
1466		BREAK_TO_DEBUGGER();
1467		goto fail;
1468	}
1469
1470	dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1471	memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1472	memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1473
1474	DC_FP_START();
1475	dcn10_resource_construct_fp(dc);
1476	DC_FP_END();
1477
1478	if (!dc->config.is_vmin_only_asic)
1479		if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev))
1480			switch (dc->ctx->asic_id.pci_revision_id) {
1481			case PRID_DALI_DE:
1482			case PRID_DALI_DF:
1483			case PRID_DALI_E3:
1484			case PRID_DALI_E4:
1485			case PRID_POLLOCK_94:
1486			case PRID_POLLOCK_95:
1487			case PRID_POLLOCK_E9:
1488			case PRID_POLLOCK_EA:
1489			case PRID_POLLOCK_EB:
1490				dc->config.is_vmin_only_asic = true;
1491				break;
1492			default:
1493				break;
1494			}
1495
1496	pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1497
1498	/*
1499	 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
1500	 * implemented. So AZ D3 should work.For issue 197007.                   *
1501	 */
1502	if (pool->base.pp_smu != NULL
1503			&& pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
1504		dc->debug.az_endpoint_mute_only = false;
1505
1506
1507	if (!dc->debug.disable_pplib_clock_request) {
1508		/*
1509		 * TODO: This is not the proper way to obtain
1510		 * fabric_and_dram_bandwidth, should be min(fclk, memclk).
1511		 */
1512		res = dm_pp_get_clock_levels_by_type_with_voltage(
1513				ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1514
1515		DC_FP_START();
1516
1517		if (res)
1518			res = verify_clock_values(&fclks);
1519
1520		if (res)
1521			dcn_bw_update_from_pplib_fclks(dc, &fclks);
1522		else
1523			BREAK_TO_DEBUGGER();
1524
1525		DC_FP_END();
1526
1527		res = dm_pp_get_clock_levels_by_type_with_voltage(
1528			ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1529
1530		DC_FP_START();
1531
1532		if (res)
1533			res = verify_clock_values(&dcfclks);
1534
1535		if (res)
1536			dcn_bw_update_from_pplib_dcfclks(dc, &dcfclks);
1537		else
1538			BREAK_TO_DEBUGGER();
1539
1540		DC_FP_END();
1541	}
1542
1543	dcn_bw_sync_calcs_and_dml(dc);
1544	if (!dc->debug.disable_pplib_wm_range) {
1545		dc->res_pool = &pool->base;
1546		DC_FP_START();
1547		dcn_get_soc_clks(
1548			dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);
1549		DC_FP_END();
1550		dcn_bw_notify_pplib_of_wm_ranges(
1551			dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);
1552	}
1553
1554	{
1555		struct irq_service_init_data init_data;
1556		init_data.ctx = dc->ctx;
1557		pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1558		if (!pool->base.irqs)
1559			goto fail;
1560	}
1561
1562	/* index to valid pipe resource  */
1563	j = 0;
1564	/* mem input -> ipp -> dpp -> opp -> TG */
1565	for (i = 0; i < pool->base.pipe_count; i++) {
1566		/* if pipe is disabled, skip instance of HW pipe,
1567		 * i.e, skip ASIC register instance
1568		 */
1569		if ((pipe_fuses & (1 << i)) != 0)
1570			continue;
1571
1572		pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1573		if (pool->base.hubps[j] == NULL) {
1574			BREAK_TO_DEBUGGER();
1575			dm_error(
1576				"DC: failed to create memory input!\n");
1577			goto fail;
1578		}
1579
1580		pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1581		if (pool->base.ipps[j] == NULL) {
1582			BREAK_TO_DEBUGGER();
1583			dm_error(
1584				"DC: failed to create input pixel processor!\n");
1585			goto fail;
1586		}
1587
1588		pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1589		if (pool->base.dpps[j] == NULL) {
1590			BREAK_TO_DEBUGGER();
1591			dm_error(
1592				"DC: failed to create dpp!\n");
1593			goto fail;
1594		}
1595
1596		pool->base.opps[j] = dcn10_opp_create(ctx, i);
1597		if (pool->base.opps[j] == NULL) {
1598			BREAK_TO_DEBUGGER();
1599			dm_error(
1600				"DC: failed to create output pixel processor!\n");
1601			goto fail;
1602		}
1603
1604		pool->base.timing_generators[j] = dcn10_timing_generator_create(
1605				ctx, i);
1606		if (pool->base.timing_generators[j] == NULL) {
1607			BREAK_TO_DEBUGGER();
1608			dm_error("DC: failed to create tg!\n");
1609			goto fail;
1610		}
1611		/* check next valid pipe */
1612		j++;
1613	}
1614
1615	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1616		pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1617		if (pool->base.engines[i] == NULL) {
1618			BREAK_TO_DEBUGGER();
1619			dm_error(
1620				"DC:failed to create aux engine!!\n");
1621			goto fail;
1622		}
1623		pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);
1624		if (pool->base.hw_i2cs[i] == NULL) {
1625			BREAK_TO_DEBUGGER();
1626			dm_error(
1627				"DC:failed to create hw i2c!!\n");
1628			goto fail;
1629		}
1630		pool->base.sw_i2cs[i] = NULL;
1631	}
1632
1633	/* valid pipe num */
1634	pool->base.pipe_count = j;
1635	pool->base.timing_generator_count = j;
1636	pool->base.mpcc_count = j;
1637
1638	/* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1639	 * the value may be changed
1640	 */
1641	dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1642	dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1643
1644	pool->base.mpc = dcn10_mpc_create(ctx);
1645	if (pool->base.mpc == NULL) {
1646		BREAK_TO_DEBUGGER();
1647		dm_error("DC: failed to create mpc!\n");
1648		goto fail;
1649	}
1650
1651	pool->base.hubbub = dcn10_hubbub_create(ctx);
1652	if (pool->base.hubbub == NULL) {
1653		BREAK_TO_DEBUGGER();
1654		dm_error("DC: failed to create hubbub!\n");
1655		goto fail;
1656	}
1657
1658	if (!resource_construct(num_virtual_links, dc, &pool->base,
1659			&res_create_funcs))
1660		goto fail;
1661
1662	dcn10_hw_sequencer_construct(dc);
1663	dc->caps.max_planes =  pool->base.pipe_count;
1664
1665	for (i = 0; i < dc->caps.max_planes; ++i)
1666		dc->caps.planes[i] = plane_cap;
1667
1668	dc->cap_funcs = cap_funcs;
1669
1670	return true;
1671
1672fail:
1673
1674	dcn10_resource_destruct(pool);
1675
1676	return false;
1677}
1678
1679struct resource_pool *dcn10_create_resource_pool(
1680		const struct dc_init_data *init_data,
1681		struct dc *dc)
1682{
1683	struct dcn10_resource_pool *pool =
1684		kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1685
1686	if (!pool)
1687		return NULL;
1688
1689	if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
1690		return &pool->base;
1691
1692	kfree(pool);
1693	BREAK_TO_DEBUGGER();
1694	return NULL;
1695}