dce112_resource.c

   1/*
   2* Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "dm_services.h"
  27
  28#include "link_encoder.h"
  29#include "stream_encoder.h"
  30
  31#include "resource.h"
  32#include "include/irq_service_interface.h"
  33#include "dce110/dce110_resource.h"
  34#include "dce110/dce110_timing_generator.h"
  35
  36#include "irq/dce110/irq_service_dce110.h"
  37#include "dce/dce_mem_input.h"
  38#include "dce/dce_transform.h"
  39#include "dce/dce_link_encoder.h"
  40#include "dce/dce_stream_encoder.h"
  41#include "dce/dce_audio.h"
  42#include "dce/dce_opp.h"
  43#include "dce/dce_ipp.h"
  44#include "dce/dce_clock_source.h"
  45
  46#include "dce/dce_hwseq.h"
  47#include "dce112/dce112_hwseq.h"
  48#include "dce/dce_abm.h"
  49#include "dce/dce_dmcu.h"
  50#include "dce/dce_aux.h"
  51#include "dce/dce_i2c.h"
  52#include "dce/dce_panel_cntl.h"
  53
  54#include "reg_helper.h"
  55
  56#include "dce/dce_11_2_d.h"
  57#include "dce/dce_11_2_sh_mask.h"
  58
  59#include "dce100/dce100_resource.h"
  60#include "dce112_resource.h"
  61
  62#define DC_LOGGER				\
  63		dc->ctx->logger
  64
  65#ifndef mmDP_DPHY_INTERNAL_CTRL
  66	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
  67	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
  68	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
  69	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
  70	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
  71	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
  72	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
  73	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
  74	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
  75	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
  76#endif
  77
  78#ifndef mmBIOS_SCRATCH_2
  79	#define mmBIOS_SCRATCH_0 0x05C9
  80	#define mmBIOS_SCRATCH_2 0x05CB
  81	#define mmBIOS_SCRATCH_3 0x05CC
  82	#define mmBIOS_SCRATCH_6 0x05CF
  83#endif
  84
  85#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
  86	#define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
  87	#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
  88	#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
  89	#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
  90	#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
  91	#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
  92	#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
  93	#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
  94#endif
  95
  96#ifndef mmDP_DPHY_FAST_TRAINING
  97	#define mmDP_DPHY_FAST_TRAINING                         0x4ABC
  98	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
  99	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
 100	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
 101	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
 102	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
 103	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
 104	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
 105#endif
 106
 107enum dce112_clk_src_array_id {
 108	DCE112_CLK_SRC_PLL0,
 109	DCE112_CLK_SRC_PLL1,
 110	DCE112_CLK_SRC_PLL2,
 111	DCE112_CLK_SRC_PLL3,
 112	DCE112_CLK_SRC_PLL4,
 113	DCE112_CLK_SRC_PLL5,
 114
 115	DCE112_CLK_SRC_TOTAL
 116};
 117
 118static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
 119	{
 120		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 121		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
 122	},
 123	{
 124		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 125		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 126	},
 127	{
 128		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 129		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 130	},
 131	{
 132		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 133		.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 134	},
 135	{
 136		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 137		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 138	},
 139	{
 140		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 141		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 142	}
 143};
 144
 145/* set register offset */
 146#define SR(reg_name)\
 147	.reg_name = mm ## reg_name
 148
 149/* set register offset with instance */
 150#define SRI(reg_name, block, id)\
 151	.reg_name = mm ## block ## id ## _ ## reg_name
 152
 153static const struct dce_dmcu_registers dmcu_regs = {
 154		DMCU_DCE110_COMMON_REG_LIST()
 155};
 156
 157static const struct dce_dmcu_shift dmcu_shift = {
 158		DMCU_MASK_SH_LIST_DCE110(__SHIFT)
 159};
 160
 161static const struct dce_dmcu_mask dmcu_mask = {
 162		DMCU_MASK_SH_LIST_DCE110(_MASK)
 163};
 164
 165static const struct dce_abm_registers abm_regs = {
 166		ABM_DCE110_COMMON_REG_LIST()
 167};
 168
 169static const struct dce_abm_shift abm_shift = {
 170		ABM_MASK_SH_LIST_DCE110(__SHIFT)
 171};
 172
 173static const struct dce_abm_mask abm_mask = {
 174		ABM_MASK_SH_LIST_DCE110(_MASK)
 175};
 176
 177static const struct dce110_aux_registers_shift aux_shift = {
 178	DCE_AUX_MASK_SH_LIST(__SHIFT)
 179};
 180
 181static const struct dce110_aux_registers_mask aux_mask = {
 182	DCE_AUX_MASK_SH_LIST(_MASK)
 183};
 184
 185#define ipp_regs(id)\
 186[id] = {\
 187		IPP_DCE110_REG_LIST_DCE_BASE(id)\
 188}
 189
 190static const struct dce_ipp_registers ipp_regs[] = {
 191		ipp_regs(0),
 192		ipp_regs(1),
 193		ipp_regs(2),
 194		ipp_regs(3),
 195		ipp_regs(4),
 196		ipp_regs(5)
 197};
 198
 199static const struct dce_ipp_shift ipp_shift = {
 200		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 201};
 202
 203static const struct dce_ipp_mask ipp_mask = {
 204		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 205};
 206
 207#define transform_regs(id)\
 208[id] = {\
 209		XFM_COMMON_REG_LIST_DCE110(id)\
 210}
 211
 212static const struct dce_transform_registers xfm_regs[] = {
 213		transform_regs(0),
 214		transform_regs(1),
 215		transform_regs(2),
 216		transform_regs(3),
 217		transform_regs(4),
 218		transform_regs(5)
 219};
 220
 221static const struct dce_transform_shift xfm_shift = {
 222		XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 223};
 224
 225static const struct dce_transform_mask xfm_mask = {
 226		XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
 227};
 228
 229#define aux_regs(id)\
 230[id] = {\
 231	AUX_REG_LIST(id)\
 232}
 233
 234static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 235		aux_regs(0),
 236		aux_regs(1),
 237		aux_regs(2),
 238		aux_regs(3),
 239		aux_regs(4),
 240		aux_regs(5)
 241};
 242
 243static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 244	{ DCE_PANEL_CNTL_REG_LIST() }
 245};
 246
 247static const struct dce_panel_cntl_shift panel_cntl_shift = {
 248	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 249};
 250
 251static const struct dce_panel_cntl_mask panel_cntl_mask = {
 252	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 253};
 254
 255#define hpd_regs(id)\
 256[id] = {\
 257	HPD_REG_LIST(id)\
 258}
 259
 260static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 261		hpd_regs(0),
 262		hpd_regs(1),
 263		hpd_regs(2),
 264		hpd_regs(3),
 265		hpd_regs(4),
 266		hpd_regs(5)
 267};
 268
 269#define link_regs(id)\
 270[id] = {\
 271	LE_DCE110_REG_LIST(id)\
 272}
 273
 274static const struct dce110_link_enc_registers link_enc_regs[] = {
 275	link_regs(0),
 276	link_regs(1),
 277	link_regs(2),
 278	link_regs(3),
 279	link_regs(4),
 280	link_regs(5),
 281	link_regs(6),
 282};
 283
 284#define stream_enc_regs(id)\
 285[id] = {\
 286	SE_COMMON_REG_LIST(id),\
 287	.TMDS_CNTL = 0,\
 288}
 289
 290static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 291	stream_enc_regs(0),
 292	stream_enc_regs(1),
 293	stream_enc_regs(2),
 294	stream_enc_regs(3),
 295	stream_enc_regs(4),
 296	stream_enc_regs(5)
 297};
 298
 299static const struct dce_stream_encoder_shift se_shift = {
 300		SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
 301};
 302
 303static const struct dce_stream_encoder_mask se_mask = {
 304		SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
 305};
 306
 307#define opp_regs(id)\
 308[id] = {\
 309	OPP_DCE_112_REG_LIST(id),\
 310}
 311
 312static const struct dce_opp_registers opp_regs[] = {
 313	opp_regs(0),
 314	opp_regs(1),
 315	opp_regs(2),
 316	opp_regs(3),
 317	opp_regs(4),
 318	opp_regs(5)
 319};
 320
 321static const struct dce_opp_shift opp_shift = {
 322	OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
 323};
 324
 325static const struct dce_opp_mask opp_mask = {
 326	OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
 327};
 328
 329#define aux_engine_regs(id)\
 330[id] = {\
 331	AUX_COMMON_REG_LIST(id), \
 332	.AUX_RESET_MASK = 0 \
 333}
 334
 335static const struct dce110_aux_registers aux_engine_regs[] = {
 336		aux_engine_regs(0),
 337		aux_engine_regs(1),
 338		aux_engine_regs(2),
 339		aux_engine_regs(3),
 340		aux_engine_regs(4),
 341		aux_engine_regs(5)
 342};
 343
 344#define audio_regs(id)\
 345[id] = {\
 346	AUD_COMMON_REG_LIST(id)\
 347}
 348
 349static const struct dce_audio_registers audio_regs[] = {
 350	audio_regs(0),
 351	audio_regs(1),
 352	audio_regs(2),
 353	audio_regs(3),
 354	audio_regs(4),
 355	audio_regs(5)
 356};
 357
 358static const struct dce_audio_shift audio_shift = {
 359		AUD_COMMON_MASK_SH_LIST(__SHIFT)
 360};
 361
 362static const struct dce_audio_mask audio_mask = {
 363		AUD_COMMON_MASK_SH_LIST(_MASK)
 364};
 365
 366#define clk_src_regs(index, id)\
 367[index] = {\
 368	CS_COMMON_REG_LIST_DCE_112(id),\
 369}
 370
 371static const struct dce110_clk_src_regs clk_src_regs[] = {
 372	clk_src_regs(0, A),
 373	clk_src_regs(1, B),
 374	clk_src_regs(2, C),
 375	clk_src_regs(3, D),
 376	clk_src_regs(4, E),
 377	clk_src_regs(5, F)
 378};
 379
 380static const struct dce110_clk_src_shift cs_shift = {
 381		CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
 382};
 383
 384static const struct dce110_clk_src_mask cs_mask = {
 385		CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
 386};
 387
 388static const struct bios_registers bios_regs = {
 389	.BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0,
 390	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
 391	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 392};
 393
 394static const struct resource_caps polaris_10_resource_cap = {
 395		.num_timing_generator = 6,
 396		.num_audio = 6,
 397		.num_stream_encoder = 6,
 398		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
 399		.num_ddc = 6,
 400};
 401
 402static const struct resource_caps polaris_11_resource_cap = {
 403		.num_timing_generator = 5,
 404		.num_audio = 5,
 405		.num_stream_encoder = 5,
 406		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
 407		.num_ddc = 5,
 408};
 409
 410static const struct dc_plane_cap plane_cap = {
 411	.type = DC_PLANE_TYPE_DCE_RGB,
 412
 413	.pixel_format_support = {
 414			.argb8888 = true,
 415			.nv12 = false,
 416			.fp16 = true
 417	},
 418
 419	.max_upscale_factor = {
 420			.argb8888 = 16000,
 421			.nv12 = 1,
 422			.fp16 = 1
 423	},
 424
 425	.max_downscale_factor = {
 426			.argb8888 = 250,
 427			.nv12 = 1,
 428			.fp16 = 1
 429	},
 430	64,
 431	64
 432};
 433
 434static const struct dc_debug_options debug_defaults = { 0 };
 435
 436static const struct dc_check_config config_defaults = {
 437	.enable_legacy_fast_update = true,
 438};
 439
 440#define CTX  ctx
 441#define REG(reg) mm ## reg
 442
 443#ifndef mmCC_DC_HDMI_STRAPS
 444#define mmCC_DC_HDMI_STRAPS 0x4819
 445#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 446#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 447#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 448#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 449#endif
 450
 451static int map_transmitter_id_to_phy_instance(
 452	enum transmitter transmitter)
 453{
 454	switch (transmitter) {
 455	case TRANSMITTER_UNIPHY_A:
 456		return 0;
 457	case TRANSMITTER_UNIPHY_B:
 458		return 1;
 459	case TRANSMITTER_UNIPHY_C:
 460		return 2;
 461	case TRANSMITTER_UNIPHY_D:
 462		return 3;
 463	case TRANSMITTER_UNIPHY_E:
 464		return 4;
 465	case TRANSMITTER_UNIPHY_F:
 466		return 5;
 467	case TRANSMITTER_UNIPHY_G:
 468		return 6;
 469	default:
 470		ASSERT(0);
 471		return 0;
 472	}
 473}
 474
 475static void read_dce_straps(
 476	struct dc_context *ctx,
 477	struct resource_straps *straps)
 478{
 479	REG_GET_2(CC_DC_HDMI_STRAPS,
 480			HDMI_DISABLE, &straps->hdmi_disable,
 481			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 482
 483	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 484}
 485
 486static struct audio *create_audio(
 487		struct dc_context *ctx, unsigned int inst)
 488{
 489	return dce_audio_create(ctx, inst,
 490			&audio_regs[inst], &audio_shift, &audio_mask);
 491}
 492
 493
 494static struct timing_generator *dce112_timing_generator_create(
 495		struct dc_context *ctx,
 496		uint32_t instance,
 497		const struct dce110_timing_generator_offsets *offsets)
 498{
 499	struct dce110_timing_generator *tg110 =
 500		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 501
 502	if (!tg110)
 503		return NULL;
 504
 505	dce110_timing_generator_construct(tg110, ctx, instance, offsets);
 506	return &tg110->base;
 507}
 508
 509static struct stream_encoder *dce112_stream_encoder_create(
 510	enum engine_id eng_id,
 511	struct dc_context *ctx)
 512{
 513	struct dce110_stream_encoder *enc110 =
 514		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 515
 516	if (!enc110)
 517		return NULL;
 518
 519	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 520					&stream_enc_regs[eng_id],
 521					&se_shift, &se_mask);
 522	return &enc110->base;
 523}
 524
 525#define SRII(reg_name, block, id)\
 526	.reg_name[id] = mm ## block ## id ## _ ## reg_name
 527
 528static const struct dce_hwseq_registers hwseq_reg = {
 529		HWSEQ_DCE112_REG_LIST()
 530};
 531
 532static const struct dce_hwseq_shift hwseq_shift = {
 533		HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
 534};
 535
 536static const struct dce_hwseq_mask hwseq_mask = {
 537		HWSEQ_DCE112_MASK_SH_LIST(_MASK)
 538};
 539
 540static struct dce_hwseq *dce112_hwseq_create(
 541	struct dc_context *ctx)
 542{
 543	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 544
 545	if (hws) {
 546		hws->ctx = ctx;
 547		hws->regs = &hwseq_reg;
 548		hws->shifts = &hwseq_shift;
 549		hws->masks = &hwseq_mask;
 550	}
 551	return hws;
 552}
 553
 554static const struct resource_create_funcs res_create_funcs = {
 555	.read_dce_straps = read_dce_straps,
 556	.create_audio = create_audio,
 557	.create_stream_encoder = dce112_stream_encoder_create,
 558	.create_hwseq = dce112_hwseq_create,
 559};
 560
 561#define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
 562static const struct dce_mem_input_registers mi_regs[] = {
 563		mi_inst_regs(0),
 564		mi_inst_regs(1),
 565		mi_inst_regs(2),
 566		mi_inst_regs(3),
 567		mi_inst_regs(4),
 568		mi_inst_regs(5),
 569};
 570
 571static const struct dce_mem_input_shift mi_shifts = {
 572		MI_DCE11_2_MASK_SH_LIST(__SHIFT)
 573};
 574
 575static const struct dce_mem_input_mask mi_masks = {
 576		MI_DCE11_2_MASK_SH_LIST(_MASK)
 577};
 578
 579static struct mem_input *dce112_mem_input_create(
 580	struct dc_context *ctx,
 581	uint32_t inst)
 582{
 583	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 584					       GFP_KERNEL);
 585
 586	if (!dce_mi) {
 587		BREAK_TO_DEBUGGER();
 588		return NULL;
 589	}
 590
 591	dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 592	return &dce_mi->base;
 593}
 594
 595static void dce112_transform_destroy(struct transform **xfm)
 596{
 597	kfree(TO_DCE_TRANSFORM(*xfm));
 598	*xfm = NULL;
 599}
 600
 601static struct transform *dce112_transform_create(
 602	struct dc_context *ctx,
 603	uint32_t inst)
 604{
 605	struct dce_transform *transform =
 606		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 607
 608	if (!transform)
 609		return NULL;
 610
 611	dce_transform_construct(transform, ctx, inst,
 612				&xfm_regs[inst], &xfm_shift, &xfm_mask);
 613	transform->lb_memory_size = 0x1404; /*5124*/
 614	return &transform->base;
 615}
 616
 617static const struct encoder_feature_support link_enc_feature = {
 618		.max_hdmi_deep_color = COLOR_DEPTH_121212,
 619		.max_hdmi_pixel_clock = 600000,
 620		.hdmi_ycbcr420_supported = true,
 621		.dp_ycbcr420_supported = false,
 622		.flags.bits.IS_HBR2_CAPABLE = true,
 623		.flags.bits.IS_HBR3_CAPABLE = true,
 624		.flags.bits.IS_TPS3_CAPABLE = true,
 625		.flags.bits.IS_TPS4_CAPABLE = true
 626};
 627
 628static struct link_encoder *dce112_link_encoder_create(
 629	struct dc_context *ctx,
 630	const struct encoder_init_data *enc_init_data)
 631{
 632	struct dce110_link_encoder *enc110 =
 633		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 634	int link_regs_id;
 635
 636	if (!enc110)
 637		return NULL;
 638
 639	link_regs_id =
 640		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
 641
 642	dce110_link_encoder_construct(enc110,
 643				      enc_init_data,
 644				      &link_enc_feature,
 645				      &link_enc_regs[link_regs_id],
 646				      &link_enc_aux_regs[enc_init_data->channel - 1],
 647				      enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ?
 648				      NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]);
 649	return &enc110->base;
 650}
 651
 652static struct panel_cntl *dce112_panel_cntl_create(const struct panel_cntl_init_data *init_data)
 653{
 654	struct dce_panel_cntl *panel_cntl =
 655		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
 656
 657	if (!panel_cntl)
 658		return NULL;
 659
 660	dce_panel_cntl_construct(panel_cntl,
 661			init_data,
 662			&panel_cntl_regs[init_data->inst],
 663			&panel_cntl_shift,
 664			&panel_cntl_mask);
 665
 666	return &panel_cntl->base;
 667}
 668
 669static struct input_pixel_processor *dce112_ipp_create(
 670	struct dc_context *ctx, uint32_t inst)
 671{
 672	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 673
 674	if (!ipp) {
 675		BREAK_TO_DEBUGGER();
 676		return NULL;
 677	}
 678
 679	dce_ipp_construct(ipp, ctx, inst,
 680			&ipp_regs[inst], &ipp_shift, &ipp_mask);
 681	return &ipp->base;
 682}
 683
 684static struct output_pixel_processor *dce112_opp_create(
 685	struct dc_context *ctx,
 686	uint32_t inst)
 687{
 688	struct dce110_opp *opp =
 689		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 690
 691	if (!opp)
 692		return NULL;
 693
 694	dce110_opp_construct(opp,
 695			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 696	return &opp->base;
 697}
 698
 699static struct dce_aux *dce112_aux_engine_create(
 700	struct dc_context *ctx,
 701	uint32_t inst)
 702{
 703	struct aux_engine_dce110 *aux_engine =
 704		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 705
 706	if (!aux_engine)
 707		return NULL;
 708
 709	dce110_aux_engine_construct(aux_engine, ctx, inst,
 710				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 711				    &aux_engine_regs[inst],
 712					&aux_mask,
 713					&aux_shift,
 714					ctx->dc->caps.extended_aux_timeout_support);
 715
 716	return &aux_engine->base;
 717}
 718#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 719
 720static const struct dce_i2c_registers i2c_hw_regs[] = {
 721		i2c_inst_regs(1),
 722		i2c_inst_regs(2),
 723		i2c_inst_regs(3),
 724		i2c_inst_regs(4),
 725		i2c_inst_regs(5),
 726		i2c_inst_regs(6),
 727};
 728
 729static const struct dce_i2c_shift i2c_shifts = {
 730		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 731};
 732
 733static const struct dce_i2c_mask i2c_masks = {
 734		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
 735};
 736
 737static struct dce_i2c_hw *dce112_i2c_hw_create(
 738	struct dc_context *ctx,
 739	uint32_t inst)
 740{
 741	struct dce_i2c_hw *dce_i2c_hw =
 742		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 743
 744	if (!dce_i2c_hw)
 745		return NULL;
 746
 747	dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 748				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 749
 750	return dce_i2c_hw;
 751}
 752static struct clock_source *dce112_clock_source_create(
 753	struct dc_context *ctx,
 754	struct dc_bios *bios,
 755	enum clock_source_id id,
 756	const struct dce110_clk_src_regs *regs,
 757	bool dp_clk_src)
 758{
 759	struct dce110_clk_src *clk_src =
 760		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 761
 762	if (!clk_src)
 763		return NULL;
 764
 765	if (dce112_clk_src_construct(clk_src, ctx, bios, id,
 766			regs, &cs_shift, &cs_mask)) {
 767		clk_src->base.dp_clk_src = dp_clk_src;
 768		return &clk_src->base;
 769	}
 770
 771	kfree(clk_src);
 772	BREAK_TO_DEBUGGER();
 773	return NULL;
 774}
 775
 776static void dce112_clock_source_destroy(struct clock_source **clk_src)
 777{
 778	kfree(TO_DCE110_CLK_SRC(*clk_src));
 779	*clk_src = NULL;
 780}
 781
 782static void dce112_resource_destruct(struct dce110_resource_pool *pool)
 783{
 784	unsigned int i;
 785
 786	for (i = 0; i < pool->base.pipe_count; i++) {
 787		if (pool->base.opps[i] != NULL)
 788			dce110_opp_destroy(&pool->base.opps[i]);
 789
 790		if (pool->base.transforms[i] != NULL)
 791			dce112_transform_destroy(&pool->base.transforms[i]);
 792
 793		if (pool->base.ipps[i] != NULL)
 794			dce_ipp_destroy(&pool->base.ipps[i]);
 795
 796		if (pool->base.mis[i] != NULL) {
 797			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 798			pool->base.mis[i] = NULL;
 799		}
 800
 801		if (pool->base.timing_generators[i] != NULL) {
 802			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 803			pool->base.timing_generators[i] = NULL;
 804		}
 805	}
 806
 807	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 808		if (pool->base.engines[i] != NULL)
 809			dce110_engine_destroy(&pool->base.engines[i]);
 810		if (pool->base.hw_i2cs[i] != NULL) {
 811			kfree(pool->base.hw_i2cs[i]);
 812			pool->base.hw_i2cs[i] = NULL;
 813		}
 814		if (pool->base.sw_i2cs[i] != NULL) {
 815			kfree(pool->base.sw_i2cs[i]);
 816			pool->base.sw_i2cs[i] = NULL;
 817		}
 818	}
 819
 820	for (i = 0; i < pool->base.stream_enc_count; i++) {
 821		if (pool->base.stream_enc[i] != NULL)
 822			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 823	}
 824
 825	for (i = 0; i < pool->base.clk_src_count; i++) {
 826		if (pool->base.clock_sources[i] != NULL) {
 827			dce112_clock_source_destroy(&pool->base.clock_sources[i]);
 828		}
 829	}
 830
 831	if (pool->base.dp_clock_source != NULL)
 832		dce112_clock_source_destroy(&pool->base.dp_clock_source);
 833
 834	for (i = 0; i < pool->base.audio_count; i++)	{
 835		if (pool->base.audios[i] != NULL) {
 836			dce_aud_destroy(&pool->base.audios[i]);
 837		}
 838	}
 839
 840	if (pool->base.abm != NULL)
 841		dce_abm_destroy(&pool->base.abm);
 842
 843	if (pool->base.dmcu != NULL)
 844		dce_dmcu_destroy(&pool->base.dmcu);
 845
 846	if (pool->base.irqs != NULL) {
 847		dal_irq_service_destroy(&pool->base.irqs);
 848	}
 849}
 850
 851static struct clock_source *find_matching_pll(
 852		struct resource_context *res_ctx,
 853		const struct resource_pool *pool,
 854		const struct dc_stream_state *const stream)
 855{
 856	switch (stream->link->link_enc->transmitter) {
 857	case TRANSMITTER_UNIPHY_A:
 858		return pool->clock_sources[DCE112_CLK_SRC_PLL0];
 859	case TRANSMITTER_UNIPHY_B:
 860		return pool->clock_sources[DCE112_CLK_SRC_PLL1];
 861	case TRANSMITTER_UNIPHY_C:
 862		return pool->clock_sources[DCE112_CLK_SRC_PLL2];
 863	case TRANSMITTER_UNIPHY_D:
 864		return pool->clock_sources[DCE112_CLK_SRC_PLL3];
 865	case TRANSMITTER_UNIPHY_E:
 866		return pool->clock_sources[DCE112_CLK_SRC_PLL4];
 867	case TRANSMITTER_UNIPHY_F:
 868		return pool->clock_sources[DCE112_CLK_SRC_PLL5];
 869	default:
 870		return NULL;
 871	}
 872}
 873
 874static enum dc_status build_mapped_resource(
 875		const struct dc *dc,
 876		struct dc_state *context,
 877		struct dc_stream_state *stream)
 878{
 879	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
 880
 881	if (!pipe_ctx)
 882		return DC_ERROR_UNEXPECTED;
 883
 884	dce110_resource_build_pipe_hw_param(pipe_ctx);
 885
 886	resource_build_info_frame(pipe_ctx);
 887
 888	return DC_OK;
 889}
 890
 891enum dc_status dce112_validate_bandwidth(
 892	struct dc *dc,
 893	struct dc_state *context,
 894	enum dc_validate_mode validate_mode)
 895{
 896	bool result = false;
 897
 898	DC_LOG_BANDWIDTH_CALCS(
 899		"%s: start",
 900		__func__);
 901
 902	if (bw_calcs(
 903			dc->ctx,
 904			dc->bw_dceip,
 905			dc->bw_vbios,
 906			context->res_ctx.pipe_ctx,
 907			dc->res_pool->pipe_count,
 908			&context->bw_ctx.bw.dce))
 909		result = true;
 910
 911	if (!result)
 912		DC_LOG_BANDWIDTH_VALIDATION(
 913			"%s: Bandwidth validation failed!",
 914			__func__);
 915
 916	if (memcmp(&dc->current_state->bw_ctx.bw.dce,
 917			&context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
 918
 919		DC_LOG_BANDWIDTH_CALCS(
 920			"%s: finish,\n"
 921			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 922			"stutMark_b: %d stutMark_a: %d\n"
 923			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 924			"stutMark_b: %d stutMark_a: %d\n"
 925			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 926			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
 927			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
 928			"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
 929			,
 930			__func__,
 931			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
 932			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
 933			context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
 934			context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
 935			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
 936			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
 937			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
 938			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
 939			context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
 940			context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
 941			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
 942			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
 943			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
 944			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
 945			context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
 946			context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
 947			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
 948			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
 949			context->bw_ctx.bw.dce.stutter_mode_enable,
 950			context->bw_ctx.bw.dce.cpuc_state_change_enable,
 951			context->bw_ctx.bw.dce.cpup_state_change_enable,
 952			context->bw_ctx.bw.dce.nbp_state_change_enable,
 953			context->bw_ctx.bw.dce.all_displays_in_sync,
 954			context->bw_ctx.bw.dce.dispclk_khz,
 955			context->bw_ctx.bw.dce.sclk_khz,
 956			context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
 957			context->bw_ctx.bw.dce.yclk_khz,
 958			context->bw_ctx.bw.dce.blackout_recovery_time_us);
 959	}
 960	return result ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
 961}
 962
 963enum dc_status resource_map_phy_clock_resources(
 964		const struct dc *dc,
 965		struct dc_state *context,
 966		struct dc_stream_state *stream)
 967{
 968
 969	/* acquire new resources */
 970	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(
 971			&context->res_ctx, stream);
 972
 973	if (!pipe_ctx)
 974		return DC_ERROR_UNEXPECTED;
 975
 976	if (dc_is_dp_signal(pipe_ctx->stream->signal)
 977		|| dc_is_virtual_signal(pipe_ctx->stream->signal))
 978		pipe_ctx->clock_source =
 979				dc->res_pool->dp_clock_source;
 980	else {
 981		if (stream && stream->link && stream->link->link_enc)
 982			pipe_ctx->clock_source = find_matching_pll(
 983				&context->res_ctx, dc->res_pool,
 984				stream);
 985	}
 986
 987	if (pipe_ctx->clock_source == NULL)
 988		return DC_NO_CLOCK_SOURCE_RESOURCE;
 989
 990	resource_reference_clock_source(
 991		&context->res_ctx,
 992		dc->res_pool,
 993		pipe_ctx->clock_source);
 994
 995	return DC_OK;
 996}
 997
 998static bool dce112_validate_surface_sets(
 999		struct dc_state *context)
1000{
1001	int i;
1002
1003	for (i = 0; i < context->stream_count; i++) {
1004		if (context->stream_status[i].plane_count == 0)
1005			continue;
1006
1007		if (context->stream_status[i].plane_count > 1)
1008			return false;
1009
1010		if (context->stream_status[i].plane_states[0]->format
1011				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
1012			return false;
1013	}
1014
1015	return true;
1016}
1017
1018enum dc_status dce112_add_stream_to_ctx(
1019		struct dc *dc,
1020		struct dc_state *new_ctx,
1021		struct dc_stream_state *dc_stream)
1022{
1023	enum dc_status result;
1024
1025	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1026
1027	if (result == DC_OK)
1028		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1029
1030
1031	if (result == DC_OK)
1032		result = build_mapped_resource(dc, new_ctx, dc_stream);
1033
1034	return result;
1035}
1036
1037static enum dc_status dce112_validate_global(
1038		struct dc *dc,
1039		struct dc_state *context)
1040{
1041	if (!dce112_validate_surface_sets(context))
1042		return DC_FAIL_SURFACE_VALIDATE;
1043
1044	return DC_OK;
1045}
1046
1047static void dce112_destroy_resource_pool(struct resource_pool **pool)
1048{
1049	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1050
1051	dce112_resource_destruct(dce110_pool);
1052	kfree(dce110_pool);
1053	*pool = NULL;
1054}
1055
1056static const struct resource_funcs dce112_res_pool_funcs = {
1057	.destroy = dce112_destroy_resource_pool,
1058	.link_enc_create = dce112_link_encoder_create,
1059	.panel_cntl_create = dce112_panel_cntl_create,
1060	.validate_bandwidth = dce112_validate_bandwidth,
1061	.validate_plane = dce100_validate_plane,
1062	.add_stream_to_ctx = dce112_add_stream_to_ctx,
1063	.validate_global = dce112_validate_global,
1064	.find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1065};
1066
1067static void bw_calcs_data_update_from_pplib(struct dc *dc)
1068{
1069	struct dm_pp_clock_levels_with_latency eng_clks = {0};
1070	struct dm_pp_clock_levels_with_latency mem_clks = {0};
1071	struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
1072	struct dm_pp_clock_levels clks = {0};
1073	int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
1074
1075	if (!dc->bw_vbios)
1076		return;
1077
1078	if (dc->bw_vbios->memory_type == bw_def_hbm)
1079		memory_type_multiplier = MEMORY_TYPE_HBM;
1080
1081	/*do system clock  TODO PPLIB: after PPLIB implement,
1082	 * then remove old way
1083	 */
1084	if (!dm_pp_get_clock_levels_by_type_with_latency(
1085			dc->ctx,
1086			DM_PP_CLOCK_TYPE_ENGINE_CLK,
1087			&eng_clks)) {
1088
1089		/* This is only for temporary */
1090		dm_pp_get_clock_levels_by_type(
1091				dc->ctx,
1092				DM_PP_CLOCK_TYPE_ENGINE_CLK,
1093				&clks);
1094		/* convert all the clock fro kHz to fix point mHz */
1095		dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1096				clks.clocks_in_khz[clks.num_levels-1], 1000);
1097		dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1098				clks.clocks_in_khz[clks.num_levels/8], 1000);
1099		dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1100				clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1101		dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1102				clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1103		dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1104				clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1105		dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1106				clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1107		dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1108				clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1109		dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1110				clks.clocks_in_khz[0], 1000);
1111
1112		/*do memory clock*/
1113		dm_pp_get_clock_levels_by_type(
1114				dc->ctx,
1115				DM_PP_CLOCK_TYPE_MEMORY_CLK,
1116				&clks);
1117
1118		dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1119			(int64_t)clks.clocks_in_khz[0] * memory_type_multiplier, 1000);
1120		dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1121			(int64_t)clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
1122			1000);
1123		dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1124			(int64_t)clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
1125			1000);
1126
1127		return;
1128	}
1129
1130	/* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
1131	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1132		eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1133	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1134		eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1135	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1136		eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1137	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1138		eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1139	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1140		eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1141	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1142		eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1143	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1144		eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1145	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1146			eng_clks.data[0].clocks_in_khz, 1000);
1147
1148	/*do memory clock*/
1149	dm_pp_get_clock_levels_by_type_with_latency(
1150			dc->ctx,
1151			DM_PP_CLOCK_TYPE_MEMORY_CLK,
1152			&mem_clks);
1153
1154	/* we don't need to call PPLIB for validation clock since they
1155	 * also give us the highest sclk and highest mclk (UMA clock).
1156	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
1157	 * YCLK = UMACLK*m_memoryTypeMultiplier
1158	 */
1159	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1160		(int64_t)mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
1161	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1162		(int64_t)mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
1163		1000);
1164	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1165		(int64_t)mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
1166		1000);
1167
1168	/* Now notify PPLib/SMU about which Watermarks sets they should select
1169	 * depending on DPM state they are in. And update BW MGR GFX Engine and
1170	 * Memory clock member variables for Watermarks calculations for each
1171	 * Watermark Set
1172	 */
1173	clk_ranges.num_wm_sets = 4;
1174	clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1175	clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1176			eng_clks.data[0].clocks_in_khz;
1177	clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1178			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1179	clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1180			mem_clks.data[0].clocks_in_khz;
1181	clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1182			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1183
1184	clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1185	clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1186			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1187	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1188	clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1189	clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1190			mem_clks.data[0].clocks_in_khz;
1191	clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1192			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1193
1194	clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1195	clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1196			eng_clks.data[0].clocks_in_khz;
1197	clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1198			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1199	clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1200			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1201	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1202	clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1203
1204	clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1205	clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1206			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1207	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1208	clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1209	clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1210			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1211	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1212	clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1213
1214	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1215	dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1216}
1217
1218static const struct resource_caps *dce112_resource_cap(
1219	struct hw_asic_id *asic_id)
1220{
1221	if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1222	    ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1223		return &polaris_11_resource_cap;
1224	else
1225		return &polaris_10_resource_cap;
1226}
1227
1228static bool dce112_resource_construct(
1229	uint8_t num_virtual_links,
1230	struct dc *dc,
1231	struct dce110_resource_pool *pool)
1232{
1233	unsigned int i;
1234	struct dc_context *ctx = dc->ctx;
1235
1236	ctx->dc_bios->regs = &bios_regs;
1237
1238	pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1239	pool->base.funcs = &dce112_res_pool_funcs;
1240
1241	/*************************************************
1242	 *  Resource + asic cap harcoding                *
1243	 *************************************************/
1244	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1245	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1246	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1247	dc->caps.max_downscale_ratio = 200;
1248	dc->caps.i2c_speed_in_khz = 100;
1249	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1250	dc->caps.max_cursor_size = 128;
1251	dc->caps.min_horizontal_blanking_period = 80;
1252	dc->caps.dual_link_dvi = true;
1253	dc->caps.extended_aux_timeout_support = false;
1254	dc->debug = debug_defaults;
1255	dc->check_config = config_defaults;
1256
1257	/*************************************************
1258	 *  Create resources                             *
1259	 *************************************************/
1260
1261	pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1262			dce112_clock_source_create(
1263				ctx, ctx->dc_bios,
1264				CLOCK_SOURCE_COMBO_PHY_PLL0,
1265				&clk_src_regs[0], false);
1266	pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1267			dce112_clock_source_create(
1268				ctx, ctx->dc_bios,
1269				CLOCK_SOURCE_COMBO_PHY_PLL1,
1270				&clk_src_regs[1], false);
1271	pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1272			dce112_clock_source_create(
1273				ctx, ctx->dc_bios,
1274				CLOCK_SOURCE_COMBO_PHY_PLL2,
1275				&clk_src_regs[2], false);
1276	pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1277			dce112_clock_source_create(
1278				ctx, ctx->dc_bios,
1279				CLOCK_SOURCE_COMBO_PHY_PLL3,
1280				&clk_src_regs[3], false);
1281	pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1282			dce112_clock_source_create(
1283				ctx, ctx->dc_bios,
1284				CLOCK_SOURCE_COMBO_PHY_PLL4,
1285				&clk_src_regs[4], false);
1286	pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1287			dce112_clock_source_create(
1288				ctx, ctx->dc_bios,
1289				CLOCK_SOURCE_COMBO_PHY_PLL5,
1290				&clk_src_regs[5], false);
1291	pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1292
1293	pool->base.dp_clock_source =  dce112_clock_source_create(
1294		ctx, ctx->dc_bios,
1295		CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1296
1297
1298	for (i = 0; i < pool->base.clk_src_count; i++) {
1299		if (pool->base.clock_sources[i] == NULL) {
1300			dm_error("DC: failed to create clock sources!\n");
1301			BREAK_TO_DEBUGGER();
1302			goto res_create_fail;
1303		}
1304	}
1305
1306	pool->base.dmcu = dce_dmcu_create(ctx,
1307			&dmcu_regs,
1308			&dmcu_shift,
1309			&dmcu_mask);
1310	if (pool->base.dmcu == NULL) {
1311		dm_error("DC: failed to create dmcu!\n");
1312		BREAK_TO_DEBUGGER();
1313		goto res_create_fail;
1314	}
1315
1316	pool->base.abm = dce_abm_create(ctx,
1317			&abm_regs,
1318			&abm_shift,
1319			&abm_mask);
1320	if (pool->base.abm == NULL) {
1321		dm_error("DC: failed to create abm!\n");
1322		BREAK_TO_DEBUGGER();
1323		goto res_create_fail;
1324	}
1325
1326	{
1327		struct irq_service_init_data init_data;
1328		init_data.ctx = dc->ctx;
1329		pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1330		if (!pool->base.irqs)
1331			goto res_create_fail;
1332	}
1333
1334	for (i = 0; i < pool->base.pipe_count; i++) {
1335		pool->base.timing_generators[i] =
1336				dce112_timing_generator_create(
1337					ctx,
1338					i,
1339					&dce112_tg_offsets[i]);
1340		if (pool->base.timing_generators[i] == NULL) {
1341			BREAK_TO_DEBUGGER();
1342			dm_error("DC: failed to create tg!\n");
1343			goto res_create_fail;
1344		}
1345
1346		pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1347		if (pool->base.mis[i] == NULL) {
1348			BREAK_TO_DEBUGGER();
1349			dm_error(
1350				"DC: failed to create memory input!\n");
1351			goto res_create_fail;
1352		}
1353
1354		pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1355		if (pool->base.ipps[i] == NULL) {
1356			BREAK_TO_DEBUGGER();
1357			dm_error(
1358				"DC:failed to create input pixel processor!\n");
1359			goto res_create_fail;
1360		}
1361
1362		pool->base.transforms[i] = dce112_transform_create(ctx, i);
1363		if (pool->base.transforms[i] == NULL) {
1364			BREAK_TO_DEBUGGER();
1365			dm_error(
1366				"DC: failed to create transform!\n");
1367			goto res_create_fail;
1368		}
1369
1370		pool->base.opps[i] = dce112_opp_create(
1371			ctx,
1372			i);
1373		if (pool->base.opps[i] == NULL) {
1374			BREAK_TO_DEBUGGER();
1375			dm_error(
1376				"DC:failed to create output pixel processor!\n");
1377			goto res_create_fail;
1378		}
1379	}
1380
1381	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1382		pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1383		if (pool->base.engines[i] == NULL) {
1384			BREAK_TO_DEBUGGER();
1385			dm_error(
1386				"DC:failed to create aux engine!!\n");
1387			goto res_create_fail;
1388		}
1389		pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1390		if (pool->base.hw_i2cs[i] == NULL) {
1391			BREAK_TO_DEBUGGER();
1392			dm_error(
1393				"DC:failed to create i2c engine!!\n");
1394			goto res_create_fail;
1395		}
1396		pool->base.sw_i2cs[i] = NULL;
1397	}
1398
1399	if (!resource_construct(num_virtual_links, dc, &pool->base,
1400			  &res_create_funcs))
1401		goto res_create_fail;
1402
1403	dc->caps.max_planes =  pool->base.pipe_count;
1404
1405	for (i = 0; i < dc->caps.max_planes; ++i)
1406		dc->caps.planes[i] = plane_cap;
1407
1408	/* Create hardware sequencer */
1409	dce112_hw_sequencer_construct(dc);
1410
1411	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1412
1413	bw_calcs_data_update_from_pplib(dc);
1414
1415	return true;
1416
1417res_create_fail:
1418	dce112_resource_destruct(pool);
1419	return false;
1420}
1421
1422struct resource_pool *dce112_create_resource_pool(
1423	uint8_t num_virtual_links,
1424	struct dc *dc)
1425{
1426	struct dce110_resource_pool *pool =
1427		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1428
1429	if (!pool)
1430		return NULL;
1431
1432	if (dce112_resource_construct(num_virtual_links, dc, pool))
1433		return &pool->base;
1434
1435	kfree(pool);
1436	BREAK_TO_DEBUGGER();
1437	return NULL;
1438}