dcn401_optc.c

  1// SPDX-License-Identifier: MIT
  2//
  3// Copyright 2024 Advanced Micro Devices, Inc.
  4
  5#include "dcn401_optc.h"
  6#include "dcn30/dcn30_optc.h"
  7#include "dcn31/dcn31_optc.h"
  8#include "dcn32/dcn32_optc.h"
  9#include "reg_helper.h"
 10#include "dc.h"
 11#include "dcn_calc_math.h"
 12#include "dc_dmub_srv.h"
 13
 14#define REG(reg)\
 15	optc1->tg_regs->reg
 16
 17#define CTX \
 18	optc1->base.ctx
 19
 20#undef FN
 21#define FN(reg_name, field_name) \
 22	optc1->tg_shift->field_name, optc1->tg_mask->field_name
 23
 24/*
 25 * OPTC uses ODM_MEM sub block to merge pixel data coming from different OPPs
 26 * into unified memory location per horizontal line. ODM_MEM contains shared
 27 * memory resources global to the ASIC. Each memory resource is capable of
 28 * storing 2048 pixels independent from actual pixel data size. Total number of
 29 * memory allocated must be even. The memory resource allocation is described in
 30 * a memory bit map per OPTC instance. Driver has to make sure that there is no
 31 * double allocation across different OPTC instances. Bit offset in the map
 32 * represents memory instance id. Driver allocates a memory instance to the
 33 * current OPTC by setting the bit with offset associated with the desired
 34 * memory instance to 1 in the current OPTC memory map register.
 35 *
 36 * It is upto software to decide how to allocate the shared memory resources
 37 * across different OPTC instances. Driver understands that the total number
 38 * of memory available is always 2 times the max number of OPP pipes. So each
 39 * OPP pipe can be mapped 2 pieces of memory. However there exists cases such as
 40 * 11520x2160 which could use 6 pieces of memory for 2 OPP pipes i.e. 3 pieces
 41 * for each OPP pipe.
 42 *
 43 * Driver will reserve the first and second preferred memory instances for each
 44 * OPP pipe. For example, OPP0's first and second preferred memory is ODM_MEM0
 45 * and ODM_MEM1. OPP1's first and second preferred memory is  ODM_MEM2 and
 46 * ODM_MEM3 so on so forth.
 47 *
 48 * Driver will first allocate from first preferred memory instances associated
 49 * with current OPP pipes in use. If needed driver will then allocate from
 50 * second preferred memory instances associated with current OPP pipes in use.
 51 * Finally if still needed, driver will allocate from second preferred memory
 52 * instances not associated with current OPP pipes. So if memory instances are
 53 * enough other OPTCs can still allocate from their OPPs' first preferred memory
 54 * instances without worrying about double allocation.
 55 */
 56
 57static uint32_t decide_odm_mem_bit_map(int *opp_id, int opp_cnt, int h_active)
 58{
 59	bool first_preferred_memory_for_opp[MAX_PIPES] = {0};
 60	bool second_preferred_memory_for_opp[MAX_PIPES] = {0};
 61	uint32_t memory_bit_map = 0;
 62	int total_required = ((h_active + 4095) / 4096) * 2;
 63	int total_allocated = 0;
 64	int i;
 65
 66	for (i = 0; i < opp_cnt; i++) {
 67		first_preferred_memory_for_opp[opp_id[i]] = true;
 68		total_allocated++;
 69		if (total_required == total_allocated)
 70			break;
 71	}
 72
 73	if (total_required > total_allocated) {
 74		for (i = 0; i < opp_cnt; i++) {
 75			second_preferred_memory_for_opp[opp_id[i]] = true;
 76			total_allocated++;
 77			if (total_required == total_allocated)
 78				break;
 79		}
 80	}
 81
 82	if (total_required > total_allocated) {
 83		for (i = 0; i < MAX_PIPES; i++) {
 84			if (second_preferred_memory_for_opp[i] == false) {
 85				second_preferred_memory_for_opp[i] = true;
 86				total_allocated++;
 87				if (total_required == total_allocated)
 88					break;
 89			}
 90		}
 91	}
 92	ASSERT(total_required == total_allocated);
 93
 94	for (i = 0; i < MAX_PIPES; i++) {
 95		if (first_preferred_memory_for_opp[i])
 96			memory_bit_map |= 0x1 << (i * 2);
 97		if (second_preferred_memory_for_opp[i])
 98			memory_bit_map |= 0x2 << (i * 2);
 99	}
100
101	return memory_bit_map;
102}
103
104void optc401_set_odm_combine(struct timing_generator *optc, int *opp_id,
105		int opp_cnt, int segment_width, int last_segment_width)
106{
107	struct optc *optc1 = DCN10TG_FROM_TG(optc);
108	uint32_t h_active = segment_width * (opp_cnt - 1) + last_segment_width;
109	uint32_t odm_mem_bit_map = decide_odm_mem_bit_map(
110			opp_id, opp_cnt, h_active);
111
112	REG_SET(OPTC_MEMORY_CONFIG, 0,
113		OPTC_MEM_SEL, odm_mem_bit_map);
114
115	switch (opp_cnt) {
116	case 2: /* ODM Combine 2:1 */
117		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
118				OPTC_NUM_OF_INPUT_SEGMENT, 1,
119				OPTC_SEG0_SRC_SEL, opp_id[0],
120				OPTC_SEG1_SRC_SEL, opp_id[1]);
121		REG_UPDATE(OPTC_WIDTH_CONTROL,
122					OPTC_SEGMENT_WIDTH, segment_width);
123
124		REG_UPDATE(OTG_H_TIMING_CNTL,
125				OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY2);
126		break;
127	case 3: /* ODM Combine 3:1 */
128		REG_SET_4(OPTC_DATA_SOURCE_SELECT, 0,
129				OPTC_NUM_OF_INPUT_SEGMENT, 2,
130				OPTC_SEG0_SRC_SEL, opp_id[0],
131				OPTC_SEG1_SRC_SEL, opp_id[1],
132				OPTC_SEG2_SRC_SEL, opp_id[2]);
133		REG_UPDATE(OPTC_WIDTH_CONTROL,
134				OPTC_SEGMENT_WIDTH, segment_width);
135		REG_UPDATE(OPTC_WIDTH_CONTROL2,
136				OPTC_SEGMENT_WIDTH_LAST,
137				last_segment_width);
138		/* In ODM combine 3:1 mode ODM packs 4 pixels per data transfer
139		 * so OTG_H_TIMING_DIV_MODE should be configured to
140		 * H_TIMING_DIV_BY4 even though ODM combines 3 OPP inputs, it
141		 * outputs 4 pixels from single OPP at a time.
142		 */
143		REG_UPDATE(OTG_H_TIMING_CNTL,
144				OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY4);
145		break;
146	case 4: /* ODM Combine 4:1 */
147		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
148				OPTC_NUM_OF_INPUT_SEGMENT, 3,
149				OPTC_SEG0_SRC_SEL, opp_id[0],
150				OPTC_SEG1_SRC_SEL, opp_id[1],
151				OPTC_SEG2_SRC_SEL, opp_id[2],
152				OPTC_SEG3_SRC_SEL, opp_id[3]);
153		REG_UPDATE(OPTC_WIDTH_CONTROL,
154					OPTC_SEGMENT_WIDTH, segment_width);
155		REG_UPDATE(OTG_H_TIMING_CNTL,
156				OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY4);
157		break;
158	default:
159		ASSERT(false);
160	}
161;
162	optc1->opp_count = opp_cnt;
163}
164
165void optc401_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
166{
167	struct optc *optc1 = DCN10TG_FROM_TG(optc);
168
169	REG_UPDATE(OTG_H_TIMING_CNTL,
170			OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
171}
172/**
173 * optc401_enable_crtc() - Enable CRTC
174 * @optc: Pointer to the timing generator structure
175 *
176 * This function calls ASIC Control Object to enable Timing generator.
177 *
178 * Return: Always returns true
179 */
180bool optc401_enable_crtc(struct timing_generator *optc)
181{
182	struct optc *optc1 = DCN10TG_FROM_TG(optc);
183
184	/* opp instance for OTG, 1 to 1 mapping and odm will adjust */
185	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
186			OPTC_SEG0_SRC_SEL, optc->inst);
187
188	/* VTG enable first is for HW workaround */
189	REG_UPDATE(CONTROL,
190			VTG0_ENABLE, 1);
191
192	REG_SEQ_START();
193
194	/* Enable CRTC */
195	REG_UPDATE_2(OTG_CONTROL,
196			OTG_DISABLE_POINT_CNTL, 2,
197			OTG_MASTER_EN, 1);
198
199	REG_SEQ_SUBMIT();
200	REG_SEQ_WAIT_DONE();
201
202	return true;
203}
204
205/* disable_crtc */
206bool optc401_disable_crtc(struct timing_generator *optc)
207{
208	struct optc *optc1 = DCN10TG_FROM_TG(optc);
209
210	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
211			OPTC_SEG0_SRC_SEL, 0xf,
212			OPTC_SEG1_SRC_SEL, 0xf,
213			OPTC_SEG2_SRC_SEL, 0xf,
214			OPTC_SEG3_SRC_SEL, 0xf,
215			OPTC_NUM_OF_INPUT_SEGMENT, 0);
216
217	REG_UPDATE(OPTC_MEMORY_CONFIG,
218			OPTC_MEM_SEL, 0);
219
220	/* disable otg request until end of the first line
221	 * in the vertical blank region
222	 */
223	REG_UPDATE(OTG_CONTROL,
224			OTG_MASTER_EN, 0);
225
226	REG_UPDATE(CONTROL,
227			VTG0_ENABLE, 0);
228
229	// wait until CRTC_CURRENT_MASTER_EN_STATE == 0
230	REG_WAIT(OTG_CONTROL,
231			 OTG_CURRENT_MASTER_EN_STATE,
232			 0, 10, 15000);
233
234	/* CRTC disabled, so disable  clock. */
235	REG_WAIT(OTG_CLOCK_CONTROL,
236			OTG_BUSY, 0,
237			1, 150000);
238
239	return true;
240}
241
242void optc401_phantom_crtc_post_enable(struct timing_generator *optc)
243{
244	struct optc *optc1 = DCN10TG_FROM_TG(optc);
245
246	/* Disable immediately. */
247	REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
248
249	/* CRTC disabled, so disable  clock. */
250	REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
251}
252
253void optc401_disable_phantom_otg(struct timing_generator *optc)
254{
255	struct optc *optc1 = DCN10TG_FROM_TG(optc);
256
257	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
258			OPTC_SEG0_SRC_SEL, 0xf,
259			OPTC_SEG1_SRC_SEL, 0xf,
260			OPTC_SEG2_SRC_SEL, 0xf,
261			OPTC_SEG3_SRC_SEL, 0xf,
262			OPTC_NUM_OF_INPUT_SEGMENT, 0);
263
264	REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
265}
266
267void optc401_set_odm_bypass(struct timing_generator *optc,
268		const struct dc_crtc_timing *dc_crtc_timing)
269{
270	struct optc *optc1 = DCN10TG_FROM_TG(optc);
271	enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
272
273	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
274			OPTC_NUM_OF_INPUT_SEGMENT, 0,
275			OPTC_SEG0_SRC_SEL, optc->inst,
276			OPTC_SEG1_SRC_SEL, 0xf,
277			OPTC_SEG2_SRC_SEL, 0xf,
278			OPTC_SEG3_SRC_SEL, 0xf
279			);
280
281	h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);
282	REG_UPDATE(OTG_H_TIMING_CNTL,
283			OTG_H_TIMING_DIV_MODE, h_div);
284
285	REG_SET(OPTC_MEMORY_CONFIG, 0,
286			OPTC_MEM_SEL, 0);
287	optc1->opp_count = 1;
288}
289
290/* only to be used when FAMS2 is disabled or unsupported */
291void optc401_setup_manual_trigger(struct timing_generator *optc)
292{
293	struct optc *optc1 = DCN10TG_FROM_TG(optc);
294	struct dc *dc = optc->ctx->dc;
295
296	if (dc->caps.dmub_caps.fams_ver == 1 && !dc->debug.disable_fams)
297		/* FAMS */
298		dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
299	else {
300		/*
301		 * MIN_MASK_EN is gone and MASK is now always enabled.
302		 *
303		 * To get it to it work with manual trigger we need to make sure
304		 * we program the correct bit.
305		 */
306		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
307				OTG_V_TOTAL_MIN_SEL, 1,
308				OTG_V_TOTAL_MAX_SEL, 1,
309				OTG_FORCE_LOCK_ON_EVENT, 0,
310				OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
311	}
312}
313
314void optc401_set_drr(
315	struct timing_generator *optc,
316	const struct drr_params *params)
317{
318	struct optc *optc1 = DCN10TG_FROM_TG(optc);
319	struct dc *dc = optc->ctx->dc;
320	struct drr_params amended_params = { 0 };
321	bool program_manual_trigger = false;
322
323	if (dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver && dc->debug.fams2_config.bits.enable) {
324		if (params != NULL &&
325				params->vertical_total_max > 0 &&
326				params->vertical_total_min > 0) {
327			amended_params.vertical_total_max = params->vertical_total_max - 1;
328			amended_params.vertical_total_min = params->vertical_total_min - 1;
329			if (params->vertical_total_mid != 0) {
330				amended_params.vertical_total_mid = params->vertical_total_mid - 1;
331				amended_params.vertical_total_mid_frame_num = params->vertical_total_mid_frame_num;
332			}
333			program_manual_trigger = true;
334		}
335
336		dc_dmub_srv_fams2_drr_update(dc, optc->inst,
337				amended_params.vertical_total_min,
338				amended_params.vertical_total_max,
339				amended_params.vertical_total_mid,
340				amended_params.vertical_total_mid_frame_num,
341				program_manual_trigger);
342	} else {
343		if (params != NULL &&
344			params->vertical_total_max > 0 &&
345			params->vertical_total_min > 0) {
346
347			if (params->vertical_total_mid != 0) {
348
349				REG_SET(OTG_V_TOTAL_MID, 0,
350					OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
351
352				REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
353						OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
354						OTG_VTOTAL_MID_FRAME_NUM,
355						(uint8_t)params->vertical_total_mid_frame_num);
356
357			}
358
359			optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
360			optc401_setup_manual_trigger(optc);
361		} else {
362			REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
363					OTG_SET_V_TOTAL_MIN_MASK, 0,
364					OTG_V_TOTAL_MIN_SEL, 0,
365					OTG_V_TOTAL_MAX_SEL, 0,
366					OTG_FORCE_LOCK_ON_EVENT, 0);
367
368			optc->funcs->set_vtotal_min_max(optc, 0, 0);
369		}
370	}
371}
372
373void optc401_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)
374{
375	struct optc *optc1 = DCN10TG_FROM_TG(optc);
376
377	/* 00 - OTG_CONTROL_OTG_OUT_MUX_0 : Connects to DIO.
378	   01 - OTG_CONTROL_OTG_OUT_MUX_1 : Reserved.
379	   02 - OTG_CONTROL_OTG_OUT_MUX_2 : Connects to HPO.
380	*/
381	REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);
382}
383
384void optc401_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
385{
386	struct dc *dc = optc->ctx->dc;
387
388	if (dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver && dc->debug.fams2_config.bits.enable) {
389		/* FAMS2 */
390		dc_dmub_srv_fams2_drr_update(dc, optc->inst,
391				vtotal_min,
392				vtotal_max,
393				0,
394				0,
395				false);
396	} else if (dc->caps.dmub_caps.fams_ver == 1 && !dc->debug.disable_fams) {
397		/* FAMS */
398		dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);
399	} else {
400		optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);
401	}
402}
403
404void optc401_program_global_sync(
405		struct timing_generator *optc,
406		int vready_offset,
407		int vstartup_start,
408		int vupdate_offset,
409		int vupdate_width,
410		int pstate_keepout)
411{
412	struct optc *optc1 = DCN10TG_FROM_TG(optc);
413
414	optc1->vready_offset = vready_offset;
415	optc1->vstartup_start = vstartup_start;
416	optc1->vupdate_offset = vupdate_offset;
417	optc1->vupdate_width = vupdate_width;
418	optc1->pstate_keepout = pstate_keepout;
419
420	if (optc1->vstartup_start == 0) {
421		BREAK_TO_DEBUGGER();
422		return;
423	}
424
425	REG_SET(OTG_VSTARTUP_PARAM, 0,
426		VSTARTUP_START, optc1->vstartup_start);
427
428	REG_SET_2(OTG_VUPDATE_PARAM, 0,
429			VUPDATE_OFFSET, optc1->vupdate_offset,
430			VUPDATE_WIDTH, optc1->vupdate_width);
431
432	REG_SET(OTG_VREADY_PARAM, 0,
433			VREADY_OFFSET, optc1->vready_offset);
434
435	REG_UPDATE(OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, pstate_keepout);
436}
437
438void optc401_set_vupdate_keepout(struct timing_generator *tg, bool enable)
439{
440	struct optc *optc1 = DCN10TG_FROM_TG(tg);
441
442	REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
443		MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
444		MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, optc1->vready_offset + 10,
445		OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, enable);
446
447	return;
448}
449
450bool optc401_wait_update_lock_status(struct timing_generator *tg, bool locked)
451{
452	struct optc *optc1 = DCN10TG_FROM_TG(tg);
453	uint32_t lock_status = 0;
454
455	REG_WAIT(OTG_MASTER_UPDATE_LOCK,
456			UPDATE_LOCK_STATUS, locked,
457			1, 150000);
458
459	REG_GET(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, &lock_status);
460
461	if (lock_status != locked)
462		return false;
463
464	return true;
465}
466
467static const struct timing_generator_funcs dcn401_tg_funcs = {
468		.validate_timing = optc1_validate_timing,
469		.program_timing = optc1_program_timing,
470		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
471		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
472		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
473		.program_global_sync = optc401_program_global_sync,
474		.enable_crtc = optc401_enable_crtc,
475		.disable_crtc = optc401_disable_crtc,
476		.phantom_crtc_post_enable = optc401_phantom_crtc_post_enable,
477		.disable_phantom_crtc = optc401_disable_phantom_otg,
478		/* used by enable_timing_synchronization. Not need for FPGA */
479		.is_counter_moving = optc1_is_counter_moving,
480		.get_position = optc1_get_position,
481		.get_frame_count = optc1_get_vblank_counter,
482		.get_scanoutpos = optc1_get_crtc_scanoutpos,
483		.get_otg_active_size = optc1_get_otg_active_size,
484		.set_early_control = optc1_set_early_control,
485		/* used by enable_timing_synchronization. Not need for FPGA */
486		.wait_for_state = optc1_wait_for_state,
487		.set_blank_color = optc3_program_blank_color,
488		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
489		.triplebuffer_lock = optc3_triplebuffer_lock,
490		.triplebuffer_unlock = optc2_triplebuffer_unlock,
491		.enable_reset_trigger = optc1_enable_reset_trigger,
492		.enable_crtc_reset = optc1_enable_crtc_reset,
493		.disable_reset_trigger = optc1_disable_reset_trigger,
494		.lock = optc3_lock,
495		.unlock = optc1_unlock,
496		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
497		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
498		.enable_optc_clock = optc1_enable_optc_clock,
499		.set_drr = optc401_set_drr,
500		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
501		.set_vtotal_min_max = optc401_set_vtotal_min_max,
502		.set_static_screen_control = optc1_set_static_screen_control,
503		.program_stereo = optc1_program_stereo,
504		.is_stereo_left_eye = optc1_is_stereo_left_eye,
505		.tg_init = optc3_tg_init,
506		.is_tg_enabled = optc1_is_tg_enabled,
507		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
508		.clear_optc_underflow = optc1_clear_optc_underflow,
509		.setup_global_swap_lock = NULL,
510		.get_crc = optc1_get_crc,
511		.configure_crc = optc1_configure_crc,
512		.set_dsc_config = optc3_set_dsc_config,
513		.get_dsc_status = optc2_get_dsc_status,
514		.set_dwb_source = NULL,
515		.set_odm_bypass = optc401_set_odm_bypass,
516		.set_odm_combine = optc401_set_odm_combine,
517		.wait_odm_doublebuffer_pending_clear = optc32_wait_odm_doublebuffer_pending_clear,
518		.set_h_timing_div_manual_mode = optc401_set_h_timing_div_manual_mode,
519		.get_optc_source = optc2_get_optc_source,
520		.set_out_mux = optc401_set_out_mux,
521		.set_drr_trigger_window = optc3_set_drr_trigger_window,
522		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
523		.set_gsl = optc2_set_gsl,
524		.set_gsl_source_select = optc2_set_gsl_source_select,
525		.set_vtg_params = optc1_set_vtg_params,
526		.program_manual_trigger = optc2_program_manual_trigger,
527		.setup_manual_trigger = optc2_setup_manual_trigger,
528		.get_hw_timing = optc1_get_hw_timing,
529		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,
530		.get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending,
531		.get_otg_double_buffer_pending = optc3_get_otg_update_pending,
532		.get_pipe_update_pending = optc3_get_pipe_update_pending,
533		.set_vupdate_keepout = optc401_set_vupdate_keepout,
534		.wait_update_lock_status = optc401_wait_update_lock_status,
535		.read_otg_state = optc31_read_otg_state,
536		.optc_read_reg_state = optc31_read_reg_state,
537};
538
539void dcn401_timing_generator_init(struct optc *optc1)
540{
541	optc1->base.funcs = &dcn401_tg_funcs;
542
543	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
544	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
545
546	optc1->min_h_blank = 32;
547	optc1->min_v_blank = 3;
548	optc1->min_v_blank_interlace = 5;
549	optc1->min_h_sync_width = 4;
550	optc1->min_v_sync_width = 1;
551}
552