dcn35_optc.c

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright 2023 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 * Authors: AMD
 24 *
 25 */
 26
 27#include "dcn35_optc.h"
 28
 29#include "dcn30/dcn30_optc.h"
 30#include "dcn31/dcn31_optc.h"
 31#include "dcn32/dcn32_optc.h"
 32#include "reg_helper.h"
 33#include "dc.h"
 34#include "dcn_calc_math.h"
 35#include "dc_dmub_srv.h"
 36
 37#define REG(reg)\
 38	optc1->tg_regs->reg
 39
 40#define CTX \
 41	optc1->base.ctx
 42
 43#undef FN
 44#define FN(reg_name, field_name) \
 45	optc1->tg_shift->field_name, optc1->tg_mask->field_name
 46
 47/**
 48 * optc35_set_odm_combine() - Enable CRTC - call ASIC Control Object to enable Timing generator.
 49 *
 50 * @optc: Output Pipe Timing Combine instance reference.
 51 * @opp_id: Output Plane Processor instance ID.
 52 * @opp_cnt: Output Plane Processor count.
 53 * @segment_width: Width of the segment.
 54 * @last_segment_width: Width of the last segment.
 55 *
 56 * Return: void.
 57 */
 58static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
 59		int segment_width, int last_segment_width)
 60{
 61	struct optc *optc1 = DCN10TG_FROM_TG(optc);
 62	uint32_t memory_mask = 0;
 63	int h_active = segment_width * opp_cnt;
 64	/* Each memory instance is 2048x(314x2) bits to support half line of 4096 */
 65	int odm_mem_count = (h_active + 2047) / 2048;
 66
 67	/*
 68	 * display <= 4k : 2 memories + 2 pipes
 69	 * 4k < display <= 8k : 4 memories + 2 pipes
 70	 * 8k < display <= 12k : 6 memories + 4 pipes
 71	 */
 72	if (opp_cnt == 4) {
 73		if (odm_mem_count <= 2)
 74			memory_mask = 0x3;
 75		else if (odm_mem_count <= 4)
 76			memory_mask = 0xf;
 77		else
 78			memory_mask = 0x3f;
 79	} else {
 80		if (odm_mem_count <= 2)
 81			memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
 82		else if (odm_mem_count <= 4)
 83			memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
 84		else
 85			memory_mask = 0x77;
 86	}
 87
 88	REG_SET(OPTC_MEMORY_CONFIG, 0,
 89		OPTC_MEM_SEL, memory_mask);
 90
 91	if (opp_cnt == 2) {
 92		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
 93				OPTC_NUM_OF_INPUT_SEGMENT, 1,
 94				OPTC_SEG0_SRC_SEL, opp_id[0],
 95				OPTC_SEG1_SRC_SEL, opp_id[1]);
 96	} else if (opp_cnt == 4) {
 97		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
 98				OPTC_NUM_OF_INPUT_SEGMENT, 3,
 99				OPTC_SEG0_SRC_SEL, opp_id[0],
100				OPTC_SEG1_SRC_SEL, opp_id[1],
101				OPTC_SEG2_SRC_SEL, opp_id[2],
102				OPTC_SEG3_SRC_SEL, opp_id[3]);
103	}
104
105	REG_UPDATE(OPTC_WIDTH_CONTROL,
106			OPTC_SEGMENT_WIDTH, segment_width);
107
108	REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
109	optc1->opp_count = opp_cnt;
110}
111
112static bool optc35_enable_crtc(struct timing_generator *optc)
113{
114	struct optc *optc1 = DCN10TG_FROM_TG(optc);
115
116	/* opp instance for OTG, 1 to 1 mapping and odm will adjust */
117	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
118			OPTC_SEG0_SRC_SEL, optc->inst);
119
120	/* VTG enable first is for HW workaround */
121	REG_UPDATE(CONTROL,
122			VTG0_ENABLE, 1);
123
124	REG_SEQ_START();
125
126	/* Enable CRTC */
127	REG_UPDATE_2(OTG_CONTROL,
128			OTG_DISABLE_POINT_CNTL, 2,
129			OTG_MASTER_EN, 1);
130
131	REG_SEQ_SUBMIT();
132	REG_SEQ_WAIT_DONE();
133
134	return true;
135}
136
137/* disable_crtc */
138static bool optc35_disable_crtc(struct timing_generator *optc)
139{
140	struct optc *optc1 = DCN10TG_FROM_TG(optc);
141
142	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
143			OPTC_SEG0_SRC_SEL, 0xf,
144			OPTC_SEG1_SRC_SEL, 0xf,
145			OPTC_SEG2_SRC_SEL, 0xf,
146			OPTC_SEG3_SRC_SEL, 0xf,
147			OPTC_NUM_OF_INPUT_SEGMENT, 0);
148
149	REG_UPDATE(OPTC_MEMORY_CONFIG,
150			OPTC_MEM_SEL, 0);
151
152	/* disable otg request until end of the first line
153	 * in the vertical blank region
154	 */
155	REG_UPDATE(OTG_CONTROL,
156			OTG_MASTER_EN, 0);
157
158	REG_UPDATE(CONTROL,
159			VTG0_ENABLE, 0);
160
161	/* CRTC disabled, so disable  clock. */
162	REG_WAIT(OTG_CLOCK_CONTROL,
163			OTG_BUSY, 0,
164			1, 100000);
165	REG_WAIT(OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, 0, 1, 100000);
166
167	optc1_clear_optc_underflow(optc);
168
169	return true;
170}
171
172static void optc35_phantom_crtc_post_enable(struct timing_generator *optc)
173{
174	struct optc *optc1 = DCN10TG_FROM_TG(optc);
175
176	/* Disable immediately. */
177	REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
178
179	/* CRTC disabled, so disable  clock. */
180	REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
181}
182
183static bool optc35_configure_crc(struct timing_generator *optc,
184				 const struct crc_params *params)
185{
186	struct optc *optc1 = DCN10TG_FROM_TG(optc);
187
188	/* Cannot configure crc on a CRTC that is disabled */
189	if (!optc1_is_tg_enabled(optc))
190		return false;
191
192	if (!params->enable || params->reset)
193		REG_WRITE(OTG_CRC_CNTL, 0);
194
195	if (!params->enable)
196		return true;
197
198	/* Program frame boundaries */
199	switch (params->crc_eng_inst) {
200	case 0:
201		/* Window A x axis start and end. */
202		REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
203				OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
204				OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
205
206		/* Window A y axis start and end. */
207		REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
208				OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
209				OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
210
211		/* Window B x axis start and end. */
212		REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
213				OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
214				OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
215
216		/* Window B y axis start and end. */
217		REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
218				OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
219				OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
220
221		if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0)
222			REG_UPDATE_4(OTG_CRC_CNTL,
223					OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
224					OTG_CRC0_SELECT, params->selection,
225					OTG_CRC_EN, 1,
226					OTG_CRC_WINDOW_DB_EN, 1);
227		else
228			REG_UPDATE_3(OTG_CRC_CNTL,
229					OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
230					OTG_CRC0_SELECT, params->selection,
231					OTG_CRC_EN, 1);
232		break;
233	case 1:
234		/* Window A x axis start and end. */
235		REG_UPDATE_2(OTG_CRC1_WINDOWA_X_CONTROL,
236				OTG_CRC1_WINDOWA_X_START, params->windowa_x_start,
237				OTG_CRC1_WINDOWA_X_END, params->windowa_x_end);
238
239		/* Window A y axis start and end. */
240		REG_UPDATE_2(OTG_CRC1_WINDOWA_Y_CONTROL,
241				OTG_CRC1_WINDOWA_Y_START, params->windowa_y_start,
242				OTG_CRC1_WINDOWA_Y_END, params->windowa_y_end);
243
244		/* Window B x axis start and end. */
245		REG_UPDATE_2(OTG_CRC1_WINDOWB_X_CONTROL,
246				OTG_CRC1_WINDOWB_X_START, params->windowb_x_start,
247				OTG_CRC1_WINDOWB_X_END, params->windowb_x_end);
248
249		/* Window B y axis start and end. */
250		REG_UPDATE_2(OTG_CRC1_WINDOWB_Y_CONTROL,
251				OTG_CRC1_WINDOWB_Y_START, params->windowb_y_start,
252				OTG_CRC1_WINDOWB_Y_END, params->windowb_y_end);
253
254		if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0)
255			REG_UPDATE_4(OTG_CRC_CNTL,
256					OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
257					OTG_CRC1_SELECT, params->selection,
258					OTG_CRC_EN, 1,
259					OTG_CRC_WINDOW_DB_EN, 1);
260		else
261			REG_UPDATE_3(OTG_CRC_CNTL,
262					OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
263					OTG_CRC1_SELECT, params->selection,
264					OTG_CRC_EN, 1);
265		break;
266	default:
267		return false;
268	}
269	return true;
270}
271
272static void optc35_setup_manual_trigger(struct timing_generator *optc)
273{
274	if (!optc || !optc->ctx)
275		return;
276
277	struct optc *optc1 = DCN10TG_FROM_TG(optc);
278	struct dc *dc = optc->ctx->dc;
279
280	if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
281		dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
282	else {
283		/*
284		 * MIN_MASK_EN is gone and MASK is now always enabled.
285		 *
286		 * To get it to it work with manual trigger we need to make sure
287		 * we program the correct bit.
288		 */
289		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
290				OTG_V_TOTAL_MIN_SEL, 1,
291				OTG_V_TOTAL_MAX_SEL, 1,
292				OTG_FORCE_LOCK_ON_EVENT, 0,
293				OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
294
295		// Setup manual flow control for EOF via TRIG_A
296		if (optc->funcs && optc->funcs->setup_manual_trigger)
297			optc->funcs->setup_manual_trigger(optc);
298	}
299}
300
301void optc35_set_drr(
302	struct timing_generator *optc,
303	const struct drr_params *params)
304{
305	if (!optc || !params)
306		return;
307
308	struct optc *optc1 = DCN10TG_FROM_TG(optc);
309	uint32_t max_otg_v_total = optc1->max_v_total - 1;
310
311	if (params != NULL &&
312		params->vertical_total_max > 0 &&
313		params->vertical_total_min > 0) {
314
315		if (params->vertical_total_mid != 0) {
316
317			REG_SET(OTG_V_TOTAL_MID, 0,
318				OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
319
320			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
321					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
322					OTG_VTOTAL_MID_FRAME_NUM,
323					(uint8_t)params->vertical_total_mid_frame_num);
324
325		}
326
327		if (optc->funcs && optc->funcs->set_vtotal_min_max)
328			optc->funcs->set_vtotal_min_max(optc,
329				params->vertical_total_min - 1, params->vertical_total_max - 1);
330		optc35_setup_manual_trigger(optc);
331	} else {
332		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
333				OTG_SET_V_TOTAL_MIN_MASK, 0,
334				OTG_V_TOTAL_MIN_SEL, 0,
335				OTG_V_TOTAL_MAX_SEL, 0,
336				OTG_FORCE_LOCK_ON_EVENT, 0);
337
338		if (optc->funcs && optc->funcs->set_vtotal_min_max)
339			optc->funcs->set_vtotal_min_max(optc, 0, 0);
340	}
341
342	REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);
343	REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);
344}
345
346static void optc35_set_long_vtotal(
347	struct timing_generator *optc,
348	const struct long_vtotal_params *params)
349{
350	if (!optc || !params)
351		return;
352
353	struct optc *optc1 = DCN10TG_FROM_TG(optc);
354	uint32_t vcount_stop_timer = 0, vcount_stop = 0;
355	uint32_t max_otg_v_total = optc1->max_v_total - 1;
356
357	if (params->vertical_total_min <= max_otg_v_total && params->vertical_total_max <= max_otg_v_total)
358		return;
359
360	if (params->vertical_total_max == 0 || params->vertical_total_min == 0) {
361		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
362						OTG_SET_V_TOTAL_MIN_MASK, 0,
363						OTG_V_TOTAL_MIN_SEL, 0,
364						OTG_V_TOTAL_MAX_SEL, 0,
365						OTG_FORCE_LOCK_ON_EVENT, 0);
366
367		if (optc->funcs && optc->funcs->set_vtotal_min_max)
368			optc->funcs->set_vtotal_min_max(optc, 0, 0);
369	} else if (params->vertical_total_max == params->vertical_total_min) {
370		vcount_stop = params->vertical_blank_start;
371		vcount_stop_timer = params->vertical_total_max - max_otg_v_total;
372
373		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
374				OTG_V_TOTAL_MIN_SEL, 1,
375				OTG_V_TOTAL_MAX_SEL, 1,
376				OTG_FORCE_LOCK_ON_EVENT, 0,
377				OTG_SET_V_TOTAL_MIN_MASK, 0);
378
379		if (optc->funcs && optc->funcs->set_vtotal_min_max)
380			optc->funcs->set_vtotal_min_max(optc, max_otg_v_total, max_otg_v_total);
381
382		REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);
383		REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);
384	} else {
385		// Variable rate, keep DRR trigger mask
386		if (params->vertical_total_min > max_otg_v_total) {
387			// cannot be supported
388			// If MAX_OTG_V_COUNT < DRR trigger < v_total_min < v_total_max,
389			// DRR trigger will drop the vtotal counting directly to a new frame.
390			// But it should trigger between v_total_min and v_total_max.
391			ASSERT(0);
392
393			REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
394				OTG_SET_V_TOTAL_MIN_MASK, 0,
395				OTG_V_TOTAL_MIN_SEL, 0,
396				OTG_V_TOTAL_MAX_SEL, 0,
397				OTG_FORCE_LOCK_ON_EVENT, 0);
398
399			if (optc->funcs && optc->funcs->set_vtotal_min_max)
400				optc->funcs->set_vtotal_min_max(optc, 0, 0);
401
402			REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);
403			REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);
404		} else {
405			// For total_min <= MAX_OTG_V_COUNT and total_max > MAX_OTG_V_COUNT
406			vcount_stop = params->vertical_total_min;
407			vcount_stop_timer = params->vertical_total_max - max_otg_v_total;
408
409			// Example:
410			// params->vertical_total_min 1000
411			// params->vertical_total_max 2000
412			// MAX_OTG_V_COUNT_STOP = 1500
413			//
414			// If DRR event not happened,
415			//     time     0,1,2,3,4,...1000,1001,........,1500,1501,1502,     ...1999
416			//     vcount   0,1,2,3,4....1000...................,1001,1002,1003,...1399
417			//     vcount2                       0,1,2,3,4,..499,
418			// else (DRR event happened, ex : at line 1004)
419			//     time    0,1,2,3,4,...1000,1001.....1004, 0
420			//     vcount  0,1,2,3,4....1000,.............. 0 (new frame)
421			//     vcount2                      0,1,2,   3, -
422			if (optc->funcs && optc->funcs->set_vtotal_min_max)
423				optc->funcs->set_vtotal_min_max(optc,
424					params->vertical_total_min - 1, max_otg_v_total);
425			optc35_setup_manual_trigger(optc);
426
427			REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);
428			REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);
429		}
430	}
431}
432
433static void optc35_wait_otg_disable(struct timing_generator *optc)
434{
435	struct optc *optc1;
436	uint32_t is_master_en;
437
438	if (!optc || !optc->ctx)
439		return;
440
441	optc1 = DCN10TG_FROM_TG(optc);
442
443	REG_GET(OTG_CONTROL, OTG_MASTER_EN, &is_master_en);
444	if (!is_master_en)
445		REG_WAIT(OTG_CLOCK_CONTROL, OTG_CURRENT_MASTER_EN_STATE, 0, 1, 100000);
446}
447
448static const struct timing_generator_funcs dcn35_tg_funcs = {
449		.validate_timing = optc1_validate_timing,
450		.program_timing = optc1_program_timing,
451		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
452		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
453		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
454		.program_global_sync = optc1_program_global_sync,
455		.enable_crtc = optc35_enable_crtc,
456		.disable_crtc = optc35_disable_crtc,
457		.immediate_disable_crtc = optc31_immediate_disable_crtc,
458		.phantom_crtc_post_enable = optc35_phantom_crtc_post_enable,
459		/* used by enable_timing_synchronization. Not need for FPGA */
460		.is_counter_moving = optc1_is_counter_moving,
461		.get_position = optc1_get_position,
462		.get_frame_count = optc1_get_vblank_counter,
463		.get_scanoutpos = optc1_get_crtc_scanoutpos,
464		.get_otg_active_size = optc1_get_otg_active_size,
465		.set_early_control = optc1_set_early_control,
466		/* used by enable_timing_synchronization. Not need for FPGA */
467		.wait_for_state = optc1_wait_for_state,
468		.set_blank_color = optc3_program_blank_color,
469		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
470		.triplebuffer_lock = optc3_triplebuffer_lock,
471		.triplebuffer_unlock = optc2_triplebuffer_unlock,
472		.enable_reset_trigger = optc1_enable_reset_trigger,
473		.enable_crtc_reset = optc1_enable_crtc_reset,
474		.disable_reset_trigger = optc1_disable_reset_trigger,
475		.lock = optc3_lock,
476		.unlock = optc1_unlock,
477		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
478		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
479		.enable_optc_clock = optc1_enable_optc_clock,
480		.set_drr = optc35_set_drr,
481		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
482		.set_vtotal_min_max = optc1_set_vtotal_min_max,
483		.set_static_screen_control = optc1_set_static_screen_control,
484		.program_stereo = optc1_program_stereo,
485		.is_stereo_left_eye = optc1_is_stereo_left_eye,
486		.tg_init = optc3_tg_init,
487		.is_tg_enabled = optc1_is_tg_enabled,
488		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
489		.clear_optc_underflow = optc1_clear_optc_underflow,
490		.setup_global_swap_lock = NULL,
491		.get_crc = optc1_get_crc,
492		.configure_crc = optc35_configure_crc,
493		.set_dsc_config = optc3_set_dsc_config,
494		.get_dsc_status = optc2_get_dsc_status,
495		.set_dwb_source = NULL,
496		.set_odm_bypass = optc32_set_odm_bypass,
497		.set_odm_combine = optc35_set_odm_combine,
498		.get_optc_source = optc2_get_optc_source,
499		.wait_otg_disable = optc35_wait_otg_disable,
500		.set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
501		.set_out_mux = optc3_set_out_mux,
502		.set_drr_trigger_window = optc3_set_drr_trigger_window,
503		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
504		.set_gsl = optc2_set_gsl,
505		.set_gsl_source_select = optc2_set_gsl_source_select,
506		.set_vtg_params = optc1_set_vtg_params,
507		.program_manual_trigger = optc2_program_manual_trigger,
508		.setup_manual_trigger = optc2_setup_manual_trigger,
509		.get_hw_timing = optc1_get_hw_timing,
510		.init_odm = optc3_init_odm,
511		.set_long_vtotal = optc35_set_long_vtotal,
512		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,
513		.read_otg_state = optc31_read_otg_state,
514		.optc_read_reg_state = optc31_read_reg_state,
515};
516
517void dcn35_timing_generator_init(struct optc *optc1)
518{
519	optc1->base.funcs = &dcn35_tg_funcs;
520
521	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
522	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
523
524	optc1->min_h_blank = 32;
525	optc1->min_v_blank = 3;
526	optc1->min_v_blank_interlace = 5;
527	optc1->min_h_sync_width = 4;
528	optc1->min_v_sync_width = 1;
529	optc1->max_frame_count = 0xFFFFFF;
530
531	dcn35_timing_generator_set_fgcg(
532		optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc);
533}
534
535void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable)
536{
537	REG_UPDATE(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, !enable);
538}