dcn32_optc.c

  1/*
  2 * Copyright 2022 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dcn32_optc.h"
 27
 28#include "dcn30/dcn30_optc.h"
 29#include "dcn31/dcn31_optc.h"
 30#include "reg_helper.h"
 31#include "dc.h"
 32#include "dcn_calc_math.h"
 33#include "dc_dmub_srv.h"
 34
 35#define REG(reg)\
 36	optc1->tg_regs->reg
 37
 38#define CTX \
 39	optc1->base.ctx
 40
 41#undef FN
 42#define FN(reg_name, field_name) \
 43	optc1->tg_shift->field_name, optc1->tg_mask->field_name
 44
 45static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
 46		int segment_width, int last_segment_width)
 47{
 48	struct optc *optc1 = DCN10TG_FROM_TG(optc);
 49	uint32_t memory_mask = 0;
 50	int h_active = segment_width * opp_cnt;
 51	/* Each memory instance is 2048x(32x2) bits to support half line of 4096 */
 52	int odm_mem_count = (h_active + 2047) / 2048;
 53
 54	/*
 55	 * display <= 4k : 2 memories + 2 pipes
 56	 * 4k < display <= 8k : 4 memories + 2 pipes
 57	 * 8k < display <= 12k : 6 memories + 4 pipes
 58	 */
 59	if (opp_cnt == 4) {
 60		if (odm_mem_count <= 2)
 61			memory_mask = 0x3;
 62		else if (odm_mem_count <= 4)
 63			memory_mask = 0xf;
 64		else
 65			memory_mask = 0x3f;
 66	} else {
 67		if (odm_mem_count <= 2)
 68			memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
 69		else if (odm_mem_count <= 4)
 70			memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
 71		else
 72			memory_mask = 0x77;
 73	}
 74
 75	REG_SET(OPTC_MEMORY_CONFIG, 0,
 76		OPTC_MEM_SEL, memory_mask);
 77
 78	if (opp_cnt == 2) {
 79		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
 80				OPTC_NUM_OF_INPUT_SEGMENT, 1,
 81				OPTC_SEG0_SRC_SEL, opp_id[0],
 82				OPTC_SEG1_SRC_SEL, opp_id[1]);
 83	} else if (opp_cnt == 4) {
 84		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
 85				OPTC_NUM_OF_INPUT_SEGMENT, 3,
 86				OPTC_SEG0_SRC_SEL, opp_id[0],
 87				OPTC_SEG1_SRC_SEL, opp_id[1],
 88				OPTC_SEG2_SRC_SEL, opp_id[2],
 89				OPTC_SEG3_SRC_SEL, opp_id[3]);
 90	}
 91
 92	REG_UPDATE(OPTC_WIDTH_CONTROL,
 93			OPTC_SEGMENT_WIDTH, segment_width);
 94
 95	REG_UPDATE(OTG_H_TIMING_CNTL,
 96			OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
 97	optc1->opp_count = opp_cnt;
 98}
 99
100void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments)
101{
102	struct optc *optc1 = DCN10TG_FROM_TG(tg);
103	int segments;
104
105	REG_GET(OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, &segments);
106
107	switch (segments) {
108	case 0:
109		*odm_combine_segments = 1;
110		break;
111	case 1:
112		*odm_combine_segments = 2;
113		break;
114	case 3:
115		*odm_combine_segments = 4;
116		break;
117	/* 2 is reserved */
118	case 2:
119	default:
120		*odm_combine_segments = -1;
121	}
122}
123
124void optc32_wait_odm_doublebuffer_pending_clear(struct timing_generator *tg)
125{
126	struct optc *optc1 = DCN10TG_FROM_TG(tg);
127
128	REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING, 0, 2, 50000);
129}
130
131void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
132{
133	struct optc *optc1 = DCN10TG_FROM_TG(optc);
134
135	REG_UPDATE(OTG_H_TIMING_CNTL,
136			OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
137}
138/**
139 * optc32_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
140 *
141 * @optc: timing_generator instance.
142 *
143 * Return: If CRTC is enabled, return true.
144 */
145static bool optc32_enable_crtc(struct timing_generator *optc)
146{
147	struct optc *optc1 = DCN10TG_FROM_TG(optc);
148
149	/* opp instance for OTG, 1 to 1 mapping and odm will adjust */
150	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
151			OPTC_SEG0_SRC_SEL, optc->inst);
152
153	/* VTG enable first is for HW workaround */
154	REG_UPDATE(CONTROL,
155			VTG0_ENABLE, 1);
156
157	REG_SEQ_START();
158
159	/* Enable CRTC */
160	REG_UPDATE_2(OTG_CONTROL,
161			OTG_DISABLE_POINT_CNTL, 2,
162			OTG_MASTER_EN, 1);
163
164	REG_SEQ_SUBMIT();
165	REG_SEQ_WAIT_DONE();
166
167	return true;
168}
169
170/* disable_crtc */
171static bool optc32_disable_crtc(struct timing_generator *optc)
172{
173	struct optc *optc1 = DCN10TG_FROM_TG(optc);
174
175	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
176			OPTC_SEG0_SRC_SEL, 0xf,
177			OPTC_SEG1_SRC_SEL, 0xf,
178			OPTC_SEG2_SRC_SEL, 0xf,
179			OPTC_SEG3_SRC_SEL, 0xf,
180			OPTC_NUM_OF_INPUT_SEGMENT, 0);
181
182	REG_UPDATE(OPTC_MEMORY_CONFIG,
183			OPTC_MEM_SEL, 0);
184
185	/* disable otg request until end of the first line
186	 * in the vertical blank region
187	 */
188	REG_UPDATE(OTG_CONTROL,
189			OTG_MASTER_EN, 0);
190
191	REG_UPDATE(CONTROL,
192			VTG0_ENABLE, 0);
193
194	/* CRTC disabled, so disable  clock. */
195	REG_WAIT(OTG_CLOCK_CONTROL,
196			OTG_BUSY, 0,
197			1, 150000);
198
199	return true;
200}
201
202static void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
203{
204	struct optc *optc1 = DCN10TG_FROM_TG(optc);
205
206	/* Disable immediately. */
207	REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
208
209	/* CRTC disabled, so disable  clock. */
210	REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
211}
212
213static void optc32_disable_phantom_otg(struct timing_generator *optc)
214{
215	struct optc *optc1 = DCN10TG_FROM_TG(optc);
216
217	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
218			OPTC_SEG0_SRC_SEL, 0xf,
219			OPTC_SEG1_SRC_SEL, 0xf,
220			OPTC_SEG2_SRC_SEL, 0xf,
221			OPTC_SEG3_SRC_SEL, 0xf,
222			OPTC_NUM_OF_INPUT_SEGMENT, 0);
223
224	REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
225}
226
227void optc32_set_odm_bypass(struct timing_generator *optc,
228		const struct dc_crtc_timing *dc_crtc_timing)
229{
230	struct optc *optc1 = DCN10TG_FROM_TG(optc);
231	enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
232
233	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
234			OPTC_NUM_OF_INPUT_SEGMENT, 0,
235			OPTC_SEG0_SRC_SEL, optc->inst,
236			OPTC_SEG1_SRC_SEL, 0xf,
237			OPTC_SEG2_SRC_SEL, 0xf,
238			OPTC_SEG3_SRC_SEL, 0xf
239			);
240
241	h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);
242	REG_UPDATE(OTG_H_TIMING_CNTL,
243			OTG_H_TIMING_DIV_MODE, h_div);
244
245	REG_SET(OPTC_MEMORY_CONFIG, 0,
246			OPTC_MEM_SEL, 0);
247	optc1->opp_count = 1;
248}
249
250static void optc32_setup_manual_trigger(struct timing_generator *optc)
251{
252	struct optc *optc1 = DCN10TG_FROM_TG(optc);
253	struct dc *dc = optc->ctx->dc;
254
255	if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
256		dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
257	else {
258		/*
259		 * MIN_MASK_EN is gone and MASK is now always enabled.
260		 *
261		 * To get it to it work with manual trigger we need to make sure
262		 * we program the correct bit.
263		 */
264		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
265				OTG_V_TOTAL_MIN_SEL, 1,
266				OTG_V_TOTAL_MAX_SEL, 1,
267				OTG_FORCE_LOCK_ON_EVENT, 0,
268				OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
269	}
270}
271
272static void optc32_set_drr(
273	struct timing_generator *optc,
274	const struct drr_params *params)
275{
276	struct optc *optc1 = DCN10TG_FROM_TG(optc);
277
278	if (params != NULL &&
279		params->vertical_total_max > 0 &&
280		params->vertical_total_min > 0) {
281
282		if (params->vertical_total_mid != 0) {
283
284			REG_SET(OTG_V_TOTAL_MID, 0,
285				OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
286
287			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
288					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
289					OTG_VTOTAL_MID_FRAME_NUM,
290					(uint8_t)params->vertical_total_mid_frame_num);
291
292		}
293
294		optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
295	}
296
297	optc32_setup_manual_trigger(optc);
298}
299
300static const struct timing_generator_funcs dcn32_tg_funcs = {
301		.validate_timing = optc1_validate_timing,
302		.program_timing = optc1_program_timing,
303		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
304		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
305		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
306		.program_global_sync = optc1_program_global_sync,
307		.enable_crtc = optc32_enable_crtc,
308		.disable_crtc = optc32_disable_crtc,
309		.phantom_crtc_post_enable = optc32_phantom_crtc_post_enable,
310		.disable_phantom_crtc = optc32_disable_phantom_otg,
311		/* used by enable_timing_synchronization. Not need for FPGA */
312		.is_counter_moving = optc1_is_counter_moving,
313		.get_position = optc1_get_position,
314		.get_frame_count = optc1_get_vblank_counter,
315		.get_scanoutpos = optc1_get_crtc_scanoutpos,
316		.get_otg_active_size = optc1_get_otg_active_size,
317		.set_early_control = optc1_set_early_control,
318		/* used by enable_timing_synchronization. Not need for FPGA */
319		.wait_for_state = optc1_wait_for_state,
320		.set_blank_color = optc3_program_blank_color,
321		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
322		.triplebuffer_lock = optc3_triplebuffer_lock,
323		.triplebuffer_unlock = optc2_triplebuffer_unlock,
324		.enable_reset_trigger = optc1_enable_reset_trigger,
325		.enable_crtc_reset = optc1_enable_crtc_reset,
326		.disable_reset_trigger = optc1_disable_reset_trigger,
327		.lock = optc3_lock,
328		.unlock = optc1_unlock,
329		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
330		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
331		.enable_optc_clock = optc1_enable_optc_clock,
332		.set_drr = optc32_set_drr,
333		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
334		.set_vtotal_min_max = optc3_set_vtotal_min_max,
335		.set_static_screen_control = optc1_set_static_screen_control,
336		.program_stereo = optc1_program_stereo,
337		.is_stereo_left_eye = optc1_is_stereo_left_eye,
338		.tg_init = optc3_tg_init,
339		.is_tg_enabled = optc1_is_tg_enabled,
340		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
341		.clear_optc_underflow = optc1_clear_optc_underflow,
342		.setup_global_swap_lock = NULL,
343		.get_crc = optc1_get_crc,
344		.configure_crc = optc1_configure_crc,
345		.set_dsc_config = optc3_set_dsc_config,
346		.get_dsc_status = optc2_get_dsc_status,
347		.set_dwb_source = NULL,
348		.set_odm_bypass = optc32_set_odm_bypass,
349		.set_odm_combine = optc32_set_odm_combine,
350		.get_odm_combine_segments = optc32_get_odm_combine_segments,
351		.wait_odm_doublebuffer_pending_clear = optc32_wait_odm_doublebuffer_pending_clear,
352		.set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
353		.get_optc_source = optc2_get_optc_source,
354		.set_out_mux = optc3_set_out_mux,
355		.set_drr_trigger_window = optc3_set_drr_trigger_window,
356		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
357		.set_gsl = optc2_set_gsl,
358		.set_gsl_source_select = optc2_set_gsl_source_select,
359		.set_vtg_params = optc1_set_vtg_params,
360		.program_manual_trigger = optc2_program_manual_trigger,
361		.setup_manual_trigger = optc2_setup_manual_trigger,
362		.get_hw_timing = optc1_get_hw_timing,
363		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,
364		.get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending,
365		.get_otg_double_buffer_pending = optc3_get_otg_update_pending,
366		.get_pipe_update_pending = optc3_get_pipe_update_pending,
367		.read_otg_state = optc31_read_otg_state,
368		.optc_read_reg_state = optc31_read_reg_state,
369};
370
371void dcn32_timing_generator_init(struct optc *optc1)
372{
373	optc1->base.funcs = &dcn32_tg_funcs;
374
375	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
376	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
377
378	optc1->min_h_blank = 32;
379	optc1->min_v_blank = 3;
380	optc1->min_v_blank_interlace = 5;
381	optc1->min_h_sync_width = 4;
382	optc1->min_v_sync_width = 1;
383}
384