dcn314_optc.c

  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright 2022 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 * Authors: AMD
 24 *
 25 */
 26
 27#include "dcn314_optc.h"
 28
 29#include "dcn30/dcn30_optc.h"
 30#include "dcn31/dcn31_optc.h"
 31#include "reg_helper.h"
 32#include "dc.h"
 33#include "dcn_calc_math.h"
 34
 35#define REG(reg)\
 36	optc1->tg_regs->reg
 37
 38#define CTX \
 39	optc1->base.ctx
 40
 41#undef FN
 42#define FN(reg_name, field_name) \
 43	optc1->tg_shift->field_name, optc1->tg_mask->field_name
 44
 45/*
 46 * Enable CRTC
 47 * Enable CRTC - call ASIC Control Object to enable Timing generator.
 48 */
 49
 50static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
 51		int segment_width, int last_segment_width)
 52{
 53	struct optc *optc1 = DCN10TG_FROM_TG(optc);
 54	uint32_t memory_mask = 0;
 55	int h_active = segment_width * opp_cnt;
 56	/* Each memory instance is 2048x(314x2) bits to support half line of 4096 */
 57	int odm_mem_count = (h_active + 2047) / 2048;
 58
 59	/*
 60	 * display <= 4k : 2 memories + 2 pipes
 61	 * 4k < display <= 8k : 4 memories + 2 pipes
 62	 * 8k < display <= 12k : 6 memories + 4 pipes
 63	 */
 64	if (opp_cnt == 4) {
 65		if (odm_mem_count <= 2)
 66			memory_mask = 0x3;
 67		else if (odm_mem_count <= 4)
 68			memory_mask = 0xf;
 69		else
 70			memory_mask = 0x3f;
 71	} else {
 72		if (odm_mem_count <= 2)
 73			memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
 74		else if (odm_mem_count <= 4)
 75			memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
 76		else
 77			memory_mask = 0x77;
 78	}
 79
 80	REG_SET(OPTC_MEMORY_CONFIG, 0,
 81		OPTC_MEM_SEL, memory_mask);
 82
 83	if (opp_cnt == 2) {
 84		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
 85				OPTC_NUM_OF_INPUT_SEGMENT, 1,
 86				OPTC_SEG0_SRC_SEL, opp_id[0],
 87				OPTC_SEG1_SRC_SEL, opp_id[1]);
 88	} else if (opp_cnt == 4) {
 89		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
 90				OPTC_NUM_OF_INPUT_SEGMENT, 3,
 91				OPTC_SEG0_SRC_SEL, opp_id[0],
 92				OPTC_SEG1_SRC_SEL, opp_id[1],
 93				OPTC_SEG2_SRC_SEL, opp_id[2],
 94				OPTC_SEG3_SRC_SEL, opp_id[3]);
 95	}
 96
 97	REG_UPDATE(OPTC_WIDTH_CONTROL,
 98			OPTC_SEGMENT_WIDTH, segment_width);
 99
100	REG_UPDATE(OTG_H_TIMING_CNTL,
101			OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
102	optc1->opp_count = opp_cnt;
103}
104
105static bool optc314_enable_crtc(struct timing_generator *optc)
106{
107	struct optc *optc1 = DCN10TG_FROM_TG(optc);
108
109	/* opp instance for OTG, 1 to 1 mapping and odm will adjust */
110	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
111			OPTC_SEG0_SRC_SEL, optc->inst);
112
113	/* VTG enable first is for HW workaround */
114	REG_UPDATE(CONTROL,
115			VTG0_ENABLE, 1);
116
117	REG_SEQ_START();
118
119	/* Enable CRTC */
120	REG_UPDATE_2(OTG_CONTROL,
121			OTG_DISABLE_POINT_CNTL, 2,
122			OTG_MASTER_EN, 1);
123
124	REG_SEQ_SUBMIT();
125	REG_SEQ_WAIT_DONE();
126
127	return true;
128}
129
130/* disable_crtc */
131static bool optc314_disable_crtc(struct timing_generator *optc)
132{
133	struct optc *optc1 = DCN10TG_FROM_TG(optc);
134
135	/* disable otg request until end of the first line
136	 * in the vertical blank region
137	 */
138	REG_UPDATE(OTG_CONTROL,
139			OTG_MASTER_EN, 0);
140
141	REG_UPDATE(CONTROL,
142			VTG0_ENABLE, 0);
143
144	/* CRTC disabled, so disable  clock. */
145	REG_WAIT(OTG_CLOCK_CONTROL,
146			OTG_BUSY, 0,
147			1, 100000);
148
149	return true;
150}
151
152static void optc314_phantom_crtc_post_enable(struct timing_generator *optc)
153{
154	struct optc *optc1 = DCN10TG_FROM_TG(optc);
155
156	/* Disable immediately. */
157	REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
158
159	/* CRTC disabled, so disable  clock. */
160	REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
161}
162
163static void optc314_set_odm_bypass(struct timing_generator *optc,
164		const struct dc_crtc_timing *dc_crtc_timing)
165{
166	struct optc *optc1 = DCN10TG_FROM_TG(optc);
167	enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
168
169	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
170			OPTC_NUM_OF_INPUT_SEGMENT, 0,
171			OPTC_SEG0_SRC_SEL, optc->inst,
172			OPTC_SEG1_SRC_SEL, 0xf,
173			OPTC_SEG2_SRC_SEL, 0xf,
174			OPTC_SEG3_SRC_SEL, 0xf
175			);
176
177	h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);
178	REG_UPDATE(OTG_H_TIMING_CNTL,
179			OTG_H_TIMING_DIV_MODE, h_div);
180
181	REG_SET(OPTC_MEMORY_CONFIG, 0,
182			OPTC_MEM_SEL, 0);
183	optc1->opp_count = 1;
184}
185
186static void optc314_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
187{
188	struct optc *optc1 = DCN10TG_FROM_TG(optc);
189
190	REG_UPDATE(OTG_H_TIMING_CNTL,
191			OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
192}
193
194
195static const struct timing_generator_funcs dcn314_tg_funcs = {
196		.validate_timing = optc1_validate_timing,
197		.program_timing = optc1_program_timing,
198		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
199		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
200		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
201		.program_global_sync = optc1_program_global_sync,
202		.enable_crtc = optc314_enable_crtc,
203		.disable_crtc = optc314_disable_crtc,
204		.immediate_disable_crtc = optc31_immediate_disable_crtc,
205		.phantom_crtc_post_enable = optc314_phantom_crtc_post_enable,
206		/* used by enable_timing_synchronization. Not need for FPGA */
207		.is_counter_moving = optc1_is_counter_moving,
208		.get_position = optc1_get_position,
209		.get_frame_count = optc1_get_vblank_counter,
210		.get_scanoutpos = optc1_get_crtc_scanoutpos,
211		.get_otg_active_size = optc1_get_otg_active_size,
212		.set_early_control = optc1_set_early_control,
213		/* used by enable_timing_synchronization. Not need for FPGA */
214		.wait_for_state = optc1_wait_for_state,
215		.set_blank_color = optc3_program_blank_color,
216		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
217		.triplebuffer_lock = optc3_triplebuffer_lock,
218		.triplebuffer_unlock = optc2_triplebuffer_unlock,
219		.enable_reset_trigger = optc1_enable_reset_trigger,
220		.enable_crtc_reset = optc1_enable_crtc_reset,
221		.disable_reset_trigger = optc1_disable_reset_trigger,
222		.lock = optc3_lock,
223		.unlock = optc1_unlock,
224		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
225		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
226		.enable_optc_clock = optc1_enable_optc_clock,
227		.set_drr = optc31_set_drr,
228		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
229		.set_vtotal_min_max = optc1_set_vtotal_min_max,
230		.set_static_screen_control = optc1_set_static_screen_control,
231		.program_stereo = optc1_program_stereo,
232		.is_stereo_left_eye = optc1_is_stereo_left_eye,
233		.tg_init = optc3_tg_init,
234		.is_tg_enabled = optc1_is_tg_enabled,
235		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
236		.clear_optc_underflow = optc1_clear_optc_underflow,
237		.setup_global_swap_lock = NULL,
238		.get_crc = optc1_get_crc,
239		.configure_crc = optc1_configure_crc,
240		.set_dsc_config = optc3_set_dsc_config,
241		.get_dsc_status = optc2_get_dsc_status,
242		.set_dwb_source = NULL,
243		.get_optc_source = optc2_get_optc_source,
244		.set_out_mux = optc3_set_out_mux,
245		.set_drr_trigger_window = optc3_set_drr_trigger_window,
246		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
247		.set_gsl = optc2_set_gsl,
248		.set_gsl_source_select = optc2_set_gsl_source_select,
249		.set_vtg_params = optc1_set_vtg_params,
250		.program_manual_trigger = optc2_program_manual_trigger,
251		.setup_manual_trigger = optc2_setup_manual_trigger,
252		.get_hw_timing = optc1_get_hw_timing,
253		.init_odm = optc3_init_odm,
254		.set_odm_bypass = optc314_set_odm_bypass,
255		.set_odm_combine = optc314_set_odm_combine,
256		.set_h_timing_div_manual_mode = optc314_set_h_timing_div_manual_mode,
257		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,
258		.read_otg_state = optc31_read_otg_state,
259		.optc_read_reg_state = optc31_read_reg_state,
260};
261
262void dcn314_timing_generator_init(struct optc *optc1)
263{
264	optc1->base.funcs = &dcn314_tg_funcs;
265
266	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
267	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
268
269	optc1->min_h_blank = 32;
270	optc1->min_v_blank = 3;
271	optc1->min_v_blank_interlace = 5;
272	optc1->min_h_sync_width = 4;
273	optc1->min_v_sync_width = 1;
274}
275