FILE
dcn31_optc.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
1/* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "dcn31_optc.h" 27 28#include "dcn30/dcn30_optc.h" 29#include "reg_helper.h" 30#include "dc.h" 31#include "dcn_calc_math.h" 32 33#define REG(reg)\ 34 optc1->tg_regs->reg 35 36#define CTX \ 37 optc1->base.ctx 38 39#undef FN 40#define FN(reg_name, field_name) \ 41 optc1->tg_shift->field_name, optc1->tg_mask->field_name 42 43static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 44 int segment_width, int last_segment_width) 45{ 46 struct optc *optc1 = DCN10TG_FROM_TG(optc); 47 uint32_t memory_mask = 0; 48 int mem_count_per_opp = (segment_width + 2559) / 2560; 49 50 /* Assume less than 6 pipes */ 51 if (opp_cnt == 4) { 52 if (mem_count_per_opp == 1) 53 memory_mask = 0xf; 54 else { 55 ASSERT(mem_count_per_opp == 2); 56 memory_mask = 0xff; 57 } 58 } else if (mem_count_per_opp == 1) 59 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); 60 else if (mem_count_per_opp == 2) 61 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); 62 else if (mem_count_per_opp == 3) 63 memory_mask = 0x77; 64 else if (mem_count_per_opp == 4) 65 memory_mask = 0xff; 66 67 if (REG(OPTC_MEMORY_CONFIG)) 68 REG_SET(OPTC_MEMORY_CONFIG, 0, 69 OPTC_MEM_SEL, memory_mask); 70 71 if (opp_cnt == 2) { 72 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 73 OPTC_NUM_OF_INPUT_SEGMENT, 1, 74 OPTC_SEG0_SRC_SEL, opp_id[0], 75 OPTC_SEG1_SRC_SEL, opp_id[1]); 76 } else if (opp_cnt == 4) { 77 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 78 OPTC_NUM_OF_INPUT_SEGMENT, 3, 79 OPTC_SEG0_SRC_SEL, opp_id[0], 80 OPTC_SEG1_SRC_SEL, opp_id[1], 81 OPTC_SEG2_SRC_SEL, opp_id[2], 82 OPTC_SEG3_SRC_SEL, opp_id[3]); 83 } 84 85 REG_UPDATE(OPTC_WIDTH_CONTROL, 86 OPTC_SEGMENT_WIDTH, segment_width); 87 88 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); 89 optc1->opp_count = opp_cnt; 90} 91 92/* 93 * Enable CRTC - call ASIC Control Object to enable Timing generator. 94 */ 95static bool optc31_enable_crtc(struct timing_generator *optc) 96{ 97 struct optc *optc1 = DCN10TG_FROM_TG(optc); 98 99 /* opp instance for OTG, 1 to 1 mapping and odm will adjust */ 100 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 101 OPTC_SEG0_SRC_SEL, optc->inst); 102 103 /* VTG enable first is for HW workaround */ 104 REG_UPDATE(CONTROL, 105 VTG0_ENABLE, 1); 106 107 REG_SEQ_START(); 108 109 /* Enable CRTC */ 110 REG_UPDATE_2(OTG_CONTROL, 111 OTG_DISABLE_POINT_CNTL, 2, 112 OTG_MASTER_EN, 1); 113 114 REG_SEQ_SUBMIT(); 115 REG_SEQ_WAIT_DONE(); 116 117 return true; 118} 119 120/* disable_crtc - call ASIC Control Object to disable Timing generator. */ 121static bool optc31_disable_crtc(struct timing_generator *optc) 122{ 123 struct optc *optc1 = DCN10TG_FROM_TG(optc); 124 125 REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT, 126 OPTC_SEG0_SRC_SEL, 0xf, 127 OPTC_SEG1_SRC_SEL, 0xf, 128 OPTC_SEG2_SRC_SEL, 0xf, 129 OPTC_SEG3_SRC_SEL, 0xf, 130 OPTC_NUM_OF_INPUT_SEGMENT, 0); 131 132 REG_UPDATE(OPTC_MEMORY_CONFIG, 133 OPTC_MEM_SEL, 0); 134 135 /* disable otg request until end of the first line 136 * in the vertical blank region 137 */ 138 REG_UPDATE(OTG_CONTROL, 139 OTG_MASTER_EN, 0); 140 141 REG_UPDATE(CONTROL, 142 VTG0_ENABLE, 0); 143 144 /* CRTC disabled, so disable clock. */ 145 REG_WAIT(OTG_CLOCK_CONTROL, 146 OTG_BUSY, 0, 147 1, 100000); 148 optc1_clear_optc_underflow(optc); 149 150 return true; 151} 152/* 153 * Immediate_Disable_Crtc - this is to temp disable Timing generator without reset ODM. 154 */ 155bool optc31_immediate_disable_crtc(struct timing_generator *optc) 156{ 157 struct optc *optc1 = DCN10TG_FROM_TG(optc); 158 159 REG_UPDATE_2(OTG_CONTROL, 160 OTG_DISABLE_POINT_CNTL, 0, 161 OTG_MASTER_EN, 0); 162 163 REG_UPDATE(CONTROL, 164 VTG0_ENABLE, 0); 165 166 /* CRTC disabled, so disable clock. */ 167 if (optc->ctx->dce_environment != DCE_ENV_DIAG) 168 REG_WAIT(OTG_CLOCK_CONTROL, 169 OTG_BUSY, 0, 170 1, 100000); 171 172 173 /* clear the false state */ 174 optc1_clear_optc_underflow(optc); 175 176 return true; 177} 178 179void optc31_set_drr( 180 struct timing_generator *optc, 181 const struct drr_params *params) 182{ 183 struct optc *optc1 = DCN10TG_FROM_TG(optc); 184 185 if (params != NULL && 186 params->vertical_total_max > 0 && 187 params->vertical_total_min > 0) { 188 189 if (params->vertical_total_mid != 0) { 190 191 REG_SET(OTG_V_TOTAL_MID, 0, 192 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 193 194 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 195 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 196 OTG_VTOTAL_MID_FRAME_NUM, 197 (uint8_t)params->vertical_total_mid_frame_num); 198 199 } 200 201 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1); 202 203 /* 204 * MIN_MASK_EN is gone and MASK is now always enabled. 205 * 206 * To get it to it work with manual trigger we need to make sure 207 * we program the correct bit. 208 */ 209 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 210 OTG_V_TOTAL_MIN_SEL, 1, 211 OTG_V_TOTAL_MAX_SEL, 1, 212 OTG_FORCE_LOCK_ON_EVENT, 0, 213 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */ 214 215 // Setup manual flow control for EOF via TRIG_A 216 optc->funcs->setup_manual_trigger(optc); 217 } else { 218 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 219 OTG_SET_V_TOTAL_MIN_MASK, 0, 220 OTG_V_TOTAL_MIN_SEL, 0, 221 OTG_V_TOTAL_MAX_SEL, 0, 222 OTG_FORCE_LOCK_ON_EVENT, 0); 223 224 optc->funcs->set_vtotal_min_max(optc, 0, 0); 225 } 226} 227 228void optc3_init_odm(struct timing_generator *optc) 229{ 230 struct optc *optc1 = DCN10TG_FROM_TG(optc); 231 232 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 233 OPTC_NUM_OF_INPUT_SEGMENT, 0, 234 OPTC_SEG0_SRC_SEL, optc->inst, 235 OPTC_SEG1_SRC_SEL, 0xf, 236 OPTC_SEG2_SRC_SEL, 0xf, 237 OPTC_SEG3_SRC_SEL, 0xf 238 ); 239 240 REG_SET(OTG_H_TIMING_CNTL, 0, 241 OTG_H_TIMING_DIV_MODE, 0); 242 243 REG_SET(OPTC_MEMORY_CONFIG, 0, 244 OPTC_MEM_SEL, 0); 245 optc1->opp_count = 1; 246} 247 248void optc31_read_otg_state(struct timing_generator *optc, 249 struct dcn_otg_state *s) 250{ 251 struct optc *optc1 = DCN10TG_FROM_TG(optc); 252 253 REG_GET(OTG_CONTROL, 254 OTG_MASTER_EN, &s->otg_enabled); 255 256 REG_GET_2(OTG_V_BLANK_START_END, 257 OTG_V_BLANK_START, &s->v_blank_start, 258 OTG_V_BLANK_END, &s->v_blank_end); 259 260 REG_GET(OTG_V_SYNC_A_CNTL, 261 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 262 263 REG_GET(OTG_V_TOTAL, 264 OTG_V_TOTAL, &s->v_total); 265 266 REG_GET(OTG_V_TOTAL_MAX, 267 OTG_V_TOTAL_MAX, &s->v_total_max); 268 269 REG_GET(OTG_V_TOTAL_MIN, 270 OTG_V_TOTAL_MIN, &s->v_total_min); 271 272 REG_GET(OTG_V_TOTAL_CONTROL, 273 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 274 275 REG_GET(OTG_V_TOTAL_CONTROL, 276 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 277 278 REG_GET_2(OTG_V_SYNC_A, 279 OTG_V_SYNC_A_START, &s->v_sync_a_start, 280 OTG_V_SYNC_A_END, &s->v_sync_a_end); 281 282 REG_GET_2(OTG_H_BLANK_START_END, 283 OTG_H_BLANK_START, &s->h_blank_start, 284 OTG_H_BLANK_END, &s->h_blank_end); 285 286 REG_GET_2(OTG_H_SYNC_A, 287 OTG_H_SYNC_A_START, &s->h_sync_a_start, 288 OTG_H_SYNC_A_END, &s->h_sync_a_end); 289 290 REG_GET(OTG_H_SYNC_A_CNTL, 291 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 292 293 REG_GET(OTG_H_TOTAL, 294 OTG_H_TOTAL, &s->h_total); 295 296 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 297 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 298 299 REG_GET(OTG_VERTICAL_INTERRUPT1_CONTROL, 300 OTG_VERTICAL_INTERRUPT1_INT_ENABLE, &s->vertical_interrupt1_en); 301 302 REG_GET(OTG_VERTICAL_INTERRUPT1_POSITION, 303 OTG_VERTICAL_INTERRUPT1_LINE_START, &s->vertical_interrupt1_line); 304 305 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL, 306 OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en); 307 308 REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION, 309 OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line); 310 311 REG_GET(INTERRUPT_DEST, 312 OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, &s->vertical_interrupt2_dest); 313 314 s->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK); 315 s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL); 316} 317 318void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_state *optc_reg_state) 319{ 320 struct optc *optc1 = DCN10TG_FROM_TG(optc); 321 322 optc_reg_state->optc_bytes_per_pixel = REG_READ(OPTC_BYTES_PER_PIXEL); 323 optc_reg_state->optc_data_format_control = REG_READ(OPTC_DATA_FORMAT_CONTROL); 324 optc_reg_state->optc_data_source_select = REG_READ(OPTC_DATA_SOURCE_SELECT); 325 optc_reg_state->optc_input_clock_control = REG_READ(OPTC_INPUT_CLOCK_CONTROL); 326 optc_reg_state->optc_input_global_control = REG_READ(OPTC_INPUT_GLOBAL_CONTROL); 327 optc_reg_state->optc_input_spare_register = REG_READ(OPTC_INPUT_SPARE_REGISTER); 328 optc_reg_state->optc_memory_config = REG_READ(OPTC_MEMORY_CONFIG); 329 optc_reg_state->optc_rsmu_underflow = REG_READ(OPTC_RSMU_UNDERFLOW); 330 optc_reg_state->optc_underflow_threshold = REG_READ(OPTC_UNDERFLOW_THRESHOLD); 331 optc_reg_state->optc_width_control = REG_READ(OPTC_WIDTH_CONTROL); 332 optc_reg_state->otg_3d_structure_control = REG_READ(OTG_3D_STRUCTURE_CONTROL); 333 optc_reg_state->otg_clock_control = REG_READ(OTG_CLOCK_CONTROL); 334 optc_reg_state->otg_control = REG_READ(OTG_CONTROL); 335 optc_reg_state->otg_count_control = REG_READ(OTG_COUNT_CONTROL); 336 optc_reg_state->otg_count_reset = REG_READ(OTG_COUNT_RESET); 337 optc_reg_state->otg_crc_cntl = REG_READ(OTG_CRC_CNTL); 338 optc_reg_state->otg_crc_sig_blue_control_mask = REG_READ(OTG_CRC_SIG_BLUE_CONTROL_MASK); 339 optc_reg_state->otg_crc_sig_red_green_mask = REG_READ(OTG_CRC_SIG_RED_GREEN_MASK); 340 optc_reg_state->otg_crc0_data_b = REG_READ(OTG_CRC0_DATA_B); 341 optc_reg_state->otg_crc0_data_rg = REG_READ(OTG_CRC0_DATA_RG); 342 optc_reg_state->otg_crc0_windowa_x_control = REG_READ(OTG_CRC0_WINDOWA_X_CONTROL); 343 optc_reg_state->otg_crc0_windowa_x_control_readback = REG_READ(OTG_CRC0_WINDOWA_X_CONTROL_READBACK); 344 optc_reg_state->otg_crc0_windowa_y_control = REG_READ(OTG_CRC0_WINDOWA_Y_CONTROL); 345 optc_reg_state->otg_crc0_windowa_y_control_readback = REG_READ(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK); 346 optc_reg_state->otg_crc0_windowb_x_control = REG_READ(OTG_CRC0_WINDOWB_X_CONTROL); 347 optc_reg_state->otg_crc0_windowb_x_control_readback = REG_READ(OTG_CRC0_WINDOWB_X_CONTROL_READBACK); 348 optc_reg_state->otg_crc0_windowb_y_control = REG_READ(OTG_CRC0_WINDOWB_Y_CONTROL); 349 optc_reg_state->otg_crc0_windowb_y_control_readback = REG_READ(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK); 350 optc_reg_state->otg_crc1_data_b = REG_READ(OTG_CRC1_DATA_B); 351 optc_reg_state->otg_crc1_data_rg = REG_READ(OTG_CRC1_DATA_RG); 352 optc_reg_state->otg_crc1_windowa_x_control = REG_READ(OTG_CRC1_WINDOWA_X_CONTROL); 353 optc_reg_state->otg_crc1_windowa_x_control_readback = REG_READ(OTG_CRC1_WINDOWA_X_CONTROL_READBACK); 354 optc_reg_state->otg_crc1_windowa_y_control = REG_READ(OTG_CRC1_WINDOWA_Y_CONTROL); 355 optc_reg_state->otg_crc1_windowa_y_control_readback = REG_READ(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK); 356 optc_reg_state->otg_crc1_windowb_x_control = REG_READ(OTG_CRC1_WINDOWB_X_CONTROL); 357 optc_reg_state->otg_crc1_windowb_x_control_readback = REG_READ(OTG_CRC1_WINDOWB_X_CONTROL_READBACK); 358 optc_reg_state->otg_crc1_windowb_y_control = REG_READ(OTG_CRC1_WINDOWB_Y_CONTROL); 359 optc_reg_state->otg_crc1_windowb_y_control_readback = REG_READ(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK); 360 optc_reg_state->otg_crc2_data_b = REG_READ(OTG_CRC2_DATA_B); 361 optc_reg_state->otg_crc2_data_rg = REG_READ(OTG_CRC2_DATA_RG); 362 optc_reg_state->otg_crc3_data_b = REG_READ(OTG_CRC3_DATA_B); 363 optc_reg_state->otg_crc3_data_rg = REG_READ(OTG_CRC3_DATA_RG); 364 optc_reg_state->otg_dlpc_control = REG_READ(OTG_DLPC_CONTROL); 365 optc_reg_state->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL); 366 optc_reg_state->otg_drr_control2 = REG_READ(OTG_DRR_CONTROL2); 367 optc_reg_state->otg_drr_control = REG_READ(OTG_DRR_CONTROL); 368 optc_reg_state->otg_drr_timing_int_status = REG_READ(OTG_DRR_TIMING_INT_STATUS); 369 optc_reg_state->otg_drr_trigger_window = REG_READ(OTG_DRR_TRIGGER_WINDOW); 370 optc_reg_state->otg_drr_v_total_change = REG_READ(OTG_DRR_V_TOTAL_CHANGE); 371 optc_reg_state->otg_dsc_start_position = REG_READ(OTG_DSC_START_POSITION); 372 optc_reg_state->otg_force_count_now_cntl = REG_READ(OTG_FORCE_COUNT_NOW_CNTL); 373 optc_reg_state->otg_global_control0 = REG_READ(OTG_GLOBAL_CONTROL0); 374 optc_reg_state->otg_global_control1 = REG_READ(OTG_GLOBAL_CONTROL1); 375 optc_reg_state->otg_global_control2 = REG_READ(OTG_GLOBAL_CONTROL2); 376 optc_reg_state->otg_global_control3 = REG_READ(OTG_GLOBAL_CONTROL3); 377 optc_reg_state->otg_global_control4 = REG_READ(OTG_GLOBAL_CONTROL4); 378 optc_reg_state->otg_global_sync_status = REG_READ(OTG_GLOBAL_SYNC_STATUS); 379 optc_reg_state->otg_gsl_control = REG_READ(OTG_GSL_CONTROL); 380 optc_reg_state->otg_gsl_vsync_gap = REG_READ(OTG_GSL_VSYNC_GAP); 381 optc_reg_state->otg_gsl_window_x = REG_READ(OTG_GSL_WINDOW_X); 382 optc_reg_state->otg_gsl_window_y = REG_READ(OTG_GSL_WINDOW_Y); 383 optc_reg_state->otg_h_blank_start_end = REG_READ(OTG_H_BLANK_START_END); 384 optc_reg_state->otg_h_sync_a = REG_READ(OTG_H_SYNC_A); 385 optc_reg_state->otg_h_sync_a_cntl = REG_READ(OTG_H_SYNC_A_CNTL); 386 optc_reg_state->otg_h_timing_cntl = REG_READ(OTG_H_TIMING_CNTL); 387 optc_reg_state->otg_h_total = REG_READ(OTG_H_TOTAL); 388 optc_reg_state->otg_interlace_control = REG_READ(OTG_INTERLACE_CONTROL); 389 optc_reg_state->otg_interlace_status = REG_READ(OTG_INTERLACE_STATUS); 390 optc_reg_state->otg_interrupt_control = REG_READ(OTG_INTERRUPT_CONTROL); 391 optc_reg_state->otg_long_vblank_status = REG_READ(OTG_LONG_VBLANK_STATUS); 392 optc_reg_state->otg_m_const_dto0 = REG_READ(OTG_M_CONST_DTO0); 393 optc_reg_state->otg_m_const_dto1 = REG_READ(OTG_M_CONST_DTO1); 394 optc_reg_state->otg_manual_force_vsync_next_line = REG_READ(OTG_MANUAL_FORCE_VSYNC_NEXT_LINE); 395 optc_reg_state->otg_master_en = REG_READ(OTG_MASTER_EN); 396 optc_reg_state->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK); 397 optc_reg_state->otg_master_update_mode = REG_READ(OTG_MASTER_UPDATE_MODE); 398 optc_reg_state->otg_nom_vert_position = REG_READ(OTG_NOM_VERT_POSITION); 399 optc_reg_state->otg_pipe_update_status = REG_READ(OTG_PIPE_UPDATE_STATUS); 400 optc_reg_state->otg_pixel_data_readback0 = REG_READ(OTG_PIXEL_DATA_READBACK0); 401 optc_reg_state->otg_pixel_data_readback1 = REG_READ(OTG_PIXEL_DATA_READBACK1); 402 optc_reg_state->otg_request_control = REG_READ(OTG_REQUEST_CONTROL); 403 optc_reg_state->otg_snapshot_control = REG_READ(OTG_SNAPSHOT_CONTROL); 404 optc_reg_state->otg_snapshot_frame = REG_READ(OTG_SNAPSHOT_FRAME); 405 optc_reg_state->otg_snapshot_position = REG_READ(OTG_SNAPSHOT_POSITION); 406 optc_reg_state->otg_snapshot_status = REG_READ(OTG_SNAPSHOT_STATUS); 407 optc_reg_state->otg_spare_register = REG_READ(OTG_SPARE_REGISTER); 408 optc_reg_state->otg_static_screen_control = REG_READ(OTG_STATIC_SCREEN_CONTROL); 409 optc_reg_state->otg_status = REG_READ(OTG_STATUS); 410 optc_reg_state->otg_status_frame_count = REG_READ(OTG_STATUS_FRAME_COUNT); 411 optc_reg_state->otg_status_hv_count = REG_READ(OTG_STATUS_HV_COUNT); 412 optc_reg_state->otg_status_position = REG_READ(OTG_STATUS_POSITION); 413 optc_reg_state->otg_status_vf_count = REG_READ(OTG_STATUS_VF_COUNT); 414 optc_reg_state->otg_stereo_control = REG_READ(OTG_STEREO_CONTROL); 415 optc_reg_state->otg_stereo_force_next_eye = REG_READ(OTG_STEREO_FORCE_NEXT_EYE); 416 optc_reg_state->otg_stereo_status = REG_READ(OTG_STEREO_STATUS); 417 optc_reg_state->otg_trig_manual_control = REG_READ(OTG_TRIG_MANUAL_CONTROL); 418 optc_reg_state->otg_triga_cntl = REG_READ(OTG_TRIGA_CNTL); 419 optc_reg_state->otg_triga_manual_trig = REG_READ(OTG_TRIGA_MANUAL_TRIG); 420 optc_reg_state->otg_trigb_cntl = REG_READ(OTG_TRIGB_CNTL); 421 optc_reg_state->otg_trigb_manual_trig = REG_READ(OTG_TRIGB_MANUAL_TRIG); 422 optc_reg_state->otg_update_lock = REG_READ(OTG_UPDATE_LOCK); 423 optc_reg_state->otg_v_blank_start_end = REG_READ(OTG_V_BLANK_START_END); 424 optc_reg_state->otg_v_count_stop_control = REG_READ(OTG_V_COUNT_STOP_CONTROL); 425 optc_reg_state->otg_v_count_stop_control2 = REG_READ(OTG_V_COUNT_STOP_CONTROL2); 426 optc_reg_state->otg_v_sync_a = REG_READ(OTG_V_SYNC_A); 427 optc_reg_state->otg_v_sync_a_cntl = REG_READ(OTG_V_SYNC_A_CNTL); 428 optc_reg_state->otg_v_total = REG_READ(OTG_V_TOTAL); 429 optc_reg_state->otg_v_total_control = REG_READ(OTG_V_TOTAL_CONTROL); 430 optc_reg_state->otg_v_total_int_status = REG_READ(OTG_V_TOTAL_INT_STATUS); 431 optc_reg_state->otg_v_total_max = REG_READ(OTG_V_TOTAL_MAX); 432 optc_reg_state->otg_v_total_mid = REG_READ(OTG_V_TOTAL_MID); 433 optc_reg_state->otg_v_total_min = REG_READ(OTG_V_TOTAL_MIN); 434 optc_reg_state->otg_vert_sync_control = REG_READ(OTG_VERT_SYNC_CONTROL); 435 optc_reg_state->otg_vertical_interrupt0_control = REG_READ(OTG_VERTICAL_INTERRUPT0_CONTROL); 436 optc_reg_state->otg_vertical_interrupt0_position = REG_READ(OTG_VERTICAL_INTERRUPT0_POSITION); 437 optc_reg_state->otg_vertical_interrupt1_control = REG_READ(OTG_VERTICAL_INTERRUPT1_CONTROL); 438 optc_reg_state->otg_vertical_interrupt1_position = REG_READ(OTG_VERTICAL_INTERRUPT1_POSITION); 439 optc_reg_state->otg_vertical_interrupt2_control = REG_READ(OTG_VERTICAL_INTERRUPT2_CONTROL); 440 optc_reg_state->otg_vertical_interrupt2_position = REG_READ(OTG_VERTICAL_INTERRUPT2_POSITION); 441 optc_reg_state->otg_vready_param = REG_READ(OTG_VREADY_PARAM); 442 optc_reg_state->otg_vstartup_param = REG_READ(OTG_VSTARTUP_PARAM); 443 optc_reg_state->otg_vsync_nom_int_status = REG_READ(OTG_VSYNC_NOM_INT_STATUS); 444 optc_reg_state->otg_vupdate_keepout = REG_READ(OTG_VUPDATE_KEEPOUT); 445 optc_reg_state->otg_vupdate_param = REG_READ(OTG_VUPDATE_PARAM); 446} 447 448static const struct timing_generator_funcs dcn31_tg_funcs = { 449 .validate_timing = optc1_validate_timing, 450 .program_timing = optc1_program_timing, 451 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 452 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 453 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 454 .program_global_sync = optc1_program_global_sync, 455 .enable_crtc = optc31_enable_crtc, 456 .disable_crtc = optc31_disable_crtc, 457 .immediate_disable_crtc = optc31_immediate_disable_crtc, 458 /* used by enable_timing_synchronization. Not need for FPGA */ 459 .is_counter_moving = optc1_is_counter_moving, 460 .get_position = optc1_get_position, 461 .get_frame_count = optc1_get_vblank_counter, 462 .get_scanoutpos = optc1_get_crtc_scanoutpos, 463 .get_otg_active_size = optc1_get_otg_active_size, 464 .set_early_control = optc1_set_early_control, 465 /* used by enable_timing_synchronization. Not need for FPGA */ 466 .wait_for_state = optc1_wait_for_state, 467 .set_blank_color = optc3_program_blank_color, 468 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 469 .triplebuffer_lock = optc3_triplebuffer_lock, 470 .triplebuffer_unlock = optc2_triplebuffer_unlock, 471 .enable_reset_trigger = optc1_enable_reset_trigger, 472 .enable_crtc_reset = optc1_enable_crtc_reset, 473 .disable_reset_trigger = optc1_disable_reset_trigger, 474 .lock = optc3_lock, 475 .unlock = optc1_unlock, 476 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, 477 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, 478 .enable_optc_clock = optc1_enable_optc_clock, 479 .set_drr = optc31_set_drr, 480 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, 481 .set_vtotal_min_max = optc1_set_vtotal_min_max, 482 .set_static_screen_control = optc1_set_static_screen_control, 483 .program_stereo = optc1_program_stereo, 484 .is_stereo_left_eye = optc1_is_stereo_left_eye, 485 .tg_init = optc3_tg_init, 486 .is_tg_enabled = optc1_is_tg_enabled, 487 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 488 .clear_optc_underflow = optc1_clear_optc_underflow, 489 .setup_global_swap_lock = NULL, 490 .get_crc = optc1_get_crc, 491 .configure_crc = optc2_configure_crc, 492 .set_dsc_config = optc3_set_dsc_config, 493 .get_dsc_status = optc2_get_dsc_status, 494 .set_dwb_source = NULL, 495 .set_odm_bypass = optc3_set_odm_bypass, 496 .set_odm_combine = optc31_set_odm_combine, 497 .get_optc_source = optc2_get_optc_source, 498 .set_out_mux = optc3_set_out_mux, 499 .set_drr_trigger_window = optc3_set_drr_trigger_window, 500 .set_vtotal_change_limit = optc3_set_vtotal_change_limit, 501 .set_gsl = optc2_set_gsl, 502 .set_gsl_source_select = optc2_set_gsl_source_select, 503 .set_vtg_params = optc1_set_vtg_params, 504 .program_manual_trigger = optc2_program_manual_trigger, 505 .setup_manual_trigger = optc2_setup_manual_trigger, 506 .get_hw_timing = optc1_get_hw_timing, 507 .init_odm = optc3_init_odm, 508 .is_two_pixels_per_container = optc1_is_two_pixels_per_container, 509 .read_otg_state = optc31_read_otg_state, 510 .optc_read_reg_state = optc31_read_reg_state, 511}; 512 513void dcn31_timing_generator_init(struct optc *optc1) 514{ 515 optc1->base.funcs = &dcn31_tg_funcs; 516 517 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 518 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 519 520 optc1->min_h_blank = 32; 521 optc1->min_v_blank = 3; 522 optc1->min_v_blank_interlace = 5; 523 optc1->min_h_sync_width = 4; 524 optc1->min_v_sync_width = 1; 525} 526
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