dcn35_opp.h

 1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright 2023 Advanced Micro Devices, Inc.
 4 *
 5 * Permission is hereby granted, free of charge, to any person obtaining a
 6 * copy of this software and associated documentation files (the "Software"),
 7 * to deal in the Software without restriction, including without limitation
 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#ifndef __DCN35_OPP_H
28#define __DCN35_OPP_H
29
30#include "dcn20/dcn20_opp.h"
31
32#define OPP_REG_VARIABLE_LIST_DCN3_5  \
33	OPP_REG_VARIABLE_LIST_DCN2_0; \
34	uint32_t OPP_TOP_CLK_CONTROL; \
35	uint32_t OPP_ABM_CONTROL
36
37#define OPP_MASK_SH_LIST_DCN35(mask_sh)  \
38	OPP_MASK_SH_LIST_DCN20(mask_sh), \
39		OPP_SF(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, mask_sh)
40
41#define OPP_DCN35_REG_FIELD_LIST(type)          \
42	struct {                                \
43		OPP_DCN20_REG_FIELD_LIST(type); \
44		type OPP_FGCG_REP_DIS;          \
45	}
46
47struct dcn35_opp_registers {
48	OPP_REG_VARIABLE_LIST_DCN3_5;
49};
50
51struct dcn35_opp_shift {
52	OPP_DCN35_REG_FIELD_LIST(uint8_t);
53};
54
55struct dcn35_opp_mask {
56	OPP_DCN35_REG_FIELD_LIST(uint32_t);
57};
58
59void dcn35_opp_construct(struct dcn20_opp *oppn20,
60	struct dc_context *ctx,
61	uint32_t inst,
62	const struct dcn35_opp_registers *regs,
63	const struct dcn35_opp_shift *opp_shift,
64	const struct dcn35_opp_mask *opp_mask);
65
66void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable);
67
68void dcn35_opp_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state);
69#endif