dcn401_mpc.h

  1/*
  2 * Copyright 2023 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DC_MPCC_DCN401_H__
 27#define __DC_MPCC_DCN401_H__
 28#include "dcn30/dcn30_mpc.h"
 29#include "dcn32/dcn32_mpc.h"
 30
 31#define TO_DCN401_MPC(mpc_base) \
 32	container_of(mpc_base, struct dcn401_mpc, base)
 33
 34#define MPC_REG_VARIABLE_LIST_DCN4_01 \
 35	MPC_REG_VARIABLE_LIST_DCN3_0; \
 36	MPC_REG_VARIABLE_LIST_DCN32; \
 37	uint32_t MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \
 38	uint32_t MPCC_MCM_FIRST_GAMUT_REMAP_MODE[MAX_MPCC]; \
 39	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \
 40	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \
 41	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \
 42	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \
 43	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \
 44	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \
 45	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \
 46	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B[MAX_MPCC]; \
 47	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B[MAX_MPCC]; \
 48	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B[MAX_MPCC]; \
 49	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B[MAX_MPCC]; \
 50	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \
 51	uint32_t MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \
 52	uint32_t MPCC_MCM_SECOND_GAMUT_REMAP_MODE[MAX_MPCC]; \
 53	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \
 54	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \
 55	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \
 56	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \
 57	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \
 58	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \
 59	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \
 60	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B[MAX_MPCC]; \
 61	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B[MAX_MPCC]; \
 62	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B[MAX_MPCC]; \
 63	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B[MAX_MPCC]; \
 64	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \
 65	uint32_t MPCC_MCM_3DLUT_FAST_LOAD_SELECT[MAX_MPCC]; \
 66	uint32_t MPCC_MCM_3DLUT_FAST_LOAD_STATUS[MAX_MPCC];
 67
 68#define MPC_COMMON_MASK_SH_LIST_DCN4_01(mask_sh) \
 69	MPC_COMMON_MASK_SH_LIST_DCN32(mask_sh), \
 70	SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, mask_sh), \
 71	SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE, mask_sh), \
 72	SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, mask_sh), \
 73	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C11_A, mask_sh), \
 74	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C12_A, mask_sh), \
 75	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C13_A, mask_sh), \
 76	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C14_A, mask_sh), \
 77	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C21_A, mask_sh), \
 78	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C22_A, mask_sh), \
 79	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C23_A, mask_sh), \
 80	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C24_A, mask_sh), \
 81	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C31_A, mask_sh), \
 82	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C32_A, mask_sh), \
 83	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C33_A, mask_sh), \
 84	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C34_A, mask_sh), \
 85	SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, mask_sh), \
 86	SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE, mask_sh), \
 87	SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT, mask_sh), \
 88	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C11_A, mask_sh), \
 89	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C12_A, mask_sh), \
 90	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C13_A, mask_sh), \
 91	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C14_A, mask_sh), \
 92	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C21_A, mask_sh), \
 93	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C22_A, mask_sh), \
 94	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C23_A, mask_sh), \
 95	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C24_A, mask_sh), \
 96	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C31_A, mask_sh), \
 97	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C32_A, mask_sh), \
 98	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C33_A, mask_sh), \
 99	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C34_A, mask_sh), \
100	SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM_3DLUT_FL_SEL, mask_sh), \
101	SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_DONE, mask_sh), \
102	SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW, mask_sh), \
103	SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW, mask_sh)
104
105
106#define MPC_REG_LIST_DCN4_01_RI(inst) \
107	MPC_REG_LIST_DCN3_2_RI(inst),\
108	SRII(MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst),\
109	SRII(MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM, inst),\
110	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst),\
111	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst),\
112	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst),\
113	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst),\
114	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst),\
115	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst),\
116	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst),\
117	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst),\
118	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B, MPCC_MCM, inst),\
119	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B, MPCC_MCM, inst),\
120	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B, MPCC_MCM, inst),\
121	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B, MPCC_MCM, inst),\
122	SRII(MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst), \
123	SRII(MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM, inst), \
124	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst), \
125	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst), \
126	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst), \
127	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst), \
128	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst), \
129	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst), \
130	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst), \
131	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst), \
132	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B, MPCC_MCM, inst), \
133	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B, MPCC_MCM, inst), \
134	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B, MPCC_MCM, inst), \
135	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B, MPCC_MCM, inst), \
136	SRII(MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM, inst),\
137	SRII(MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM, inst)
138
139#define MPC_REG_FIELD_LIST_DCN4_01(type)\
140	MPC_REG_FIELD_LIST_DCN3_0(type);\
141	MPC_REG_FIELD_LIST_DCN32(type);\
142	type MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT;\
143	type MPCC_MCM_FIRST_GAMUT_REMAP_MODE;\
144	type MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT;\
145	type MPCC_MCM_FIRST_GAMUT_REMAP_C11_A;\
146	type MPCC_MCM_FIRST_GAMUT_REMAP_C12_A;\
147	type MPCC_MCM_FIRST_GAMUT_REMAP_C13_A;\
148	type MPCC_MCM_FIRST_GAMUT_REMAP_C14_A;\
149	type MPCC_MCM_FIRST_GAMUT_REMAP_C21_A;\
150	type MPCC_MCM_FIRST_GAMUT_REMAP_C22_A;\
151	type MPCC_MCM_FIRST_GAMUT_REMAP_C23_A;\
152	type MPCC_MCM_FIRST_GAMUT_REMAP_C24_A;\
153	type MPCC_MCM_FIRST_GAMUT_REMAP_C31_A; \
154	type MPCC_MCM_FIRST_GAMUT_REMAP_C32_A; \
155	type MPCC_MCM_FIRST_GAMUT_REMAP_C33_A; \
156	type MPCC_MCM_FIRST_GAMUT_REMAP_C34_A; \
157	type MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT;\
158	type MPCC_MCM_SECOND_GAMUT_REMAP_MODE;\
159	type MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT;\
160	type MPCC_MCM_SECOND_GAMUT_REMAP_C11_A;\
161	type MPCC_MCM_SECOND_GAMUT_REMAP_C12_A;\
162	type MPCC_MCM_SECOND_GAMUT_REMAP_C13_A;\
163	type MPCC_MCM_SECOND_GAMUT_REMAP_C14_A;\
164	type MPCC_MCM_SECOND_GAMUT_REMAP_C21_A;\
165	type MPCC_MCM_SECOND_GAMUT_REMAP_C22_A;\
166	type MPCC_MCM_SECOND_GAMUT_REMAP_C23_A;\
167	type MPCC_MCM_SECOND_GAMUT_REMAP_C24_A;\
168	type MPCC_MCM_SECOND_GAMUT_REMAP_C31_A; \
169	type MPCC_MCM_SECOND_GAMUT_REMAP_C32_A; \
170	type MPCC_MCM_SECOND_GAMUT_REMAP_C33_A; \
171	type MPCC_MCM_SECOND_GAMUT_REMAP_C34_A; \
172	type MPCC_MCM_3DLUT_FL_SEL;\
173	type MPCC_MCM_3DLUT_FL_DONE;\
174	type MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW;\
175	type MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW
176
177struct dcn401_mpc_shift {
178	MPC_REG_FIELD_LIST_DCN4_01(uint8_t);
179};
180
181struct dcn401_mpc_mask {
182	MPC_REG_FIELD_LIST_DCN4_01(uint32_t);
183};
184
185struct dcn401_mpc_registers {
186	MPC_REG_VARIABLE_LIST_DCN4_01
187};
188
189struct dcn401_mpc {
190	struct mpc base;
191
192	int mpcc_in_use_mask;
193	int num_mpcc;
194	const struct dcn401_mpc_registers *mpc_regs;
195	const struct dcn401_mpc_shift *mpc_shift;
196	const struct dcn401_mpc_mask *mpc_mask;
197	int num_rmu;
198};
199void dcn401_mpc_construct(struct dcn401_mpc *mpc401,
200	struct dc_context *ctx,
201	const struct dcn401_mpc_registers *mpc_regs,
202	const struct dcn401_mpc_shift *mpc_shift,
203	const struct dcn401_mpc_mask *mpc_mask,
204	int num_mpcc,
205	int num_rmu);
206
207void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id);
208void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params,
209		bool lut_bank_a, int mpcc_id);
210
211void mpc401_program_lut_mode(
212		struct mpc *mpc,
213		const enum MCM_LUT_ID id,
214		const enum MCM_LUT_XABLE xable,
215		bool lut_bank_a,
216		int mpcc_id);
217
218void mpc401_program_lut_read_write_control(
219		struct mpc *mpc,
220		const enum MCM_LUT_ID id,
221		bool lut_bank_a,
222		int mpcc_id);
223
224void mpc401_set_gamut_remap(
225	struct mpc *mpc,
226	int mpcc_id,
227	const struct mpc_grph_gamut_adjustment *adjust);
228
229void mpc401_get_gamut_remap(
230	struct mpc *mpc,
231	int mpcc_id,
232	struct mpc_grph_gamut_adjustment *adjust);
233
234void mpc401_update_3dlut_fast_load_select(
235	struct mpc *mpc,
236	int mpcc_id,
237	int hubp_idx);
238
239void mpc_program_gamut_remap(
240	struct mpc *mpc,
241	unsigned int mpcc_id,
242	const uint16_t *regval,
243	enum mpcc_gamut_remap_id gamut_remap_block_id,
244	enum mpcc_gamut_remap_mode_select mode_select);
245
246void mpc_read_gamut_remap(struct mpc *mpc,
247	int mpcc_id,
248	uint16_t *regval,
249	enum mpcc_gamut_remap_id gamut_remap_block_id,
250	uint32_t *mode_select);
251
252void mpc401_update_3dlut_fast_load_select(
253	struct mpc *mpc,
254	int mpcc_id,
255	int hubp_idx);
256
257#endif