dcn32_mpc.c

   1/*
   2 * Copyright 2021 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "reg_helper.h"
  27#include "dcn30/dcn30_mpc.h"
  28#include "dcn30/dcn30_cm_common.h"
  29#include "dcn32_mpc.h"
  30#include "basics/conversion.h"
  31#include "dcn10/dcn10_cm_common.h"
  32#include "dc.h"
  33
  34#define REG(reg)\
  35	mpc30->mpc_regs->reg
  36
  37#define CTX \
  38	mpc30->base.ctx
  39
  40#undef FN
  41#define FN(reg_name, field_name) \
  42	mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
  43
  44
  45void mpc32_mpc_init(struct mpc *mpc)
  46{
  47	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
  48	int mpcc_id;
  49
  50	mpc3_mpc_init(mpc);
  51
  52	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
  53		if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) {
  54			for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) {
  55				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3);
  56				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3);
  57				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3);
  58			}
  59		}
  60		if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {
  61			for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++)
  62				REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);
  63		}
  64	}
  65}
  66
  67void mpc32_power_on_blnd_lut(
  68	struct mpc *mpc,
  69	uint32_t mpcc_id,
  70	bool power_on)
  71{
  72	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
  73
  74	REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, MPCC_MCM_1DLUT_MEM_PWR_DIS, power_on);
  75
  76	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {
  77		if (power_on) {
  78			REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
  79			REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
  80		} else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
  81			/* TODO: change to mpc
  82			 *  dpp_base->ctx->dc->optimized_required = true;
  83			 *  dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
  84			 */
  85		}
  86	} else {
  87		REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
  88				MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
  89	}
  90}
  91
  92static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)
  93{
  94	enum dc_lut_mode mode;
  95	uint32_t mode_current = 0;
  96	uint32_t in_use = 0;
  97
  98	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
  99
 100	REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
 101			MPCC_MCM_1DLUT_MODE_CURRENT, &mode_current);
 102	REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
 103			MPCC_MCM_1DLUT_SELECT_CURRENT, &in_use);
 104
 105	switch (mode_current) {
 106	case 0:
 107	case 1:
 108		mode = LUT_BYPASS;
 109		break;
 110
 111	case 2:
 112		if (in_use == 0)
 113			mode = LUT_RAM_A;
 114		else
 115			mode = LUT_RAM_B;
 116		break;
 117	default:
 118		mode = LUT_BYPASS;
 119		break;
 120	}
 121	return mode;
 122}
 123
 124void mpc32_configure_post1dlut(
 125		struct mpc *mpc,
 126		uint32_t mpcc_id,
 127		bool is_ram_a)
 128{
 129	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 130
 131	//TODO: this
 132	REG_UPDATE_2(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id],
 133			MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 7,
 134			MPCC_MCM_1DLUT_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
 135
 136	REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
 137}
 138
 139static void mpc32_post1dlut_get_reg_field(
 140		struct dcn30_mpc *mpc,
 141		struct dcn3_xfer_func_reg *reg)
 142{
 143	reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
 144	reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
 145	reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
 146	reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
 147	reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
 148	reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
 149	reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
 150	reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
 151
 152	reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
 153	reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
 154	reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
 155	reg->masks.field_region_end_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
 156	reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
 157	reg->masks.field_region_end_base = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
 158	reg->shifts.field_region_linear_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
 159	reg->masks.field_region_linear_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
 160	reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
 161	reg->masks.exp_region_start = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
 162	reg->shifts.exp_resion_start_segment = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
 163	reg->masks.exp_resion_start_segment = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
 164}
 165
 166/*program blnd lut RAM A*/
 167void mpc32_program_post1dluta_settings(
 168		struct mpc *mpc,
 169		uint32_t mpcc_id,
 170		const struct pwl_params *params)
 171{
 172	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 173	struct dcn3_xfer_func_reg gam_regs;
 174
 175	mpc32_post1dlut_get_reg_field(mpc30, &gam_regs);
 176
 177	gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]);
 178	gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_G[mpcc_id]);
 179	gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_R[mpcc_id]);
 180	gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
 181	gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
 182	gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
 183	gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[mpcc_id]);
 184	gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[mpcc_id]);
 185	gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G[mpcc_id]);
 186	gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G[mpcc_id]);
 187	gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R[mpcc_id]);
 188	gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R[mpcc_id]);
 189	gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMA_REGION_0_1[mpcc_id]);
 190	gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMA_REGION_32_33[mpcc_id]);
 191
 192	cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
 193}
 194
 195/*program blnd lut RAM B*/
 196void mpc32_program_post1dlutb_settings(
 197		struct mpc *mpc,
 198		uint32_t mpcc_id,
 199		const struct pwl_params *params)
 200{
 201	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 202	struct dcn3_xfer_func_reg gam_regs;
 203
 204	mpc32_post1dlut_get_reg_field(mpc30, &gam_regs);
 205
 206	gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_B[mpcc_id]);
 207	gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_G[mpcc_id]);
 208	gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_R[mpcc_id]);
 209	gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B[mpcc_id]);
 210	gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G[mpcc_id]);
 211	gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R[mpcc_id]);
 212	gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B[mpcc_id]);
 213	gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B[mpcc_id]);
 214	gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G[mpcc_id]);
 215	gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G[mpcc_id]);
 216	gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R[mpcc_id]);
 217	gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R[mpcc_id]);
 218	gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMB_REGION_0_1[mpcc_id]);
 219	gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMB_REGION_32_33[mpcc_id]);
 220
 221	cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
 222}
 223
 224void mpc32_program_post1dlut_pwl(
 225		struct mpc *mpc,
 226		uint32_t mpcc_id,
 227		const struct pwl_result_data *rgb,
 228		uint32_t num)
 229{
 230	uint32_t i;
 231	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 232	uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
 233	uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
 234	uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
 235
 236	if (is_rgb_equal(rgb, num)) {
 237		for (i = 0 ; i < num; i++)
 238			REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
 239		REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
 240	} else {
 241		REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
 242		REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 4);
 243		for (i = 0 ; i < num; i++)
 244			REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
 245		REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
 246
 247		REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
 248		REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 2);
 249		for (i = 0 ; i < num; i++)
 250			REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].green_reg);
 251		REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_green);
 252
 253		REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
 254		REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 1);
 255		for (i = 0 ; i < num; i++)
 256			REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].blue_reg);
 257		REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_blue);
 258	}
 259}
 260
 261bool mpc32_program_post1dlut(
 262		struct mpc *mpc,
 263		const struct pwl_params *params,
 264		uint32_t mpcc_id)
 265{
 266	enum dc_lut_mode current_mode;
 267	enum dc_lut_mode next_mode;
 268	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 269
 270	if (params == NULL) {
 271		REG_SET(MPCC_MCM_1DLUT_CONTROL[mpcc_id], 0, MPCC_MCM_1DLUT_MODE, 0);
 272		if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm)
 273			mpc32_power_on_blnd_lut(mpc, mpcc_id, false);
 274		return false;
 275	}
 276
 277	current_mode = mpc32_get_post1dlut_current(mpc, mpcc_id);
 278	if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
 279		next_mode = LUT_RAM_A;
 280	else
 281		next_mode = LUT_RAM_B;
 282
 283	mpc32_power_on_blnd_lut(mpc, mpcc_id, true);
 284	mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);
 285
 286	if (next_mode == LUT_RAM_A)
 287		mpc32_program_post1dluta_settings(mpc, mpcc_id, params);
 288	else
 289		mpc32_program_post1dlutb_settings(mpc, mpcc_id, params);
 290
 291	mpc32_program_post1dlut_pwl(
 292			mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);
 293
 294	REG_UPDATE_2(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
 295			MPCC_MCM_1DLUT_MODE, 2,
 296			MPCC_MCM_1DLUT_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
 297
 298	return true;
 299}
 300
 301static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id)
 302{
 303	enum dc_lut_mode mode;
 304	uint32_t state_mode;
 305	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 306
 307	REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
 308
 309	switch (state_mode) {
 310	case 0:
 311		mode = LUT_BYPASS;
 312		break;
 313	case 1:
 314		mode = LUT_RAM_A;
 315		break;
 316	case 2:
 317		mode = LUT_RAM_B;
 318		break;
 319	default:
 320		mode = LUT_BYPASS;
 321		break;
 322	}
 323
 324	return mode;
 325}
 326
 327
 328void mpc32_configure_shaper_lut(
 329		struct mpc *mpc,
 330		bool is_ram_a,
 331		uint32_t mpcc_id)
 332{
 333	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 334
 335	REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
 336			MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7);
 337	REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
 338			MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
 339	REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0);
 340}
 341
 342
 343void mpc32_program_shaper_luta_settings(
 344		struct mpc *mpc,
 345		const struct pwl_params *params,
 346		uint32_t mpcc_id)
 347{
 348	const struct gamma_curve *curve;
 349	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 350
 351	REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0,
 352		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
 353		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 354	REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0,
 355			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
 356			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 357	REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0,
 358			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
 359			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 360
 361	REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0,
 362			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
 363			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
 364	REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0,
 365			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
 366			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
 367	REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0,
 368			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
 369			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
 370
 371	curve = params->arr_curve_points;
 372	if (curve) {
 373		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0,
 374			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 375			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 376			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 377			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 378
 379		curve += 2;
 380		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0,
 381			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 382			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 383			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 384			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 385
 386		curve += 2;
 387		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0,
 388			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 389			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 390			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 391			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 392
 393		curve += 2;
 394		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0,
 395			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 396			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 397			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 398			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 399
 400		curve += 2;
 401		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0,
 402			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 403			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 404			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 405			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 406
 407		curve += 2;
 408		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0,
 409			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 410			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 411			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 412			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 413
 414		curve += 2;
 415		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0,
 416			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 417			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 418			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 419			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 420
 421		curve += 2;
 422		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0,
 423			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 424			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 425			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 426			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 427
 428
 429		curve += 2;
 430		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0,
 431			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 432			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 433			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 434			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 435
 436		curve += 2;
 437		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0,
 438			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 439			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 440			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 441			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 442
 443		curve += 2;
 444		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0,
 445			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 446			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 447			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 448			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 449
 450		curve += 2;
 451		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0,
 452			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 453			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 454			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 455			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 456
 457		curve += 2;
 458		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0,
 459			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 460			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 461			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 462			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 463
 464		curve += 2;
 465		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0,
 466				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 467				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 468				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 469				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 470
 471		curve += 2;
 472		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0,
 473			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 474			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 475			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 476			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 477
 478		curve += 2;
 479		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0,
 480			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 481			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 482			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 483			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 484
 485		curve += 2;
 486		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0,
 487			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 488			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 489			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 490			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 491	}
 492}
 493
 494
 495void mpc32_program_shaper_lutb_settings(
 496		struct mpc *mpc,
 497		const struct pwl_params *params,
 498		uint32_t mpcc_id)
 499{
 500	const struct gamma_curve *curve;
 501	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 502
 503	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,
 504		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
 505		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 506	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,
 507			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
 508			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 509	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,
 510			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
 511			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 512
 513	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,
 514			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
 515			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
 516	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,
 517			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
 518			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
 519	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,
 520			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
 521			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
 522
 523	curve = params->arr_curve_points;
 524	if (curve) {
 525		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0,
 526			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 527			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 528			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 529			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 530
 531		curve += 2;
 532		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0,
 533				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 534				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 535				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 536				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 537
 538
 539		curve += 2;
 540		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0,
 541				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 542				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 543				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 544				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 545
 546		curve += 2;
 547		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0,
 548				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 549				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 550				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 551				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 552
 553		curve += 2;
 554		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0,
 555			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 556			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 557			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 558			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 559
 560		curve += 2;
 561		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0,
 562				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 563				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 564				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 565				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 566
 567		curve += 2;
 568		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0,
 569				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 570				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 571				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 572				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 573
 574		curve += 2;
 575		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0,
 576				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 577				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 578				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 579				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 580
 581
 582		curve += 2;
 583		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0,
 584				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 585				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 586				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 587				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 588
 589		curve += 2;
 590		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0,
 591				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 592				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 593				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 594				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 595
 596		curve += 2;
 597		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0,
 598				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 599				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 600				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 601				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 602
 603		curve += 2;
 604		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0,
 605				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 606				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 607				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 608				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 609
 610		curve += 2;
 611		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0,
 612				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 613				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 614				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 615				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 616
 617		curve += 2;
 618		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0,
 619				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 620				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 621				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 622				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 623
 624		curve += 2;
 625		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0,
 626				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 627				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 628				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 629				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 630
 631		curve += 2;
 632		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0,
 633				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 634				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 635				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 636				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 637
 638		curve += 2;
 639		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0,
 640				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 641				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 642				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 643				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 644	}
 645}
 646
 647
 648void mpc32_program_shaper_lut(
 649		struct mpc *mpc,
 650		const struct pwl_result_data *rgb,
 651		uint32_t num,
 652		uint32_t mpcc_id)
 653{
 654	uint32_t i, red, green, blue;
 655	uint32_t  red_delta, green_delta, blue_delta;
 656	uint32_t  red_value, green_value, blue_value;
 657
 658	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 659
 660	for (i = 0 ; i < num; i++) {
 661
 662		red   = rgb[i].red_reg;
 663		green = rgb[i].green_reg;
 664		blue  = rgb[i].blue_reg;
 665
 666		red_delta   = rgb[i].delta_red_reg;
 667		green_delta = rgb[i].delta_green_reg;
 668		blue_delta  = rgb[i].delta_blue_reg;
 669
 670		red_value   = ((red_delta   & 0x3ff) << 14) | (red   & 0x3fff);
 671		green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
 672		blue_value  = ((blue_delta  & 0x3ff) << 14) | (blue  & 0x3fff);
 673
 674		REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, red_value);
 675		REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, green_value);
 676		REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, blue_value);
 677	}
 678
 679}
 680
 681
 682void mpc32_power_on_shaper_3dlut(
 683		struct mpc *mpc,
 684		uint32_t mpcc_id,
 685		bool power_on)
 686{
 687	uint32_t power_status_shaper = 2;
 688	uint32_t power_status_3dlut  = 2;
 689	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 690	int max_retries = 10;
 691
 692	REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
 693	MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0);
 694	/* wait for memory to fully power up */
 695	if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
 696		REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
 697		REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
 698	}
 699
 700	/*read status is not mandatory, it is just for debugging*/
 701	REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper);
 702	REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
 703
 704	if (power_status_shaper != 0 && power_on == true)
 705		BREAK_TO_DEBUGGER();
 706
 707	if (power_status_3dlut != 0 && power_on == true)
 708		BREAK_TO_DEBUGGER();
 709}
 710
 711
 712bool mpc32_program_shaper(
 713		struct mpc *mpc,
 714		const struct pwl_params *params,
 715		uint32_t mpcc_id)
 716{
 717	enum dc_lut_mode current_mode;
 718	enum dc_lut_mode next_mode;
 719
 720	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 721
 722	if (params == NULL) {
 723		REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0);
 724		return false;
 725	}
 726
 727	mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
 728
 729	current_mode = mpc32_get_shaper_current(mpc, mpcc_id);
 730
 731	if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
 732		next_mode = LUT_RAM_B;
 733	else
 734		next_mode = LUT_RAM_A;
 735
 736	mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);
 737
 738	if (next_mode == LUT_RAM_A)
 739		mpc32_program_shaper_luta_settings(mpc, params, mpcc_id);
 740	else
 741		mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id);
 742
 743	mpc32_program_shaper_lut(
 744			mpc, params->rgb_resulted, params->hw_points_num, mpcc_id);
 745
 746	REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
 747	mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
 748
 749	return true;
 750}
 751
 752
 753static enum dc_lut_mode get3dlut_config(
 754			struct mpc *mpc,
 755			bool *is_17x17x17,
 756			bool *is_12bits_color_channel,
 757			int mpcc_id)
 758{
 759	uint32_t i_mode, i_enable_10bits, lut_size;
 760	enum dc_lut_mode mode;
 761	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 762
 763	REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id],
 764			MPCC_MCM_3DLUT_MODE_CURRENT,  &i_mode);
 765
 766	REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
 767			MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits);
 768
 769	switch (i_mode) {
 770	case 0:
 771		mode = LUT_BYPASS;
 772		break;
 773	case 1:
 774		mode = LUT_RAM_A;
 775		break;
 776	case 2:
 777		mode = LUT_RAM_B;
 778		break;
 779	default:
 780		mode = LUT_BYPASS;
 781		break;
 782	}
 783	if (i_enable_10bits > 0)
 784		*is_12bits_color_channel = false;
 785	else
 786		*is_12bits_color_channel = true;
 787
 788	REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size);
 789
 790	if (lut_size == 0)
 791		*is_17x17x17 = true;
 792	else
 793		*is_17x17x17 = false;
 794
 795	return mode;
 796}
 797
 798
 799void mpc32_select_3dlut_ram(
 800		struct mpc *mpc,
 801		enum dc_lut_mode mode,
 802		bool is_color_channel_12bits,
 803		uint32_t mpcc_id)
 804{
 805	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 806
 807	REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
 808		MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
 809		MPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1);
 810}
 811
 812
 813void mpc32_select_3dlut_ram_mask(
 814		struct mpc *mpc,
 815		uint32_t ram_selection_mask,
 816		uint32_t mpcc_id)
 817{
 818	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 819
 820	REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK,
 821			ram_selection_mask);
 822	REG_SET(MPCC_MCM_3DLUT_INDEX[mpcc_id], 0, MPCC_MCM_3DLUT_INDEX, 0);
 823}
 824
 825
 826void mpc32_set3dlut_ram12(
 827		struct mpc *mpc,
 828		const struct dc_rgb *lut,
 829		uint32_t entries,
 830		uint32_t mpcc_id)
 831{
 832	uint32_t i, red, green, blue, red1, green1, blue1;
 833	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 834
 835	for (i = 0 ; i < entries; i += 2) {
 836		red   = lut[i].red<<4;
 837		green = lut[i].green<<4;
 838		blue  = lut[i].blue<<4;
 839		red1   = lut[i+1].red<<4;
 840		green1 = lut[i+1].green<<4;
 841		blue1  = lut[i+1].blue<<4;
 842
 843		REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
 844				MPCC_MCM_3DLUT_DATA0, red,
 845				MPCC_MCM_3DLUT_DATA1, red1);
 846
 847		REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
 848				MPCC_MCM_3DLUT_DATA0, green,
 849				MPCC_MCM_3DLUT_DATA1, green1);
 850
 851		REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
 852				MPCC_MCM_3DLUT_DATA0, blue,
 853				MPCC_MCM_3DLUT_DATA1, blue1);
 854	}
 855}
 856
 857
 858void mpc32_set3dlut_ram10(
 859		struct mpc *mpc,
 860		const struct dc_rgb *lut,
 861		uint32_t entries,
 862		uint32_t mpcc_id)
 863{
 864	uint32_t i, red, green, blue, value;
 865	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 866
 867	for (i = 0; i < entries; i++) {
 868		red   = lut[i].red;
 869		green = lut[i].green;
 870		blue  = lut[i].blue;
 871		//should we shift red 22bit and green 12?
 872		value = (red<<20) | (green<<10) | blue;
 873
 874		REG_SET(MPCC_MCM_3DLUT_DATA_30BIT[mpcc_id], 0, MPCC_MCM_3DLUT_DATA_30BIT, value);
 875	}
 876
 877}
 878
 879
 880void mpc32_set_3dlut_mode(
 881		struct mpc *mpc,
 882		enum dc_lut_mode mode,
 883		bool is_color_channel_12bits,
 884		bool is_lut_size17x17x17,
 885		uint32_t mpcc_id)
 886{
 887	uint32_t lut_mode;
 888	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 889
 890	// set default 3DLUT to pre-blend
 891	// TODO: implement movable CM location
 892	REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id], MPCC_MOVABLE_CM_LOCATION_CNTL, 0);
 893
 894	if (mode == LUT_BYPASS)
 895		lut_mode = 0;
 896	else if (mode == LUT_RAM_A)
 897		lut_mode = 1;
 898	else
 899		lut_mode = 2;
 900
 901	REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id],
 902			MPCC_MCM_3DLUT_MODE, lut_mode,
 903			MPCC_MCM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
 904}
 905
 906
 907bool mpc32_program_3dlut(
 908		struct mpc *mpc,
 909		const struct tetrahedral_params *params,
 910		int mpcc_id)
 911{
 912	enum dc_lut_mode mode;
 913	bool is_17x17x17;
 914	bool is_12bits_color_channel;
 915	const struct dc_rgb *lut0;
 916	const struct dc_rgb *lut1;
 917	const struct dc_rgb *lut2;
 918	const struct dc_rgb *lut3;
 919	int lut_size0;
 920	int lut_size;
 921
 922	if (params == NULL) {
 923		mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id);
 924		return false;
 925	}
 926	mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
 927
 928	mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id);
 929
 930	if (mode == LUT_BYPASS || mode == LUT_RAM_B)
 931		mode = LUT_RAM_A;
 932	else
 933		mode = LUT_RAM_B;
 934
 935	is_17x17x17 = !params->use_tetrahedral_9;
 936	is_12bits_color_channel = params->use_12bits;
 937	if (is_17x17x17) {
 938		lut0 = params->tetrahedral_17.lut0;
 939		lut1 = params->tetrahedral_17.lut1;
 940		lut2 = params->tetrahedral_17.lut2;
 941		lut3 = params->tetrahedral_17.lut3;
 942		lut_size0 = sizeof(params->tetrahedral_17.lut0)/
 943					sizeof(params->tetrahedral_17.lut0[0]);
 944		lut_size  = sizeof(params->tetrahedral_17.lut1)/
 945					sizeof(params->tetrahedral_17.lut1[0]);
 946	} else {
 947		lut0 = params->tetrahedral_9.lut0;
 948		lut1 = params->tetrahedral_9.lut1;
 949		lut2 = params->tetrahedral_9.lut2;
 950		lut3 = params->tetrahedral_9.lut3;
 951		lut_size0 = sizeof(params->tetrahedral_9.lut0)/
 952				sizeof(params->tetrahedral_9.lut0[0]);
 953		lut_size  = sizeof(params->tetrahedral_9.lut1)/
 954				sizeof(params->tetrahedral_9.lut1[0]);
 955		}
 956
 957	mpc32_select_3dlut_ram(mpc, mode,
 958				is_12bits_color_channel, mpcc_id);
 959	mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);
 960	if (is_12bits_color_channel)
 961		mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);
 962	else
 963		mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);
 964
 965	mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);
 966	if (is_12bits_color_channel)
 967		mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);
 968	else
 969		mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);
 970
 971	mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);
 972	if (is_12bits_color_channel)
 973		mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);
 974	else
 975		mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);
 976
 977	mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);
 978	if (is_12bits_color_channel)
 979		mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);
 980	else
 981		mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);
 982
 983	mpc32_set_3dlut_mode(mpc, mode, is_12bits_color_channel,
 984					is_17x17x17, mpcc_id);
 985
 986	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
 987		mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
 988
 989	return true;
 990}
 991
 992static const struct mpc_funcs dcn32_mpc_funcs = {
 993	.read_mpcc_state = mpc1_read_mpcc_state,
 994	.insert_plane = mpc1_insert_plane,
 995	.remove_mpcc = mpc1_remove_mpcc,
 996	.mpc_init = mpc32_mpc_init,
 997	.mpc_init_single_inst = mpc3_mpc_init_single_inst,
 998	.update_blending = mpc2_update_blending,
 999	.cursor_lock = mpc1_cursor_lock,
1000	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
1001	.wait_for_idle = mpc2_assert_idle_mpcc,
1002	.assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
1003	.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
1004	.set_denorm =  mpc3_set_denorm,
1005	.set_denorm_clamp = mpc3_set_denorm_clamp,
1006	.set_output_csc = mpc3_set_output_csc,
1007	.set_ocsc_default = mpc3_set_ocsc_default,
1008	.set_output_gamma = mpc3_set_output_gamma,
1009	.insert_plane_to_secondary = NULL,
1010	.remove_mpcc_from_secondary =  NULL,
1011	.set_dwb_mux = mpc3_set_dwb_mux,
1012	.disable_dwb_mux = mpc3_disable_dwb_mux,
1013	.is_dwb_idle = mpc3_is_dwb_idle,
1014	.set_gamut_remap = mpc3_set_gamut_remap,
1015	.program_shaper = mpc32_program_shaper,
1016	.program_3dlut = mpc32_program_3dlut,
1017	.program_1dlut = mpc32_program_post1dlut,
1018	.acquire_rmu = NULL,
1019	.release_rmu = NULL,
1020	.power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
1021	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
1022	.mpc_read_reg_state = mpc3_read_reg_state,
1023	.set_bg_color = mpc1_set_bg_color,
1024};
1025
1026
1027void dcn32_mpc_construct(struct dcn30_mpc *mpc30,
1028	struct dc_context *ctx,
1029	const struct dcn30_mpc_registers *mpc_regs,
1030	const struct dcn30_mpc_shift *mpc_shift,
1031	const struct dcn30_mpc_mask *mpc_mask,
1032	int num_mpcc,
1033	int num_rmu)
1034{
1035	int i;
1036
1037	mpc30->base.ctx = ctx;
1038
1039	mpc30->base.funcs = &dcn32_mpc_funcs;
1040
1041	mpc30->mpc_regs = mpc_regs;
1042	mpc30->mpc_shift = mpc_shift;
1043	mpc30->mpc_mask = mpc_mask;
1044
1045	mpc30->mpcc_in_use_mask = 0;
1046	mpc30->num_mpcc = num_mpcc;
1047	mpc30->num_rmu = num_rmu;
1048
1049	for (i = 0; i < MAX_MPCC; i++)
1050		mpc3_init_mpcc(&mpc30->base.mpcc_array[i], i);
1051}