dcn10_mpc.c

  1/*
  2 * Copyright 2012-15 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "reg_helper.h"
 27#include "dcn10_mpc.h"
 28
 29#define REG(reg)\
 30	mpc10->mpc_regs->reg
 31
 32#define CTX \
 33	mpc10->base.ctx
 34
 35#undef FN
 36#define FN(reg_name, field_name) \
 37	mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
 38
 39
 40void mpc1_set_bg_color(struct mpc *mpc,
 41		struct tg_color *bg_color,
 42		int mpcc_id)
 43{
 44	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
 45	struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
 46	uint32_t bg_r_cr, bg_g_y, bg_b_cb;
 47
 48	bottommost_mpcc->blnd_cfg.black_color = *bg_color;
 49
 50	/* find bottommost mpcc. */
 51	while (bottommost_mpcc->mpcc_bot) {
 52		/* avoid circular linked link */
 53		ASSERT(bottommost_mpcc != bottommost_mpcc->mpcc_bot);
 54		if (bottommost_mpcc == bottommost_mpcc->mpcc_bot)
 55			break;
 56
 57		bottommost_mpcc = bottommost_mpcc->mpcc_bot;
 58	}
 59
 60	/* mpc color is 12 bit.  tg_color is 10 bit */
 61	/* todo: might want to use 16 bit to represent color and have each
 62	 * hw block translate to correct color depth.
 63	 */
 64	bg_r_cr = bg_color->color_r_cr << 2;
 65	bg_g_y = bg_color->color_g_y << 2;
 66	bg_b_cb = bg_color->color_b_cb << 2;
 67
 68	REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0,
 69			MPCC_BG_R_CR, bg_r_cr);
 70	REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0,
 71			MPCC_BG_G_Y, bg_g_y);
 72	REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,
 73			MPCC_BG_B_CB, bg_b_cb);
 74}
 75
 76static void mpc1_update_blending(
 77	struct mpc *mpc,
 78	struct mpcc_blnd_cfg *blnd_cfg,
 79	int mpcc_id)
 80{
 81	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
 82	struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
 83
 84	REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
 85			MPCC_ALPHA_BLND_MODE,		blnd_cfg->alpha_mode,
 86			MPCC_ALPHA_MULTIPLIED_MODE,	blnd_cfg->pre_multiplied_alpha,
 87			MPCC_BLND_ACTIVE_OVERLAP_ONLY,	blnd_cfg->overlap_only,
 88			MPCC_GLOBAL_ALPHA,		blnd_cfg->global_alpha,
 89			MPCC_GLOBAL_GAIN,		blnd_cfg->global_gain);
 90
 91	mpcc->blnd_cfg = *blnd_cfg;
 92}
 93
 94void mpc1_update_stereo_mix(
 95	struct mpc *mpc,
 96	struct mpcc_sm_cfg *sm_cfg,
 97	int mpcc_id)
 98{
 99	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
100
101	REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id],
102			MPCC_SM_EN,			sm_cfg->enable,
103			MPCC_SM_MODE,			sm_cfg->sm_mode,
104			MPCC_SM_FRAME_ALT,		sm_cfg->frame_alt,
105			MPCC_SM_FIELD_ALT,		sm_cfg->field_alt,
106			MPCC_SM_FORCE_NEXT_FRAME_POL,	sm_cfg->force_next_frame_porlarity,
107			MPCC_SM_FORCE_NEXT_TOP_POL,	sm_cfg->force_next_field_polarity);
108}
109void mpc1_assert_idle_mpcc(struct mpc *mpc, int id)
110{
111	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
112
113	ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));
114	REG_WAIT(MPCC_STATUS[id],
115			MPCC_IDLE, 1,
116			1, 100000);
117}
118
119struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)
120{
121	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
122
123	ASSERT(mpcc_id < mpc10->num_mpcc);
124	return &(mpc->mpcc_array[mpcc_id]);
125}
126
127struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
128{
129	struct mpcc *tmp_mpcc = tree->opp_list;
130
131	while (tmp_mpcc != NULL) {
132		if (tmp_mpcc->dpp_id == dpp_id)
133			return tmp_mpcc;
134
135		/* avoid circular linked list */
136		ASSERT(tmp_mpcc != tmp_mpcc->mpcc_bot);
137		if (tmp_mpcc == tmp_mpcc->mpcc_bot)
138			break;
139
140		tmp_mpcc = tmp_mpcc->mpcc_bot;
141	}
142	return NULL;
143}
144
145void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
146{
147	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
148	unsigned int top_sel, mpc_busy, mpc_idle;
149
150	REG_GET(MPCC_TOP_SEL[mpcc_id],
151			MPCC_TOP_SEL, &top_sel);
152
153	if (top_sel == 0xf) {
154		REG_GET_2(MPCC_STATUS[mpcc_id],
155				MPCC_BUSY, &mpc_busy,
156				MPCC_IDLE, &mpc_idle);
157
158		ASSERT(mpc_busy == 0);
159		ASSERT(mpc_idle == 1);
160	}
161}
162
163/*
164 * Insert DPP into MPC tree based on specified blending position.
165 * Only used for planes that are part of blending chain for OPP output
166 *
167 * Parameters:
168 * [in/out] mpc		- MPC context.
169 * [in/out] tree	- MPC tree structure that plane will be added to.
170 * [in]	blnd_cfg	- MPCC blending configuration for the new blending layer.
171 * [in]	sm_cfg		- MPCC stereo mix configuration for the new blending layer.
172 *			  stereo mix must disable for the very bottom layer of the tree config.
173 * [in]	insert_above_mpcc - Insert new plane above this MPCC.  If NULL, insert as bottom plane.
174 * [in]	dpp_id		- DPP instance for the plane to be added.
175 * [in]	mpcc_id		- The MPCC physical instance to use for blending.
176 *
177 * Return:  struct mpcc* - MPCC that was added.
178 */
179struct mpcc *mpc1_insert_plane(
180	struct mpc *mpc,
181	struct mpc_tree *tree,
182	struct mpcc_blnd_cfg *blnd_cfg,
183	struct mpcc_sm_cfg *sm_cfg,
184	struct mpcc *insert_above_mpcc,
185	int dpp_id,
186	int mpcc_id)
187{
188	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
189	struct mpcc *new_mpcc = NULL;
190
191	/* sanity check parameters */
192	ASSERT(mpcc_id < mpc10->num_mpcc);
193	ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));
194
195	if (insert_above_mpcc) {
196		/* check insert_above_mpcc exist in tree->opp_list */
197		struct mpcc *temp_mpcc = tree->opp_list;
198
199		if (temp_mpcc != insert_above_mpcc)
200			while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
201				temp_mpcc = temp_mpcc->mpcc_bot;
202		if (temp_mpcc == NULL)
203			return NULL;
204	}
205
206	/* Get and update MPCC struct parameters */
207	new_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
208	new_mpcc->dpp_id = dpp_id;
209
210	/* program mux and MPCC_MODE */
211	if (insert_above_mpcc) {
212		new_mpcc->mpcc_bot = insert_above_mpcc;
213		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id);
214		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
215	} else {
216		new_mpcc->mpcc_bot = NULL;
217		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
218		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);
219	}
220	REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
221	REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
222
223	/* Configure VUPDATE lock set for this MPCC to map to the OPP */
224	REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id);
225
226	/* update mpc tree mux setting */
227	if (tree->opp_list == insert_above_mpcc) {
228		/* insert the toppest mpcc */
229		tree->opp_list = new_mpcc;
230		REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);
231	} else {
232		/* find insert position */
233		struct mpcc *temp_mpcc = tree->opp_list;
234
235		while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
236			temp_mpcc = temp_mpcc->mpcc_bot;
237		if (temp_mpcc && temp_mpcc->mpcc_bot == insert_above_mpcc) {
238			REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id);
239			temp_mpcc->mpcc_bot = new_mpcc;
240			if (!insert_above_mpcc)
241				REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
242						MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
243		}
244	}
245
246	/* update the blending configuration */
247	mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
248
249	/* update the stereo mix settings, if provided */
250	if (sm_cfg != NULL) {
251		new_mpcc->sm_cfg = *sm_cfg;
252		mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id);
253	}
254
255	/* mark this mpcc as in use */
256	mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
257
258	return new_mpcc;
259}
260
261/*
262 * Remove a specified MPCC from the MPC tree.
263 *
264 * Parameters:
265 * [in/out] mpc		- MPC context.
266 * [in/out] tree	- MPC tree structure that plane will be removed from.
267 * [in/out] mpcc	- MPCC to be removed from tree.
268 *
269 * Return:  void
270 */
271void mpc1_remove_mpcc(
272	struct mpc *mpc,
273	struct mpc_tree *tree,
274	struct mpcc *mpcc_to_remove)
275{
276	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
277	bool found = false;
278	int mpcc_id = mpcc_to_remove->mpcc_id;
279
280	if (tree->opp_list == mpcc_to_remove) {
281		found = true;
282		/* remove MPCC from top of tree */
283		if (mpcc_to_remove->mpcc_bot) {
284			/* set the next MPCC in list to be the top MPCC */
285			tree->opp_list = mpcc_to_remove->mpcc_bot;
286			REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id);
287		} else {
288			/* there are no other MPCC is list */
289			tree->opp_list = NULL;
290			REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);
291		}
292	} else {
293		/* find mpcc to remove MPCC list */
294		struct mpcc *temp_mpcc = tree->opp_list;
295
296		while (temp_mpcc && temp_mpcc->mpcc_bot != mpcc_to_remove)
297			temp_mpcc = temp_mpcc->mpcc_bot;
298
299		if (temp_mpcc && temp_mpcc->mpcc_bot == mpcc_to_remove) {
300			found = true;
301			temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot;
302			if (mpcc_to_remove->mpcc_bot) {
303				/* remove MPCC in middle of list */
304				REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
305						MPCC_BOT_SEL, mpcc_to_remove->mpcc_bot->mpcc_id);
306			} else {
307				/* remove MPCC from bottom of list */
308				REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
309						MPCC_BOT_SEL, 0xf);
310				REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
311						MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);
312			}
313		}
314	}
315
316	if (found) {
317		/* turn off MPCC mux registers */
318		REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
319		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
320		REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
321		REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
322
323		/* mark this mpcc as not in use */
324		mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
325		mpcc_to_remove->dpp_id = 0xf;
326		mpcc_to_remove->mpcc_bot = NULL;
327	} else {
328		/* In case of resume from S3/S4, remove mpcc from bios left over */
329		REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
330		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
331		REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
332		REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
333	}
334}
335
336static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
337{
338	mpcc->mpcc_id = mpcc_inst;
339	mpcc->dpp_id = 0xf;
340	mpcc->mpcc_bot = NULL;
341	mpcc->blnd_cfg.overlap_only = false;
342	mpcc->blnd_cfg.global_alpha = 0xff;
343	mpcc->blnd_cfg.global_gain = 0xff;
344	mpcc->sm_cfg.enable = false;
345}
346
347/*
348 * Reset the MPCC HW status by disconnecting all muxes.
349 *
350 * Parameters:
351 * [in/out] mpc		- MPC context.
352 *
353 * Return:  void
354 */
355void mpc1_mpc_init(struct mpc *mpc)
356{
357	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
358	int mpcc_id;
359	int opp_id;
360
361	mpc10->mpcc_in_use_mask = 0;
362	for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
363		REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
364		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
365		REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
366		REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
367
368		mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
369	}
370
371	for (opp_id = 0; opp_id < MAX_OPP; opp_id++) {
372		if (REG(MUX[opp_id]))
373			REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
374	}
375}
376
377void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)
378{
379	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
380	int opp_id;
381
382	REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
383
384	REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
385	REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
386	REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
387	REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
388
389	mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
390
391	if (opp_id < MAX_OPP && REG(MUX[opp_id]))
392		REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
393}
394
395
396void mpc1_init_mpcc_list_from_hw(
397	struct mpc *mpc,
398	struct mpc_tree *tree)
399{
400	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
401	unsigned int opp_id;
402	unsigned int top_sel;
403	unsigned int bot_sel;
404	unsigned int out_mux;
405	struct mpcc *mpcc;
406	int mpcc_id;
407	int bot_mpcc_id;
408
409	REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux);
410
411	if (out_mux != 0xf) {
412		for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
413			REG_GET(MPCC_OPP_ID[mpcc_id],  MPCC_OPP_ID,  &opp_id);
414			REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
415			REG_GET(MPCC_BOT_SEL[mpcc_id],  MPCC_BOT_SEL, &bot_sel);
416
417			if (bot_sel == mpcc_id)
418				bot_sel = 0xf;
419
420			if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
421				mpcc = mpc1_get_mpcc(mpc, mpcc_id);
422				mpcc->dpp_id = top_sel;
423				mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
424
425				if (out_mux == mpcc_id)
426					tree->opp_list = mpcc;
427				if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) {
428					bot_mpcc_id = bot_sel;
429					REG_GET(MPCC_OPP_ID[bot_mpcc_id],  MPCC_OPP_ID,  &opp_id);
430					REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel);
431					if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
432						struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);
433
434						mpcc->mpcc_bot = mpcc_bottom;
435					}
436				}
437			}
438		}
439	}
440}
441
442void mpc1_read_mpcc_state(
443		struct mpc *mpc,
444		int mpcc_inst,
445		struct mpcc_state *s)
446{
447	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
448
449	REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
450	REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
451	REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
452	REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
453			MPCC_ALPHA_BLND_MODE, &s->alpha_mode,
454			MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,
455			MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only);
456	REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
457			MPCC_BUSY, &s->busy);
458}
459
460void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
461{
462	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
463
464	REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0);
465}
466
467unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)
468{
469	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
470	uint32_t val = 0xf;
471
472	if (opp_id < MAX_OPP && REG(MUX[opp_id]))
473		REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);
474
475	return val;
476}
477
478static const struct mpc_funcs dcn10_mpc_funcs = {
479	.read_mpcc_state = mpc1_read_mpcc_state,
480	.insert_plane = mpc1_insert_plane,
481	.remove_mpcc = mpc1_remove_mpcc,
482	.mpc_init = mpc1_mpc_init,
483	.mpc_init_single_inst = mpc1_mpc_init_single_inst,
484	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
485	.wait_for_idle = mpc1_assert_idle_mpcc,
486	.assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
487	.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
488	.update_blending = mpc1_update_blending,
489	.cursor_lock = mpc1_cursor_lock,
490	.set_denorm = NULL,
491	.set_denorm_clamp = NULL,
492	.set_output_csc = NULL,
493	.set_output_gamma = NULL,
494	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
495	.set_bg_color = mpc1_set_bg_color,
496};
497
498void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
499	struct dc_context *ctx,
500	const struct dcn_mpc_registers *mpc_regs,
501	const struct dcn_mpc_shift *mpc_shift,
502	const struct dcn_mpc_mask *mpc_mask,
503	int num_mpcc)
504{
505	int i;
506
507	mpc10->base.ctx = ctx;
508
509	mpc10->base.funcs = &dcn10_mpc_funcs;
510
511	mpc10->mpc_regs = mpc_regs;
512	mpc10->mpc_shift = mpc_shift;
513	mpc10->mpc_mask = mpc_mask;
514
515	mpc10->mpcc_in_use_mask = 0;
516	mpc10->num_mpcc = num_mpcc;
517
518	for (i = 0; i < MAX_MPCC; i++)
519		mpc1_init_mpcc(&mpc10->base.mpcc_array[i], i);
520}
521