link_dp_training_auxless.c

 1/*
 2 * Copyright 2022 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26/* FILE POLICY AND INTENDED USAGE:
27 *
28 */
29#include "link_dp_training_auxless.h"
30#include "link_dp_phy.h"
31#define DC_LOGGER \
32	link->ctx->logger
33bool dp_perform_link_training_skip_aux(
34	struct dc_link *link,
35	const struct link_resource *link_res,
36	const struct dc_link_settings *link_setting)
37{
38	struct link_training_settings lt_settings = {0};
39
40	dp_decide_training_settings(
41			link,
42			link_res,
43			link_setting,
44			&lt_settings);
45	override_training_settings(
46			link,
47			&link->preferred_training_settings,
48			&lt_settings);
49
50	/* 1. Perform_clock_recovery_sequence. */
51
52	/* transmit training pattern for clock recovery */
53	dp_set_hw_training_pattern(link, link_res, lt_settings.pattern_for_cr, DPRX);
54
55	/* call HWSS to set lane settings*/
56	dp_set_hw_lane_settings(link, link_res, &lt_settings, DPRX);
57
58	/* wait receiver to lock-on*/
59	dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
60
61	/* 2. Perform_channel_equalization_sequence. */
62
63	/* transmit training pattern for channel equalization. */
64	dp_set_hw_training_pattern(link, link_res, lt_settings.pattern_for_eq, DPRX);
65
66	/* call HWSS to set lane settings*/
67	dp_set_hw_lane_settings(link, link_res, &lt_settings, DPRX);
68
69	/* wait receiver to lock-on. */
70	dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
71
72	/* 3. Perform_link_training_int. */
73
74	/* Mainlink output idle pattern. */
75	dp_set_hw_test_pattern(link, link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
76
77	dp_log_training_result(link, &lt_settings, LINK_TRAINING_SUCCESS);
78
79	return true;
80}