link_dp_phy.c

  1/*
  2 * Copyright 2022 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26/* FILE POLICY AND INTENDED USAGE:
 27 * This file implements basic dp phy functionality such as enable/disable phy
 28 * output and set lane/drive settings. This file is responsible for maintaining
 29 * and update software state representing current phy status such as current
 30 * link settings.
 31 */
 32
 33#include "link_dp_phy.h"
 34#include "link_dpcd.h"
 35#include "link_dp_training.h"
 36#include "link_dp_capability.h"
 37#include "clk_mgr.h"
 38#include "resource.h"
 39#include "link_enc_cfg.h"
 40#include "atomfirmware.h"
 41#define DC_LOGGER \
 42	link->ctx->logger
 43
 44void dpcd_write_rx_power_ctrl(struct dc_link *link, bool on)
 45{
 46	uint8_t state;
 47
 48	state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3;
 49
 50	if (link->sync_lt_in_progress)
 51		return;
 52
 53	core_link_write_dpcd(link, DP_SET_POWER, &state,
 54						 sizeof(state));
 55
 56}
 57
 58void dp_enable_link_phy(
 59	struct dc_link *link,
 60	const struct link_resource *link_res,
 61	enum signal_type signal,
 62	enum clock_source_id clock_source,
 63	const struct dc_link_settings *link_settings)
 64{
 65	link->cur_link_settings = *link_settings;
 66	link->dc->hwss.enable_dp_link_output(link, link_res, signal,
 67			clock_source, link_settings);
 68	dpcd_write_rx_power_ctrl(link, true);
 69}
 70
 71void dp_disable_link_phy(struct dc_link *link,
 72		const struct link_resource *link_res,
 73		enum signal_type signal)
 74{
 75	struct dc  *dc = link->ctx->dc;
 76
 77	if (!link->wa_flags.dp_keep_receiver_powered &&
 78			!link->skip_implict_edp_power_control &&
 79			link->type != dc_connection_none)
 80		dpcd_write_rx_power_ctrl(link, false);
 81
 82	dc->hwss.disable_link_output(link, link_res, signal);
 83	/* Clear current link setting.*/
 84	memset(&link->cur_link_settings, 0,
 85			sizeof(link->cur_link_settings));
 86
 87	if (dc->clk_mgr->funcs->notify_link_rate_change)
 88		dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
 89}
 90
 91static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset)
 92{
 93	return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) ==
 94			offset);
 95}
 96
 97void dp_set_hw_lane_settings(
 98	struct dc_link *link,
 99	const struct link_resource *link_res,
100	const struct link_training_settings *link_settings,
101	uint32_t offset)
102{
103	const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
104
105	// Don't return here if using FIXED_VS link HWSS and encoding is 128b/132b
106	if ((link_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) &&
107			!is_immediate_downstream(link, offset) &&
108			(!((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) ||
109			link_dp_get_encoding_format(&link_settings->link_settings) == DP_8b_10b_ENCODING))
110		return;
111
112	if (link_hwss->ext.set_dp_lane_settings)
113		link_hwss->ext.set_dp_lane_settings(link, link_res,
114				&link_settings->link_settings,
115				link_settings->hw_lane_settings);
116
117	memmove(link->cur_lane_setting,
118			link_settings->hw_lane_settings,
119			sizeof(link->cur_lane_setting));
120}
121
122void dp_set_drive_settings(
123	struct dc_link *link,
124	const struct link_resource *link_res,
125	struct link_training_settings *lt_settings)
126{
127	/* program ASIC PHY settings*/
128	dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
129
130	dp_hw_to_dpcd_lane_settings(lt_settings,
131			lt_settings->hw_lane_settings,
132			lt_settings->dpcd_lane_settings);
133
134	/* Notify DP sink the PHY settings from source */
135	dpcd_set_lane_settings(link, lt_settings, DPRX);
136}
137
138enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready)
139{
140	/* FEC has to be "set ready" before the link training.
141	 * The policy is to always train with FEC
142	 * if the sink supports it and leave it enabled on link.
143	 * If FEC is not supported, disable it.
144	 */
145	struct link_encoder *link_enc = link_res->dio_link_enc;
146	enum dc_status status = DC_OK;
147	uint8_t fec_config = 0;
148
149	if (!link->dc->config.unify_link_enc_assignment)
150		link_enc = link_enc_cfg_get_link_enc(link);
151	ASSERT(link_enc);
152	if (link_enc->funcs->fec_set_ready == NULL)
153		return DC_NOT_SUPPORTED;
154
155	if (ready && dp_should_enable_fec(link)) {
156		fec_config = 1;
157
158		status = core_link_write_dpcd(link, DP_FEC_CONFIGURATION,
159				&fec_config, sizeof(fec_config));
160
161		if (status == DC_OK) {
162			link_enc->funcs->fec_set_ready(link_enc, true);
163			link->fec_state = dc_link_fec_ready;
164		}
165	} else {
166		if (link->fec_state == dc_link_fec_ready) {
167			fec_config = 0;
168			if (link->type != dc_connection_none)
169				core_link_write_dpcd(link, DP_FEC_CONFIGURATION,
170					&fec_config, sizeof(fec_config));
171
172			link_enc->funcs->fec_set_ready(link_enc, false);
173			link->fec_state = dc_link_fec_not_ready;
174		}
175	}
176
177	return status;
178}
179
180void dp_set_fec_enable(struct dc_link *link, const struct link_resource *link_res, bool enable)
181{
182	struct link_encoder *link_enc = link_res->dio_link_enc;
183
184	if (!link->dc->config.unify_link_enc_assignment)
185		link_enc = link_enc_cfg_get_link_enc(link);
186
187	if (link_enc == NULL || link_enc->funcs == NULL || link_enc->funcs->fec_set_enable == NULL)
188		return;
189
190	if (enable && dp_should_enable_fec(link)) {
191		if (link->fec_state == dc_link_fec_ready) {
192			/* According to DP spec, FEC enable sequence can first
193			 * be transmitted anytime after 1000 LL codes have
194			 * been transmitted on the link after link training
195			 * completion. Using 1 lane RBR should have the maximum
196			 * time for transmitting 1000 LL codes which is 6.173 us.
197			 * So use 7 microseconds delay instead.
198			 */
199			udelay(7);
200			link_enc->funcs->fec_set_enable(link_enc, true);
201			link->fec_state = dc_link_fec_enabled;
202		}
203	} else {
204		if (link->fec_state == dc_link_fec_enabled) {
205			link_enc->funcs->fec_set_enable(link_enc, false);
206			link->fec_state = dc_link_fec_ready;
207		}
208	}
209}
210