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link_dp_capability.c
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linux-6.19.14/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26/* FILE POLICY AND INTENDED USAGE: 27 * This file implements dp specific link capability retrieval sequence. It is 28 * responsible for retrieving, parsing, overriding, deciding capability obtained 29 * from dp link. Link capability consists of encoders, DPRXs, cables, retimers, 30 * usb and all other possible backend capabilities. Other components should 31 * include this header file in order to access link capability. Accessing link 32 * capability by dereferencing dc_link outside dp_link_capability is not a 33 * recommended method as it makes the component dependent on the underlying data 34 * structure used to represent link capability instead of function interfaces. 35 */ 36 37#include "link_dp_capability.h" 38#include "link_ddc.h" 39#include "link_dpcd.h" 40#include "link_dp_dpia.h" 41#include "link_dp_phy.h" 42#include "link_edp_panel_control.h" 43#include "link_dp_irq_handler.h" 44#include "link/accessories/link_dp_trace.h" 45#include "link/link_detection.h" 46#include "link/link_validation.h" 47#include "link_dp_training.h" 48#include "atomfirmware.h" 49#include "resource.h" 50#include "link_enc_cfg.h" 51#include "dc_dmub_srv.h" 52#include "gpio_service_interface.h" 53 54#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ 55 56#define DC_LOGGER \ 57 link->ctx->logger 58 59#ifndef MAX 60#define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 61#endif 62#ifndef MIN 63#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 64#endif 65 66struct dp_lt_fallback_entry { 67 enum dc_lane_count lane_count; 68 enum dc_link_rate link_rate; 69}; 70 71static const struct dp_lt_fallback_entry dp_lt_fallbacks[] = { 72 /* This link training fallback array is ordered by 73 * link bandwidth from highest to lowest. 74 * DP specs makes it a normative policy to always 75 * choose the next highest link bandwidth during 76 * link training fallback. 77 */ 78 {LANE_COUNT_FOUR, LINK_RATE_UHBR20}, 79 {LANE_COUNT_FOUR, LINK_RATE_UHBR13_5}, 80 {LANE_COUNT_TWO, LINK_RATE_UHBR20}, 81 {LANE_COUNT_FOUR, LINK_RATE_UHBR10}, 82 {LANE_COUNT_TWO, LINK_RATE_UHBR13_5}, 83 {LANE_COUNT_FOUR, LINK_RATE_HIGH3}, 84 {LANE_COUNT_ONE, LINK_RATE_UHBR20}, 85 {LANE_COUNT_TWO, LINK_RATE_UHBR10}, 86 {LANE_COUNT_FOUR, LINK_RATE_HIGH2}, 87 {LANE_COUNT_ONE, LINK_RATE_UHBR13_5}, 88 {LANE_COUNT_TWO, LINK_RATE_HIGH3}, 89 {LANE_COUNT_ONE, LINK_RATE_UHBR10}, 90 {LANE_COUNT_TWO, LINK_RATE_HIGH2}, 91 {LANE_COUNT_FOUR, LINK_RATE_HIGH}, 92 {LANE_COUNT_ONE, LINK_RATE_HIGH3}, 93 {LANE_COUNT_FOUR, LINK_RATE_LOW}, 94 {LANE_COUNT_ONE, LINK_RATE_HIGH2}, 95 {LANE_COUNT_TWO, LINK_RATE_HIGH}, 96 {LANE_COUNT_TWO, LINK_RATE_LOW}, 97 {LANE_COUNT_ONE, LINK_RATE_HIGH}, 98 {LANE_COUNT_ONE, LINK_RATE_LOW}, 99}; 100 101static const struct dc_link_settings fail_safe_link_settings = { 102 .lane_count = LANE_COUNT_ONE, 103 .link_rate = LINK_RATE_LOW, 104 .link_spread = LINK_SPREAD_DISABLED, 105}; 106 107bool is_dp_active_dongle(const struct dc_link *link) 108{ 109 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) && 110 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER); 111} 112 113bool is_dp_branch_device(const struct dc_link *link) 114{ 115 return link->dpcd_caps.is_branch_dev; 116} 117 118static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc) 119{ 120 switch (bpc) { 121 case DOWN_STREAM_MAX_8BPC: 122 return 8; 123 case DOWN_STREAM_MAX_10BPC: 124 return 10; 125 case DOWN_STREAM_MAX_12BPC: 126 return 12; 127 case DOWN_STREAM_MAX_16BPC: 128 return 16; 129 default: 130 break; 131 } 132 133 return -1; 134} 135 136uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count) 137{ 138 switch (lttpr_repeater_count) { 139 case 0x80: // 1 lttpr repeater 140 return 1; 141 case 0x40: // 2 lttpr repeaters 142 return 2; 143 case 0x20: // 3 lttpr repeaters 144 return 3; 145 case 0x10: // 4 lttpr repeaters 146 return 4; 147 case 0x08: // 5 lttpr repeaters 148 return 5; 149 case 0x04: // 6 lttpr repeaters 150 return 6; 151 case 0x02: // 7 lttpr repeaters 152 return 7; 153 case 0x01: // 8 lttpr repeaters 154 return 8; 155 default: 156 break; 157 } 158 return 0; // invalid value 159} 160 161uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count) 162{ 163 /* Calculate offset for LTTPR closest to DPTX which is highest in the chain 164 * Offset is 0 for single LTTPR cases as base LTTPR DPCD addresses target LTTPR 1 165 */ 166 return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1); 167} 168 169uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) 170{ 171 switch (bw) { 172 case 0b001: 173 return 9000000; 174 case 0b010: 175 return 18000000; 176 case 0b011: 177 return 24000000; 178 case 0b100: 179 return 32000000; 180 case 0b101: 181 return 40000000; 182 case 0b110: 183 return 48000000; 184 } 185 186 return 0; 187} 188 189static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) 190{ 191 enum dc_link_rate link_rate; 192 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation. 193 switch (link_rate_in_khz) { 194 case 1620000: 195 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane 196 break; 197 case 2160000: 198 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane 199 break; 200 case 2430000: 201 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane 202 break; 203 case 2700000: 204 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane 205 break; 206 case 3240000: 207 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane 208 break; 209 case 4320000: 210 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane 211 break; 212 case 5400000: 213 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane 214 break; 215 case 6750000: 216 link_rate = LINK_RATE_RATE_8; // Rate_8 - 6.75 Gbps/Lane 217 break; 218 case 8100000: 219 link_rate = LINK_RATE_HIGH3; // Rate_9 (HBR3)- 8.10 Gbps/Lane 220 break; 221 case 10000000: 222 link_rate = LINK_RATE_UHBR10; // UHBR10 - 10.0 Gbps/Lane 223 break; 224 case 13500000: 225 link_rate = LINK_RATE_UHBR13_5; // UHBR13.5 - 13.5 Gbps/Lane 226 break; 227 case 20000000: 228 link_rate = LINK_RATE_UHBR20; // UHBR20 - 20.0 Gbps/Lane 229 break; 230 231 default: 232 link_rate = LINK_RATE_UNKNOWN; 233 break; 234 } 235 return link_rate; 236} 237 238static union dp_cable_id intersect_cable_id( 239 union dp_cable_id *a, union dp_cable_id *b) 240{ 241 union dp_cable_id out; 242 243 out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY, 244 b->bits.UHBR10_20_CAPABILITY); 245 out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY, 246 b->bits.UHBR13_5_CAPABILITY); 247 out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE); 248 249 return out; 250} 251 252/* 253 * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. 254 */ 255static uint32_t intersect_frl_link_bw_support( 256 const uint32_t max_supported_frl_bw_in_kbps, 257 const union hdmi_encoded_link_bw hdmi_encoded_link_bw) 258{ 259 uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps; 260 261 /* Skip checking FRL_MODE bit, as certain PCON will clear 262 * it despite supporting the link BW indicated in the other bits. 263 */ 264 if (hdmi_encoded_link_bw.bits.BW_48Gbps) 265 supported_bw_in_kbps = 48000000; 266 else if (hdmi_encoded_link_bw.bits.BW_40Gbps) 267 supported_bw_in_kbps = 40000000; 268 else if (hdmi_encoded_link_bw.bits.BW_32Gbps) 269 supported_bw_in_kbps = 32000000; 270 else if (hdmi_encoded_link_bw.bits.BW_24Gbps) 271 supported_bw_in_kbps = 24000000; 272 else if (hdmi_encoded_link_bw.bits.BW_18Gbps) 273 supported_bw_in_kbps = 18000000; 274 else if (hdmi_encoded_link_bw.bits.BW_9Gbps) 275 supported_bw_in_kbps = 9000000; 276 else if (hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED) 277 supported_bw_in_kbps = 0; /* This case should only get hit in regulated autonomous mode. */ 278 279 return supported_bw_in_kbps; 280} 281 282static enum clock_source_id get_clock_source_id(struct dc_link *link) 283{ 284 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED; 285 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; 286 287 if (dp_cs != NULL) { 288 dp_cs_id = dp_cs->id; 289 } else { 290 /* 291 * dp clock source is not initialized for some reason. 292 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used 293 */ 294 ASSERT(dp_cs); 295 } 296 297 return dp_cs_id; 298} 299 300static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data, 301 int length) 302{ 303 int retry = 0; 304 305 if (!link->dpcd_caps.dpcd_rev.raw) { 306 do { 307 dpcd_write_rx_power_ctrl(link, true); 308 core_link_read_dpcd(link, DP_DPCD_REV, 309 dpcd_data, length); 310 link->dpcd_caps.dpcd_rev.raw = dpcd_data[ 311 DP_DPCD_REV - 312 DP_DPCD_REV]; 313 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw); 314 } 315 316 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) { 317 switch (link->dpcd_caps.branch_dev_id) { 318 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down 319 * all internal circuits including AUX communication preventing 320 * reading DPCD table and EDID (spec violation). 321 * Encoder will skip DP RX power down on disable_output to 322 * keep receiver powered all the time.*/ 323 case DP_BRANCH_DEVICE_ID_0010FA: 324 case DP_BRANCH_DEVICE_ID_0080E1: 325 case DP_BRANCH_DEVICE_ID_00E04C: 326 link->wa_flags.dp_keep_receiver_powered = true; 327 break; 328 329 /* TODO: May need work around for other dongles. */ 330 default: 331 link->wa_flags.dp_keep_receiver_powered = false; 332 break; 333 } 334 } else 335 link->wa_flags.dp_keep_receiver_powered = false; 336} 337 338bool dp_is_fec_supported(const struct dc_link *link) 339{ 340 /* TODO - use asic cap instead of link_enc->features 341 * we no longer know which link enc to use for this link before commit 342 */ 343 struct resource_context *res_ctx = &link->dc->current_state->res_ctx; 344 struct resource_pool *res_pool = link->dc->res_pool; 345 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); 346 347 if (!link->dc->config.unify_link_enc_assignment) 348 link_enc = link_enc_cfg_get_link_enc(link); 349 ASSERT(link_enc); 350 351 return (dc_is_dp_signal(link->connector_signal) && link_enc && 352 link_enc->features.fec_supported && 353 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE); 354} 355 356bool dp_should_enable_fec(const struct dc_link *link) 357{ 358 bool force_disable = false; 359 360 if (link->dc->debug.disable_fec) 361 force_disable = true; 362 else if (link->fec_state == dc_link_fec_enabled) 363 force_disable = false; 364 else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST && 365 link->local_sink && 366 link->local_sink->edid_caps.panel_patch.disable_fec) 367 force_disable = true; 368 else if (link->connector_signal == SIGNAL_TYPE_EDP 369 && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields. 370 dsc_support.DSC_SUPPORT == false 371 || link->panel_config.dsc.disable_dsc_edp 372 || !link->dc->caps.edp_dsc_support)) 373 force_disable = true; 374 375 return !force_disable && dp_is_fec_supported(link); 376} 377 378bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx) 379{ 380 /* If this assert is hit then we have a link encoder dynamic management issue */ 381 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); 382 return (pipe_ctx->stream_res.hpo_dp_stream_enc && 383 pipe_ctx->link_res.hpo_dp_link_enc && 384 dc_is_dp_signal(pipe_ctx->stream->signal)); 385} 386 387bool dp_is_lttpr_present(struct dc_link *link) 388{ 389 /* Some sink devices report invalid LTTPR revision, so don't validate against that cap */ 390 uint32_t lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); 391 bool is_lttpr_present = (lttpr_count > 0 && 392 link->dpcd_caps.lttpr_caps.max_lane_count > 0 && 393 link->dpcd_caps.lttpr_caps.max_lane_count <= 4); 394 395 if (lttpr_count > 0 && !is_lttpr_present) 396 DC_LOG_ERROR("LTTPR count is nonzero but invalid lane count reported. Assuming no LTTPR present.\n"); 397 398 return is_lttpr_present; 399} 400 401/* in DP compliance test, DPR-120 may have 402 * a random value in its MAX_LINK_BW dpcd field. 403 * We map it to the maximum supported link rate that 404 * is smaller than MAX_LINK_BW in this case. 405 */ 406static enum dc_link_rate get_link_rate_from_max_link_bw( 407 uint8_t max_link_bw) 408{ 409 enum dc_link_rate link_rate; 410 411 if (max_link_bw >= LINK_RATE_HIGH3) { 412 link_rate = LINK_RATE_HIGH3; 413 } else if (max_link_bw < LINK_RATE_HIGH3 414 && max_link_bw >= LINK_RATE_HIGH2) { 415 link_rate = LINK_RATE_HIGH2; 416 } else if (max_link_bw < LINK_RATE_HIGH2 417 && max_link_bw >= LINK_RATE_HIGH) { 418 link_rate = LINK_RATE_HIGH; 419 } else if (max_link_bw < LINK_RATE_HIGH 420 && max_link_bw >= LINK_RATE_LOW) { 421 link_rate = LINK_RATE_LOW; 422 } else { 423 link_rate = LINK_RATE_UNKNOWN; 424 } 425 426 return link_rate; 427} 428 429static enum dc_lane_count get_lttpr_max_lane_count(struct dc_link *link) 430{ 431 enum dc_lane_count lttpr_max_lane_count = LANE_COUNT_UNKNOWN; 432 433 if (link->dpcd_caps.lttpr_caps.max_lane_count <= LANE_COUNT_DP_MAX) 434 lttpr_max_lane_count = link->dpcd_caps.lttpr_caps.max_lane_count; 435 436 /* if bw_allocation is enabled and nrd_max_lane_count is set, use it */ 437 if (link->dpia_bw_alloc_config.bw_alloc_enabled && 438 link->dpia_bw_alloc_config.nrd_max_lane_count > 0) 439 lttpr_max_lane_count = link->dpia_bw_alloc_config.nrd_max_lane_count; 440 441 return lttpr_max_lane_count; 442} 443 444static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link) 445{ 446 447 enum dc_link_rate lttpr_max_link_rate = LINK_RATE_UNKNOWN; 448 449 switch (link->dpcd_caps.lttpr_caps.max_link_rate) { 450 case LINK_RATE_LOW: 451 case LINK_RATE_HIGH: 452 case LINK_RATE_HIGH2: 453 case LINK_RATE_HIGH3: 454 lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate; 455 break; 456 } 457 458 /* if bw_allocation is enabled and nrd_max_link_rate is set, use it */ 459 if (link->dpia_bw_alloc_config.bw_alloc_enabled && 460 link->dpia_bw_alloc_config.nrd_max_link_rate > 0) 461 lttpr_max_link_rate = link->dpia_bw_alloc_config.nrd_max_link_rate; 462 463 if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20) 464 lttpr_max_link_rate = LINK_RATE_UHBR20; 465 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5) 466 lttpr_max_link_rate = LINK_RATE_UHBR13_5; 467 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10) 468 lttpr_max_link_rate = LINK_RATE_UHBR10; 469 470 return lttpr_max_link_rate; 471} 472 473static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) 474{ 475 enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN; 476 477 if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20) { 478 cable_max_link_rate = LINK_RATE_UHBR20; 479 } else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY) { 480 cable_max_link_rate = LINK_RATE_UHBR13_5; 481 } else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10) { 482 // allow DP40 cables to do UHBR13.5 for passive or unknown cable type 483 if (link->dpcd_caps.cable_id.bits.CABLE_TYPE < 2) { 484 cable_max_link_rate = LINK_RATE_UHBR13_5; 485 } else { 486 cable_max_link_rate = LINK_RATE_UHBR10; 487 } 488 } 489 490 return cable_max_link_rate; 491} 492 493static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) 494{ 495 return lane_count <= LANE_COUNT_ONE; 496} 497 498static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate) 499{ 500 return link_rate <= LINK_RATE_LOW; 501} 502 503static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) 504{ 505 switch (lane_count) { 506 case LANE_COUNT_FOUR: 507 return LANE_COUNT_TWO; 508 case LANE_COUNT_TWO: 509 return LANE_COUNT_ONE; 510 case LANE_COUNT_ONE: 511 return LANE_COUNT_UNKNOWN; 512 default: 513 return LANE_COUNT_UNKNOWN; 514 } 515} 516 517static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum dc_link_rate link_rate) 518{ 519 // NEEDSWORK: provide some details about why this function never returns some of the 520 // obscure link rates such as 4.32 Gbps or 3.24 Gbps and if such behavior is intended. 521 // 522 523 switch (link_rate) { 524 case LINK_RATE_UHBR20: 525 return LINK_RATE_UHBR13_5; 526 case LINK_RATE_UHBR13_5: 527 return LINK_RATE_UHBR10; 528 case LINK_RATE_UHBR10: 529 return LINK_RATE_HIGH3; 530 case LINK_RATE_HIGH3: 531 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5) 532 return LINK_RATE_RATE_8; 533 return LINK_RATE_HIGH2; 534 case LINK_RATE_RATE_8: 535 return LINK_RATE_HIGH2; 536 case LINK_RATE_HIGH2: 537 return LINK_RATE_HIGH; 538 case LINK_RATE_RATE_6: 539 case LINK_RATE_RBR2: 540 return LINK_RATE_HIGH; 541 case LINK_RATE_HIGH: 542 return LINK_RATE_LOW; 543 case LINK_RATE_RATE_3: 544 case LINK_RATE_RATE_2: 545 return LINK_RATE_LOW; 546 case LINK_RATE_LOW: 547 default: 548 return LINK_RATE_UNKNOWN; 549 } 550} 551 552static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) 553{ 554 switch (lane_count) { 555 case LANE_COUNT_ONE: 556 return LANE_COUNT_TWO; 557 case LANE_COUNT_TWO: 558 return LANE_COUNT_FOUR; 559 default: 560 return LANE_COUNT_UNKNOWN; 561 } 562} 563 564static enum dc_link_rate increase_link_rate(struct dc_link *link, 565 enum dc_link_rate link_rate) 566{ 567 switch (link_rate) { 568 case LINK_RATE_LOW: 569 return LINK_RATE_HIGH; 570 case LINK_RATE_HIGH: 571 return LINK_RATE_HIGH2; 572 case LINK_RATE_HIGH2: 573 return LINK_RATE_HIGH3; 574 case LINK_RATE_HIGH3: 575 return LINK_RATE_UHBR10; 576 case LINK_RATE_UHBR10: 577 /* upto DP2.x specs UHBR13.5 is the only link rate that could be 578 * not supported by DPRX when higher link rate is supported. 579 * so we treat it as a special case for code simplicity. When we 580 * have new specs with more link rates like this, we should 581 * consider a more generic solution to handle discrete link 582 * rate capabilities. 583 */ 584 return link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 ? 585 LINK_RATE_UHBR13_5 : LINK_RATE_UHBR20; 586 case LINK_RATE_UHBR13_5: 587 return LINK_RATE_UHBR20; 588 default: 589 return LINK_RATE_UNKNOWN; 590 } 591} 592 593static void increase_edp_link_rate(struct dc_link *link, 594 struct dc_link_settings *current_link_setting) 595{ 596 if (current_link_setting->use_link_rate_set) { 597 if (current_link_setting->link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { 598 current_link_setting->link_rate_set++; 599 current_link_setting->link_rate = 600 link->dpcd_caps.edp_supported_link_rates[current_link_setting->link_rate_set]; 601 } else { 602 current_link_setting->use_link_rate_set = false; 603 current_link_setting->link_rate = LINK_RATE_UHBR10; 604 } 605 } else { 606 current_link_setting->link_rate = increase_link_rate(link, current_link_setting->link_rate); 607 } 608} 609 610static bool decide_fallback_link_setting_max_bw_policy( 611 struct dc_link *link, 612 const struct dc_link_settings *max, 613 struct dc_link_settings *cur, 614 enum link_training_result training_result) 615{ 616 uint32_t cur_idx = 0, next_idx; 617 bool found = false; 618 619 if (training_result == LINK_TRAINING_ABORT) 620 return false; 621 622 while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks)) 623 /* find current index */ 624 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && 625 dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate) 626 break; 627 else 628 cur_idx++; 629 630 next_idx = cur_idx + 1; 631 632 while (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) 633 /* find next index */ 634 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count || 635 dp_lt_fallbacks[next_idx].link_rate > max->link_rate) 636 next_idx++; 637 else if (dp_lt_fallbacks[next_idx].link_rate == LINK_RATE_UHBR13_5 && 638 link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 == 0) 639 /* upto DP2.x specs UHBR13.5 is the only link rate that 640 * could be not supported by DPRX when higher link rate 641 * is supported. so we treat it as a special case for 642 * code simplicity. When we have new specs with more 643 * link rates like this, we should consider a more 644 * generic solution to handle discrete link rate 645 * capabilities. 646 */ 647 next_idx++; 648 else 649 break; 650 651 if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) { 652 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count; 653 cur->link_rate = dp_lt_fallbacks[next_idx].link_rate; 654 found = true; 655 } 656 657 return found; 658} 659 660/* 661 * function: set link rate and lane count fallback based 662 * on current link setting and last link training result 663 * return value: 664 * true - link setting could be set 665 * false - has reached minimum setting 666 * and no further fallback could be done 667 */ 668bool decide_fallback_link_setting( 669 struct dc_link *link, 670 struct dc_link_settings *max, 671 struct dc_link_settings *cur, 672 enum link_training_result training_result) 673{ 674 if (link_dp_get_encoding_format(max) == DP_128b_132b_ENCODING || 675 link->dc->debug.force_dp2_lt_fallback_method) 676 return decide_fallback_link_setting_max_bw_policy(link, max, 677 cur, training_result); 678 679 switch (training_result) { 680 case LINK_TRAINING_CR_FAIL_LANE0: 681 case LINK_TRAINING_CR_FAIL_LANE1: 682 case LINK_TRAINING_CR_FAIL_LANE23: 683 case LINK_TRAINING_LQA_FAIL: 684 { 685 if (!reached_minimum_link_rate(cur->link_rate)) { 686 cur->link_rate = reduce_link_rate(link, cur->link_rate); 687 } else if (!reached_minimum_lane_count(cur->lane_count)) { 688 cur->link_rate = max->link_rate; 689 if (training_result == LINK_TRAINING_CR_FAIL_LANE0) 690 return false; 691 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1) 692 cur->lane_count = LANE_COUNT_ONE; 693 else if (training_result == LINK_TRAINING_CR_FAIL_LANE23) 694 cur->lane_count = LANE_COUNT_TWO; 695 else 696 cur->lane_count = reduce_lane_count(cur->lane_count); 697 } else { 698 return false; 699 } 700 break; 701 } 702 case LINK_TRAINING_EQ_FAIL_EQ: 703 case LINK_TRAINING_EQ_FAIL_CR_PARTIAL: 704 { 705 if (!reached_minimum_lane_count(cur->lane_count)) { 706 cur->lane_count = reduce_lane_count(cur->lane_count); 707 } else if (!reached_minimum_link_rate(cur->link_rate)) { 708 cur->link_rate = reduce_link_rate(link, cur->link_rate); 709 /* Reduce max link rate to avoid potential infinite loop. 710 * Needed so that any subsequent CR_FAIL fallback can't 711 * re-set the link rate higher than the link rate from 712 * the latest EQ_FAIL fallback. 713 */ 714 max->link_rate = cur->link_rate; 715 cur->lane_count = max->lane_count; 716 } else { 717 return false; 718 } 719 break; 720 } 721 case LINK_TRAINING_EQ_FAIL_CR: 722 { 723 if (!reached_minimum_link_rate(cur->link_rate)) { 724 cur->link_rate = reduce_link_rate(link, cur->link_rate); 725 /* Reduce max link rate to avoid potential infinite loop. 726 * Needed so that any subsequent CR_FAIL fallback can't 727 * re-set the link rate higher than the link rate from 728 * the latest EQ_FAIL fallback. 729 */ 730 max->link_rate = cur->link_rate; 731 cur->lane_count = max->lane_count; 732 } else { 733 return false; 734 } 735 break; 736 } 737 default: 738 return false; 739 } 740 return true; 741} 742static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw) 743{ 744 struct dc_link_settings initial_link_setting = { 745 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0}; 746 struct dc_link_settings current_link_setting = 747 initial_link_setting; 748 uint32_t link_bw; 749 750 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap)) 751 return false; 752 753 /* search for the minimum link setting that: 754 * 1. is supported according to the link training result 755 * 2. could support the b/w requested by the timing 756 */ 757 while (current_link_setting.link_rate <= 758 link->verified_link_cap.link_rate) { 759 link_bw = dp_link_bandwidth_kbps( 760 link, 761 ¤t_link_setting); 762 if (req_bw <= link_bw) { 763 *link_setting = current_link_setting; 764 return true; 765 } 766 767 if (current_link_setting.lane_count < 768 link->verified_link_cap.lane_count) { 769 current_link_setting.lane_count = 770 increase_lane_count( 771 current_link_setting.lane_count); 772 } else { 773 current_link_setting.link_rate = 774 increase_link_rate(link, 775 current_link_setting.link_rate); 776 current_link_setting.lane_count = 777 initial_link_setting.lane_count; 778 } 779 } 780 781 return false; 782} 783 784bool edp_decide_link_settings(struct dc_link *link, 785 struct dc_link_settings *link_setting, uint32_t req_bw) 786{ 787 struct dc_link_settings initial_link_setting; 788 struct dc_link_settings current_link_setting; 789 uint32_t link_bw; 790 791 /* 792 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. 793 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" 794 */ 795 if (!edp_is_ilr_optimization_enabled(link)) { 796 *link_setting = link->verified_link_cap; 797 return true; 798 } 799 800 memset(&initial_link_setting, 0, sizeof(initial_link_setting)); 801 initial_link_setting.lane_count = LANE_COUNT_ONE; 802 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0]; 803 initial_link_setting.link_spread = LINK_SPREAD_DISABLED; 804 initial_link_setting.use_link_rate_set = true; 805 initial_link_setting.link_rate_set = 0; 806 current_link_setting = initial_link_setting; 807 808 /* search for the minimum link setting that: 809 * 1. is supported according to the link training result 810 * 2. could support the b/w requested by the timing 811 */ 812 while (current_link_setting.link_rate <= 813 link->verified_link_cap.link_rate) { 814 link_bw = dp_link_bandwidth_kbps( 815 link, 816 ¤t_link_setting); 817 if (req_bw <= link_bw) { 818 *link_setting = current_link_setting; 819 return true; 820 } 821 822 if (current_link_setting.lane_count < 823 link->verified_link_cap.lane_count) { 824 current_link_setting.lane_count = 825 increase_lane_count( 826 current_link_setting.lane_count); 827 } else { 828 increase_edp_link_rate(link, ¤t_link_setting); 829 } 830 } 831 return false; 832} 833 834bool decide_edp_link_settings_with_dsc(struct dc_link *link, 835 struct dc_link_settings *link_setting, 836 uint32_t req_bw, 837 enum dc_link_rate max_link_rate) 838{ 839 struct dc_link_settings initial_link_setting; 840 struct dc_link_settings current_link_setting; 841 uint32_t link_bw; 842 843 unsigned int policy = 0; 844 845 policy = link->panel_config.dsc.force_dsc_edp_policy; 846 if (max_link_rate == LINK_RATE_UNKNOWN) 847 max_link_rate = link->verified_link_cap.link_rate; 848 /* 849 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. 850 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" 851 */ 852 if (!edp_is_ilr_optimization_enabled(link)) { 853 /* for DSC enabled case, we search for minimum lane count */ 854 memset(&initial_link_setting, 0, sizeof(initial_link_setting)); 855 initial_link_setting.lane_count = LANE_COUNT_ONE; 856 initial_link_setting.link_rate = LINK_RATE_LOW; 857 initial_link_setting.link_spread = LINK_SPREAD_DISABLED; 858 initial_link_setting.use_link_rate_set = false; 859 initial_link_setting.link_rate_set = 0; 860 current_link_setting = initial_link_setting; 861 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap)) 862 return false; 863 864 /* search for the minimum link setting that: 865 * 1. is supported according to the link training result 866 * 2. could support the b/w requested by the timing 867 */ 868 while (current_link_setting.link_rate <= 869 max_link_rate) { 870 link_bw = dp_link_bandwidth_kbps( 871 link, 872 ¤t_link_setting); 873 if (req_bw <= link_bw) { 874 *link_setting = current_link_setting; 875 return true; 876 } 877 if (policy) { 878 /* minimize lane */ 879 if (current_link_setting.link_rate < max_link_rate) { 880 increase_edp_link_rate(link, ¤t_link_setting); 881 } else { 882 if (current_link_setting.lane_count < 883 link->verified_link_cap.lane_count) { 884 current_link_setting.lane_count = 885 increase_lane_count( 886 current_link_setting.lane_count); 887 current_link_setting.link_rate = initial_link_setting.link_rate; 888 } else 889 break; 890 } 891 } else { 892 /* minimize link rate */ 893 if (current_link_setting.lane_count < 894 link->verified_link_cap.lane_count) { 895 current_link_setting.lane_count = 896 increase_lane_count( 897 current_link_setting.lane_count); 898 } else { 899 increase_edp_link_rate(link, ¤t_link_setting); 900 current_link_setting.lane_count = 901 initial_link_setting.lane_count; 902 } 903 } 904 } 905 return false; 906 } 907 908 /* if optimize edp link is supported */ 909 memset(&initial_link_setting, 0, sizeof(initial_link_setting)); 910 initial_link_setting.lane_count = LANE_COUNT_ONE; 911 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0]; 912 initial_link_setting.link_spread = LINK_SPREAD_DISABLED; 913 initial_link_setting.use_link_rate_set = true; 914 initial_link_setting.link_rate_set = 0; 915 current_link_setting = initial_link_setting; 916 917 /* search for the minimum link setting that: 918 * 1. is supported according to the link training result 919 * 2. could support the b/w requested by the timing 920 */ 921 while (current_link_setting.link_rate <= 922 max_link_rate) { 923 link_bw = dp_link_bandwidth_kbps( 924 link, 925 ¤t_link_setting); 926 if (req_bw <= link_bw) { 927 *link_setting = current_link_setting; 928 return true; 929 } 930 if (policy) { 931 /* minimize lane */ 932 if (current_link_setting.link_rate < max_link_rate) { 933 increase_edp_link_rate(link, ¤t_link_setting); 934 } else { 935 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) { 936 current_link_setting.lane_count = 937 increase_lane_count( 938 current_link_setting.lane_count); 939 current_link_setting.link_rate_set = initial_link_setting.link_rate_set; 940 current_link_setting.use_link_rate_set = initial_link_setting.use_link_rate_set; 941 current_link_setting.link_rate = 942 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; 943 } else 944 break; 945 } 946 } else { 947 /* minimize link rate */ 948 if (current_link_setting.lane_count < 949 link->verified_link_cap.lane_count) { 950 current_link_setting.lane_count = 951 increase_lane_count( 952 current_link_setting.lane_count); 953 } else { 954 increase_edp_link_rate(link, ¤t_link_setting); 955 if (current_link_setting.link_rate == LINK_RATE_UNKNOWN) 956 break; 957 } 958 } 959 } 960 return false; 961} 962 963static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting) 964{ 965 *link_setting = link->verified_link_cap; 966 return true; 967} 968 969bool link_decide_link_settings(struct dc_stream_state *stream, 970 struct dc_link_settings *link_setting) 971{ 972 struct dc_link *link = stream->link; 973 uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link)); 974 975 memset(link_setting, 0, sizeof(*link_setting)); 976 977 if (dc_is_dp_signal(stream->signal) && 978 link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN && 979 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) { 980 /* if preferred is specified through AMDDP, use it, if it's enough 981 * to drive the mode 982 */ 983 *link_setting = link->preferred_link_setting; 984 } else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 985 /* MST doesn't perform link training for now 986 * TODO: add MST specific link training routine 987 */ 988 decide_mst_link_settings(link, link_setting); 989 } else if (stream->signal == SIGNAL_TYPE_VIRTUAL) { 990 link_setting->lane_count = LANE_COUNT_FOUR; 991 link_setting->link_rate = LINK_RATE_HIGH3; 992 } else if (link->connector_signal == SIGNAL_TYPE_EDP) { 993 /* enable edp link optimization for DSC eDP case */ 994 if (stream->timing.flags.DSC) { 995 enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN; 996 997 if (link->panel_config.dsc.force_dsc_edp_policy) { 998 /* calculate link max link rate cap*/ 999 struct dc_link_settings tmp_link_setting; 1000 struct dc_crtc_timing tmp_timing = stream->timing; 1001 uint32_t orig_req_bw; 1002 1003 tmp_link_setting.link_rate = LINK_RATE_UNKNOWN; 1004 tmp_timing.flags.DSC = 0; 1005 orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing, 1006 dc_link_get_highest_encoding_format(link)); 1007 edp_decide_link_settings(link, &tmp_link_setting, orig_req_bw); 1008 max_link_rate = tmp_link_setting.link_rate; 1009 } 1010 decide_edp_link_settings_with_dsc(link, link_setting, req_bw, max_link_rate); 1011 } else { 1012 edp_decide_link_settings(link, link_setting, req_bw); 1013 } 1014 } else { 1015 decide_dp_link_settings(link, link_setting, req_bw); 1016 } 1017 1018 return link_setting->lane_count != LANE_COUNT_UNKNOWN && 1019 link_setting->link_rate != LINK_RATE_UNKNOWN; 1020} 1021 1022enum dp_link_encoding link_dp_get_encoding_format(const struct dc_link_settings *link_settings) 1023{ 1024 if ((link_settings->link_rate >= LINK_RATE_LOW) && 1025 (link_settings->link_rate <= LINK_RATE_HIGH3)) 1026 return DP_8b_10b_ENCODING; 1027 else if ((link_settings->link_rate >= LINK_RATE_UHBR10) && 1028 (link_settings->link_rate <= LINK_RATE_UHBR20)) 1029 return DP_128b_132b_ENCODING; 1030 return DP_UNKNOWN_ENCODING; 1031} 1032 1033enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link) 1034{ 1035 struct dc_link_settings link_settings = {0}; 1036 1037 if (!dc_is_dp_signal(link->connector_signal)) 1038 return DP_UNKNOWN_ENCODING; 1039 1040 if (link->preferred_link_setting.lane_count != 1041 LANE_COUNT_UNKNOWN && 1042 link->preferred_link_setting.link_rate != 1043 LINK_RATE_UNKNOWN) { 1044 link_settings = link->preferred_link_setting; 1045 } else { 1046 decide_mst_link_settings(link, &link_settings); 1047 } 1048 1049 return link_dp_get_encoding_format(&link_settings); 1050} 1051 1052static void read_dp_device_vendor_id(struct dc_link *link) 1053{ 1054 struct dp_device_vendor_id dp_id = {0}; 1055 1056 /* read IEEE branch device id */ 1057 core_link_read_dpcd( 1058 link, 1059 DP_BRANCH_OUI, 1060 (uint8_t *)&dp_id, 1061 sizeof(dp_id)); 1062 1063 link->dpcd_caps.branch_dev_id = 1064 (dp_id.ieee_oui[0] << 16) + 1065 (dp_id.ieee_oui[1] << 8) + 1066 dp_id.ieee_oui[2]; 1067 1068 memmove( 1069 link->dpcd_caps.branch_dev_name, 1070 dp_id.ieee_device_id, 1071 sizeof(dp_id.ieee_device_id)); 1072} 1073 1074static enum dc_status wake_up_aux_channel(struct dc_link *link) 1075{ 1076 enum dc_status status = DC_ERROR_UNEXPECTED; 1077 uint32_t aux_channel_retry_cnt = 0; 1078 uint8_t dpcd_power_state = '\0'; 1079 1080 while (status != DC_OK && aux_channel_retry_cnt < 10) { 1081 status = core_link_read_dpcd(link, DP_SET_POWER, 1082 &dpcd_power_state, sizeof(dpcd_power_state)); 1083 1084 /* Delay 1 ms if AUX CH is in power down state. Based on spec 1085 * section 2.3.1.2, if AUX CH may be powered down due to 1086 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential 1087 * signal and may need up to 1 ms before being able to reply. 1088 */ 1089 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) { 1090 fsleep(1000); 1091 aux_channel_retry_cnt++; 1092 } 1093 } 1094 1095 if (status != DC_OK) { 1096 dpcd_power_state = DP_SET_POWER_D0; 1097 status = core_link_write_dpcd( 1098 link, 1099 DP_SET_POWER, 1100 &dpcd_power_state, 1101 sizeof(dpcd_power_state)); 1102 1103 dpcd_power_state = DP_SET_POWER_D3; 1104 status = core_link_write_dpcd( 1105 link, 1106 DP_SET_POWER, 1107 &dpcd_power_state, 1108 sizeof(dpcd_power_state)); 1109 DC_LOG_DC("%s: Failed to power up sink\n", __func__); 1110 return DC_ERROR_UNEXPECTED; 1111 } 1112 1113 return DC_OK; 1114} 1115 1116static void read_and_intersect_post_frl_lt_status( 1117 struct dc_link *link) 1118{ 1119 union autonomous_mode_and_frl_link_status autonomous_mode_caps = {0}; 1120 union hdmi_tx_link_status hdmi_tx_link_status = {0}; 1121 union hdmi_encoded_link_bw hdmi_encoded_link_bw = {0}; 1122 1123 /* Check if dongle supports regulated autonomous mode. */ 1124 core_link_read_dpcd(link, DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS, 1125 &autonomous_mode_caps.raw, sizeof(autonomous_mode_caps)); 1126 1127 link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support = 1128 autonomous_mode_caps.bits.REGULATED_AUTONOMOUS_MODE_SUPPORTED; 1129 1130 if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support) { 1131 DC_LOG_DC("%s: PCON supports regulated autonomous mode.\n", __func__); 1132 1133 core_link_read_dpcd(link, DP_PCON_HDMI_TX_LINK_STATUS, 1134 &hdmi_tx_link_status.raw, sizeof(hdmi_tx_link_status)); 1135 } 1136 1137 // Intersect reported max link bw support with the supported link rate post FRL link training 1138 if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS, 1139 &hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) { 1140 1141 if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support && 1142 (!hdmi_tx_link_status.bits.HDMI_TX_READY_STATUS || 1143 !hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)) { 1144 DC_LOG_WARNING("%s: PCON TX link training has not finished.\n", __func__); 1145 1146 /* Link training not finished, ignore values from this DPCD reg. */ 1147 return; 1148 } 1149 1150 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support( 1151 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps, 1152 hdmi_encoded_link_bw); 1153 DC_LOG_DC("%s: pcon frl link bw = %u\n", __func__, 1154 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps); 1155 } 1156} 1157 1158static void get_active_converter_info( 1159 uint8_t data, struct dc_link *link) 1160{ 1161 union dp_downstream_port_present ds_port = { .byte = data }; 1162 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps)); 1163 1164 /* decode converter info*/ 1165 if (!ds_port.fields.PORT_PRESENT) { 1166 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; 1167 set_dongle_type(link->ddc, 1168 link->dpcd_caps.dongle_type); 1169 link->dpcd_caps.is_branch_dev = false; 1170 return; 1171 } 1172 1173 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */ 1174 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT; 1175 1176 switch (ds_port.fields.PORT_TYPE) { 1177 case DOWNSTREAM_VGA: 1178 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER; 1179 break; 1180 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS: 1181 /* At this point we don't know is it DVI or HDMI or DP++, 1182 * assume DVI.*/ 1183 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER; 1184 break; 1185 default: 1186 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; 1187 break; 1188 } 1189 1190 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) { 1191 uint8_t det_caps[16] = {0}; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/ 1192 union dwnstream_port_caps_byte0 *port_caps = 1193 (union dwnstream_port_caps_byte0 *)det_caps; 1194 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0, 1195 det_caps, sizeof(det_caps)) == DC_OK) { 1196 1197 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) { 1198 /*Handle DP case as DONGLE_NONE*/ 1199 case DOWN_STREAM_DETAILED_DP: 1200 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; 1201 break; 1202 case DOWN_STREAM_DETAILED_VGA: 1203 link->dpcd_caps.dongle_type = 1204 DISPLAY_DONGLE_DP_VGA_CONVERTER; 1205 break; 1206 case DOWN_STREAM_DETAILED_DVI: 1207 link->dpcd_caps.dongle_type = 1208 DISPLAY_DONGLE_DP_DVI_CONVERTER; 1209 break; 1210 case DOWN_STREAM_DETAILED_HDMI: 1211 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS: 1212 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/ 1213 link->dpcd_caps.dongle_type = 1214 DISPLAY_DONGLE_DP_HDMI_CONVERTER; 1215 1216 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type; 1217 if (ds_port.fields.DETAILED_CAPS) { 1218 1219 union dwnstream_port_caps_byte3_hdmi 1220 hdmi_caps = {.raw = det_caps[3] }; 1221 union dwnstream_port_caps_byte2 1222 hdmi_color_caps = {.raw = det_caps[2] }; 1223 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz = 1224 det_caps[1] * 2500; 1225 1226 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter = 1227 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK; 1228 /*YCBCR capability only for HDMI case*/ 1229 if (port_caps->bits.DWN_STRM_PORTX_TYPE 1230 == DOWN_STREAM_DETAILED_HDMI) { 1231 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through = 1232 hdmi_caps.bits.YCrCr422_PASS_THROUGH; 1233 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through = 1234 hdmi_caps.bits.YCrCr420_PASS_THROUGH; 1235 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter = 1236 hdmi_caps.bits.YCrCr422_CONVERSION; 1237 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter = 1238 hdmi_caps.bits.YCrCr420_CONVERSION; 1239 } 1240 1241 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc = 1242 translate_dpcd_max_bpc( 1243 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); 1244 1245 if (link->dc->caps.dp_hdmi21_pcon_support) { 1246 1247 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = 1248 link_bw_kbps_from_raw_frl_link_rate_data( 1249 hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT); 1250 1251 read_and_intersect_post_frl_lt_status(link); 1252 1253 if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0) 1254 link->dpcd_caps.dongle_caps.extendedCapValid = true; 1255 } 1256 1257 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) 1258 link->dpcd_caps.dongle_caps.extendedCapValid = true; 1259 } 1260 1261 break; 1262 } 1263 } 1264 } 1265 1266 set_dongle_type(link->ddc, link->dpcd_caps.dongle_type); 1267 1268 { 1269 struct dp_sink_hw_fw_revision dp_hw_fw_revision = {0}; 1270 1271 core_link_read_dpcd( 1272 link, 1273 DP_BRANCH_REVISION_START, 1274 (uint8_t *)&dp_hw_fw_revision, 1275 sizeof(dp_hw_fw_revision)); 1276 1277 link->dpcd_caps.branch_hw_revision = 1278 dp_hw_fw_revision.ieee_hw_rev; 1279 1280 memmove( 1281 link->dpcd_caps.branch_fw_revision, 1282 dp_hw_fw_revision.ieee_fw_rev, 1283 sizeof(dp_hw_fw_revision.ieee_fw_rev)); 1284 } 1285 1286 core_link_read_dpcd( 1287 link, 1288 DP_BRANCH_VENDOR_SPECIFIC_START, 1289 (uint8_t *)link->dpcd_caps.branch_vendor_specific_data, 1290 sizeof(link->dpcd_caps.branch_vendor_specific_data)); 1291 1292 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 && 1293 link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) { 1294 union dp_dfp_cap_ext dfp_cap_ext; 1295 memset(&dfp_cap_ext, '\0', sizeof (dfp_cap_ext)); 1296 core_link_read_dpcd( 1297 link, 1298 DP_DFP_CAPABILITY_EXTENSION_SUPPORT, 1299 dfp_cap_ext.raw, 1300 sizeof(dfp_cap_ext.raw)); 1301 link->dpcd_caps.dongle_caps.dfp_cap_ext.supported = dfp_cap_ext.fields.supported; 1302 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps = 1303 dfp_cap_ext.fields.max_pixel_rate_in_mps[0] + 1304 (dfp_cap_ext.fields.max_pixel_rate_in_mps[1] << 8); 1305 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width = 1306 dfp_cap_ext.fields.max_video_h_active_width[0] + 1307 (dfp_cap_ext.fields.max_video_h_active_width[1] << 8); 1308 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height = 1309 dfp_cap_ext.fields.max_video_v_active_height[0] + 1310 (dfp_cap_ext.fields.max_video_v_active_height[1] << 8); 1311 link->dpcd_caps.dongle_caps.dfp_cap_ext.encoding_format_caps = 1312 dfp_cap_ext.fields.encoding_format_caps; 1313 link->dpcd_caps.dongle_caps.dfp_cap_ext.rgb_color_depth_caps = 1314 dfp_cap_ext.fields.rgb_color_depth_caps; 1315 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr444_color_depth_caps = 1316 dfp_cap_ext.fields.ycbcr444_color_depth_caps; 1317 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr422_color_depth_caps = 1318 dfp_cap_ext.fields.ycbcr422_color_depth_caps; 1319 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr420_color_depth_caps = 1320 dfp_cap_ext.fields.ycbcr420_color_depth_caps; 1321 DC_LOG_DP2("DFP capability extension is read at link %d", link->link_index); 1322 DC_LOG_DP2("\tdfp_cap_ext.supported = %s", link->dpcd_caps.dongle_caps.dfp_cap_ext.supported ? "true" : "false"); 1323 DC_LOG_DP2("\tdfp_cap_ext.max_pixel_rate_in_mps = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps); 1324 DC_LOG_DP2("\tdfp_cap_ext.max_video_h_active_width = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width); 1325 DC_LOG_DP2("\tdfp_cap_ext.max_video_v_active_height = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height); 1326 } 1327} 1328 1329static void apply_usbc_combo_phy_reset_wa(struct dc_link *link, 1330 struct dc_link_settings *link_settings) 1331{ 1332 /* Temporary Renoir-specific workaround PHY will sometimes be in bad 1333 * state on hotplugging display from certain USB-C dongle, so add extra 1334 * cycle of enabling and disabling the PHY before first link training. 1335 */ 1336 struct link_resource link_res = {0}; 1337 enum clock_source_id dp_cs_id = get_clock_source_id(link); 1338 1339 dp_enable_link_phy(link, &link_res, link->connector_signal, 1340 dp_cs_id, link_settings); 1341 dp_disable_link_phy(link, &link_res, link->connector_signal); 1342} 1343 1344bool dp_overwrite_extended_receiver_cap(struct dc_link *link) 1345{ 1346 uint8_t dpcd_data[16] = {0}; 1347 uint32_t read_dpcd_retry_cnt = 3; 1348 enum dc_status status = DC_ERROR_UNEXPECTED; 1349 union dp_downstream_port_present ds_port = { 0 }; 1350 union down_stream_port_count down_strm_port_count; 1351 union edp_configuration_cap edp_config_cap; 1352 1353 int i; 1354 1355 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1356 status = core_link_read_dpcd( 1357 link, 1358 DP_DPCD_REV, 1359 dpcd_data, 1360 sizeof(dpcd_data)); 1361 if (status == DC_OK) 1362 break; 1363 } 1364 1365 link->dpcd_caps.dpcd_rev.raw = 1366 dpcd_data[DP_DPCD_REV - DP_DPCD_REV]; 1367 1368 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) 1369 return false; 1370 1371 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT - 1372 DP_DPCD_REV]; 1373 1374 get_active_converter_info(ds_port.byte, link); 1375 1376 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT - 1377 DP_DPCD_REV]; 1378 1379 link->dpcd_caps.allow_invalid_MSA_timing_param = 1380 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM; 1381 1382 link->dpcd_caps.max_ln_count.raw = dpcd_data[ 1383 DP_MAX_LANE_COUNT - DP_DPCD_REV]; 1384 1385 link->dpcd_caps.max_down_spread.raw = dpcd_data[ 1386 DP_MAX_DOWNSPREAD - DP_DPCD_REV]; 1387 1388 link->reported_link_cap.lane_count = 1389 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; 1390 link->reported_link_cap.link_rate = dpcd_data[ 1391 DP_MAX_LINK_RATE - DP_DPCD_REV]; 1392 link->reported_link_cap.link_spread = 1393 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? 1394 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 1395 1396 edp_config_cap.raw = dpcd_data[ 1397 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV]; 1398 link->dpcd_caps.panel_mode_edp = 1399 edp_config_cap.bits.ALT_SCRAMBLER_RESET; 1400 link->dpcd_caps.dpcd_display_control_capable = 1401 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE; 1402 1403 return true; 1404} 1405 1406void dpcd_set_source_specific_data(struct dc_link *link) 1407{ 1408 if (!link->dc->vendor_signature.is_valid) { 1409 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED; 1410 struct dpcd_amd_signature amd_signature = {0}; 1411 struct dpcd_amd_device_id amd_device_id = {0}; 1412 1413 if (link->is_dds) { 1414 uint8_t dpcd_dp_edp_backlight_mode = 0; 1415 1416 /* 1417 * Write 0 to bits 0:1 for dp_edp_backlight_mode_set register 1418 * if platform is DDS 1419 */ 1420 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, 1421 &dpcd_dp_edp_backlight_mode, sizeof(uint8_t)); 1422 dpcd_dp_edp_backlight_mode &= ~0x3; 1423 1424 core_link_write_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, 1425 &dpcd_dp_edp_backlight_mode, sizeof(uint8_t)); 1426 } 1427 1428 amd_device_id.device_id_byte1 = 1429 (uint8_t)(link->ctx->asic_id.chip_id); 1430 amd_device_id.device_id_byte2 = 1431 (uint8_t)(link->ctx->asic_id.chip_id >> 8); 1432 amd_device_id.dce_version = 1433 (uint8_t)(link->ctx->dce_version); 1434 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get? 1435 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get? 1436 1437 core_link_read_dpcd(link, DP_SOURCE_OUI, 1438 (uint8_t *)(&amd_signature), 1439 sizeof(amd_signature)); 1440 1441 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) && 1442 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) && 1443 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) { 1444 1445 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0; 1446 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0; 1447 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A; 1448 1449 core_link_write_dpcd(link, DP_SOURCE_OUI, 1450 (uint8_t *)(&amd_signature), 1451 sizeof(amd_signature)); 1452 } 1453 1454 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03, 1455 (uint8_t *)(&amd_device_id), 1456 sizeof(amd_device_id)); 1457 1458 if (link->ctx->dce_version >= DCN_VERSION_2_0 && 1459 link->dc->caps.min_horizontal_blanking_period != 0) { 1460 1461 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period; 1462 1463 result_write_min_hblank = core_link_write_dpcd(link, 1464 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size), 1465 sizeof(hblank_size)); 1466 } 1467 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, 1468 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS, 1469 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'", 1470 result_write_min_hblank, 1471 link->link_index, 1472 link->ctx->dce_version, 1473 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, 1474 link->dc->caps.min_horizontal_blanking_period, 1475 link->dpcd_caps.branch_dev_id, 1476 link->dpcd_caps.branch_dev_name[0], 1477 link->dpcd_caps.branch_dev_name[1], 1478 link->dpcd_caps.branch_dev_name[2], 1479 link->dpcd_caps.branch_dev_name[3], 1480 link->dpcd_caps.branch_dev_name[4], 1481 link->dpcd_caps.branch_dev_name[5]); 1482 } else { 1483 core_link_write_dpcd(link, DP_SOURCE_OUI, 1484 link->dc->vendor_signature.data.raw, 1485 sizeof(link->dc->vendor_signature.data.raw)); 1486 } 1487} 1488 1489void dpcd_write_cable_id_to_dprx(struct dc_link *link) 1490{ 1491 if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED || 1492 link->dpcd_caps.cable_id.raw == 0 || 1493 link->dprx_states.cable_id_written) 1494 return; 1495 1496 core_link_write_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX, 1497 &link->dpcd_caps.cable_id.raw, 1498 sizeof(link->dpcd_caps.cable_id.raw)); 1499 1500 link->dprx_states.cable_id_written = 1; 1501} 1502 1503static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id) 1504{ 1505 union dmub_rb_cmd cmd; 1506 1507 if (!link->ctx->dmub_srv || 1508 link->ep_type != DISPLAY_ENDPOINT_PHY || 1509 link->link_enc->features.flags.bits.DP_IS_USB_C == 0) 1510 return false; 1511 1512 memset(&cmd, 0, sizeof(cmd)); 1513 cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID; 1514 cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data); 1515 cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx( 1516 link->dc, link->link_enc->transmitter); 1517 if (dc_wake_and_execute_dmub_cmd(link->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 1518 cmd.cable_id.header.ret_status == 1) { 1519 cable_id->raw = cmd.cable_id.data.output_raw; 1520 DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw); 1521 } 1522 return cmd.cable_id.header.ret_status == 1; 1523} 1524 1525static void retrieve_cable_id(struct dc_link *link) 1526{ 1527 union dp_cable_id usbc_cable_id = {0}; 1528 1529 link->dpcd_caps.cable_id.raw = 0; 1530 core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX, 1531 &link->dpcd_caps.cable_id.raw, sizeof(uint8_t)); 1532 1533 if (get_usbc_cable_id(link, &usbc_cable_id)) 1534 link->dpcd_caps.cable_id = intersect_cable_id( 1535 &link->dpcd_caps.cable_id, &usbc_cable_id); 1536} 1537 1538bool read_is_mst_supported(struct dc_link *link) 1539{ 1540 bool mst = false; 1541 enum dc_status st = DC_OK; 1542 union dpcd_rev rev; 1543 union mstm_cap cap; 1544 1545 if (link->preferred_training_settings.mst_enable && 1546 *link->preferred_training_settings.mst_enable == false) { 1547 return false; 1548 } 1549 1550 rev.raw = 0; 1551 cap.raw = 0; 1552 1553 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw, 1554 sizeof(rev)); 1555 1556 if (st == DC_OK && rev.raw >= DPCD_REV_12) { 1557 1558 st = core_link_read_dpcd(link, DP_MSTM_CAP, 1559 &cap.raw, sizeof(cap)); 1560 if (st == DC_OK && cap.bits.MST_CAP == 1) 1561 mst = true; 1562 } 1563 return mst; 1564 1565} 1566 1567/* Read additional sink caps defined in source specific DPCD area 1568 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP) 1569 * TODO: Add FS caps and read from DP_SOURCE_SINK_FS_CAP as well 1570 */ 1571static bool dpcd_read_sink_ext_caps(struct dc_link *link) 1572{ 1573 uint8_t dpcd_data = 0; 1574 uint8_t edp_general_cap2 = 0; 1575 1576 if (!link) 1577 return false; 1578 1579 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK) 1580 return false; 1581 1582 link->dpcd_sink_ext_caps.raw = dpcd_data; 1583 if (link->is_dds && !link->dpcd_sink_ext_caps.bits.oled) { 1584 link->dpcd_sink_ext_caps.raw = 0; 1585 return false; 1586 } 1587 1588 if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &edp_general_cap2, 1) != DC_OK) 1589 return false; 1590 1591 link->dpcd_caps.panel_luminance_control = (edp_general_cap2 & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) != 0; 1592 1593 return true; 1594} 1595 1596enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link) 1597{ 1598 uint8_t lttpr_dpcd_data[10] = {0}; 1599 enum dc_status status; 1600 bool is_lttpr_present; 1601 uint32_t lttpr_count; 1602 uint32_t closest_lttpr_offset; 1603 1604 /* Logic to determine LTTPR support*/ 1605 bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware; 1606 1607 if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support) 1608 return DC_NOT_SUPPORTED; 1609 1610 /* By reading LTTPR capability, RX assumes that we will enable 1611 * LTTPR extended aux timeout if LTTPR is present. 1612 */ 1613 status = core_link_read_dpcd( 1614 link, 1615 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, 1616 lttpr_dpcd_data, 1617 sizeof(lttpr_dpcd_data)); 1618 1619 link->dpcd_caps.lttpr_caps.revision.raw = 1620 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV - 1621 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1622 1623 link->dpcd_caps.lttpr_caps.max_link_rate = 1624 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER - 1625 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1626 1627 link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 1628 lttpr_dpcd_data[DP_PHY_REPEATER_CNT - 1629 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1630 1631 link->dpcd_caps.lttpr_caps.max_lane_count = 1632 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER - 1633 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1634 1635 link->dpcd_caps.lttpr_caps.mode = 1636 lttpr_dpcd_data[DP_PHY_REPEATER_MODE - 1637 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1638 1639 link->dpcd_caps.lttpr_caps.max_ext_timeout = 1640 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT - 1641 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1642 link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw = 1643 lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 1644 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1645 1646 link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw = 1647 lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - 1648 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1649 1650 link->dpcd_caps.lttpr_caps.alpm.raw = 1651 lttpr_dpcd_data[DP_LTTPR_ALPM_CAPABILITIES - 1652 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1653 1654 lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); 1655 1656 /* If this chip cap is set, at least one retimer must exist in the chain 1657 * Override count to 1 if we receive a known bad count (0 or an invalid value) */ 1658 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 1659 lttpr_count == 0) { 1660 /* If you see this message consistently, either the host platform has FIXED_VS flag 1661 * incorrectly configured or the sink device is returning an invalid count. 1662 */ 1663 DC_LOG_ERROR("lttpr_caps phy_repeater_cnt is 0x%x, forcing it to 0x80.", 1664 link->dpcd_caps.lttpr_caps.phy_repeater_cnt); 1665 link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80; 1666 lttpr_count = 1; 1667 DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt); 1668 } 1669 1670 is_lttpr_present = dp_is_lttpr_present(link); 1671 1672 DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present); 1673 1674 if (is_lttpr_present) { 1675 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: "); 1676 1677 // Identify closest LTTPR to determine if workarounds required for known embedded LTTPR 1678 closest_lttpr_offset = dp_get_closest_lttpr_offset(lttpr_count); 1679 1680 core_link_read_dpcd(link, (DP_LTTPR_IEEE_OUI + closest_lttpr_offset), 1681 link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui)); 1682 core_link_read_dpcd(link, (DP_LTTPR_DEVICE_ID + closest_lttpr_offset), 1683 link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id)); 1684 1685 if (lttpr_count > 1) { 1686 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui), 1687 "Closest LTTPR To Host's IEEE OUI: "); 1688 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id), 1689 "Closest LTTPR To Host's LTTPR Device ID: "); 1690 } else { 1691 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui), 1692 "LTTPR IEEE OUI: "); 1693 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id), 1694 "LTTPR Device ID: "); 1695 } 1696 } 1697 1698 return status; 1699} 1700 1701static bool retrieve_link_cap(struct dc_link *link) 1702{ 1703 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16, 1704 * which means size 16 will be good for both of those DPCD register block reads 1705 */ 1706 uint8_t dpcd_data[16]; 1707 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST. 1708 */ 1709 uint8_t dpcd_dprx_data = '\0'; 1710 1711 struct dp_device_vendor_id sink_id; 1712 union down_stream_port_count down_strm_port_count; 1713 union edp_configuration_cap edp_config_cap; 1714 union dp_downstream_port_present ds_port = { 0 }; 1715 enum dc_status status = DC_ERROR_UNEXPECTED; 1716 uint32_t read_dpcd_retry_cnt = 20; 1717 int i; 1718 struct dp_sink_hw_fw_revision dp_hw_fw_revision; 1719 const uint32_t post_oui_delay = 30; // 30ms 1720 bool is_fec_supported = false; 1721 bool is_dsc_basic_supported = false; 1722 bool is_dsc_passthrough_supported = false; 1723 1724 memset(dpcd_data, '\0', sizeof(dpcd_data)); 1725 memset(&down_strm_port_count, 1726 '\0', sizeof(union down_stream_port_count)); 1727 memset(&edp_config_cap, '\0', 1728 sizeof(union edp_configuration_cap)); 1729 1730 /* if extended timeout is supported in hardware, 1731 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 1732 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 1733 */ 1734 try_to_configure_aux_timeout(link->ddc, 1735 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 1736 1737 status = dp_retrieve_lttpr_cap(link); 1738 1739 if (status != DC_OK) { 1740 status = wake_up_aux_channel(link); 1741 if (status == DC_OK) 1742 dp_retrieve_lttpr_cap(link); 1743 else 1744 return false; 1745 } 1746 1747 if (dp_is_lttpr_present(link)) { 1748 configure_lttpr_mode_transparent(link); 1749 1750 // Echo TOTAL_LTTPR_CNT back downstream 1751 core_link_write_dpcd( 1752 link, 1753 DP_TOTAL_LTTPR_CNT, 1754 &link->dpcd_caps.lttpr_caps.phy_repeater_cnt, 1755 sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt)); 1756 } 1757 1758 dpcd_set_source_specific_data(link); 1759 1760 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1761 /* 1762 * Sink may need to configure internals based on vendor, so allow some 1763 * time before proceeding with possibly vendor specific transactions 1764 */ 1765 msleep(post_oui_delay); 1766 status = core_link_read_dpcd( 1767 link, 1768 DP_DPCD_REV, 1769 dpcd_data, 1770 sizeof(dpcd_data)); 1771 if (status == DC_OK) 1772 break; 1773 } 1774 1775 1776 if (status != DC_OK) { 1777 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__); 1778 return false; 1779 } 1780 1781 if (!dp_is_lttpr_present(link)) 1782 try_to_configure_aux_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 1783 1784 1785 { 1786 union training_aux_rd_interval aux_rd_interval; 1787 1788 aux_rd_interval.raw = 1789 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL]; 1790 1791 link->dpcd_caps.ext_receiver_cap_field_present = 1792 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1; 1793 1794 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) { 1795 uint8_t ext_cap_data[16]; 1796 1797 memset(ext_cap_data, '\0', sizeof(ext_cap_data)); 1798 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1799 status = core_link_read_dpcd( 1800 link, 1801 DP_DP13_DPCD_REV, 1802 ext_cap_data, 1803 sizeof(ext_cap_data)); 1804 if (status == DC_OK) { 1805 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data)); 1806 break; 1807 } 1808 } 1809 if (status != DC_OK) 1810 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__); 1811 } 1812 } 1813 1814 link->dpcd_caps.dpcd_rev.raw = 1815 dpcd_data[DP_DPCD_REV - DP_DPCD_REV]; 1816 1817 if (link->dpcd_caps.ext_receiver_cap_field_present) { 1818 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1819 status = core_link_read_dpcd( 1820 link, 1821 DP_DPRX_FEATURE_ENUMERATION_LIST, 1822 &dpcd_dprx_data, 1823 sizeof(dpcd_dprx_data)); 1824 if (status == DC_OK) 1825 break; 1826 } 1827 1828 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data; 1829 1830 if (status != DC_OK) 1831 dm_error("%s: Read DPRX feature list failed.\n", __func__); 1832 1833 /* AdaptiveSyncCapability */ 1834 dpcd_dprx_data = 0; 1835 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1836 status = core_link_read_dpcd( 1837 link, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1, 1838 &dpcd_dprx_data, sizeof(dpcd_dprx_data)); 1839 if (status == DC_OK) 1840 break; 1841 } 1842 1843 link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.raw = dpcd_dprx_data; 1844 1845 if (status != DC_OK) 1846 dm_error("%s: Read DPRX feature list_1 failed. Addr:%#x\n", 1847 __func__, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1); 1848 } 1849 else { 1850 link->dpcd_caps.dprx_feature.raw = 0; 1851 } 1852 1853 /* Error condition checking... 1854 * It is impossible for Sink to report Max Lane Count = 0. 1855 * It is possible for Sink to report Max Link Rate = 0, if it is 1856 * an eDP device that is reporting specialized link rates in the 1857 * SUPPORTED_LINK_RATE table. 1858 */ 1859 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) 1860 return false; 1861 1862 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT - 1863 DP_DPCD_REV]; 1864 1865 read_dp_device_vendor_id(link); 1866 1867 /* TODO - decouple raw mst capability from policy decision */ 1868 link->dpcd_caps.is_mst_capable = read_is_mst_supported(link); 1869 DC_LOG_DC("%s: MST_Support: %s\n", __func__, str_yes_no(link->dpcd_caps.is_mst_capable)); 1870 1871 /* Some MST docks seem to NAK I2C writes to segment pointer with mot=0. */ 1872 if (link->dpcd_caps.is_mst_capable) 1873 link->wa_flags.dp_mot_reset_segment = true; 1874 else 1875 link->wa_flags.dp_mot_reset_segment = false; 1876 1877 get_active_converter_info(ds_port.byte, link); 1878 1879 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data)); 1880 1881 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT - 1882 DP_DPCD_REV]; 1883 1884 link->dpcd_caps.allow_invalid_MSA_timing_param = 1885 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM; 1886 1887 link->dpcd_caps.max_ln_count.raw = dpcd_data[ 1888 DP_MAX_LANE_COUNT - DP_DPCD_REV]; 1889 1890 link->dpcd_caps.max_down_spread.raw = dpcd_data[ 1891 DP_MAX_DOWNSPREAD - DP_DPCD_REV]; 1892 1893 link->reported_link_cap.lane_count = 1894 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; 1895 link->reported_link_cap.link_rate = get_link_rate_from_max_link_bw( 1896 dpcd_data[DP_MAX_LINK_RATE - DP_DPCD_REV]); 1897 link->reported_link_cap.link_spread = 1898 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? 1899 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 1900 1901 edp_config_cap.raw = dpcd_data[ 1902 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV]; 1903 link->dpcd_caps.panel_mode_edp = 1904 edp_config_cap.bits.ALT_SCRAMBLER_RESET; 1905 link->dpcd_caps.dpcd_display_control_capable = 1906 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE; 1907 link->dpcd_caps.channel_coding_cap.raw = 1908 dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV]; 1909 link->test_pattern_enabled = false; 1910 link->compliance_test_state.raw = 0; 1911 1912 link->dpcd_caps.receive_port0_cap.raw[0] = 1913 dpcd_data[DP_RECEIVE_PORT_0_CAP_0 - DP_DPCD_REV]; 1914 link->dpcd_caps.receive_port0_cap.raw[1] = 1915 dpcd_data[DP_RECEIVE_PORT_0_BUFFER_SIZE - DP_DPCD_REV]; 1916 1917 /* read sink count */ 1918 core_link_read_dpcd(link, 1919 DP_SINK_COUNT, 1920 &link->dpcd_caps.sink_count.raw, 1921 sizeof(link->dpcd_caps.sink_count.raw)); 1922 1923 /* read sink ieee oui */ 1924 core_link_read_dpcd(link, 1925 DP_SINK_OUI, 1926 (uint8_t *)(&sink_id), 1927 sizeof(sink_id)); 1928 1929 link->dpcd_caps.sink_dev_id = 1930 (sink_id.ieee_oui[0] << 16) + 1931 (sink_id.ieee_oui[1] << 8) + 1932 (sink_id.ieee_oui[2]); 1933 1934 memmove( 1935 link->dpcd_caps.sink_dev_id_str, 1936 sink_id.ieee_device_id, 1937 sizeof(sink_id.ieee_device_id)); 1938 1939 core_link_read_dpcd( 1940 link, 1941 DP_SINK_HW_REVISION_START, 1942 (uint8_t *)&dp_hw_fw_revision, 1943 sizeof(dp_hw_fw_revision)); 1944 1945 link->dpcd_caps.sink_hw_revision = 1946 dp_hw_fw_revision.ieee_hw_rev; 1947 1948 memmove( 1949 link->dpcd_caps.sink_fw_revision, 1950 dp_hw_fw_revision.ieee_fw_rev, 1951 sizeof(dp_hw_fw_revision.ieee_fw_rev)); 1952 1953 /* Quirk for Retina panels: wrong DP_MAX_LINK_RATE */ 1954 { 1955 uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 }; 1956 uint8_t fwrev_mbp_2018[] = { 7, 4 }; 1957 uint8_t fwrev_mbp_2018_vega[] = { 8, 4 }; 1958 1959 /* We also check for the firmware revision as 16,1 models have an 1960 * identical device id and are incorrectly quirked otherwise. 1961 */ 1962 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) && 1963 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2018, 1964 sizeof(str_mbp_2018)) && 1965 (!memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018, 1966 sizeof(fwrev_mbp_2018)) || 1967 !memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018_vega, 1968 sizeof(fwrev_mbp_2018_vega)))) { 1969 link->reported_link_cap.link_rate = LINK_RATE_RBR2; 1970 } 1971 } 1972 1973 memset(&link->dpcd_caps.dsc_caps, '\0', 1974 sizeof(link->dpcd_caps.dsc_caps)); 1975 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); 1976 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */ 1977 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) { 1978 status = core_link_read_dpcd( 1979 link, 1980 DP_FEC_CAPABILITY, 1981 &link->dpcd_caps.fec_cap.raw, 1982 sizeof(link->dpcd_caps.fec_cap.raw)); 1983 if (status != DC_OK) 1984 DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_FEC_CAPABILITY) failed\n", __func__, __LINE__); 1985 1986 status = core_link_read_dpcd( 1987 link, 1988 DP_DSC_SUPPORT, 1989 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 1990 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw)); 1991 if (status == DC_OK) { 1992 is_fec_supported = link->dpcd_caps.fec_cap.bits.FEC_CAPABLE; 1993 is_dsc_basic_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT; 1994 is_dsc_passthrough_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT; 1995 DC_LOG_DC("%s: FEC_Sink_Support: %s\n", __func__, 1996 str_yes_no(is_fec_supported)); 1997 DC_LOG_DC("%s: DSC_Basic_Sink_Support: %s\n", __func__, 1998 str_yes_no(is_dsc_basic_supported)); 1999 DC_LOG_DC("%s: DSC_Passthrough_Sink_Support: %s\n", __func__, 2000 str_yes_no(is_dsc_passthrough_supported)); 2001 } 2002 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) { 2003 status = core_link_read_dpcd( 2004 link, 2005 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, 2006 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 2007 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw)); 2008 if (status != DC_OK) 2009 DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_DSC_BRANCH_OVERALL_THROUGHPUT_0) failed\n", __func__, __LINE__); 2010 2011 DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index); 2012 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x", 2013 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0); 2014 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x", 2015 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_1); 2016 DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x", 2017 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_MAX_LINE_WIDTH); 2018 } 2019 2020 /* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode 2021 * only if required. 2022 */ 2023 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 2024 link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around && 2025 link->dpcd_caps.is_branch_dev && 2026 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 2027 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 && 2028 (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE || 2029 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) { 2030 /* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA. 2031 * Clear FEC and DSC capabilities as a work around if that is not the case. 2032 */ 2033 link->wa_flags.dpia_forced_tbt3_mode = true; 2034 memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps)); 2035 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); 2036 DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index); 2037 } else 2038 link->wa_flags.dpia_forced_tbt3_mode = false; 2039 } 2040 2041 if (!dpcd_read_sink_ext_caps(link)) 2042 link->dpcd_sink_ext_caps.raw = 0; 2043 2044 if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) { 2045 DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index); 2046 2047 /* Read 128b/132b suppoerted link rates */ 2048 core_link_read_dpcd(link, 2049 DP_128B132B_SUPPORTED_LINK_RATES, 2050 &link->dpcd_caps.dp_128b_132b_supported_link_rates.raw, 2051 sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw)); 2052 if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20) 2053 link->reported_link_cap.link_rate = LINK_RATE_UHBR20; 2054 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5) 2055 link->reported_link_cap.link_rate = LINK_RATE_UHBR13_5; 2056 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10) 2057 link->reported_link_cap.link_rate = LINK_RATE_UHBR10; 2058 else 2059 dm_error("%s: Invalid RX 128b_132b_supported_link_rates\n", __func__); 2060 DC_LOG_DP2("128b/132b supported link rates is read at link %d", link->link_index); 2061 DC_LOG_DP2("\tmax 128b/132b link rate support is %d.%d GHz", 2062 link->reported_link_cap.link_rate / 100, 2063 link->reported_link_cap.link_rate % 100); 2064 2065 core_link_read_dpcd(link, 2066 DP_SINK_VIDEO_FALLBACK_FORMATS, 2067 &link->dpcd_caps.fallback_formats.raw, 2068 sizeof(link->dpcd_caps.fallback_formats.raw)); 2069 DC_LOG_DP2("sink video fallback format is read at link %d", link->link_index); 2070 if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support) 2071 DC_LOG_DP2("\t1920x1080@60Hz 24bpp fallback format supported"); 2072 if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support) 2073 DC_LOG_DP2("\t1280x720@60Hz 24bpp fallback format supported"); 2074 if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support) 2075 DC_LOG_DP2("\t1024x768@60Hz 24bpp fallback format supported"); 2076 if (link->dpcd_caps.fallback_formats.raw == 0) { 2077 DC_LOG_DP2("\tno supported fallback formats, assume 1920x1080@60Hz 24bpp is supported"); 2078 link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1; 2079 } 2080 2081 core_link_read_dpcd(link, 2082 DP_FEC_CAPABILITY_1, 2083 &link->dpcd_caps.fec_cap1.raw, 2084 sizeof(link->dpcd_caps.fec_cap1.raw)); 2085 DC_LOG_DP2("FEC CAPABILITY 1 is read at link %d", link->link_index); 2086 if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE) 2087 DC_LOG_DP2("\tFEC aggregated error counters are supported"); 2088 } 2089 2090 core_link_read_dpcd(link, 2091 DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP, 2092 link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw, 2093 sizeof(link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw)); 2094 2095 core_link_read_dpcd(link, 2096 DP_PANEL_REPLAY_CAPABILITY_SUPPORT, 2097 &link->dpcd_caps.pr_caps_supported.raw, 2098 sizeof(link->dpcd_caps.pr_caps_supported.raw)); 2099 2100 /* Read DP tunneling information. */ 2101 status = dpcd_get_tunneling_device_data(link); 2102 if (status != DC_OK) 2103 DC_LOG_DP2("%s: Read DP tunneling device data failed.\n", __func__); 2104 2105 retrieve_cable_id(link); 2106 dpcd_write_cable_id_to_dprx(link); 2107 2108 /* Connectivity log: detection */ 2109 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: "); 2110 2111 return true; 2112} 2113 2114bool detect_dp_sink_caps(struct dc_link *link) 2115{ 2116 return retrieve_link_cap(link); 2117} 2118 2119void detect_edp_sink_caps(struct dc_link *link) 2120{ 2121 uint8_t supported_link_rates[16]; 2122 uint32_t entry; 2123 uint32_t link_rate_in_khz; 2124 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN; 2125 uint8_t backlight_adj_cap = 0; 2126 uint8_t general_edp_cap = 0; 2127 2128 retrieve_link_cap(link); 2129 link->dpcd_caps.edp_supported_link_rates_count = 0; 2130 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 2131 2132 /* 2133 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. 2134 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" 2135 */ 2136 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13) { 2137 // Read DPCD 00010h - 0001Fh 16 bytes at one shot 2138 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES, 2139 supported_link_rates, sizeof(supported_link_rates)); 2140 2141 for (entry = 0; entry < 16; entry += 2) { 2142 // DPCD register reports per-lane link rate = 16-bit link rate capability 2143 // value X 200 kHz. Need multiplier to find link rate in kHz. 2144 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 2145 supported_link_rates[entry]) * 200; 2146 2147 DC_LOG_DC("%s: eDP v1.4 supported sink rates: [%d] %d kHz\n", __func__, 2148 entry / 2, link_rate_in_khz); 2149 2150 if (link_rate_in_khz != 0) { 2151 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz); 2152 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate; 2153 link->dpcd_caps.edp_supported_link_rates_count++; 2154 } 2155 } 2156 } 2157 2158 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP, 2159 &backlight_adj_cap, sizeof(backlight_adj_cap)); 2160 2161 link->dpcd_caps.dynamic_backlight_capable_edp = 2162 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true : false; 2163 2164 core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1, 2165 &general_edp_cap, sizeof(general_edp_cap)); 2166 2167 link->dpcd_caps.set_power_state_capable_edp = 2168 (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true : false; 2169 2170 set_default_brightness_aux(link); 2171 2172 core_link_read_dpcd(link, DP_EDP_DPCD_REV, 2173 &link->dpcd_caps.edp_rev, 2174 sizeof(link->dpcd_caps.edp_rev)); 2175 /* 2176 * PSR is only valid for eDP v1.3 or higher. 2177 */ 2178 if (link->dpcd_caps.edp_rev >= DP_EDP_13) { 2179 core_link_read_dpcd(link, DP_PSR_SUPPORT, 2180 &link->dpcd_caps.psr_info.psr_version, 2181 sizeof(link->dpcd_caps.psr_info.psr_version)); 2182 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) 2183 core_link_read_dpcd(link, DP_FORCE_PSRSU_CAPABILITY, 2184 &link->dpcd_caps.psr_info.force_psrsu_cap, 2185 sizeof(link->dpcd_caps.psr_info.force_psrsu_cap)); 2186 core_link_read_dpcd(link, DP_PSR_CAPS, 2187 &link->dpcd_caps.psr_info.psr_dpcd_caps.raw, 2188 sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw)); 2189 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) { 2190 core_link_read_dpcd(link, DP_PSR2_SU_Y_GRANULARITY, 2191 &link->dpcd_caps.psr_info.psr2_su_y_granularity_cap, 2192 sizeof(link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)); 2193 } 2194 } 2195 2196 /* 2197 * ALPM is only valid for eDP v1.4 or higher. 2198 */ 2199 if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14) 2200 core_link_read_dpcd(link, DP_RECEIVER_ALPM_CAP, 2201 &link->dpcd_caps.alpm_caps.raw, 2202 sizeof(link->dpcd_caps.alpm_caps.raw)); 2203 2204 /* 2205 * Read REPLAY info 2206 */ 2207 core_link_read_dpcd(link, DP_SINK_PR_PIXEL_DEVIATION_PER_LINE, 2208 &link->dpcd_caps.pr_info.pixel_deviation_per_line, 2209 sizeof(link->dpcd_caps.pr_info.pixel_deviation_per_line)); 2210 core_link_read_dpcd(link, DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE, 2211 &link->dpcd_caps.pr_info.max_deviation_line, 2212 sizeof(link->dpcd_caps.pr_info.max_deviation_line)); 2213 2214 /* 2215 * OLED Emission Rate info 2216 */ 2217 if (link->dpcd_sink_ext_caps.bits.emission_output) 2218 core_link_read_dpcd(link, DP_SINK_EMISSION_RATE, 2219 (uint8_t *)&link->dpcd_caps.edp_oled_emission_rate, 2220 sizeof(link->dpcd_caps.edp_oled_emission_rate)); 2221 2222 /* 2223 * Read Multi-SST (Single Stream Transport) capability 2224 * for eDP version 1.4 or higher. 2225 */ 2226 if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14) 2227 core_link_read_dpcd( 2228 link, 2229 DP_EDP_MSO_LINK_CAPABILITIES, 2230 (uint8_t *)&link->dpcd_caps.mso_cap_sst_links_supported, 2231 sizeof(link->dpcd_caps.mso_cap_sst_links_supported)); 2232 /* 2233 * Read eDP general capability 2 2234 */ 2235 core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, 2236 (uint8_t *)&link->dpcd_caps.dp_edp_general_cap_2, 2237 sizeof(link->dpcd_caps.dp_edp_general_cap_2)); 2238} 2239 2240bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap) 2241{ 2242 struct resource_context *res_ctx = &link->dc->current_state->res_ctx; 2243 struct resource_pool *res_pool = link->dc->res_pool; 2244 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); 2245 2246 if (!max_link_enc_cap) { 2247 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__); 2248 return false; 2249 } 2250 2251 if (!link->dc->config.unify_link_enc_assignment) 2252 link_enc = link_enc_cfg_get_link_enc(link); 2253 ASSERT(link_enc); 2254 2255 if (link_enc && link_enc->funcs->get_max_link_cap) { 2256 link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap); 2257 return true; 2258 } 2259 2260 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__); 2261 max_link_enc_cap->lane_count = 1; 2262 max_link_enc_cap->link_rate = 6; 2263 return false; 2264} 2265 2266const struct dc_link_settings *dp_get_verified_link_cap( 2267 const struct dc_link *link) 2268{ 2269 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN && 2270 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) 2271 return &link->preferred_link_setting; 2272 return &link->verified_link_cap; 2273} 2274 2275struct dc_link_settings dp_get_max_link_cap(struct dc_link *link) 2276{ 2277 struct dc_link_settings max_link_cap = {0}; 2278 enum dc_lane_count lttpr_max_lane_count; 2279 enum dc_link_rate lttpr_max_link_rate; 2280 enum dc_link_rate cable_max_link_rate; 2281 struct resource_context *res_ctx = &link->dc->current_state->res_ctx; 2282 struct resource_pool *res_pool = link->dc->res_pool; 2283 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); 2284 bool is_uhbr13_5_supported = true; 2285 2286 if (!link->dc->config.unify_link_enc_assignment) 2287 link_enc = link_enc_cfg_get_link_enc(link); 2288 ASSERT(link_enc); 2289 2290 /* get max link encoder capability */ 2291 if (link_enc) 2292 link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap); 2293 2294 /* Lower link settings based on sink's link cap */ 2295 if (link->reported_link_cap.lane_count < max_link_cap.lane_count) 2296 max_link_cap.lane_count = 2297 link->reported_link_cap.lane_count; 2298 if (link->reported_link_cap.link_rate < max_link_cap.link_rate) 2299 max_link_cap.link_rate = 2300 link->reported_link_cap.link_rate; 2301 if (link->reported_link_cap.link_spread < 2302 max_link_cap.link_spread) 2303 max_link_cap.link_spread = 2304 link->reported_link_cap.link_spread; 2305 2306 if (!link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5) 2307 is_uhbr13_5_supported = false; 2308 2309 /* Lower link settings based on cable attributes 2310 * Cable ID is a DP2 feature to identify max certified link rate that 2311 * a cable can carry. The cable identification method requires both 2312 * cable and display hardware support. Since the specs comes late, it is 2313 * anticipated that the first round of DP2 cables and displays may not 2314 * be fully compatible to reliably return cable ID data. Therefore the 2315 * decision of our cable id policy is that if the cable can return non 2316 * zero cable id data, we will take cable's link rate capability into 2317 * account. However if we get zero data, the cable link rate capability 2318 * is considered inconclusive. In this case, we will not take cable's 2319 * capability into account to avoid of over limiting hardware capability 2320 * from users. The max overall link rate capability is still determined 2321 * after actual dp pre-training. Cable id is considered as an auxiliary 2322 * method of determining max link bandwidth capability. 2323 */ 2324 cable_max_link_rate = get_cable_max_link_rate(link); 2325 2326 if (!link->dc->debug.ignore_cable_id && 2327 cable_max_link_rate != LINK_RATE_UNKNOWN) { 2328 if (cable_max_link_rate < max_link_cap.link_rate) 2329 max_link_cap.link_rate = cable_max_link_rate; 2330 2331 if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY && 2332 link->dpcd_caps.cable_id.bits.CABLE_TYPE >= 2) 2333 is_uhbr13_5_supported = false; 2334 } 2335 2336 /* account for lttpr repeaters cap 2337 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3). 2338 */ 2339 if (dp_is_lttpr_present(link)) { 2340 2341 /* Some LTTPR devices do not report valid DPCD revisions, if so, do not take it's link cap into consideration. */ 2342 if (link->dpcd_caps.lttpr_caps.revision.raw >= DPCD_REV_14) { 2343 lttpr_max_lane_count = get_lttpr_max_lane_count(link); 2344 2345 if (lttpr_max_lane_count < max_link_cap.lane_count) 2346 max_link_cap.lane_count = lttpr_max_lane_count; 2347 2348 lttpr_max_link_rate = get_lttpr_max_link_rate(link); 2349 2350 if (lttpr_max_link_rate < max_link_cap.link_rate) 2351 max_link_cap.link_rate = lttpr_max_link_rate; 2352 2353 if (!link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5) 2354 is_uhbr13_5_supported = false; 2355 } 2356 2357 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n", 2358 __func__, 2359 max_link_cap.lane_count, 2360 max_link_cap.link_rate); 2361 } 2362 2363 if (max_link_cap.link_rate == LINK_RATE_UHBR13_5 && 2364 !is_uhbr13_5_supported) 2365 max_link_cap.link_rate = LINK_RATE_UHBR10; 2366 2367 if (link_dp_get_encoding_format(&max_link_cap) == DP_128b_132b_ENCODING && 2368 link->dc->debug.disable_uhbr) 2369 max_link_cap.link_rate = LINK_RATE_HIGH3; 2370 2371 return max_link_cap; 2372} 2373 2374static bool dp_verify_link_cap( 2375 struct dc_link *link, 2376 struct dc_link_settings *known_limit_link_setting, 2377 int *fail_count) 2378{ 2379 struct dc_link_settings cur_link_settings = {0}; 2380 struct dc_link_settings max_link_settings = *known_limit_link_setting; 2381 bool success = false; 2382 bool skip_video_pattern; 2383 enum clock_source_id dp_cs_id = get_clock_source_id(link); 2384 enum link_training_result status = LINK_TRAINING_SUCCESS; 2385 union hpd_irq_data irq_data; 2386 struct link_resource link_res; 2387 2388 memset(&irq_data, 0, sizeof(irq_data)); 2389 cur_link_settings = max_link_settings; 2390 2391 /* Grant extended timeout request */ 2392 if (dp_is_lttpr_present(link) && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) { 2393 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80; 2394 2395 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant)); 2396 } 2397 2398 do { 2399 if (!get_temp_dp_link_res(link, &link_res, &cur_link_settings)) 2400 continue; 2401 2402 skip_video_pattern = cur_link_settings.link_rate != LINK_RATE_LOW; 2403 dp_enable_link_phy( 2404 link, 2405 &link_res, 2406 link->connector_signal, 2407 dp_cs_id, 2408 &cur_link_settings); 2409 2410 status = dp_perform_link_training( 2411 link, 2412 &link_res, 2413 &cur_link_settings, 2414 skip_video_pattern); 2415 2416 if (status == LINK_TRAINING_SUCCESS) { 2417 success = true; 2418 fsleep(1000); 2419 if (dp_read_hpd_rx_irq_data(link, &irq_data) == DC_OK && 2420 dp_parse_link_loss_status( 2421 link, 2422 &irq_data)) 2423 (*fail_count)++; 2424 } else if (status == LINK_TRAINING_LINK_LOSS) { 2425 success = true; 2426 (*fail_count)++; 2427 } else { 2428 (*fail_count)++; 2429 } 2430 dp_trace_lt_total_count_increment(link, true); 2431 dp_trace_lt_result_update(link, status, true); 2432 dp_disable_link_phy(link, &link_res, link->connector_signal); 2433 } while (!success && decide_fallback_link_setting(link, 2434 &max_link_settings, &cur_link_settings, status)); 2435 2436 link->verified_link_cap = success ? 2437 cur_link_settings : fail_safe_link_settings; 2438 return success; 2439} 2440 2441bool dp_verify_link_cap_with_retries( 2442 struct dc_link *link, 2443 struct dc_link_settings *known_limit_link_setting, 2444 int attempts) 2445{ 2446 int i = 0; 2447 bool success = false; 2448 int fail_count = 0; 2449 struct dc_link_settings last_verified_link_cap = fail_safe_link_settings; 2450 2451 dp_trace_detect_lt_init(link); 2452 2453 DC_LOG_HW_LINK_TRAINING("%s: Link[%d] LinkRate=0x%x LaneCount=%d", 2454 __func__, link->link_index, 2455 known_limit_link_setting->link_rate, 2456 known_limit_link_setting->lane_count); 2457 2458 if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C && 2459 link->dc->debug.usbc_combo_phy_reset_wa) 2460 apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting); 2461 2462 dp_trace_set_lt_start_timestamp(link, false); 2463 for (i = 0; i < attempts; i++) { 2464 enum dc_connection_type type = dc_connection_none; 2465 2466 memset(&link->verified_link_cap, 0, 2467 sizeof(struct dc_link_settings)); 2468 if (link->link_enc && (!link_detect_connection_type(link, &type) || type == dc_connection_none)) { 2469 link->verified_link_cap = fail_safe_link_settings; 2470 break; 2471 } else if (dp_verify_link_cap(link, known_limit_link_setting, &fail_count)) { 2472 last_verified_link_cap = link->verified_link_cap; 2473 if (fail_count == 0) { 2474 success = true; 2475 break; 2476 } 2477 } else { 2478 link->verified_link_cap = last_verified_link_cap; 2479 } 2480 2481 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing 2482 * current link and processing the pending HPD. Since the training is failed, we should just brak 2483 * the loop so that we have chance to process the pending HPD. 2484 */ 2485 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending) 2486 break; 2487 2488 fsleep(10 * 1000); 2489 } 2490 2491 dp_trace_lt_fail_count_update(link, fail_count, true); 2492 dp_trace_set_lt_end_timestamp(link, true); 2493 2494 DC_LOG_HW_LINK_TRAINING("%s: Link[%d] Exit. is_success=%d fail_count=%d", 2495 __func__, link->link_index, 2496 success, 2497 fail_count); 2498 2499 return success; 2500} 2501 2502/* 2503 * Check if there is a native DP or passive DP-HDMI dongle connected 2504 */ 2505bool dp_is_sink_present(struct dc_link *link) 2506{ 2507 enum gpio_result gpio_result; 2508 uint32_t clock_pin = 0; 2509 uint8_t retry = 0; 2510 struct ddc *ddc; 2511 2512 enum connector_id connector_id = 2513 dal_graphics_object_id_get_connector_id(link->link_id); 2514 2515 bool present = 2516 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || 2517 (connector_id == CONNECTOR_ID_EDP) || 2518 (connector_id == CONNECTOR_ID_USBC)); 2519 2520 ddc = get_ddc_pin(link->ddc); 2521 2522 if (!ddc) { 2523 BREAK_TO_DEBUGGER(); 2524 return present; 2525 } 2526 2527 /* Open GPIO and set it to I2C mode */ 2528 /* Note: this GpioMode_Input will be converted 2529 * to GpioConfigType_I2cAuxDualMode in GPIO component, 2530 * which indicates we need additional delay 2531 */ 2532 2533 if (dal_ddc_open(ddc, GPIO_MODE_INPUT, 2534 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) { 2535 dal_ddc_close(ddc); 2536 2537 return present; 2538 } 2539 2540 /* 2541 * Read GPIO: DP sink is present if both clock and data pins are zero 2542 * 2543 * [W/A] plug-unplug DP cable, sometimes customer board has 2544 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI 2545 * then monitor can't br light up. Add retry 3 times 2546 * But in real passive dongle, it need additional 3ms to detect 2547 */ 2548 do { 2549 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin); 2550 ASSERT(gpio_result == GPIO_RESULT_OK); 2551 if (clock_pin) 2552 fsleep(1000); 2553 else 2554 break; 2555 } while (retry++ < 3); 2556 2557 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin; 2558 2559 dal_ddc_close(ddc); 2560 2561 return present; 2562} 2563 2564uint8_t dp_get_lttpr_count(struct dc_link *link) 2565{ 2566 if (dp_is_lttpr_present(link)) 2567 return dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); 2568 2569 return 0; 2570} 2571 2572void edp_get_alpm_support(struct dc_link *link, 2573 bool *auxless_support, 2574 bool *auxwake_support) 2575{ 2576 bool lttpr_present = dp_is_lttpr_present(link); 2577 2578 if (auxless_support == NULL || auxwake_support == NULL) 2579 return; 2580 2581 *auxless_support = false; 2582 *auxwake_support = false; 2583 2584 if (!dc_is_embedded_signal(link->connector_signal)) 2585 return; 2586 2587 if (link->dpcd_caps.alpm_caps.bits.AUX_LESS_ALPM_CAP) { 2588 if (lttpr_present) { 2589 if (link->dpcd_caps.lttpr_caps.alpm.bits.AUX_LESS_ALPM_SUPPORTED) 2590 *auxless_support = true; 2591 } else 2592 *auxless_support = true; 2593 } 2594 2595 if (link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP) { 2596 if (!lttpr_present) 2597 *auxwake_support = true; 2598 } 2599}
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